Method for manufacturing a semiconductor device

Abstract

The present invention discloses a method for manufacturing a semiconductor device, which relates to the field of semiconductor technology and is used to reduce the annealing heat plan of the dipole threshold control technology to ensure that the semiconductor device has good working performance. The method for manufacturing the semiconductor device comprises: providing a semiconductor substrate. Each type of region of the semiconductor substrate is formed with a channel included in a corresponding ring-gate transistor and a first gate dielectric sublayer surrounding the outer circumference of the channel. A dipole layer of corresponding thickness and corresponding material is formed on the first gate dielectric sublayer located on at least part of the type of region. The semiconductor substrate formed with the dipole layer is annealed so that different types of regions correspond to different threshold control parameters; and the dipole layer is removed. The second gate dielectric sublayer and the gate included in the corresponding ring-gate transistor are sequentially formed on the first gate dielectric sublayer located on each type of region. The gate dielectric layer included in each ring-gate transistor includes a first gate dielectric sublayer and a second gate dielectric sublayer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] In the actual process of manufacturing semiconductor devices, the use of dipole threshold control technology can realize the control of the threshold voltage of different ring-gate transistors in the semiconductor device without reducing the formation space of the gate, thereby not affecting the subsequent gate filling and improving the yield of the semiconductor device.

[0003] However, the dipole threshold control technology used in existing semiconductor device manufacturing methods has a high annealing heat plan, which will affect the working performance of the manufactured semiconductor device. Summary of the Invention

[0004] The object of the present invention is to provide a method for manufacturing a semiconductor device, which is used to reduce the annealing heat plan of the dipole threshold control technology and ensure that the semiconductor device has good working performance.

[0005] In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, the method comprising:

[0006] A semiconductor substrate is provided. The semiconductor substrate has at least two types of regions along a direction parallel to a surface of the semiconductor substrate. Each type of region has a channel of a corresponding all-around gate transistor and a first gate dielectric sublayer surrounding the channel.

[0007] A dipole layer with a corresponding thickness and a corresponding material is formed on the first gate dielectric sublayer located on at least a portion of the sub-region.

[0008] Annealing is performed on the semiconductor substrate formed with the dipole layer so that different types of regions correspond to different threshold control parameters; and the dipole layer is removed.

[0009] The second gate dielectric sublayer and gate of the corresponding gate-all-around transistor are sequentially formed on the first gate dielectric sublayer located on each type of region. The gate dielectric layer included in each gate-all-around transistor includes the first gate dielectric sublayer and the second gate dielectric sublayer located on the corresponding type of region.

[0010] Compared to the prior art, in the semiconductor device manufacturing method provided by the present invention, a channel including a corresponding all-around gate transistor and a first gate dielectric sublayer surrounding the outer periphery of the channel are formed on each type of region of the semiconductor substrate. In addition, a dipole layer of corresponding thickness and corresponding material is formed on the first gate dielectric sublayer located on at least some of the type regions. Based on this, after annealing the semiconductor substrate with the above-mentioned dipole layer, different types of regions can correspond to different threshold control parameters. Therefore, the all-around gate transistors located in different types of regions have different threshold voltages, thereby realizing the control of the threshold voltage of the all-around gate transistor.

[0011] In addition, after removing the dipole layer, the second gate dielectric sublayer and gate included in the corresponding ring-gate transistor are sequentially formed on the first gate dielectric sublayer located on each type of region. Moreover, the gate dielectric layer included in each ring-gate transistor includes the first gate dielectric sublayer and the second gate dielectric sublayer located on the corresponding type of region. Based on this, it can be understood that before forming the dipole layer on at least part of the type of region, only a first gate dielectric sublayer with a thickness less than the thickness of the entire gate dielectric layer is formed on the periphery of the channel of each type of region. In this case, in the actual manufacturing process, the purpose of the above-mentioned annealing treatment is to push the key elements in the dipole layer formed on the first gate dielectric sublayer to the interface between the channel and the gate dielectric layer, and the time and temperature of the annealing treatment are inversely proportional to the thickness of the corresponding gate dielectric layer or gate dielectric sublayer located below the dipole layer. Therefore, compared with forming the dipole layer on the entire gate dielectric layer with a larger thickness, the manufacturing method provided by the present invention forms the dipole layer on the first gate dielectric sublayer with a smaller thickness. At this time, because the distance between the dipole layer and the corresponding channel is relatively close, the key elements in the dipole layer can be moved to the interface between the channel and the gate dielectric layer without the need for a high temperature and long time annealing treatment, thereby reducing the thermal plan of the annealing treatment, making it easier to obtain semiconductor devices while ensuring that the manufactured semiconductor devices have good working performance. Secondly, when the manufacturing method provided by the present invention is used to manufacture semiconductor devices located in the second layer or higher layers of an integrated circuit, it is also possible to prevent the influence of high-temperature annealing on the underlying semiconductor devices, thereby ensuring that the underlying semiconductor devices of the integrated circuit have good working performance. Furthermore, when the material of the channel is a germanium-containing semiconductor material, it is also possible to solve the problem of poor compatibility in the prior art, such as the change in the carrier transmission performance in the channel containing germanium due to the advancement of key elements through high-temperature annealing treatment, thereby improving the conductive performance of the ring-gate transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0013] Figure 1 A flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0014] Figure 2 A schematic diagram of a structure in the process of manufacturing a semiconductor device using the method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 1 ;

[0015] Figure 3 A schematic diagram of a structure in the process of manufacturing a semiconductor device using the method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 2 ;

[0016] Figure 4 A schematic diagram of a structure in the process of manufacturing a semiconductor device using the method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 3 ;

[0017] Figure 5 A schematic diagram of a structure in the process of manufacturing a semiconductor device using the method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 4 ;

[0018] Figure 6 A schematic diagram of a structure in the process of manufacturing a semiconductor device using the method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 5 ;

[0019] Figure 7 A schematic diagram of a structure in the process of manufacturing a semiconductor device using the method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 6 ;

[0020] Figure 8 A schematic diagram of a structure in the process of manufacturing a semiconductor device using the method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 7 ;

[0021] Figure 9 A schematic diagram of a structure in the process of manufacturing a semiconductor device using the method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 8 ;

[0022] Figure 10 A schematic diagram of a structure in the process of manufacturing a semiconductor device using the method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 9 ;

[0023] Figure 11 A schematic diagram of a structure in the process of manufacturing a semiconductor device using the method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 10 ;

[0024] Figure 12A schematic diagram of a structure in the process of manufacturing a semiconductor device using the method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 10 one;

[0025] Figure 13 A schematic diagram of a structure in the process of manufacturing a semiconductor device using the method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 10 two;

[0026] Figure 14 A schematic diagram of a structure in the process of manufacturing a semiconductor device using the method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 10 three;

[0027] Figure 15 A schematic diagram of a structure in the process of manufacturing a semiconductor device using the method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 10 Four;

[0028] Figure 16 A schematic diagram of a structure in the process of manufacturing a semiconductor device using the method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 10 five;

[0029] Figure 17 A schematic diagram of a structure in the process of manufacturing a semiconductor device using the method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 10 six;

[0030] Figure 18 A schematic diagram of a structure in a process of manufacturing a semiconductor device using a method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 10 seven;

[0031] Figure 19 A schematic diagram of a structure in the process of manufacturing a semiconductor device using the method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 10 eight;

[0032] Figure 20 A schematic diagram of a structure in the process of manufacturing a semiconductor device using the method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 10 Nine;

[0033] Figure 21 A schematic diagram of a structure in the process of manufacturing a semiconductor device using the method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 2 ten;

[0034] Figure 22 A schematic diagram of a structure in a process of manufacturing a semiconductor device using a method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 2 eleven;

[0035] Figure 23A schematic diagram of a structure in a process of manufacturing a semiconductor device using a method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 2 twelve.

[0036] Figure numerals: 11 is a semiconductor substrate, 12 is a first type of region, 13 is a second type of region, 14 is a third type of region, 15 is a channel, 16 is an interface layer, 17 is a first gate dielectric sublayer, 18 is a dipole material layer, 19 is a mask layer, 20 is a covering layer, 21 is a dipole layer, 22 is a second gate dielectric sublayer, and 23 is a gate. DETAILED DESCRIPTION

[0037] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0038] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0039] In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intervening layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed. To further clarify the technical problems, technical solutions, and beneficial effects to be solved by the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are intended solely to explain the present invention and are not intended to limit the present invention.

[0040] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0041] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and may encompass internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0042] In the actual manufacturing process of semiconductor devices, multiple "deposition-etching-deposition" methods are usually used to form gate stack structures of different thicknesses and / or different materials on the channels included in different transistors in the semiconductor device, so that different transistors correspond to different threshold control parameters, thereby realizing the control of the threshold voltage of different transistors in the semiconductor device. With the development of semiconductor technology, integrated circuits with higher performance and stronger functions require greater component density, and the size, size and space between each component, or each component itself also need to be further reduced. For ring-gate transistors, the space between two adjacent nanostructures in the channel and between the nanostructure and the semiconductor substrate is relatively small. It is difficult to form gate stack structures of different thicknesses and / or different materials in a smaller space, resulting in reduced yield and performance of semiconductor devices.

[0043] In response to the above technical problems, those skilled in the art have developed a dipole threshold control technology that does not take up space to achieve the control of the threshold voltage of different transistors in semiconductor devices. Specifically, taking the transistor as a ring-gate transistor as an example, after the channel included in the corresponding ring-gate transistor is formed on different types of regions, the gate dielectric layer of each ring-gate transistor is completely formed on the periphery of the channel located on each type of region. Then, a dipole layer of corresponding thickness and corresponding material is formed on the entire gate dielectric layer, and the key elements in the dipole layer (for example, lanthanum elements in lanthanum oxide dipole layer) are pushed to the interface between the gate dielectric layer and the channel through annealing treatment, so that different types of regions correspond to different threshold control parameters. Finally, the remaining dipole layer is removed, and the threshold voltage control of different ring-gate transistors is achieved without reducing the formation space of the gate, thereby not affecting the subsequent filling of the gate.

[0044] However, because the entire gate dielectric layer has a certain thickness, there is a problem of high annealing heat generation in the process of pushing the key elements in the dipole layer formed on the gate dielectric layer to the above-mentioned interface through the above-mentioned annealing treatment, which affects the working performance of the semiconductor device. For example: in the case where the material of the channel included in the ring-gate transistor is silicon germanium or germanium material, the above-mentioned annealing treatment will cause the carrier transmission performance in the channel to change, thereby causing the conductivity of the ring-gate transistor to deteriorate. For another example: in the case where the above-mentioned dipole threshold control technology is used to control the threshold of the ring-gate transistor located in the second layer or higher in the semiconductor device, the above-mentioned annealing treatment will also cause the underlying device to be affected by the high temperature and the electrical performance to deteriorate.

[0045] To address the above technical issues, embodiments of the present invention provide a method for manufacturing a semiconductor device. Specifically, in the method, before forming a dipole layer on at least a portion of the class region, only a first gate dielectric sublayer having a thickness less than the entire gate dielectric layer is formed around the channel periphery of each class region to reduce the thermal stress of the annealing process, thereby facilitating the production of the semiconductor device and improving the operating performance of the manufactured semiconductor device.

[0046] like Figure 1 As shown, the embodiment of the present invention provides a method for manufacturing a semiconductor device. Figures 2 to 23 The manufacturing process is described in detail with reference to the cross-sectional view of the operation shown in FIG. Specifically, the manufacturing method of the semiconductor device includes:

[0047] First, if Figure 2 and Figure 3 As shown, a semiconductor substrate 11 is provided. Along a direction parallel to the surface of the semiconductor substrate 11, the semiconductor substrate 11 has at least two types of regions. Each type of region has a channel 15 of a corresponding all-around gate transistor and a first gate dielectric sublayer 17 surrounding the outer periphery of the channel 15.

[0048] Specifically, the material and structure of the semiconductor substrate can be set according to actual needs, as long as it can be applied to the method for manufacturing a semiconductor device provided by the embodiment of the present invention.

[0049] As for the number of types of regions possessed by the semiconductor substrate, since corresponding ring-gate transistors will be formed on different types of regions possessed by the semiconductor substrate in the future, and the ring-gate transistors located in different types of regions correspond to different threshold control parameters, the number of types of regions possessed by the semiconductor substrate can be set according to the threshold control requirements of each ring-gate transistor included in the semiconductor device in the actual application scenario. For example: the semiconductor device includes one or more first ring-gate transistors and one or more second ring-gate transistors. The conductivity type of the first ring-gate transistor and the conductivity type of the second ring-gate transistor can be the same or different. In this case, if the first threshold control parameter corresponding to the first ring-gate transistor is not equal to the second threshold control parameter corresponding to the second ring-gate transistor, then the semiconductor substrate has two types of regions. Among them, the first type of region corresponds to the formation of the above-mentioned one or more first ring-gate transistors. The second type of region corresponds to the formation of the above-mentioned one or more second ring-gate transistors.

[0050] In addition, the number of ring-gate transistors corresponding to each type of region of the semiconductor substrate can refer to the number of ring-gate transistors corresponding to the same threshold control parameters, and is not specifically limited here. For example: when the semiconductor device includes two first ring-gate transistors corresponding to the first threshold control parameters, four second ring-gate transistors corresponding to the second threshold control parameters, and six third ring-gate transistors corresponding to the third threshold control parameters, the above-mentioned semiconductor substrate has three types of regions (first type of region, second type of region and third type of region). In addition, the first type of region of the semiconductor substrate has two channels including the first ring-gate transistors and the corresponding first gate dielectric sublayer formed thereon. The second type of region of the semiconductor substrate has four channels including the second ring-gate transistors and the corresponding first gate dielectric sublayer formed thereon. The third type of region of the semiconductor substrate has six channels including the third ring-gate transistors and the corresponding first gate dielectric sublayer formed thereon.

[0051] For each of the above-mentioned gate-all-around transistors, the channel Figure 2 As shown, the channel 15 included in each ring-gate transistor has at least one layer of nanostructure formed on the semiconductor substrate 11. Among them, the number of layers and spacing of the nanostructures included in the channel 15 of the ring-gate transistor located in different types of regions can be the same or different. In addition, the material of the above-mentioned channel 15 is a semiconductor material such as silicon, silicon germanium, germanium or a group III-V compound. Exemplarily, the material of the channel can be silicon germanium or germanium. For example: the material of the channel is Si 0.2 Ge 0.8 、Si 0.75 Ge 0.25In this case, since silicon germanium and germanium materials have higher carrier mobility than silicon materials, when the channel material includes silicon germanium or germanium, the carrier mobility in the manufactured all-around gate transistor can be improved, which is beneficial to improving the electrical performance of the all-around gate transistor.

[0052] In addition, the number of layers and materials of the nanostructures in the channels of different all-around gate transistors located on different types of regions and different all-around gate transistors located on the same type of region may be the same or different.

[0053] For the first gate dielectric sublayer included in each of the aforementioned gate-all-around transistors, the thickness and material of each first gate dielectric sublayer can be set based on the actual application scenario and are not specifically limited here. The thickness and material of different first gate dielectric sublayers located in different types of regions, as well as different first gate dielectric sublayers located in the same type of region, can be the same or different, as long as the thickness of the first gate dielectric sublayer formed around the channel is less than the thickness of the gate dielectric layer included in the corresponding gate-all-around transistor.

[0054] Exemplarily, the material of the first gate dielectric sublayer may be an insulating material such as HfO 2 , ZrO 2 , TiO 2 or Al 2 O 3 .

[0055] Exemplarily, the thickness of the first gate dielectric sublayer can be 0.3 nm to 1 nm. For example, the thickness of the first gate dielectric sublayer can be 0.3 nm, 0.5 nm, 0.7 nm, 0.9 nm or 1 nm. In this case, because the monolayer of the insulating material has a certain thickness, when the minimum thickness of the first gate dielectric sublayer is greater than or equal to 0.3 nm, it can be prevented that the thickness of the first gate dielectric sublayer is too small, so that some types of insulating materials cannot meet the thickness requirements, resulting in fewer material options for the first gate dielectric sublayer in the semiconductor device manufactured by the manufacturing method provided by the embodiment of the present invention. This is conducive to selecting a suitable material for the first gate dielectric sublayer according to the requirements of different application scenarios, thereby improving the applicability of the manufacturing method provided by the embodiment of the present invention in different application scenarios. At the same time, it can also prevent the thermal plan of the subsequent annealing treatment from being significantly reduced due to the large thickness of the first gate dielectric sublayer.

[0056] In some cases, a shallow trench isolation structure, a gate sidewall, a source region, a drain region and a dielectric layer may also be formed on each type of region. Specifically, the shallow trench isolation structure is used to define the active area of ​​the semiconductor substrate. The material contained in the shallow trench isolation structure may be an insulating material such as SiN, Si3N4, SiO2 or SiCO. The source region and the drain region are respectively formed on both sides of the channel along its length direction. The material of the source region and the drain region may be a semiconductor material such as silicon, silicon germanium or germanium. The dielectric layer is covered on the semiconductor substrate, and the top height of the dielectric layer is equal to the maximum top height of the gate sidewall. The gate sidewall is formed between the dielectric layer and the gate dielectric layer and the gate included in the ring-gate transistor. The material of the gate sidewall and the dielectric layer may be an insulating material such as silicon dioxide and silicon nitride.

[0057] In actual applications, the fabrication process for forming the channel of a gate-all-around transistor on a semiconductor substrate varies depending on factors such as the number and spacing of nanostructure layers within the channel located in different regions. Furthermore, the fabrication process for forming the first gate dielectric sublayer of a gate-all-around transistor on a semiconductor substrate also varies depending on factors such as the material and thickness of the first gate dielectric sublayer located in different regions. The following briefly describes the fabrication process for forming the channel of a gate-all-around transistor and the first gate dielectric sublayer on each region of a semiconductor substrate, using the example of a case where the channels located in different regions include the same number of nanostructure layers, the spacing between adjacent nanostructures within the same layer, and the same material and thickness of the first gate dielectric sublayer located in different regions. First, a stack of layers is formed on the semiconductor substrate along the thickness of the semiconductor substrate, with the number of nanostructure layers being equal to the number of nanostructure layers. Each stack includes a sacrificial layer and a channel layer located above the sacrificial layer. The stack and the semiconductor substrate are then etched using processes such as photolithography and etching to form a fin structure in each region. Next, a shallow trench isolation structure is formed on the portion of the semiconductor substrate exposed outside the fin structure. The top height of the shallow trench isolation structure is less than or equal to the bottom height of the lowest sacrificial layer. The portion of the fin structure exposed outside the shallow trench isolation structure is the fin. Along the length of the fin, each type of fin includes a source formation region, a drain formation region, and a transition region between the source and drain formation regions. Then, a sacrificial gate and gate sidewalls are formed around the transition region of each fin. The gate sidewalls are formed on at least two sides of the sacrificial gate along its width. The portion of each fin located in the source and drain formation regions is processed to form the source and drain regions of the corresponding gate-all-around transistor in each type of region. A dielectric layer is then formed overlying the semiconductor substrate, with the top height of the dielectric layer equal to the top height of the sacrificial gate. Next, the sacrificial gate and the portion of the sacrificial layer located within the transition region are removed, so that the portion of the channel layer located within the transition region forms the channel of the gate-all-around transistor. Finally, a first gate dielectric sublayer surrounding the channel can be formed using a process such as atomic layer deposition.

[0058] It is worth noting that Figure 3 As shown, when the material and thickness of the first gate dielectric sublayer 17 located on different types of regions are the same, there is no need to use multiple deposition and etching processes. The first gate dielectric sublayer 17 can be directly formed on the periphery of the channel 15 located on each type of region of the semiconductor substrate 11, thereby simplifying the manufacturing process of the semiconductor device.

[0059] It should be noted that the channel and first gate dielectric sublayer of the gate-all-around transistor can be formed in a variety of ways. Forming the above structure is not a key feature of the present invention, so this specification only briefly describes it to facilitate implementation by those skilled in the art. Those skilled in the art can readily devise alternative methods for fabricating the above structure.

[0060] In one example, Figure 4 As shown, an interface layer 16 is also formed on each of the above-mentioned regions. Each interface layer 16 is formed between the corresponding channel 15 and the first gate dielectric sublayer 17. In this case, the presence of the interface layer 16 can reduce the roughness of the surface of the channel 15, improve the interface state of the channel 15, and further improve the conductivity of the ring-gate transistor. Exemplarily, the interface layer 16 can be formed by processes such as chemical vapor deposition. The material and thickness of the interface layer 16 can be set according to actual needs and are not specifically limited here. For example: the material of the interface layer 16 can be silicon oxide, and the thickness of the interface layer 16 can be greater than 0 and less than or equal to 0.7nm.

[0061] Next, if Figure 15 and Figure 21 As shown, a dipole layer 21 of corresponding thickness and corresponding material is formed on the first gate dielectric sublayer 17 located on at least a portion of the analog region.

[0062] Specifically, a dipole layer of corresponding thickness and corresponding material can be formed on the first gate dielectric sublayer located on each type of area. Alternatively, a dipole layer of corresponding thickness and corresponding material can be formed only on the first gate dielectric sublayer located on some types of areas. Specifically, the number of types of areas where the dipole layer of corresponding thickness and corresponding material needs to be formed can be set according to the threshold control parameters corresponding to the ring-gate transistor subsequently formed on the type of area, as well as actual needs, and is not specifically limited here. For example: Figure 15 and Figure 21As shown, the semiconductor device includes a plurality of ring-gate transistors, and the plurality of ring-gate transistors correspond to three different threshold control parameters. At the same time, only the ring-gate transistors corresponding to any two of the three different threshold control parameters are required to form a dipole layer 21 of corresponding thickness and corresponding material on the first gate dielectric sublayer 17 included therein. In this case, the semiconductor substrate 11 has three types of regions, and a dipole layer 21 of corresponding thickness and corresponding material can be formed only on the first gate dielectric sublayer 17 located on the first type of region 12 and the second type of region 13. The dipole layer 21 does not need to be formed on the first gate dielectric sublayer 17 located on the third type of region 14.

[0063] In addition, the material and thickness of the dipole layer located on different types of regions can be set according to actual needs, as long as they can be applied to the manufacturing method of the semiconductor device provided by the embodiment of the present invention. Among them, the materials of the dipole layers located on different types of regions can be the same or different. For example: the semiconductor device includes multiple ring-gate transistors, and the multiple ring-gate transistors correspond to different threshold control parameters. In this case, the material of the dipole layer formed on the first gate dielectric sublayer included in the ring-gate transistors located on different types of regions can be the same or different. In addition, the thickness of the dipole layer located on different types of regions can be the same or different. For example: the semiconductor device is a CMOS device, and the N-type ring-gate transistors included in the CMOS device all have the same threshold control parameters and are all formed on the first type of region. The CMOS device includes P-type ring-gate transistors all have the same threshold control parameters and are all formed on the second type of region. In this case, the thickness of the dipole layer formed on the first gate dielectric sublayer included in the N-type ring-gate transistor and the P-type ring-gate transistor located on different types of regions can be the same or different.

[0064] It should be noted that each of the aforementioned dipole layers may be a single-layer structure made of a single material, or a laminated structure made of at least two materials. For example, when the dipole layer has a single-layer structure, the material of the dipole layer may be La2O3, Al2O3, or MgO. For another example, when the dipole layer has a laminated structure, the material of the dipole layer may be a combination of any two or three of La2O3, Al2O3, and MgO.

[0065] In addition, the dipole layers located on different types of regions may differ only in thickness, only in material, or both in thickness and material. The different thicknesses of the dipole layers located on different types of regions may mean that, when the dipole layer is a single-layer structure, the thicknesses of the dipole layers located on different types of regions are different. It may also mean that, when the dipole layer is a laminated structure, the thicknesses of some materials in the dipole layers located on different types of regions are different. It may also mean that, when the dipole layer is a laminated structure, the thicknesses of each material in the dipole layers located on different types of regions are different. Secondly, the different materials of the dipole layers located on different types of regions may mean that, when the dipole layer is a single-layer structure, the materials of the dipole layers located on different types of regions are completely different. It may also mean that, when the dipole layer is a laminated structure, some materials of the dipole layers located on different types of regions are different. It may also mean that, when the dipole layer is a laminated structure, all materials of the dipole layers located on different types of regions are different.

[0066] In one example, the above-mentioned forming of a dipole layer of corresponding thickness and corresponding material on the first gate dielectric sublayer located on at least a portion of the class region may include the following steps: Figure 5 As shown, at least a dipole material layer 18 is formed on the first gate dielectric sublayer 17 located on each type of region. The thickness of the dipole material layer 18 is greater than zero and less than or equal to the thickness of the dipole layer to be formed on the target type region. In addition, the material of the dipole material layer 18 is the same as at least part of the material of the dipole layer to be formed on the target type region. Next, as Figure 7 and Figure 8 As shown, a mask layer 19 is formed on the semiconductor substrate 11 to expose the region to be removed. The region to be removed is the region of the semiconductor substrate 11 other than the target region. Figure 9 As shown, under the masking effect of the mask layer 19, at least the portion of the dipole material layer 18 located on the to-be-removed region is selectively removed. Figure 10 As shown, the mask layer is removed. Figures 11 to 15 As shown, the above operations are repeated until a dipole layer 21 of corresponding thickness and corresponding material is formed on the first gate dielectric sublayer 17 located on at least a portion of the sub-region.

[0067] Specifically, the thickness of the dipole material layer formed in the above-mentioned single execution number can be equal to the thickness of the same material portion of the dipole layer ultimately formed on the target-type region. For example: when the dipole layer located on the target-type region is a single-layer structure and the material of the dipole layer is La2O3, the thickness of the dipole material layer made of La2O3 can be equal to the thickness of the dipole layer. For another example: when the dipole layer located on the target-type region is a stacked structure and the materials of the dipole layer include La2O3 and Al2O3, the thickness of the dipole material layer made of La2O3 can be equal to the thickness of the La2O3 portion of the dipole layer. In this case, the manufacture of the same material portion of the dipole layer on the target-type region can be achieved through a single cycle. However, when the thickness of the dipole material layer formed in a single execution number is greater than zero and less than the thickness of the same material portion of the dipole layer, the above-mentioned operation needs to be performed at least twice to achieve the manufacture of the same material portion of the dipole layer located on the target-type region. It is conceivable that, when the dipole layers to be formed on at least two types of regions are made of the same material but have different thicknesses, the second formation method (where the thickness of the dipole material layer is greater than zero and less than the thickness of the corresponding dipole layer portion made of the same material) can be more economical in manufacturing the dipole layer and reduce manufacturing costs compared to the first formation method (where the thickness of the dipole material layer is equal to the thickness of the corresponding dipole layer portion made of the same material). As can be seen from the above, the thickness of the dipole material layer formed on the first gate dielectric sublayer in each type of region can be set based on the number of repetitions required for the above operation and the actual application scenario.

[0068] For the target region and the region to be removed, the target region can be any region of the semiconductor substrate where a corresponding dipole material layer is to be formed. Figure 7 As shown, the semiconductor substrate 11 has at least a first type of region 12, a second type of region 13 and a third type of region 14. In this case, the first type of region 12 is a target type of region. Alternatively, the target type of region includes at least two types of regions of the semiconductor substrate 11. In this case, in the target type of region, the conductive types of the ring gate transistors formed on different types of regions can be the same or different. For example: Figure 8 As shown, the semiconductor substrate 11 has at least a first type of region 12, a second type of region 13, and a third type of region 14. In this case, the target type region includes the first type of region 12 and the second type of region 13. The conductivity type of the all-around gate transistors corresponding to the first type of region 12 and the second type of region 13 can both be N-type. Alternatively, the conductivity type of the all-around gate transistors corresponding to the first type of region 12 and the second type of region 13 can both be P-type. Alternatively, one of the all-around gate transistors corresponding to the first type of region 12 and the second type of region 13 can be N-type and the other can be P-type.

[0069] The area to be removed is the area of ​​the semiconductor substrate other than the target area. Figure 7 As shown, the semiconductor substrate 11 has a first type of region 12, a second type of region 13 and a third type of region 14. The target type region may be the first type of region 12 of the semiconductor substrate 11. At this time, the type regions to be removed are the second type of region 13 and the third type of region 14. For example: Figure 8 As shown, the semiconductor substrate 11 has at least a first type region 12, a second type region 13 and a third type region 14. The target type region includes the first type region 12 and the second type region 13. At this time, the type region to be removed is the third type region 14.

[0070] It is conceivable that the target class area or the to-be-removed class area under different execution times may correspond to completely different class areas. Figure 7 As shown, the semiconductor substrate 11 has a first type of region 12, a second type of region 13 and a third type of region 14. Wherein, when the number of executions is equal to 1, the target type region is the first type of region 12 of the semiconductor substrate 11. Figure 12 As shown, when the number of executions is equal to 2, the target type region is the second type region 13 of the semiconductor substrate 11 .

[0071] Alternatively, at least some of the target class regions or the regions corresponding to the to-be-removed class regions under different execution times may be the same. Figure 7 As shown, the semiconductor substrate 11 has a first type of region 12, a second type of region 13 and a third type of region 14. Wherein, when the number of executions is equal to 1, the above-mentioned type of regions to be removed can be the second type of region 13 and the third type of region 14 of the semiconductor substrate 11. Figure 12 As shown, when the number of executions is equal to 2, the regions to be removed are the first region 12 and the third region 14 of the semiconductor substrate 11 .

[0072] The material of the mask layer can be set according to actual needs and is not specifically limited here. For example, the mask layer can be a spin-on carbon layer or a bottom anti-reflection layer.

[0073] In actual applications, atomic layer deposition and other processes can be used to form at least the first gate dielectric sublayer located on each type of region on the dipole material layer. A mask layer covering the target type region can then be formed using processes such as spin coating. Under the masking action of this mask layer, dry etching or wet etching can be used to selectively remove the portion of the dipole material layer located on the type region to be removed. Specifically, the process and etchant used for selectively removing the dipole material layer can be determined based on the material of the dipole material layer and are not specifically limited here. For example, when the material of the dipole material layer is La2O3, an HPM solution can be used to selectively remove the portion of the dipole material layer located on the type region to be removed. The mass ratio of HCl, H2O2, and H2O in the HPM solution can be set according to actual needs. For example, the mass ratio of HCl, H2O2, and H2O can be 1:1:5. Finally, the mask layer can be removed using a dry or wet etching process. Specifically, the etching process and etchant used to remove the mask layer can be determined based on the material of the mask layer. For example, if the mask layer is made of spin-on carbon, the mask layer can be removed using a dry etching process and O2 plasma. The above process completes a single cycle. Specifically, the number of times the above operation needs to be performed can be set based on the material and thickness of each dipole layer, the number of regions where the dipole layer needs to be formed, and the actual application scenario.

[0074] It should be understood that in each of the above operations, a dipole material layer is formed only on the first gate dielectric sublayer. In actual application, a covering layer can also be formed on the dipole material layer. The covering layer isolates the dipole material layer from the external environment and the dipole material layer from the mask layer, preventing the dipole material layer from reacting with H2O or the mask layer in the external environment during operation, thereby improving the quality of the manufactured dipole layer and thus improving the yield of the obtained ring-gate transistor. For example, when the ring-gate transistor located on at least one type of area is an NMOS transistor, and the material of the dipole layer corresponding to the NMOS transistor can be La2O3, a covering layer can be formed on the dipole material layer whose material is La2O3. Specifically, the material of the above-mentioned covering layer can be set according to the actual application scenario. For example, when the material of the dipole material layer is La2O3, the material of the covering layer can be Al2O3 or TiN.

[0075] In one example, when a covering layer needs to be formed on the dipole material layer, the above-mentioned step of forming at least a dipole material layer on the first gate dielectric sublayer located on each type of region corresponds to: Figure 6As shown, a dipole material layer 18 and a capping layer 20 are sequentially formed on the first gate dielectric sublayer 17 located on each type of region. Furthermore, the aforementioned step of selectively removing at least the portion of the dipole material layer located on the type region to be removed under the masking action of the mask layer corresponds to the following: selectively removing the portion of the capping layer located on the type region to be removed and the portion of the dipole material layer located on the type region to be removed under the masking action of the mask layer. Furthermore, after removing the mask layer, and before repeating the aforementioned operation until a dipole layer of corresponding thickness and corresponding material is formed on the first gate dielectric sublayer located on at least some of the type regions, the aforementioned method for manufacturing a semiconductor device further includes the step of removing the remaining portion of the capping layer.

[0076] In another example, the above-mentioned forming of a dipole layer of corresponding thickness and corresponding material on the first gate dielectric sublayer located on at least a portion of the sub-region may include the following steps: Figure 16 As shown, a mask layer 19 is formed on the semiconductor substrate 11 to expose the target type area. Figure 17 and Figure 18 As shown, at least a dipole material layer 18 is formed on the first gate dielectric sublayer 17 located on the target class region. The thickness of the dipole material layer 18 is greater than zero and less than or equal to the thickness of the dipole layer to be formed on the target class region. Moreover, the material of the dipole material layer 18 is the same as at least part of the material of the dipole layer to be formed on the target class region. Then, as Figure 19 As shown, the dipole material layer 18 and the mask layer are removed in sequence. Figure 20 and Figure 21 As shown, the above operations are repeated until a dipole layer 21 of corresponding thickness and corresponding material is formed on the first gate dielectric sublayer 17 located on at least a portion of the sub-region.

[0077] Specifically, the material and thickness of the dipole material layer, and the material of the mask layer in this case can be referred to above and will not be described in detail here.

[0078] As for the target type region in this case, the target type region can be any type of region on the semiconductor substrate where a corresponding dipole material layer is to be formed. Figure 16 As shown, the semiconductor substrate 11 has at least a first type of region 12, a second type of region 13 and a third type of region 14. In this case, the first type of region 12 is a target type of region. Alternatively, the target type of region includes at least two types of regions of the semiconductor substrate 11. In the target type of region, the conductive types of the ring gate transistors formed on different types of regions can be the same or different. For example: Figure 18As shown, the semiconductor substrate 11 has at least a first type of region 12, a second type of region 13, and a third type of region 14. In this case, the target type region includes the first type of region 12 and the second type of region 13. The conductivity type of the all-around gate transistors corresponding to the first type of region 12 and the second type of region 13 can both be N-type. Alternatively, the conductivity type of the all-around gate transistors corresponding to the first type of region 12 and the second type of region 13 can both be P-type. Alternatively, one of the all-around gate transistors corresponding to the first type of region 12 and the second type of region 13 can be N-type and the other can be P-type.

[0079] It is conceivable that, in this case, the target class region may correspond to completely different class regions under different execution times. For example, the semiconductor substrate has a first class region, a second class region, and a third class region. Among them, when the execution time is equal to 1, the target class region is the first class region of the semiconductor substrate. And when the execution time is equal to 2, the target class region is the second class region of the semiconductor substrate. Alternatively, at least some of the class regions corresponding to the target class region under different execution times may be the same. For example: Figure 16 As shown, the semiconductor substrate 11 has a first type of region 12, a second type of region 13 and a third type of region 14. Wherein, when the number of executions is equal to 1, the target type region may be the first type of region 12 of the semiconductor substrate 11. Figure 20 As shown, when the number of executions is equal to 2, the target type regions are the first type region 12 and the second type region 13 of the semiconductor substrate 11 .

[0080] It should be noted that in the first case of forming a dipole layer described above, after forming the corresponding dipole material layer and mask layer, the area covered by the mask layer is the target type area, and the area exposed outside the mask layer is the to-be-removed type area, so that the mask layer protects the dipole material layer formed on the target type area. In the second case of forming a dipole layer, in each execution, a mask layer is formed on the corresponding area before forming the corresponding dipole material layer. Among them, the area exposed outside the mask layer is the target type area.

[0081] In actual application, chemical vapor deposition and etching processes can be used to form a mask layer for exposing the target class area. Next, atomic layer deposition and other processes can be used to form a dipole material layer on the first gate dielectric sublayer located on the target class area and on the mask layer. Then, the dipole material layer located on the mask layer is selectively removed, and the mask layer is removed. Among them, the etching process and etchant used to remove the dipole material layer and the mask layer can be referred to the above and will not be repeated here. A cycle is achieved through the above process. Specifically, how many times the above operations need to be performed can be set according to the material and thickness of each dipole layer, the number of types of areas where the dipole layer needs to be formed, and the actual application scenario.

[0082] like Figure 22 As shown, the semiconductor substrate 11 formed with the dipole layer is annealed so that different types of regions correspond to different threshold control parameters; and the dipole layer is removed.

[0083] Specifically, the time and temperature of the annealing treatment can be set according to the first gate dielectric sublayer and the actual application scenario, and are not specifically limited here. Exemplarily, the time of the annealing treatment can be 10s to 60s, and the temperature of the annealing treatment can be 600°C to 900°C. For example, the time of the annealing treatment can be 10s, 20s, 30s, 40s, 50s or 60s, and the temperature of the annealing treatment can be 600°C, 650°C, 700°C, 750°C, 800°C, 850°C or 900°C.

[0084] In addition, after the annealing treatment, the etching process and etchant used to remove the dipole layer can refer to the etching process and etchant used to remove the dipole material layer described above, and will not be repeated here.

[0085] like Figure 23 As shown, the second gate dielectric sublayer 22 and gate 23 of the corresponding all-around transistor are sequentially formed on the first gate dielectric sublayer 17 located on each type of region. The gate dielectric layer included in each all-around transistor includes the first gate dielectric sublayer 17 and the second gate dielectric sublayer 22 located on the corresponding type of region.

[0086] Specifically, the thickness of the second gate dielectric sublayer formed on each type of region can be determined based on the thickness of the gate dielectric layer included in the corresponding all-around gate transistor and the thickness of the first gate dielectric sublayer. Furthermore, the material of the second gate dielectric sublayer located on each type of region can be set based on actual needs and is not specifically limited here.

[0087] The second gate dielectric sublayers located on regions of different types, and the different second gate dielectric sublayers located on regions of the same type, may be made of the same or different materials and / or thicknesses. Specifically, when the second gate dielectric sublayers located on regions of different types have the same material and thickness, multiple deposition and etching processes are not required; the corresponding second gate dielectric sublayers can be directly formed on the first gate dielectric sublayer located on each type of region on the semiconductor substrate, thereby simplifying the manufacturing process of the semiconductor device.

[0088] In addition, if Figure 23 As shown, the materials of the first gate dielectric sublayer 17 and the second gate dielectric sublayer 22 included in the same all-around gate transistor can be the same or different. Since different insulating materials have different dielectric constants, when the materials of the first gate dielectric sublayer 17 and the second gate dielectric sublayer 22 included in the same all-around gate transistor are different, the k value of the gate dielectric layer included in the all-around gate transistor can be adjusted by adjusting the material of the second gate dielectric sublayer 22 according to different actual application scenarios. This helps prevent the gate 23 included in the all-around gate transistor from leaking into the semiconductor substrate 11, ensuring that the all-around gate transistor has good electrical performance.

[0089] In actual applications, at least one process such as atomic layer deposition can be used to sequentially form the second gate dielectric sublayer and the gate. When the second gate dielectric sublayers located in different types of regions have different materials and / or thicknesses, the process of forming different second gate dielectric sublayers in each type of region can refer to the process of forming the dipole layer described above and will not be repeated here.

[0090] As can be seen from the above manufacturing process, in the manufacturing method of the semiconductor device provided by the embodiment of the present invention, a channel including a corresponding all-around gate transistor and a first gate dielectric sublayer surrounding the outer periphery of the channel are formed on each type of region of the semiconductor substrate. In addition, a dipole layer of corresponding thickness and corresponding material is formed on the first gate dielectric sublayer located on at least part of the type of region. Based on this, after annealing the semiconductor substrate with the above-mentioned dipole layer, different types of regions can correspond to different threshold control parameters, so the all-around gate transistors located in different types of regions have different threshold voltages. In addition, after removing the dipole layer, the second gate dielectric sublayer and gate included in the corresponding all-around gate transistor are sequentially formed on the first gate dielectric sublayer located on each type of region. In addition, the gate dielectric layer included in each all-around gate transistor includes the first gate dielectric sublayer and the second gate dielectric sublayer located on the corresponding type of region. Based on this, it can be understood that before the dipole layer is formed on at least part of the type of region, only the first gate dielectric sublayer with a thickness less than the thickness of the entire gate dielectric layer is formed on the outer periphery of the channel of each type of region. In this case, during the actual manufacturing process, the purpose of the annealing treatment is to push the key elements in the dipole layer formed on the first gate dielectric sublayer to the interface between the channel and the gate dielectric layer, and the annealing treatment time and temperature are inversely proportional to the thickness of the corresponding gate dielectric layer or gate dielectric sublayer located between the interface and the dipole layer. Therefore, compared with forming the dipole layer on the entire gate dielectric layer with a larger thickness, the manufacturing method provided by the embodiment of the present invention forms the dipole layer on the first gate dielectric sublayer with a smaller thickness. In this case, because the distance between the dipole layer and the corresponding channel is relatively close, the key elements in the dipole layer can be moved to the interface between the channel and the gate dielectric layer without performing a high temperature and long time annealing treatment, thereby reducing the thermal load of the annealing treatment, facilitating the production of semiconductor devices, and improving the operating performance of the manufactured semiconductor devices. In addition, when using the manufacturing method provided by the embodiment of the present invention to manufacture semiconductor devices located in the second layer or higher layers of an integrated circuit, it can also prevent the high temperature annealing treatment from affecting the underlying semiconductor devices, thereby improving the operating performance of the integrated circuit. Furthermore, when the channel material is a germanium-containing semiconductor material, it can also solve the poor compatibility problem in the existing technology, such as the change in carrier transmission performance in the channel material containing germanium caused by the advancement of key elements through high-temperature annealing treatment, thereby improving the conductivity of the ring-gate transistor.

[0091] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0092] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: providing a semiconductor substrate; The semiconductor substrate has at least two types of regions along a direction parallel to the surface of the semiconductor substrate; each type of region has a channel of a corresponding all-around gate transistor and a first gate dielectric sublayer surrounding the outer periphery of the channel; forming a dipole layer of corresponding thickness and corresponding material on the first gate dielectric sublayer located on at least a portion of the region; Annealing the semiconductor substrate on which the dipole layer is formed, so that different types of regions correspond to different threshold control parameters; and removing the dipole layer; The second gate dielectric sublayer and gate of the corresponding ring-gate transistor are formed in sequence on the first gate dielectric sublayer located on each type of the region; the gate dielectric layer included in each ring-gate transistor includes the first gate dielectric sublayer and the second gate dielectric sublayer located on the corresponding type of the region.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The first gate dielectric sublayer and the second gate dielectric sublayer included in the same all-around gate transistor are made of different materials.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The thickness of the first gate dielectric sublayer is 0.3 nm to 1 nm.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The annealing treatment time is 10s to 60s, and the annealing treatment temperature is 600°C to 900°C.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The thickness and / or material of the dipole layers located on different types of the regions are different.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the channel includes silicon germanium or germanium.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The material and thickness of the first gate dielectric sublayer located on different types of regions are the same; and / or, The second gate dielectric sublayers located on the different types of regions have the same material and thickness.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The forming of a dipole layer of corresponding thickness and corresponding material on the first gate dielectric sublayer located on at least a portion of the region includes: forming at least a dipole material layer on the first gate dielectric sublayer located on each type of the region; the thickness of the dipole material layer is greater than zero and less than or equal to the thickness of the dipole layer to be formed on the target type region; the material of the dipole material layer is the same as at least a portion of the material of the dipole layer to be formed on the target type region; forming a mask layer on the semiconductor substrate to expose a region to be removed; the region to be removed is a region of the semiconductor substrate other than the target region; Under the masking action of the mask layer, selectively removing at least the portion of the dipole material layer located on the to-be-removed region; removing the mask layer; The above operation is repeated until the dipole layer with a corresponding thickness and a corresponding material is formed on the first gate dielectric sublayer located on at least a portion of the region.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The forming of at least a dipole material layer on the first gate dielectric sublayer located on each type of the region comprises: sequentially forming the dipole material layer and the cover layer on the first gate dielectric sublayer located on each type of the region; The selectively removing at least the portion of the dipole material layer located on the to-be-removed region under the masking action of the mask layer comprises: sequentially selectively removing the portion of the cover layer located on the to-be-removed region and the portion of the dipole material layer located on the to-be-removed region under the masking action of the mask layer; After removing the mask layer, repeating the above operation until the dipole layer of corresponding thickness and corresponding material is formed on the first gate dielectric sublayer located on at least part of the region, the manufacturing method of the semiconductor device further includes: removing the remaining part of the covering layer.

10. The method for manufacturing a semiconductor device according to claim 1, wherein: The forming of a dipole layer of corresponding thickness and corresponding material on the first gate dielectric sublayer located on at least a portion of the region includes: forming a mask layer on the semiconductor substrate to expose a target region; forming at least a dipole material layer on the first gate dielectric sublayer located on the target region; the thickness of the dipole material layer is greater than zero and less than or equal to the thickness of the dipole layer to be formed on the target region; and the material of the dipole material layer is the same as at least a portion of the material of the dipole layer to be formed on the target region; removing the dipole material layer and the mask layer located on the mask layer in sequence; The above operation is repeated until the dipole layer with a corresponding thickness and a corresponding material is formed on the first gate dielectric sublayer located on at least a portion of the region.

11. The method for manufacturing a semiconductor device according to claim 8 or 10, wherein: The target type region is any type of region possessed by the semiconductor substrate; or The target type region includes at least two types of regions of the semiconductor substrate; in the target type region, the conductive types of the gate-all-around transistors formed on different types of regions are the same or different.

12. The method for manufacturing a semiconductor device according to any one of claims 1 to 10, wherein: An interface layer is also formed on each type of the region; each interface layer is formed between the corresponding channel and the first gate dielectric sublayer.

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