Shielded gate trench field effect transistor structure and method of making same

Abstract

This invention provides a shielded gate trench field-effect transistor (SFET) structure and its fabrication method, comprising the following steps: providing a semiconductor layer; forming a first trench unit and a second trench unit arranged alternately in a horizontal direction in the semiconductor layer, wherein the first and second trench units each include at least one first trench and at least one second trench; forming a first dielectric layer, a first conductive layer, an isolation layer, a second dielectric layer, and a second conductive layer in the first and second trenches; forming a source and a gate on the semiconductor layer; and electrically connecting the first conductive layer and the second conductive layer in the first and second trenches to the source and the gate, respectively. The shielded gate trench field-effect transistor structure of this invention, while maintaining the same physical structure, changes the internal electrical interconnect structure of the device, improves the thermal stability of the device, thereby enhancing the SOA performance of the device and expanding the application prospects of the shielded gate trench field-effect transistor structure in load switching, hot-plugging, and other technical fields.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor devices and relates to a shielded gate trench field-effect transistor structure and its fabrication method. Background Technology

[0002] Shielded Gate Trench MOSFETs (SGT MOSFETs) are an advanced power MOSFET technology. By introducing a shielded gate electrode, they reduce the gate-drain overlap area, thereby reducing the gate-drain capacitance, which improves switching speed, reduces dynamic losses, and ultimately enhances system efficiency. Please refer to [link to relevant documentation]. Figure 1 The diagram shows a cross-sectional view of a typical SGT MOSFET device cell region. The upper polysilicon layer is the gate electrode (labeled "G"), and the lower polysilicon layer is the source electrode (labeled "S"). The source electrode is shorted to the source electrode.

[0003] Currently, power MOSFETs are widely used in load switches and hot-swappable circuits due to their low on-resistance, simple gate drive circuitry, and linear operating area characteristics, which effectively suppress inrush current. In some applications, when the power supply is suddenly disconnected from its load, the large current swing on the parasitic inductance of the circuit generates a huge voltage spike, which can adversely affect the electronic components in the circuit. MOSFETs can isolate the input power supply from other circuits, mitigating the serious consequences of destructive inrush currents. In such applications, one of the key considerations when selecting a MOSFET is its safe operating area (SOA) performance. For SGT MOSFETs, which are currently the mainstream low-to-medium voltage MOSFETs, the high cell density and small pitch between cells can lead to thermal imbalances within the device, easily causing localized heat concentration and ultimately damaging the device, thus limiting its SOA performance.

[0004] Therefore, how to provide a shielded gate trench field-effect transistor structure and its fabrication method to optimize the thermal concentration effect of the reduced cell, improve the SOA performance of SGT MOSFET, and enhance its applicability in scenarios such as load switching and hot-plugging has become an important technical problem that needs to be solved by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a shielded gate trench field-effect transistor structure and its fabrication method, so as to solve the problem that the thermal concentration effect of the cell in the prior art leads to poor thermal stability of the device and limits the SOA performance of the device.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating a shielded gate trench field-effect transistor structure, comprising the following steps:

[0008] Provide a semiconductor layer;

[0009] A first trench unit and a second trench unit are formed in the semiconductor layer, which are spaced apart and alternately arranged in the horizontal direction. The first trench unit includes at least one first trench, and the second trench unit includes at least one second trench. Both the first trench and the second trench open from the top surface of the semiconductor layer and extend downward.

[0010] A first dielectric layer, a first conductive layer, an isolation layer, a second dielectric layer, and a second conductive layer are formed in the first trench and the second trench. The second conductive layer is located above the first conductive layer and is isolated from the first conductive layer by the isolation layer. The first dielectric layer is located between the inner wall of the trench and the first conductive layer, and the second dielectric layer is located between the inner wall of the trench and the second conductive layer.

[0011] A source and a gate are formed on the semiconductor layer, and the first conductive layer and the second conductive layer in the first trench are electrically connected to the source, and the first conductive layer and the second conductive layer in the second trench are electrically connected to the gate.

[0012] Optionally, the first trench unit includes one first trench, and the second trench unit includes one second trench; or, the first trench unit includes one first trench, and the second trench unit includes two second trenches.

[0013] Optionally, after forming the second conductive layer, the method further includes the following steps:

[0014] A body region is formed on the upper surface of the semiconductor layer;

[0015] A source region is formed on the upper surface layer of the body region;

[0016] An interlayer dielectric layer is formed above the semiconductor layer, and the interlayer dielectric layer covers the second conductive layer and the source region;

[0017] A source contact hole is formed in the interlayer dielectric layer, the source contact hole penetrating the interlayer dielectric layer, the source region and extending into the body region.

[0018] Optionally, both the first trench and the second trench have a first conductive layer lead-out area, in which a first conductive layer is formed; both the first trench and the second trench have a second conductive layer lead-out area, in which a first conductive layer and a second conductive layer are formed.

[0019] Optionally, the following steps are also included:

[0020] A first contact hole, a second contact hole, a third contact hole, and a fourth contact hole are formed. The first contact hole and the third contact hole are spaced apart in the extension direction of the first trench, and the second contact hole and the fourth contact hole are spaced apart in the extension direction of the second trench. The first contact hole is located in the first conductive layer lead-out area of ​​the first trench and exposes the first conductive layer at the bottom. The second contact hole is located in the first conductive layer lead-out area of ​​the second trench and exposes the first conductive layer at the bottom. The third contact hole is located in the second conductive layer lead-out area of ​​the first trench and exposes the second conductive layer at the bottom. The fourth contact hole is located in the second conductive layer lead-out area of ​​the second trench and exposes the second conductive layer at the bottom.

[0021] A metal layer is formed on the interlayer dielectric layer, and the metal layer is patterned to obtain the source and the gate. The source is further filled with the source contact hole, the first contact hole and the third contact hole, and the gate is further filled with the second contact hole and the fourth contact hole. The source and the gate are electrically isolated.

[0022] Optionally, the top of the first conductive layer is embedded in the second conductive layer.

[0023] Optionally, the materials of the first conductive layer and the second conductive layer both include polycrystalline silicon, and the materials of the first dielectric layer, the isolation layer, the second dielectric layer and the interlayer dielectric layer all include silicon dioxide.

[0024] The present invention also provides a shielded gate trench field-effect transistor structure, comprising:

[0025] Semiconductor layer;

[0026] The first trench unit and the second trench unit are located in the semiconductor layer and are spaced apart and alternately arranged in the horizontal direction. The first trench unit includes at least one first trench, and the second trench unit includes at least one second trench. Both the first trench and the second trench open from the top surface of the semiconductor layer and extend downward.

[0027] A first dielectric layer, a first conductive layer, an isolation layer, a second dielectric layer, and a second conductive layer are located in the first trench and the second trench, respectively. The second conductive layer is located above the first conductive layer and is isolated from the first conductive layer by the isolation layer. The first dielectric layer is located between the inner wall of the trench and the first conductive layer, and the second dielectric layer is located between the inner wall of the trench and the second conductive layer.

[0028] The source and gate are located on the semiconductor layer. The first conductive layer and the second conductive layer in the first trench are electrically connected to the source, and the first conductive layer and the second conductive layer in the second trench are electrically connected to the gate.

[0029] Optionally, the transistor structure further includes:

[0030] The body region is located on the upper surface of the semiconductor layer;

[0031] The source region is located on the upper surface layer of the body region;

[0032] An interlayer dielectric layer is located above the semiconductor layer, and the interlayer dielectric layer covers the second conductive layer and the source region;

[0033] The source contact hole is located in the interlayer dielectric layer and extends through the interlayer dielectric layer, the source region and into the body region.

[0034] Optionally, the transistor structure further includes a first contact hole, a second contact hole, a third contact hole, and a fourth contact hole. The first contact hole and the third contact hole are spaced apart in the extension direction of the first trench, and the second contact hole and the fourth contact hole are spaced apart in the extension direction of the second trench. The bottom of the first contact hole exposes the first conductive layer of the first trench, the bottom of the second contact hole exposes the first conductive layer of the second trench, the bottom of the third contact hole exposes the second conductive layer of the first trench, and the bottom of the fourth contact hole exposes the second conductive layer of the second trench.

[0035] As described above, the shielded gate trench field-effect transistor structure and its fabrication method of the present invention, while maintaining the same physical structure as the existing SGT MOSFET, change the internal electrical interconnect structure of the device to improve the thermal stability of the device, thereby enhancing the SOA performance of the device and expanding the application prospects of SGT MOSFET in load switching, hot-plugging and other technical fields. Attached Figure Description

[0036] Figure 1 The diagram shows a cross-sectional view of a typical shielded gate trench field-effect transistor structure.

[0037] Figure 2 The diagram shows the steps of the method for fabricating the shielded gate trench field-effect transistor structure of the present invention.

[0038] Figure 3 The diagram shown is a cross-sectional view of the structure obtained after performing step S2 in the fabrication method of the shielded gate trench field-effect transistor structure of the present invention.

[0039] Figure 4 The diagram shown is a cross-sectional view of the structure obtained after performing step S3 in the fabrication method of the shielded gate trench field-effect transistor structure of the present invention.

[0040] Figure 5 The diagram shown is a cross-sectional view of the structure obtained after forming the source contact hole in the fabrication method of the shielded gate trench field-effect transistor structure of the present invention.

[0041] Figure 6 The diagram shows a partial cross-sectional view of the structure obtained after performing step S4 in the fabrication method of the shielded gate trench field-effect transistor structure of the present invention.

[0042] Figure 7 The diagram shown is a top view of the structure obtained after performing step S4 in the fabrication method of the shielded gate trench field-effect transistor structure of the present invention.

[0043] Component designation explanation

[0044]

[0045] 11 Interlayer dielectric layer

[0046] 12 Source contact holes

[0047] 13 Metal Layers

[0048] 131 Source

[0049] 132 gate

[0050] 14 First contact hole

[0051] 15 Second contact hole

[0052] 16 Third contact hole

[0053] 17 Fourth contact hole

[0054] Steps S1 to S4 Detailed Implementation

[0055] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0056] Please see Figures 2 to 7 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0057] Example 1

[0058] This invention provides a method for fabricating a shielded gate trench field-effect transistor structure. Since the shielded gate trench field-effect transistor structure can be an N-type device or a P-type device, this embodiment uses an N-type device as an example for illustration. Please refer to [link to relevant documentation]. Figure 2 The flowchart shows the steps involved in fabricating this transistor structure, including the following steps:

[0059] S1: Provides a semiconductor layer;

[0060] S2: A first trench unit and a second trench unit are formed in the semiconductor layer, which are spaced apart and alternately arranged in the horizontal direction. The first trench unit includes at least one first trench, and the second trench unit includes at least one second trench. Both the first trench and the second trench open from the top surface of the semiconductor layer and extend downward.

[0061] S3: A first dielectric layer, a first conductive layer, an isolation layer, a second dielectric layer, and a second conductive layer are formed in the first trench and the second trench. The second conductive layer is located above the first conductive layer and is isolated from the first conductive layer by the isolation layer. The first dielectric layer is located between the inner wall of the trench and the first conductive layer, and the second dielectric layer is located between the inner wall of the trench and the second conductive layer.

[0062] S4: A source and a gate are formed on the semiconductor layer, and the first conductive layer and the second conductive layer in the first trench are electrically connected to the source, and the first conductive layer and the second conductive layer in the second trench are electrically connected to the gate.

[0063] Please see Figure 3 In step S1, a semiconductor layer is provided. The semiconductor layer includes a substrate (not shown in the figure) and an epitaxial layer 1 located on the upper surface of the substrate. The substrate can be an N++ type doped silicon substrate, a germanium silicon substrate, a silicon carbide substrate, etc. The epitaxial layer 1 includes, but is not limited to, an N-type single crystal silicon epitaxial layer.

[0064] In step S2, a first trench unit 2 and a second trench unit 3 are formed in the semiconductor layer, which are spaced apart and alternately arranged in the horizontal direction. The first trench unit 2 includes at least one first trench 21, and the second trench unit 3 includes at least one second trench 31. Both the first trench 21 and the second trench 31 open from the top surface of the semiconductor layer and extend downward.

[0065] As an example, a photoresist layer is first formed on the upper surface of the semiconductor layer, and the photoresist layer is patterned to form an etching window. The semiconductor layer is then etched based on the etching window to form the first trench unit 2 and the second trench unit 3; or the first trench unit 2 and the second trench unit 3 are obtained by etching with a mask.

[0066] As an example, the first trench unit 2 includes one first trench 21, and the second trench unit 3 includes one second trench 31; or, the first trench unit 2 includes one first trench 21, and the second trench unit 3 includes two second trenches 31. That is, the first trench 21 and the second trench 31 can be arranged alternately or not alternately. For example, they can be arranged in a repeating unit with a "first trench-second trench" structure, or in a repeating unit with a "first trench-second trench-second trench" structure. They can be adjusted according to the actual situation to achieve different technical effects. In this embodiment, the first trench 21 and the second trench 31 are arranged alternately, that is, the first trench unit 2 includes one first trench 21, and the second trench unit 3 includes one second trench 31.

[0067] Please see Figure 4In step S3, a first dielectric layer 4, a first conductive layer 5, an isolation layer 6, a second dielectric layer 7, and a second conductive layer 8 are formed in the first trench 21 and the second trench 31. The second conductive layer 8 is located above the first conductive layer 5 and is isolated from the first conductive layer 5 by the isolation layer 6. The first dielectric layer 4 is located between the inner wall of the trench and the first conductive layer 5, and the second dielectric layer 7 is located between the inner wall of the trench and the second conductive layer 8. The first conductive layer and the second conductive layer in the first trench 21 both serve as shielding electrodes, and the first conductive layer and the second conductive layer in the second trench 31 both serve as gate electrodes.

[0068] As an example, the methods for forming the first dielectric layer 4, the first conductive layer 5, the second dielectric layer 7, and the second conductive layer 8 include chemical vapor deposition or other suitable methods, and the methods for forming the isolation layer 6 include chemical vapor deposition, thermal oxidation, or other suitable methods. Depending on the manufacturing process, the second dielectric layer 7 and the isolation layer 6 can be configured as a whole or as two independent structures. In this embodiment, the second dielectric layer 7 and the isolation layer 6 are configured as two independent structures.

[0069] As an example, the top end of the first conductive layer 5 is embedded in the second conductive layer 8, or the top end of the first conductive layer 5 is located below the bottom end of the second conductive layer 8, and the adjustment can be made according to the actual situation.

[0070] As an example, both the first trench 21 and the second trench 31 have a first conductive layer lead-out area, in which a first conductive layer 5 is formed; both the first trench 21 and the second trench 31 have a second conductive layer lead-out area, in which a first conductive layer 5 and a second conductive layer 8 are formed.

[0071] Specifically, after forming the first trench 21 (second trench 31), the first trench 21 (second trench 31) is defined in the extension direction as a first conductive layer lead-out area and a second conductive layer lead-out area. A first conductive layer 5 is formed in both the first conductive layer lead-out area and the second conductive layer lead-out area. Subsequently, a second conductive layer 8 is formed only above the first conductive layer 5 in the second conductive layer lead-out area. No second conductive layer 8 is formed above the first conductive layer 5 in the first conductive layer lead-out area. Ultimately, only the first conductive layer 5 is formed in the first conductive layer lead-out area, and no second conductive layer 8 is formed. Both the first conductive layer 5 and the second conductive layer 8 are formed in the second conductive layer lead-out area. Subsequently, the first conductive layer 5 and the second conductive layer 8 are electrically led out by forming contact holes and filling the contact holes with conductive material. Of course, the electrical lead-out of the first conductive layer 5 and the second conductive layer 8 is not limited to the above method, and may also include other suitable methods. For example, the first conductive layer 5 and the second conductive layer 8 are formed in both the first conductive layer lead-out area and the second conductive layer lead-out area, and then contact holes of different depths are formed to connect to the first conductive layer 5 and the second conductive layer 8 respectively. An insulating layer is formed at an appropriate position of the contact hole connecting the first conductive layer 5 to electrically isolate it from the second conductive layer 8.

[0072] As an example, after forming the second conductive layer 8, a chemical mechanical polishing step is also included to planarize the upper surface of the second conductive layer 8, thereby improving the interface state of the upper surface of the second conductive layer 8, enhancing the bonding between the subsequently formed structural layer and the second conductive layer 8, and reducing resistance.

[0073] For example, please refer to Figure 5 After forming the second conductive layer 8, the process further includes the following steps:

[0074] A body region 9 is formed on the upper surface of the semiconductor layer;

[0075] A source region 10 is formed on the upper surface layer of the body region 9;

[0076] An interlayer dielectric layer 11 is formed above the semiconductor layer, and the interlayer dielectric layer 11 covers the second conductive layer 8 and the source region 10.

[0077] A source contact hole 12 is formed in the interlayer dielectric layer 11, and the source contact hole 12 penetrates the interlayer dielectric layer 11, the source region 10 and extends into the body region 9.

[0078] As an example, the method for forming the body region 9 and the source region 10 includes ion implantation, the method for forming the interlayer dielectric layer 11 includes chemical vapor deposition or other suitable methods, and the method for forming the source contact hole 12 includes dry etching.

[0079] Please see Figure 6 In step S4, a source 131 and a gate 132 are formed on the semiconductor layer, and the first conductive layer and the second conductive layer in the first trench 21 are electrically connected to the source 131, and the first conductive layer and the second conductive layer in the second trench 31 are electrically connected to the gate 132.

[0080] For example, please refer to Figure 7 After forming the interlayer dielectric layer 11, the method further includes the following steps:

[0081] A first contact hole 14, a second contact hole 15, a third contact hole 16, and a fourth contact hole 17 are formed. The first contact hole 14 and the third contact hole 16 are spaced apart in the extension direction of the first trench 21. The second contact hole 15 and the fourth contact hole 17 are spaced apart in the extension direction of the second trench 31. The first contact hole 14 is located in the first conductive layer lead-out area of ​​the first trench 21 and exposes the first conductive layer 5 at the bottom. The second contact hole 15 is located in the first conductive layer lead-out area of ​​the second trench 31 and exposes the first conductive layer 5 at the bottom. The third contact hole 16 is located in the second conductive layer lead-out area of ​​the first trench 21 and exposes the second conductive layer 8 at the bottom. The fourth contact hole 17 is located in the second conductive layer lead-out area of ​​the second trench 31 and exposes the second conductive layer 8 at the bottom.

[0082] A metal layer 13 is formed on the interlayer dielectric layer 11, and the metal layer 13 is patterned to obtain the source 131 and the gate 132. The source 131 is also filled with the source contact hole 12, the first contact hole 14 and the third contact hole 16, and the gate 132 is also filled with the second contact hole 15 and the fourth contact hole 17. The source 131 and the gate 132 are electrically isolated.

[0083] As an example, the materials of the first conductive layer 5 and the second conductive layer 8 both include polycrystalline silicon, and the materials of the first dielectric layer 4, the isolation layer 6, the second dielectric layer 7 and the interlayer dielectric layer 11 all include silicon dioxide. Of course, the materials of the first conductive layer 5, the second conductive layer 8, the first dielectric layer 4, the isolation layer 6, the second dielectric layer 7 and the interlayer dielectric layer 11 are not limited to the above materials, and may also be other suitable materials.

[0084] As an example, the method for forming the metal layer 13 includes magnetron sputtering, which can produce a relatively ideal metal layer 13.

[0085] The shielded gate trench field-effect transistor structure fabricated by the method of this embodiment has the same physical structure as the existing typical SGT MOSFET structure, but there are significant differences in electrical structure. It can reduce the probability of local heat concentration effect in device cells, effectively reduce the thermal instability of the device, improve the SOA performance of the device, and thus expand the application prospects of SGT MOSFET devices in load switching and hot-plugging fields.

[0086] Example 2

[0087] This embodiment provides a shielded gate trench field-effect transistor structure. The shielded gate trench field-effect transistor can be fabricated based on the fabrication method of Embodiment 1 or other suitable methods. The description of the relevant structural layers in Embodiment 1 is fully applicable to this embodiment.

[0088] Please see Figure 6 The diagram shows a cross-sectional view of the shielded gate trench field-effect transistor structure, including a semiconductor layer, a first trench unit 2, a second trench unit 3, a first dielectric layer 4, a first conductive layer 5, an isolation layer 6, a second dielectric layer 7, a second conductive layer 8, a source 131, and a gate 132.

[0089] Specifically, the first trench unit 2 and the second trench unit 3 are both located in the semiconductor layer and are spaced apart and alternately arranged in the horizontal direction. The first trench unit 2 includes at least one first trench 21, and the second trench unit 3 includes at least one second trench 31. The first trench 21 and the second trench 31 both open from the top surface of the semiconductor layer and extend downward.

[0090] As an example, the arrangement of the first groove 21 and the second groove 31 can be alternating or not, and can be adjusted according to the actual situation.

[0091] Specifically, the first dielectric layer 4, the first conductive layer 5, the isolation layer 6, the second dielectric layer 7, and the second conductive layer 8 are all located in the first trench 21 and the second trench 31. The second conductive layer 8 is located above the first conductive layer 5 and is isolated from the first conductive layer 5 by the isolation layer 6. The first dielectric layer 4 is located between the inner wall of the trench and the first conductive layer 5, and the second dielectric layer 7 is located between the inner wall of the trench and the second conductive layer 8.

[0092] Specifically, both the source 131 and the gate 132 are located on the semiconductor layer. The first and second conductive layers in the first trench 21 are electrically connected to the source 131, and the first and second conductive layers in the second trench 31 are electrically connected to the gate 132. That is, the source 131 is electrically connected to the first and second conductive layers in the first trench 21, and the gate 132 is electrically connected to the first and second conductive layers in the second trench 31. This special electrical interconnect structure can be implemented through a special layout design. The electrical connection described above allows both the first and second conductive layers in the first trench 21 to function as shielding electrodes, and both the first and second conductive layers in the second trench 31 to function as gate electrodes. This results in a "Source-Source" electrical structure within the first trench 21 and a "Gate-Gate" electrical structure within the second trench 31. In contrast, in the existing structure, both the first conductive layers in the first trench 21 and the second conductive layers in the second trench 31 function as shielding electrodes, while both the second conductive layers in the first trench 21 and the second conductive layers in the second trench 31 function as gate electrodes, resulting in a "Gate-Source" electrical structure within both trenches. This change in electrical structure reduces the heat concentration effect in the device cells, improving the device's thermal stability and SOA performance.

[0093] As an example, the shielded gate trench field-effect transistor structure further includes a body region 9, a source region 10, an interlayer dielectric layer 11, and a source contact hole 12. The body region 9 is located on the upper surface of the semiconductor layer, the source region 10 is located on the upper surface of the body region 9, the interlayer dielectric layer 11 is located above the semiconductor layer, and also covers the second conductive layer 8 and the source region 10. The source contact hole 12 is located in the interlayer dielectric layer 11, and the source contact hole 12 penetrates the interlayer dielectric layer 11, the source region 10, and extends into the body region 9.

[0094] For example, please refer to Figure 7The transistor structure further includes a first contact hole 14, a second contact hole 15, a third contact hole 16, and a fourth contact hole 17. The first contact hole 14 and the third contact hole 16 are spaced apart in the extension direction of the first trench 21, and the second contact hole 15 and the fourth contact hole 17 are spaced apart in the extension direction of the second trench 31. The bottom of the first contact hole 14 exposes the first conductive layer 5 of the first trench 21, the bottom of the second contact hole 15 exposes the first conductive layer 5 of the second trench 31, the bottom of the third contact hole 16 exposes the second conductive layer 8 of the first trench 21, and the bottom of the fourth contact hole 17 exposes the second conductive layer 8 of the second trench 31.

[0095] The shielded gate trench field-effect transistor structure of this embodiment, while maintaining the same physical structure as the existing SGT MOSFET, changes the internal electrical interconnect structure of the device to improve the thermal stability of the device, thereby enhancing the SOA performance of the device and expanding the application prospects of SGT MOSFET in load switching, hot-plugging and other technical fields.

[0096] In summary, the shielded gate trench field-effect transistor structure and its fabrication method of the present invention, while maintaining the same physical structure as existing SGT MOSFETs, significantly reduce power consumption in thermally unstable regions compared to existing structures by altering the internal electrical interconnect structure through layout design. This reduces the device's operating temperature rise, enhances its thermal stability, improves its SOA performance, and expands the application prospects of SGT MOSFETs in load switching, hot-swappable, and other technical fields. Therefore, the present invention effectively overcomes the various shortcomings of existing technologies and possesses high industrial applicability.

[0097] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a shielded gate trench field-effect transistor structure, characterized in that, Includes the following steps: Provide a semiconductor layer; A first trench unit and a second trench unit are formed in the semiconductor layer, which are spaced apart and alternately arranged in the horizontal direction. The first trench unit includes at least one first trench, and the second trench unit includes at least one second trench. Both the first trench and the second trench open from the top surface of the semiconductor layer and extend downward. A first dielectric layer, a first conductive layer, an isolation layer, a second dielectric layer, and a second conductive layer are formed in the first trench and the second trench. The second conductive layer is located above the first conductive layer and is isolated from the first conductive layer by the isolation layer. The first dielectric layer is located between the inner wall of the trench and the first conductive layer, and the second dielectric layer is located between the inner wall of the trench and the second conductive layer. A source and a gate are formed on the semiconductor layer, and the first conductive layer and the second conductive layer in the first trench are electrically connected to the source, and the first conductive layer and the second conductive layer in the second trench are electrically connected to the gate.

2. The method for fabricating a shielded gate trench field-effect transistor structure according to claim 1, characterized in that: The first trench unit includes one first trench, and the second trench unit includes one second trench; or, the first trench unit includes one first trench, and the second trench unit includes two second trenches.

3. The method for fabricating a shielded gate trench field-effect transistor structure according to claim 1, characterized in that, After forming the second conductive layer, the method further includes the following steps: A body region is formed on the upper surface of the semiconductor layer; A source region is formed on the upper surface layer of the body region; An interlayer dielectric layer is formed above the semiconductor layer, and the interlayer dielectric layer covers the second conductive layer and the source region; A source contact hole is formed in the interlayer dielectric layer, the source contact hole penetrating the interlayer dielectric layer, the source region and extending into the body region.

4. The method for fabricating a shielded gate trench field-effect transistor structure according to claim 3, characterized in that: Both the first trench and the second trench have a first conductive layer lead-out area, in which a first conductive layer is formed; both the first trench and the second trench have a second conductive layer lead-out area, in which a first conductive layer and a second conductive layer are formed.

5. The method for fabricating a shielded gate trench field-effect transistor structure according to claim 4, characterized in that, It also includes the following steps: A first contact hole, a second contact hole, a third contact hole, and a fourth contact hole are formed. The first contact hole and the third contact hole are spaced apart in the extension direction of the first trench, and the second contact hole and the fourth contact hole are spaced apart in the extension direction of the second trench. The first contact hole is located in the first conductive layer lead-out area of ​​the first trench and exposes the first conductive layer at the bottom. The second contact hole is located in the first conductive layer lead-out area of ​​the second trench and exposes the first conductive layer at the bottom. The third contact hole is located in the second conductive layer lead-out area of ​​the first trench and exposes the second conductive layer at the bottom. The fourth contact hole is located in the second conductive layer lead-out area of ​​the second trench and exposes the second conductive layer at the bottom. A metal layer is formed on the interlayer dielectric layer, and the metal layer is patterned to obtain the source and the gate. The source is further filled with the source contact hole, the first contact hole and the third contact hole, and the gate is further filled with the second contact hole and the fourth contact hole. The source and the gate are electrically isolated.

6. The method for fabricating a shielded gate trench field-effect transistor structure according to claim 1, characterized in that: The top of the first conductive layer is embedded in the second conductive layer.

7. The method for fabricating a shielded gate trench field-effect transistor structure according to claim 3, characterized in that: The materials of the first conductive layer and the second conductive layer both include polycrystalline silicon, and the materials of the first dielectric layer, the isolation layer, the second dielectric layer and the interlayer dielectric layer all include silicon dioxide.

8. A shielded gate trench field-effect transistor structure, characterized in that, include: Semiconductor layer; The first trench unit and the second trench unit are located in the semiconductor layer and are spaced apart and alternately arranged in the horizontal direction. The first trench unit includes at least one first trench, and the second trench unit includes at least one second trench. Both the first trench and the second trench open from the top surface of the semiconductor layer and extend downward. A first dielectric layer, a first conductive layer, an isolation layer, a second dielectric layer, and a second conductive layer are located in the first trench and the second trench, respectively. The second conductive layer is located above the first conductive layer and is isolated from the first conductive layer by the isolation layer. The first dielectric layer is located between the inner wall of the trench and the first conductive layer, and the second dielectric layer is located between the inner wall of the trench and the second conductive layer. The source and gate are located on the semiconductor layer. The first conductive layer and the second conductive layer in the first trench are electrically connected to the source, and the first conductive layer and the second conductive layer in the second trench are electrically connected to the gate.

9. The shielded gate trench field-effect transistor structure according to claim 8, characterized in that, The transistor structure also includes: The body region is located on the upper surface of the semiconductor layer; The source region is located on the upper surface layer of the body region; An interlayer dielectric layer is located above the semiconductor layer, and the interlayer dielectric layer covers the second conductive layer and the source region; The source contact hole is located in the interlayer dielectric layer and extends through the interlayer dielectric layer, the source region and into the body region.

10. The shielded gate trench field-effect transistor structure according to claim 8, characterized in that: The transistor structure further includes a first contact hole, a second contact hole, a third contact hole, and a fourth contact hole. The first contact hole and the third contact hole are spaced apart in the extension direction of the first trench, and the second contact hole and the fourth contact hole are spaced apart in the extension direction of the second trench. The bottom of the first contact hole exposes the first conductive layer of the first trench, the bottom of the second contact hole exposes the first conductive layer of the second trench, the bottom of the third contact hole exposes the second conductive layer of the first trench, and the bottom of the fourth contact hole exposes the second conductive layer of the second trench.

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