A silicon carbide power MOSFET device and a manufacturing method thereof

Abstract

The present invention discloses a silicon carbide power MOSFET device and a manufacturing method thereof. By using a self-alignment process and a deep P-type sidewall region formed by one or more ion implantations on both sides of the trench gate, the side of the trench serves as the channel region, and the side below serves as the shielding layer, making the device cell structure more compact, increasing the channel density, reducing the channel resistance, and shortening the distance from the P-type shielding layer to the trench, which can effectively shield the gate oxide electric field.

Description

Technical Field

[0001] The present invention relates to the field of power devices, and particularly to a trench-gate silicon carbide power MOSFET device. Background Art

[0002] Power MOSFETs are mostly used as electronic switches, often used to control the on / off of loads, and can also be used as controllable rectifiers to achieve AC-DC conversion. They are one of the most commonly used devices in power circuits. Silicon carbide has many advantages such as a high critical breakdown electric field, high thermal conductivity, and high saturated electron drift velocity, and is more suitable than silicon for high-voltage and high-current semiconductor devices.

[0003] Silicon carbide power MOSFETs have high power switching performance and have been widely used in the field of power electronics. One of the main challenges of silicon carbide MOSFETs is the low electron mobility in the channel, which leads to a large channel resistance and constitutes an important part of the overall specific on-resistance. Silicon carbide MOSFETs mainly have two structures: planar gate and trench gate. Compared with traditional planar gate MOSFETs, the channel of trench gate MOSFETs is in the vertical direction, where higher mobility can be utilized, and the width of the JFET region is eliminated, the cells are more compact, and the channel density is large, thus significantly reducing the on-resistance of the device [1].

[0004] However, a major problem of silicon carbide trench MOSFETs is the high gate oxide electric field during device breakdown voltage, which seriously damages the reliability of the device. To solve this problem, J. Tan et al. from Purdue University in the United States proposed in 1998 to implant a grounded P-type shielding layer under the trench gate to shield the gate oxide electric field [2]. However, the process of realizing the grounding of the P-type shielding layer is relatively complex, and a considerable part of the chip area must be sacrificed to fabricate the contact holes.

[0005] T. Nakamura et al. from Rohm Semiconductor proposed the structure of a double trench MOSFET in 2011 [3]. The source and the gate are etched simultaneously, and a P-type shielding layer is implanted under the source. However, since the P-type shielding layer is far from the gate trench, a higher energy ion implantation is required to form a deep P-type doped region.

[0006] Dethard Peters et al. from Infineon proposed the structure of CoolSiC trench MOSFET in 2017 [4]. This structure forms a channel on one side of the channel and implants a deep P-type shielding layer on the other side to shield the high electric field at the bottom of the gate oxide. The shielding effect is good, but half of the channel is sacrificed, reducing the channel density.

[0007] References:

[0008] [1] Agarwal A K, Casady J B, Rowland L B, et al. 1.1 kv 4h-sic powerumosfets[J]. IEEE Electron Device Letters, 1997, 18(12): 586 - 588.

[0009] [2] Tan J, Cooper J A, Melloch M R. High-voltage accumulation-layer UMOSFET's in 4H-SiC[J]. IEEE Electron Device Letters, 1998, 19(12): 487 - 489.

[0010] [3] Nakamura T, Nakano Y, Aketa M, et al. High performance SiC trench devices with ultra-low ron[C] / / 2011 International Electron Devices Meeting. IEEE, 2011: 26.5.1 - 26.5.3.

[0011] [4] Peters D, Siemieniec R, Aichinger T, et al. Performance and ruggedness of 1200V SiC—Trench—MOSFET[C] / / 2017 29th International Symposium on Power Semiconductor Devices and IC's(ISPSD). IEEE, 2017: 239 - 242. Summary of the Invention

[0012] The object of the present invention is to propose a silicon carbide power MOSFET device to solve the problems of large channel resistance and concentrated gate oxide electric field in the device.

[0013] The silicon carbide power MOSFET device proposed by the present invention utilizes a self-alignment process and deep P-type sidewall regions formed on both sides of the trench gate by one or more ion implantations. The side of the trench serves as the channel region, and the side below serves as the shielding layer, making the device cell structure more compact, increasing the channel density, reducing the channel resistance, and shortening the distance from the P-type shielding layer to the trench, which can effectively shield the gate oxide electric field.

[0014] The technical solution of the present invention is as follows:

[0015] A silicon carbide power MOSFET device comprises an N-type heavily doped silicon carbide substrate, and an N-type lightly doped drift region and an N-type doped JFET region epitaxially grown in sequence on the substrate, wherein a gate is located in a gate trench formed by etching in the middle of the JFET region, and a gate dielectric layer is formed around the gate; on both sides of the trench are P-type sidewall regions formed by one or more ion implantations, the depth of the P-type sidewall regions is greater than the depth of the trench, the regions on the sides of the trench are used as channel regions, and the other regions below the trench sides are used as shielding layers; above the P-type sidewall regions are parallel N-type heavily doped source regions and P-type heavily doped regions, wherein the N-type heavily doped source regions are close to the gate dielectric layer; the source is located above the gate dielectric layer, the N-type heavily doped source regions and the P-type heavily doped regions, and the drain is located on the back of the substrate.

[0016] In the silicon carbide power MOSFET device of the present invention, the N-type heavily doped silicon carbide substrate generally adopts a 4° off-axis angle, a thickness of generally 20 to 2000 μm, and a doping concentration of 1×10 17 ~2×10 20 cm -3 ; The thickness of the epitaxial drift region is 5 to 100 μm, and the doping concentration is 1×10 15 ~2×10 17 cm -3 .

[0017] Preferably, the distance from the bottom of the JFET region to the bottom of the source is 1.2-5.2 μm, and the doping concentration of the JFET region is 5×10 15 ~5×10 17 cm -3 .

[0018] Preferably, the thickness of the P-type sidewall region is 0.8-4.3 μm, the thickness of the P-type sidewall region on the side of the gate trench as the channel region is 0.3-0.8 μm, and the doping concentration is 5×10 16 ~2×10 18 cm -3 The thickness of the P-type sidewall region (shielding layer) at the lower side that acts as a shield is 0.5 to 3.5 μm, and the doping concentration is 2×10 16 ~6×10 18 cm -3 .

[0019] Preferably, the source region has a thickness of 0.1 to 0.4 μm and a doping concentration of 1×10 19 ~1×10 20 cm -3 .

[0020] Preferably, the thickness of the P-type heavily doped region is 0.1-0.4 μm, and the doping concentration is 1×1019 ~1×10 20 cm -3 。

[0021] Preferably, the gate trench depth in the silicon carbide power MOSFET device structure is 0.4 to 1.2 μm.

[0022] The present invention also provides a method for manufacturing a silicon carbide power MOSFET device with the above trench gate structure, which specifically includes the following steps:

[0023] Step 1: An N-type lightly doped silicon carbide drift region and an N-type doped JFET region are sequentially epitaxially grown on an N-type heavily doped silicon carbide substrate;

[0024] Step 2: An etching mask is formed on the JFET region, and a silicon carbide trench is etched in the JFET region;

[0025] Step 3: An injection mask is filled in the silicon carbide trench;

[0026] Step 4: The etching mask is removed;

[0027] Step 5: By using a self-alignment process, a deep P-type sidewall region is formed by one or more ion implantations, which at least includes one high-energy ion implantation or a channel implantation (Channel Implantation) parallel to the <0001> direction of the silicon carbide drift region;

[0028] Step 6: On the P-type sidewall region, an N-type heavily doped source region and a P-type heavily doped region are respectively prepared by selective ion implantation;

[0029] Step 7: The injection mask is removed;

[0030] Step 8: Silicon dioxide is thermally oxidized on the inner surface of the silicon carbide trench to obtain a gate dielectric layer, and heavily doped polysilicon is deposited to form a gate;

[0031] Step 9: A silicon dioxide layer is deposited on the upper surface of the device, and a gate top dielectric layer is formed by photolithography and etching; then a source electrode and a drain electrode are respectively prepared on the upper and lower surfaces of the device.

[0032] If a 4-degree inclined silicon carbide substrate is used in step 1), then in step 5, an aluminum ion implantation inclination angle of 4 degrees can be first adopted to make the implantation direction parallel to the <0001> direction of the silicon carbide drift region, and by using the channel effect, a channel implantation is formed to increase the ion implantation depth, so as to form a P-type doped region with a relatively deep implantation depth of 2×10 16 ~6×10 18 cm -3 as a shielding layer; then through conventional aluminum ion implantation, a P-type doped region with a doping concentration of 5×1016 ~2×10 18 cm -3 The P-type doping region with a shallower implantation depth serves as the channel region.

[0033] In addition, variations in parameters such as the length, thickness, and doping concentration of each region are within the scope of the present invention, which depend on different design requirements and manufacturing processes. The focus of the present invention lies in the deep P-type sidewall regions formed by self-alignment process and one or more ion implantations on both sides of the gate trench, which serve as both the channel region and the shielding layer. It can be understood that without departing from the scope of the present invention, there can be other process sequences and combinations to ultimately achieve the same device structure. For example, the manufacturing process method of the deep P-type sidewall regions, and the manufacturing sequence of the P-type heavily doped region and the N-type heavily doped source region can be appropriately adjusted.

[0034] Advantages:

[0035] The prior art can better protect the gate oxide by forming a P-type shielding layer, but there are problems that the P-type shielding layer is not easily grounded or the channel density is sacrificed. For this reason, the present invention proposes a device structure and manufacturing method. By using the deep P-type sidewall regions formed by self-alignment process and one or more ion implantations as the channel region and the shielding layer, the device structure is made more compact, the channel density is increased, and the gate oxide electric field can be effectively shielded.

[0036] The following table can intuitively show the advantages of the present invention (refer to the literature in the background art):

[0037] Brief Description of the Drawings

[0038] Figure 1 is a schematic structural diagram of a silicon carbide power MOSFET device with a deep P-type shielding layer proposed by the present invention.

[0039] Figure 2 is the completion effect diagram of Step 1 of the embodiment.

[0040] Figure 3 is the completion effect diagram of Step 2 of the embodiment.

[0041] Figure 4 is the completion effect diagram of Step 3 of the embodiment.

[0042] Figure 5 is the completion effect diagram of Step 4 of the embodiment.

[0043] Figure 6 is the completion effect diagram of Step 5 of the embodiment.

[0044] Figure 7 is the completion effect diagram of Step 6 of the embodiment.

[0045] Figure 8 It is the effect diagram completed in Step 7 of the embodiment.

[0046] Figure 9 It is the effect diagram completed in Step 8 of the embodiment.

[0047] In the figure: 1 - source electrode, 2 - gate dielectric layer, 3 - gate electrode, 4 - source region, 5 - heavily doped P-type region, 6 - P-type sidewall region, 61 - implantation mask, 7 - JEFT region, 71 - etching mask, 8 - drift region, 9 - substrate, 10 - drain electrode. Specific implementation mode

[0048] The following introduces a process flow for fabricating the silicon carbide power MOSFET device of the present invention through an embodiment in combination with the accompanying drawings:

[0049] The structure of a silicon carbide power MOSFET device with a deep P-type sidewall region fabricated in this embodiment is as Figure 1 shown, and successively includes from bottom to top: drain electrode 10, heavily doped N-type silicon carbide substrate 9 required for epitaxy, lightly doped N-type drift region 8 as a voltage withstand structure, JEFT region 7 with medium N-type doping to reduce on-resistance; outside the JEFT region 7 is the P-type sidewall region 6 formed by one or more ion implantations as a channel region and a shielding layer; above the JEFT region 7 are the gate electrode 3 and the dielectric layer 2 surrounding the gate electrode; above the P-type sidewall region 6 are the heavily doped P-type region 5 for making an ohmic contact between the channel region and the source electrode 1, and the N-type heavily doped source region 4 juxtaposed with the heavily doped P-type region 5, and the source electrode 1 is located above the dielectric layer 2, the heavily doped P-type region 5 and the N-type heavily doped source region 4. Structures such as a passivation layer and a field plate that are necessary in traditional silicon carbide power devices are not shown in the figure, but corresponding structures are included in this embodiment.

[0050] The preparation steps of the device are as follows:

[0051] Step 1: As Figure 2 shown, on a silicon carbide substrate 9 with a phosphorus ion doping concentration of 6×10 19 cm -3 , a thickness of 300 μm, and a 4-degree bevel angle, after a standard cleaning process, a silicon carbide drift region 8 with a phosphorus ion doping concentration of 8×10 15 cm -3 and a thickness of 10 μm is epitaxially grown by chemical vapor deposition; on the drift region 8, a silicon carbide N-type doping region with a phosphorus ion doping concentration of 3.5×10 16 cm -3 and a thickness of 2.5 - 4 μm is epitaxially grown by chemical vapor deposition as the JFET region 7.

[0052] Step 2: As Figure 3As shown, silicon dioxide is deposited on the JFET region 7 as an etching mask 71. First, the silicon dioxide layer on the upper part of the trench region is selectively etched away to form an etching window for silicon carbide, and then a trench is etched in the JFET region 7 through the ICP process. The depth of the trench is 0.4 μm and the width is 0.8 μm.

[0053] Step 3: As Figure 4 shown, in the silicon carbide trench, polysilicon is filled by chemical vapor deposition and surface planarization treatment is carried out to form an implantation mask 61.

[0054] Step 4: As Figure 5 shown, the silicon dioxide etching mask 71 is removed by wet etching.

[0055] Step 5: As Figure 6 shown, using the polysilicon in the trench as the implantation mask 61, high-energy aluminum ion implantation is used to form a P-type sidewall region 6 as a shielding layer at the lower part, or a 4-degree ion implantation tilt angle is used to make the implantation direction parallel to the <0001> direction of the silicon carbide drift region. Utilizing the channeling effect, channel ion implantation is formed to increase the implantation depth of ions so as to form a deep P-type shielding layer. Preferably, aluminum is used for channel ion implantation, the implantation dose is 2×10 13 ~4×10 14 cm -2 , the implantation energy is 500 - 1200 keV, so as to form a P-type doped region with a doping concentration of 6×10 16 ~2×10 18 cm -3 and an ion implantation depth of 1.5 - 3.5 μm from the surface of the JFET region as a shielding layer; then through conventional aluminum ion implantation, a P-type doped region with a doping concentration of 2×10 17 cm -3 and a depth of 0.6 μm from the surface of the JFET region is formed as a channel region. The channel region on the side of the trench and the shielding layer on the side and below together are called the P-type sidewall region 6.

[0056] Step 6: As Figure 7 shown, a mask layer is deposited on the P-type sidewall region 6, ion implantation windows near both sides of the polysilicon implantation mask 61 are prepared through photolithography, and then nitrogen ion implantation is carried out to form a source region 4 with a doping concentration of 2×10 19 cm -3 and an ion implantation depth of 0.2 μm, and then the mask layer is removed and annealing treatment is carried out; then using the same process steps, ion implantation windows far from both sides of the polysilicon implantation mask 61 are prepared, and aluminum ion implantation is carried out to form a P-type heavily doped region 5 with a doping concentration of 2×10 19 cm -3 and an ion implantation depth of 0.2 μm and parallel to the source region 4.

[0057] Step 7: As Figure 8 shown, use wet etching to remove the polysilicon implantation mask 61.

[0058] Step 8: As Figure 9 shown, perform sacrificial oxidation on the etched trench, then remove the sacrificial oxide layer, grow a 50-nm-thick silicon dioxide layer on the inner surface of the trench by thermal oxidation, and then anneal in an atmosphere of nitric oxide to obtain the gate dielectric layer 2; use chemical vapor deposition to deposit P-type heavily doped polysilicon, and then obtain the gate 3 through steps such as photolithography and etching.

[0059] Step 9: Deposit a silicon dioxide layer on the device surface, and then through steps such as photolithography and etching, only retain the gate dielectric layer 2 on the top of the gate 3; then deposit metal aluminum on the device surface and perform a rapid thermal annealing process to form an ohmic contact to obtain the source 1; deposit metal titanium on the lower surface of the substrate 9 and form an ohmic contact to obtain the drain 10, and obtain a silicon carbide power MOSFET device as Figure 1 shown.

[0060] The specific embodiments described above have detailed the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only the specific embodiments of the present invention and is not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for manufacturing a silicon carbide power MOSFET device, comprising the following steps: 1) Epitaxially grow an N-type lightly doped silicon carbide drift region and an N-type doped JFET region on an N-type heavily doped silicon carbide substrate in sequence; 2) Form an etching mask on the JFET region, and etch a silicon carbide trench in the JFET region; 3) Fill an injection mask in the silicon carbide trench; 4) Remove the etching mask; 5) Using a self-alignment process, form a deep P-type sidewall region by one or more ion implantations, wherein at least one high-energy ion implantation or a channel ion implantation parallel to the <0001> direction of the silicon carbide drift region is included; the depth of the P-type sidewall region is greater than the depth of the trench, and the region on the side of the trench is used as the channel region, and the other regions below the side of the trench are used as the shielding layer; 6) On the P-type sidewall region, respectively prepare an N-type heavily doped source region and a P-type heavily doped region by selective ion implantation; 7) Remove the injection mask; 8) Thermally oxidize the inner surface of the silicon carbide trench to grow silicon dioxide to obtain a gate dielectric layer, and deposit heavily doped polysilicon to form a gate; 9) Deposit a silicon dioxide layer on the upper surface of the device, and form a gate top dielectric layer by photolithography and etching; then prepare a source electrode and a drain electrode on the upper and lower surfaces of the device respectively.

2. The preparation method according to claim 1, characterized in that, Step 5) First, perform aluminum ion implantation using the channel ion implantation method to form a P-type doped region with a relatively deep implantation depth and a doping concentration of 6×10 16 ~2×10 18 cm -3 , which serves as a shielding layer; Then, through conventional aluminum ion implantation, a P-type doped region with a doping concentration of 5×10 16 ~2×10 18 cm -3 and a relatively shallow implantation depth is formed as the channel region.

3. The preparation method according to claim 1, characterized in that, In step 1), a 4-degree tilted silicon carbide substrate is used, and in step 5), a 4-degree ion implantation tilt angle is used for channel ion implantation to form a deep P-type sidewall region.

4. A silicon carbide power MOSFET device obtained by the manufacturing method according to any one of claims 1 to 3, comprising an N-type heavily doped silicon carbide substrate, and an N-type lightly doped drift region and an N-type doped JEFT region epitaxially grown on the substrate in sequence. The gate is located in a gate trench formed after etching in the middle of the JFET region, and a gate dielectric layer is around the gate; on both sides of the trench is a P-type sidewall region formed by one or more ion implantations. The depth of the P-type sidewall region is greater than the depth of the trench, and the region on the side of the trench is used as the channel region, and the other regions below the side of the trench are used as the shielding layer; above the P-type sidewall region are juxtaposed an N-type heavily doped source region and a P-type heavily doped region, wherein the N-type heavily doped source region is close to the gate dielectric layer; the source electrode is located above the gate dielectric layer, the N-type heavily doped source region and the P-type heavily doped region, and the drain electrode is located on the back surface of the substrate.

5. The silicon carbide power MOSFET device according to claim 4, wherein The substrate is a 4-degree tilted silicon carbide substrate.

6. The silicon carbide power MOSFET device according to claim 4, wherein The doping concentration of the substrate is 1×10 17 ~2×10 20 cm -3 ; The doping concentration of the drift region is 1×10 15 ~2×10 17 cm -3 .

7. The silicon carbide power MOSFET device according to claim 4, characterized in that, The distance from the bottom of the JFET region to the bottom of the source is 1.2 to 5.2 μm, and the doping concentration of the JFET region is 5×10 15 ~5×10 17 cm -3 .

8. The silicon carbide power MOSFET device according to claim 4, wherein The total thickness of the P-type sidewall region is 0.8 - 4.3 μm. The thickness of the P-type sidewall region as the channel region on the side of the gate trench is 0.3 - 0.8 μm, and the doping concentration is 5×10 16 - 2×10 18 cm -3 ; The thickness of the P-type sidewall region as the shielding layer at the lower side is 0.5 - 3.5 μm, and the doping concentration is 2×10 16 - 6×10 18 cm -3 .

9. The silicon carbide power MOSFET device according to claim 4, wherein The thickness of the N-type heavily doped source region is 0.1 to 0.4 μm, and the doping concentration is 1×10 19 ~1×10 20 cm -3 ; The thickness of the P-type heavily doped region is 0.1 to 0.4 μm, and the doping concentration is 1×10 19 ~1×10 20 cm -3 .

10. The silicon carbide power MOSFET device according to claim 4, characterized in that, The depth of the gate trench is 0.4 - 1.2 μm.

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