Semiconductor device and method of manufacturing the same

Abstract

This invention discloses a semiconductor device and its fabrication method, wherein the semiconductor device includes a III-V compound semiconductor layer and a source / drain structure. The source / drain structure is disposed on the III-V compound semiconductor layer. The source / drain structure includes a metal layer and a plurality of metal silicide patterns. The metal layer is disposed on the metal silicide patterns, and a portion of the metal layer is disposed between adjacent metal silicide patterns.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device comprising a III-V compound semiconductor layer and a method for manufacturing the same. Background Technology

[0002] III-V group semiconductor compounds, due to their semiconductor properties, can be used to form many types of integrated circuit devices, such as high-power field-effect transistors, high-frequency transistors, or high electron mobility transistors (HEMTs). In HEMTs, two semiconductor materials with different band gaps are combined to form a heterojunction, providing a channel for charge carriers. In recent years, gallium nitride (GaN) series materials have become suitable for high-power and high-frequency products due to their wide band gap and high saturation velocity. GaN series HEMTs generate a two-dimensional electron gas (2DEG) through the piezoelectric effect of the material itself, which has high electron velocity and density, thus increasing switching speed. Therefore, how to further improve the electrical performance of transistors formed from III-V group compound materials through design changes in materials, structures, and / or fabrication methods has become a research direction for researchers in related fields. Summary of the Invention

[0003] The present invention provides a semiconductor device and a method thereof, which utilizes a plurality of metal silicide patterns and a metal layer disposed on the metal silicide patterns and partially located between adjacent metal silicide patterns to form a source / drain structure, thereby reducing the contact impedance between the source / drain structure and the III-V compound semiconductor layer, thereby improving the operational performance of the semiconductor device.

[0004] An embodiment of the present invention provides a semiconductor device including a III-V compound semiconductor layer and a source / drain structure. The source / drain structure is disposed on the III-V compound semiconductor layer, and the source / drain structure includes a plurality of metal silicide patterns and a metal layer. The metal layer is disposed on the metal silicide patterns, and a portion of the metal layer is disposed between adjacent metal silicide patterns.

[0005] An embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps: forming a source / drain structure on a III-V compound semiconductor layer. The source / drain structure includes a plurality of metal silicide patterns and a metal layer. The metal layer is disposed on the metal silicide patterns, and a portion of the metal layer is disposed between adjacent metal silicide patterns. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a semiconductor device according to a first embodiment of the present invention;

[0007] Figures 2 to 7 This is a schematic diagram of a method for fabricating a semiconductor device according to a first embodiment of the present invention, wherein...

[0008] Figure 3 for Figure 2 A diagram illustrating the subsequent situation;

[0009] Figure 4 for Figure 3 A diagram illustrating the subsequent situation;

[0010] Figure 5 for Figure 4 A diagram illustrating the subsequent situation;

[0011] Figure 6 for Figure 5 A diagram illustrating the subsequent situation;

[0012] Figure 7 for Figure 6 A diagram illustrating the subsequent situation.

[0013] Figure 8 This is a schematic diagram of a semiconductor device according to a second embodiment of the present invention;

[0014] Figure 9 This is a schematic diagram of a method for manufacturing a semiconductor device according to a second embodiment of the present invention;

[0015] Figure 10 This is a schematic diagram of a semiconductor device according to a third embodiment of the present invention;

[0016] Figure 11 This is a schematic diagram of a semiconductor device according to a fourth embodiment of the present invention;

[0017] Figure 12 This is a schematic diagram of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

[0018] Explanation of main component symbols

[0019] 10 base

[0020] 10B Bottom Surface

[0021] 10T upper surface

[0022] 12 Buffer Layers

[0023] 20 III-V compound semiconductor layers

[0024] 22 III-V compound semiconductor channel layer

[0025] 24 III-V compound semiconductor capping layer

[0026] 32 Metal Patterns

[0027] 34 Metal silicide patterns

[0028] 36 Metal nitride layer

[0029] 40 silicon layers

[0030] 42 Silicon nitride layer

[0031] 44 Silicon nitride layer

[0032] 52 N-type semiconductor region

[0033] 54 N-type semiconductor region

[0034] 54' N-type semiconductor region

[0035] 62 Metal Layer

[0036] 64 Metal nitride layer

[0037] 70 protective layers

[0038] 91 Annealing process

[0039] 92. Remove manufacturing process

[0040] 93 Annealing process

[0041] 101 Semiconductor Device

[0042] 102 Semiconductor Device

[0043] 103 Semiconductor Devices

[0044] 104 Semiconductor Device

[0045] D1 First Direction

[0046] D2 Second Direction

[0047] GS gate structure

[0048] RC dent

[0049] SD source / drain structure Detailed Implementation

[0050] The following detailed description of the invention discloses sufficient detail to enable those skilled in the art to practice it. The embodiments described below should be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and detail can be made without departing from the spirit and scope of the invention.

[0051] Before further describing the various embodiments, the following explanation will focus on the specific terms used throughout the text.

[0052] The meanings of the terms “on,” “above,” and “on top of” should be interpreted in the broadest sense, such that “on” means not only “directly on” something but also includes something with other intervening features or layers in between, and that “above” or “on top of” means not only “above” or “on top of” something but can also include something “above” or “on top of” without other intervening features or layers in between (i.e., directly on something).

[0053] The ordinal numbers used in the specification and claims, such as "first" and "second", are used to modify the elements of the claims. Unless otherwise specified, they do not imply or represent any prior ordinal number of the claimed element, nor do they represent the order of one claimed element with another, or the order of manufacturing methods. The use of these ordinal numbers is only to enable a claim element with a certain name to be clearly distinguished from another claim element with the same name.

[0054] The term "etching" is generally used herein to describe a fabrication process for patterning material such that at least a portion of the material is left after etching. When a material is "etched," at least a portion of the material is retained after etching. Conversely, when a material is "removed," essentially all of the material can be removed during the process. However, in some embodiments, "removal" can be considered a broad term to include etching.

[0055] The terms “forming” or “setting” are used below to describe the behavior of applying a layer of material to a substrate. These terms are intended to describe any feasible layer forming techniques, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0056] Please see Figure 1 . Figure 1 The illustration shows a schematic diagram of a semiconductor device 101 according to a first embodiment of the present invention. Figure 1As shown, the semiconductor device 101 includes a III-V compound semiconductor layer 20 and a source / drain structure SD. The source / drain structure SD is disposed on the III-V compound semiconductor layer 20, and includes a plurality of metal silicide patterns 34 and a metal layer 62. The metal layer 62 is disposed on the metal silicide patterns 34, and a portion of the metal layer 62 is disposed between adjacent metal silicide patterns 34. By disposing of the metal silicide patterns 34 and the metal layer 62, the contact resistance between the source / drain structure SD and the III-V compound semiconductor layer 20 can be reduced, thereby improving the operational performance of the semiconductor device 101.

[0057] Further, in some embodiments, the semiconductor device 101 may further include a substrate 10 and a buffer layer 12. A III-V compound semiconductor layer 20 may be disposed on the substrate 10, and the buffer layer 12 may be disposed in a vertical direction (e.g., Figure 1 The buffer layer 12 is disposed between the substrate 10 and the III-V compound semiconductor layer 20 in the first direction D1 shown. In some embodiments, the substrate 10 may include a silicon substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, a sapphire substrate, or a substrate formed of other suitable materials, while the buffer layer 12 may include, for example, gallium nitride, aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), or other suitable buffer materials.

[0058] In some embodiments, the first direction D1 described above can be considered as the thickness direction of the substrate 10, and the substrate 10 may have an upper surface 10T and a bottom surface 10B opposite to each other in the first direction D1, and the buffer layer 12, the III-V compound semiconductor layer 20, and the source / drain structure SD described above may be disposed on one side of the upper surface 10T. Furthermore, a horizontal direction that is substantially orthogonal to the first direction D1 (e.g., Figure 1The second direction D2 and other directions orthogonal to the first direction D1 shown herein may be generally parallel to the upper surface 10T and / or the bottom surface 10B of the substrate 10, but are not limited thereto. The distance in the first direction D1 between a relatively high position in the vertical direction (e.g., the first direction D1) and / or between a component and the bottom surface 10B of the substrate 10 may be greater than the distance in the first direction D1 between a relatively low position and / or between a component and the bottom surface 10B of the substrate 10. The lower part or bottom of each component may be closer to the bottom surface 10B of the substrate 10 in the first direction D1 than the upper part or top of that component. Another component above a component may be considered relatively far from the bottom surface 10B of the substrate 10 in the first direction D1, and another component below a component may be considered relatively close to the bottom surface 10B of the substrate 10 in the first direction D1.

[0059] In some embodiments, the semiconductor device 101 may further include a gate structure GS, two source / drain structures SD as described above, and a protective layer 70. The gate structure GS may be disposed on the III-V compound semiconductor layer 20 in a first direction D1, and the two source / drain structures SD may be located on opposite sides of the gate structure GS in a horizontal direction (e.g., a second direction D2), but are not limited thereto. The gate structure GS may include a metallic conductive material or other suitable conductive material. The aforementioned metallic conductive material may include gold (Au), tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al), tantalum (Ta), palladium (Pd), platinum (Pt), compounds, composite layers, or alloys of the aforementioned materials, but is not limited thereto. The protective layer 70 may cover the III-V compound semiconductor layer 20 and the source / drain structures SD, and the protective layer 70 may include a single layer or multiple layers of dielectric material, such as an oxide dielectric material or other suitable dielectric material.

[0060] Furthermore, in some embodiments, the III-V compound semiconductor layer 20 may include a III-V compound semiconductor channel layer 22 and a III-V compound semiconductor capping layer 24, wherein the III-V compound semiconductor capping layer 24 may be disposed on the III-V compound semiconductor channel layer 22 in a first direction D1. In some embodiments, the III-V compound semiconductor channel layer 22 may include gallium nitride, indium gallium nitride (InGaN), or other suitable III-V compound semiconductor materials, while the III-V compound semiconductor capping layer 24 may include aluminum gallium nitride, aluminum indium nitride, aluminum gallium indium nitride (AlGaInN), aluminum nitride (AlN), or other suitable III-V compound semiconductor materials.

[0061] In some embodiments, the gate structure GS may be disposed on the III-V compound semiconductor capping layer 24, and a portion of the III-V compound semiconductor channel layer 22 may not be covered by the III-V compound semiconductor capping layer 24 in the first direction D1. A portion of the source / drain structure SD (e.g., the metal silicide pattern 34 and a portion of the metal layer 62) may be disposed in the first direction D1 on the portion of the III-V compound semiconductor channel layer 22 not covered by the III-V compound semiconductor capping layer 24, but this is not a limitation. Furthermore, in some embodiments, the metal layer 62 in the source / drain structure SD may overlap with a portion of the III-V compound semiconductor capping layer 24 in the first direction D1. Therefore, the source / drain structure SD may cover and contact a portion of the III-V compound semiconductor capping layer 24 and a portion of the III-V compound semiconductor channel layer 22 in the first direction D1.

[0062] In some embodiments, the material composition of the metal layer 62 may differ from the material composition of each metal silicide pattern 34. For example, the metal silicide pattern 34 may include titanium silicide (TiSi). xThe metal layer 62 may comprise aluminum, tantalum, molybdenum, titanium, or other suitable conductive metal materials. In some embodiments, the metal silicide patterns 34 in the source / drain structure SD may be separated from each other, and the metal layer 62 may contact each metal silicide pattern 34 and fill the space between adjacent metal silicide patterns 34, but is not limited thereto. In some embodiments, at least some of the metal silicide patterns 34 may be connected to each other, but the III-V compound semiconductor layer 20 (e.g., III-V compound semiconductor channel layer 22) corresponding to the source / drain structure SD is not completely covered by the metal silicide patterns 34, thereby allowing the metal layer 62 to be partially formed on the III-V compound semiconductor channel layer 22 that is not covered by the metal silicide patterns 34.

[0063] In some embodiments, the source / drain structure SD may further include a plurality of metal nitride layers 36, and each metal nitride layer 36 may be disposed in the first direction D1 between one of the plurality of metal silicide patterns 34 and the III-V compound semiconductor layer 20. In other words, each metal nitride layer 36 may overlap with the corresponding metal silicide pattern 34 in the first direction D1, and each metal nitride layer 36 may be separated from each other, but is not limited thereto. In addition, each metal nitride layer 36 may include a nitride of a metal element (e.g., titanium nitride, TiN), and each metal silicide pattern 34 includes a silicide of this metal element (e.g., titanium silicide). Therefore, the metal silicide pattern 34 and the metal nitride layer 36 may have the same metal element, but are not limited thereto.

[0064] In some embodiments, the semiconductor device 101 may further include a plurality of first N-type semiconductor regions (e.g. Figure 1 The N-type semiconductor region 52 shown) and a plurality of second N-type semiconductor regions (e.g., Figure 1 The N-type semiconductor region 54 shown is an example of this. The N-type semiconductor regions 52 and 54 can be disposed in the III-V compound semiconductor layer 20, for example, in the III-V compound semiconductor channel layer 22, but are not limited thereto. Each N-type semiconductor region 52 can be correspondingly disposed in one of a plurality of metal silicide patterns 34 in the first direction D1. At least a portion of the N-type semiconductor regions 54 can be located between adjacent N-type semiconductor regions 52, and the N-type semiconductor regions 54 can be correspondingly disposed in the first direction D1 with a metal layer 62 disposed between the metal silicide patterns 34.

[0065] Each N-type semiconductor region 52 and each N-type semiconductor region 54 may respectively include an N-type III-V compound semiconductor region caused by nitrogen vacancy or other suitable types of N-type III-V compound semiconductor regions. Nitrogen vacancies in the III-V compound semiconductor channel layer 22 and / or the III-V compound semiconductor capping layer 24 can form donor-like traps, while regions with more nitrogen vacancies can exhibit the characteristics of N-type III-V compound semiconductor regions. The N-type semiconductor regions 52 and / or 54 disposed in the III-V compound semiconductor layer 20 can be used to reduce the potential barrier at the interface between the source / drain structure SD and the III-V compound semiconductor layer 20, thereby reducing the contact impedance between the source / drain structure SD and the III-V compound semiconductor layer 20 and improving the operational performance of the semiconductor device 101.

[0066] Please see Figures 1 to 7 . Figures 2 to 7 The illustration is a schematic diagram of a method for fabricating a semiconductor device according to a first embodiment of the present invention, wherein... Figure 3 It is illustrated Figure 2 A diagram illustrating the subsequent situation. Figure 4 It is illustrated Figure 3 A diagram illustrating the subsequent situation. Figure 5 It is illustrated Figure 4 A diagram illustrating the subsequent situation. Figure 6 It is illustrated Figure 5 The following is a diagram illustrating the situation, and Figure 7 It is illustrated Figure 6 A schematic diagram of the subsequent situation. In some embodiments, Figure 1 It can be regarded as a drawing Figure 7 The following is a schematic diagram of the situation, but it is not limited to this. For example... Figure 1 As shown, the method for fabricating semiconductor device 101 may include the following steps: A source / drain structure SD is formed on a III-V compound semiconductor layer 20. The source / drain structure SD includes a plurality of metal silicide patterns 34 and a metal layer 62. The metal layer 62 is disposed on the metal silicide patterns 34, and a portion of the metal layer 62 is disposed between adjacent metal silicide patterns 34.

[0067] Further explanation: The method for fabricating the semiconductor device in this embodiment may include, but is not limited to, the following steps. First, as... Figure 2 As shown, a buffer layer 12 and a III-V compound semiconductor layer 20 can be sequentially formed on the substrate 10, and the III-V compound semiconductor layer 20 may include the aforementioned III-V compound semiconductor channel layer 22 and III-V compound semiconductor capping layer 24. Then, as... Figure 3 As shown, a portion of the III-V compound semiconductor capping layer 24 is removed to form a recess RC corresponding to the subsequently formed source / drain structure. In some embodiments, the recess RC may penetrate the III-V compound semiconductor capping layer 24 to expose a portion of the III-V compound semiconductor channel layer 22, but is not limited thereto. In some embodiments, two recess RCs may be formed to correspond to two subsequently formed source / drain structures, and at least a portion of the III-V compound semiconductor capping layer 24 may be located between the two recess RCs in the second direction D2.

[0068] Then, as Figures 3 to 4 As shown, a plurality of metal patterns 32 are formed on a III-V compound semiconductor layer 20, and a silicon layer 40 is formed covering each metal pattern 32 and the III-V compound semiconductor layer 20. In some embodiments, the metal patterns 32 may be formed on and in contact with the III-V compound semiconductor channel layer 22 exposed by the recessed RC, but are not limited thereto. In some embodiments, the metal patterns 32 may include titanium, aluminum, tantalum, molybdenum, or other suitable metallic materials. Subsequently, as... Figures 4 to 5 As shown, an annealing process 91 is performed, and at least a portion of each metal pattern 32 and a portion of the silicon layer 40 can be transformed into a metal silicide pattern 34 through the annealing process 91. Therefore, the volume of each metal silicide pattern 34 may be slightly larger than the volume of each metal pattern 32, but is not limited thereto. In some embodiments, multiple metal patterns 32 may be separated from each other, and multiple metal silicide patterns 34 formed using metal patterns 32 may also be separated from each other, but is not limited thereto. In some embodiments, the annealing process 91 may include rapid thermal processing (RTP) or other suitable thermal processing methods. Furthermore, the method for forming the metal silicide pattern 34 of the present invention is not limited to the above steps and may form the metal silicide pattern 34 in other ways as required by the design.

[0069] In some embodiments, the III-V compound semiconductor layer 20 may include nitrogen, and a plurality of metal nitride layers 36 may be formed by an annealing process 91, with each metal nitride layer 36 located between one of a plurality of metal silicide patterns 34 and the III-V compound semiconductor layer 20. In some embodiments, nitrogen in the III-V compound semiconductor layer 20 may be moved upward into the metal pattern 32 by the annealing process 91 and bonded to a portion of each metal pattern 32 (e.g., the lower portion of each metal pattern 32) to form a metal nitride layer 36. Therefore, each metal nitride layer 36 may include a nitride of a metal element in the metal pattern 32 (e.g., but not limited to titanium nitride, aluminum nitride, tantalum nitride, or molybdenum nitride), and each metal silicide pattern 34 may include a silicide of this metal element (e.g., but not limited to titanium silicide, aluminum silicide, tantalum silicide, or molybdenum silicide), but is not limited thereto. In some embodiments, since the surface area of ​​the silicon layer 40 in contact with the metal pattern 32 is relatively large and / or there is more silicon in the metal pattern 32 than nitrogen in the metal pattern 32, the thickness of each metal silicide pattern 34 formed after the annealing process 91 may be greater than the thickness of each metal nitride layer 36, but is not limited thereto.

[0070] In some embodiments, a plurality of N-type semiconductor regions 52 and a plurality of N-type semiconductor regions 52 may be formed in the III-V compound semiconductor layer 20 by an annealing process 91, for example, in the III-V compound semiconductor channel layer 22. Each N-type semiconductor region 52 may be correspondingly disposed in the first direction D1 to one of a plurality of metal silicide patterns 34, and the N-type semiconductor region 54 may be correspondingly disposed in the first direction D1 to the gap between adjacent metal silicide patterns 34. In some embodiments, nitrogen in the III-V compound semiconductor layer 20 may be moved upward to the metal pattern 32 and / or the silicon layer 40 by an annealing process 91, thereby forming a metal nitride layer 36 and a silicon nitride layer (e.g., Figure 5 The silicon nitride layer 42 and / or multiple silicon nitride layers 44 shown. Conversely, the N-type semiconductor regions 52 and 54 can be considered as regions in the III-V compound semiconductor layer 20 that have relatively more nitrogen vacancies due to nitrogen loss. Therefore, each N-type semiconductor region 52 and each N-type semiconductor region 54 may respectively include N-type III-V compound semiconductor regions caused by nitrogen vacancies. In some embodiments, each silicon nitride layer 44 may be located between the silicon layer 40 and the corresponding N-type semiconductor region 54 in the first direction D1, and at least a portion of the silicon nitride layer 44 may be located between adjacent metal nitride layers 36, while the silicon nitride layer 42 may be located between the silicon layer 40 and the III-V compound semiconductor capping layer 24.

[0071] In some embodiments, if an entire metal layer (instead of the aforementioned metal pattern 32 with gaps) is formed on the III-V compound semiconductor layer 20 corresponding to the source / drain structure and the annealing process is performed directly, a large amount of nitrogen will move upward into the metal layer at the interface between the metal layer and the III-V compound semiconductor layer 20, which may generate too many nitrogen vacancies in the III-V compound semiconductor layer 20. Excessive nitrogen vacancies can easily cause the crystal structure of the III-V compound semiconductor layer 20 to be destroyed, resulting in defects (e.g., the formation of voids in the crystal lattice structure), which negatively affects the semiconductor properties of the III-V compound semiconductor layer 20. Therefore, by using the metal pattern 32 and the silicon layer 40 covering the metal pattern 32 for annealing fabrication process 91, the problems caused by covering the corresponding source / drain structure III-V compound semiconductor layer 20 with a whole metal layer can be improved. Furthermore, the metal silicide pattern 34 formed by the reaction of the silicon layer 40 and the metal pattern 32 can also reduce the effect of the metal pattern 32 in receiving nitrogen in the III-V compound semiconductor layer 20, thus further avoiding the formation of excessive nitrogen vacancies in the III-V compound semiconductor layer 20.

[0072] In some embodiments, the nitrogen-receiving and / or attracting capacity of the metal pattern 32 may differ from that of the silicon layer 40, and the corresponding N-type semiconductor regions 52 and 54 may therefore have different depths and / or nitrogen vacancy densities, but are not limited thereto. Furthermore, in some embodiments, the silicon nitride layer (e.g., silicon nitride layer 42 and / or silicon nitride layer 44) formed by the annealing process 91 can adsorb dangling bonds on the surface of the III-V compound semiconductor layer 20, which positively contributes to the electrical performance of the semiconductor device.

[0073] like Figures 5 to 6 As shown, after the annealing fabrication process 91, a removal fabrication process 92 can be performed to remove the silicon layer 40, the silicon nitride layer 42, and the silicon nitride layer 44. In some embodiments, the removal fabrication process 92 may include one or more etching processes with a high etch selectivity to remove the silicon layer 40, the silicon nitride layer 42, and the silicon nitride layer 44 and reduce etch damage to other material layers (e.g., the metal silicide pattern 34, the metal nitride layer 36, and / or the III-V compound semiconductor layer 20). For example, the removal fabrication process 92 may include, but is not limited to, a wet etching step using hydrofluoric acid (HF), a buffered oxide etchant (BOE), or / and other suitable etchants. Then, as... Figures 6 to 7As shown, after removing silicon layer 40, silicon nitride layer 42, and silicon nitride layer 44 using removal fabrication process 92, metal layer 62 is formed, thereby forming a source / drain structure SD having metal layer 62, metal silicide pattern 34, and metal nitride layer 36. In other words, silicon layer 40, silicon nitride layer 42, and silicon nitride layer 44 can be removed before forming metal layer 62.

[0074] like Figure 7 and Figure 1 As shown, after forming the source / drain structure SD, the aforementioned protective layer 70 and gate structure GS can be formed, thereby forming... Figure 1 The semiconductor device 101 shown above. Through the fabrication method described above, N-type semiconductor regions 52 and 54 can be formed in the III-V compound semiconductor layer 20, thereby reducing the contact impedance between the source / drain structure SD and the III-V compound semiconductor layer 20. In some embodiments, the contact impedance between the metal silicide pattern 34 and / or the metal nitride layer 36 and the III-V compound semiconductor layer 20 can be less than the contact impedance between the metal layer 62 and the III-V compound semiconductor layer 20. Therefore, the metal silicide pattern 34 and / or the metal nitride layer 36 can also be used to further reduce the contact impedance between the source / drain structure SD and the III-V compound semiconductor layer 20. Furthermore, in the above-described fabrication method, an annealing process can be performed using a metal pattern and a silicon layer covering the metal pattern to form a metal silicide pattern 34, a metal nitride layer 36, an N-type semiconductor region 52, and an N-type semiconductor region 54. This allows for control over the formation of the N-type semiconductor regions 52 and 54 and avoids the formation of excessive nitrogen vacancies in the III-V compound semiconductor layer 20, thus preventing negative effects. Therefore, the fabrication method of this embodiment can be used to improve the electrical surface of the semiconductor device 101 and enhance the stability of the fabrication process.

[0075] The following description will focus on different embodiments of the present invention. For the sake of simplicity, the description will mainly focus on the differences between the embodiments, and will not repeat the same points. In addition, the same elements in the various embodiments of the present invention are identified by the same reference numerals to facilitate comparison between the embodiments.

[0076] Please see Figure 8 . Figure 8 The illustration shows a schematic diagram of a semiconductor device 102 according to a second embodiment of the present invention. Figure 8As shown, the semiconductor device 102 may include a plurality of N-type semiconductor regions 54' disposed in the III-V compound semiconductor layer 20, for example, disposed in the III-V compound semiconductor channel layer 22, but is not limited thereto. The N-type semiconductor regions 54' may include N-type III-V compound semiconductor regions caused by nitrogen vacancies or other suitable types of N-type III-V compound semiconductor regions. The N-type semiconductor regions 54' may be disposed corresponding to the metal layers 62 disposed between the metal silicide patterns 34 in the first direction D1, and at least a portion of the N-type semiconductor regions 54' may be located between adjacent N-type semiconductor regions 52. In addition, the semiconductor device 102 may also include a plurality of metal nitride layers 64, each metal nitride layer 64 may be disposed between the metal layer 62 and the corresponding N-type semiconductor region 54' in the first direction D1, and at least a portion of the metal nitride layers 64 may be disposed between adjacent metal nitride layers 36. In some embodiments, each metal nitride layer 64 may include nitrides of the metal elements in the metal layer 62, and when the metal layer 62 and the metal silicide pattern 34 have different metal elements, the material composition of the metal nitride layer 64 may be different from the material composition of the metal nitride layer 36.

[0077] Please see Figure 9 , Figure 7 and Figure 8 . Figure 9 The illustration is a schematic diagram of a method for fabricating a semiconductor device according to a second embodiment of the present invention. In some embodiments, Figure 9 It can be regarded as a drawing Figure 7 The following is a diagram illustrating the situation, and Figure 8 It can be regarded as a drawing Figure 9 The following is a schematic diagram of the situation, but it is not limited to this. For example... Figure 7 , Figure 9 as well as Figure 8 As shown, in some embodiments, after the metal layer 62 is formed, an annealing process 93 can be performed. The aforementioned metal nitride layer 64 can be formed through the annealing process 93, and the N-type semiconductor region 54' can be transformed into an N-type semiconductor region 54' through the annealing process 93. In some embodiments, the annealing process 93 may include rapid heat treatment or other suitable heat treatment methods. It is worth noting that the annealing process 93 and the correspondingly formed metal nitride layer 64 and / or N-type semiconductor region 54' of this embodiment can also be applied in other embodiments of the present invention as needed by the design.

[0078] Please see Figure 10 . Figure 10 The illustration shows a schematic diagram of a semiconductor device 103 according to a third embodiment of the present invention. Figure 10As shown, in the semiconductor device 103, the source / drain structure SD can be disposed on the III-V compound semiconductor capping layer 24, and at least a portion of the N-type semiconductor region 52 and at least a portion of the N-type semiconductor region 54 can be disposed in the III-V compound semiconductor capping layer 24. In some embodiments, the metal layer 62, the metal silicide pattern 34, and the metal nitride layer 36 of the source / drain structure SD can be disposed on the III-V compound semiconductor capping layer 24 in the first direction D1, and the N-type semiconductor region 52 and the N-type semiconductor region 54 can be respectively N-type III-V compound semiconductor regions in the III-V compound semiconductor capping layer 24 caused by nitrogen vacancies. Furthermore, the fabrication method of the semiconductor device 103 in this embodiment can be similar to the fabrication method of the first embodiment described above, but does not include the following: Figure 3 The steps for forming the RC depression are shown in the diagram.

[0079] Please see Figure 11 . Figure 11 The illustration shows a schematic diagram of a semiconductor device 104 according to a fourth embodiment of the present invention. Figure 11 As shown, in the semiconductor device 104, the source / drain structure SD can be disposed on the III-V compound semiconductor capping layer 24, while the N-type semiconductor region 52 can be partially formed in the III-V compound semiconductor capping layer 24 and partially formed in the III-V compound semiconductor channel layer 22. Furthermore, the N-type semiconductor region 54 can also be partially formed in the III-V compound semiconductor capping layer 24 and partially formed in the III-V compound semiconductor channel layer 22, or disposed only in the III-V compound semiconductor capping layer 24. Additionally, the interface between the source / drain structure SD and the III-V compound semiconductor capping layer 24 can be lower than the uppermost surface of the III-V compound semiconductor capping layer 24 in the first direction D1. The fabrication method of the semiconductor device 104 in this embodiment can be similar to the fabrication method of the first embodiment described above, but the recess formation condition corresponding to the source / drain structure SD is different.

[0080] Please see Figure 11 and Figure 12 . Figure 12 The illustration shows a schematic diagram of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. In some embodiments, Figure 11 It can be regarded as a drawing Figure 12 The following is a schematic diagram of the situation, but it is not limited to this. For example... Figure 11 and Figure 12As shown, the recess RC corresponding to the source / drain structure SD may not penetrate the III-V compound semiconductor capping layer 24 and may not expose the III-V compound semiconductor channel layer 22. Therefore, the metal pattern used to form the metal silicide pattern 34 may be formed on the III-V compound semiconductor capping layer 24 corresponding to the recess RC, and the N-type semiconductor region 52 and / or the N-type semiconductor region 54 may be partially formed in the III-V compound semiconductor capping layer 24 and partially formed in the III-V compound semiconductor channel layer 22.

[0081] In summary, in the semiconductor device and its fabrication method of the present invention, a source / drain structure can be formed using a metal silicide pattern and a metal layer disposed on the metal silicide pattern and partially located between adjacent metal silicide patterns, thereby reducing the contact impedance between the source / drain structure and the III-V compound semiconductor layer. Furthermore, by using a metal pattern and an annealing process to form the metal silicide pattern and the N-type semiconductor region, the formation of the N-type semiconductor region can be controlled, and excessive nitrogen vacancies in the III-V compound semiconductor layer can be avoided, thus preventing negative effects. Therefore, the fabrication method of the present invention can improve the electrical surface properties of the semiconductor device and enhance the stability of the fabrication process.

[0082] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor device, comprising: III-V compound semiconductor layer; A source / drain structure is disposed on the III-V compound semiconductor layer, wherein the source / drain structure includes: Multiple metal silicide patterns; and A metal layer is disposed on the plurality of metal silicide patterns, wherein a portion of the metal layer is disposed between adjacent plurality of metal silicide patterns. A plurality of first N-type semiconductor regions are disposed in the III-V compound semiconductor layer, wherein each of the first N-type semiconductor regions is disposed in a vertical direction corresponding to one of the plurality of metal silicide patterns; and A plurality of second N-type semiconductor regions are disposed in the III-V compound semiconductor layer, wherein the plurality of second N-type semiconductor regions are disposed in the vertical direction corresponding to the portion of the metal layer disposed between the plurality of metal silicide patterns.

2. The semiconductor device of claim 1, wherein the plurality of metal silicide patterns are separated from each other.

3. The semiconductor device of claim 1, wherein the material composition of the metal layer is different from the material composition of each of the metal silicide patterns.

4. The semiconductor device of claim 1, wherein the source / drain structure further comprises a plurality of metal nitride layers, and each of the metal nitride layers is disposed between one of the plurality of metal silicide patterns and the III-V compound semiconductor layer.

5. The semiconductor device of claim 4, wherein each of the metal nitride layers comprises a nitride of a metal element, and each of the metal silicide patterns comprises a silicide of the metal element.

6. The semiconductor device of claim 1, wherein the III-V compound semiconductor layer comprises: III-V compound semiconductor channel layer; as well as A III-V compound semiconductor capping layer is disposed on the III-V compound semiconductor channel layer, wherein at least a portion of each of the first N-type semiconductor regions is disposed in the III-V compound semiconductor channel layer.

7. The semiconductor device of claim 1, wherein the III-V compound semiconductor layer comprises: III-V compound semiconductor channel layer; as well as A III-V compound semiconductor capping layer is disposed on the III-V compound semiconductor channel layer, wherein at least a portion of each of the first N-type semiconductor regions is disposed in the III-V compound semiconductor capping layer.

8. The semiconductor device of claim 1, wherein each of the first N-type semiconductor regions and each of the second N-type semiconductor regions respectively comprises an N-type III-V compound semiconductor region caused by nitrogen vacancy.

9. A method for manufacturing a semiconductor device, comprising: A source / drain structure is formed on a III-V compound semiconductor layer, wherein the source / drain structure includes: Multiple metal silicide patterns; and A metal layer is disposed on the plurality of metal silicide patterns, wherein a portion of the metal layer is disposed between adjacent plurality of metal silicide patterns. The methods for forming the plurality of metal silicide patterns include: Multiple metal patterns are formed on the III-V compound semiconductor layer; A silicon layer is formed covering the plurality of metal patterns and the III-V compound semiconductor layer; and An annealing process is performed, wherein at least a portion of each metal pattern and a portion of the silicon layer are transformed into the metal silicide pattern through the annealing process. Multiple first N-type semiconductor regions and multiple second N-type semiconductor regions are formed in the III-V compound semiconductor layer through the annealing process. Each of the first N-type semiconductor regions is disposed in a vertical direction corresponding to one of the multiple metal silicide patterns, and the multiple second N-type semiconductor regions are disposed in the vertical direction corresponding to the portion of the metal layer disposed between the multiple metal silicide patterns.

10. The method of fabricating a semiconductor device as claimed in claim 9, wherein the plurality of metal patterns are separated from each other, and the plurality of metal silicide patterns are separated from each other.

11. The method of fabricating a semiconductor device as claimed in claim 9, wherein the III-V compound semiconductor layer comprises nitrogen, a plurality of metal nitride layers are formed by the annealing process, and each of the metal nitride layers is located between one of the plurality of metal silicide patterns and the III-V compound semiconductor layer.

12. The method of fabricating a semiconductor device as claimed in claim 11, wherein each of the metal nitride layers comprises a nitride of a metal element in the plurality of metal patterns, and each of the metal silicide patterns comprises a silicide of the metal element.

13. The method of manufacturing a semiconductor device as claimed in claim 9, wherein each of the first N-type semiconductor regions and each of the second N-type semiconductor regions respectively includes an N-type III-V compound semiconductor region caused by nitrogen vacancies.

14. The method of fabricating a semiconductor device as claimed in claim 9, wherein the III-V compound semiconductor layer comprises: III-V compound semiconductor channel layer; as well as A III-V compound semiconductor capping layer is disposed on the III-V compound semiconductor channel layer, wherein at least a portion of each of the first N-type semiconductor regions is disposed and at least a portion of each of the second N-type semiconductor regions is formed in the III-V compound semiconductor channel layer.

15. The method of manufacturing a semiconductor device as claimed in claim 9, further comprising: The silicon layer is removed before the metal layer is formed.

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