Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: forming an initial first trench within an interlayer dielectric layer, the initial first trench exposing a first etch stop layer on the top surface of a source / drain layer; forming an initial second trench within the interlayer dielectric layer, the initial second trench exposing a first etch stop layer on the gate surface, and the initial second trench being connected to the initial first trench; etching the first etch stop layer exposed by the initial first trench and the initial second trench to form a first trench and a second trench, the first trench exposing the source / drain layer surface and the second trench exposing the gate, which facilitates control of etching depth, reduces the probability of over-etching the source / drain layer surface, and thereby improves the performance of the formed device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of microelectronics technology, memory is showing a trend towards high integration, high speed, and low power consumption. Compared to Dynamic Random Access Memory (DRAM), Static Random-Access Memory (SRAM) can retain data stored in its internal standard without a refresh circuit. Furthermore, unlike DRAM, it does not require periodic flushing and charging, otherwise the internal data will be lost. Therefore, SRAM has better performance. SRAM has seen significant development in recent years and, as an important type of semiconductor memory, has been widely used in high-speed data exchange systems such as computers, communications, and multimedia.

[0003] However, static random access memory (SRAM) has low integration density and requires a much larger volume compared to SRAM of the same capacity. Therefore, a key indicator of dynamic random access memory (DRAM) is its area. To improve integration density, shared contact via (Shared CT) technology is used to directly connect the gate and active region, saving area by shortening the interconnection. However, existing shared contact via technology is prone to leakage current problems. With the miniaturization of semiconductor devices, leakage current has become a critical and unavoidable issue, and severe leakage current directly affects the operation of SRAM.

[0004] Therefore, existing static random access memory (SRAM) technology needs further improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including a base and a fin located on a portion of the base, the fin extending along a first direction; a gate spanning the fin, the gate extending along a second direction perpendicular to the first direction, the gate also located on a portion of the sidewalls and top surface of the fin; source / drain layers located within the fin on one or both sides of the gate; a first etch stop layer located on the surface of the substrate and the surface of the gate, the first etch stop layer including a first protective layer on the surface of the gate, a second etch stop layer on the surface of the source / drain layers, and a second protective layer on the surface of the second etch stop layer and the surface of the first protective layer, the thickness of the first protective layer being the same as the thickness of the second etch stop layer on the surface of the source / drain layers; and an interlayer dielectric layer located on the surface of the first etch stop layer, the top surface of the interlayer dielectric layer being higher than the top surface of the gate.

[0007] Accordingly, the present invention also provides a semiconductor structure, comprising: a substrate, the substrate including a base and a fin located on a portion of the base, the fin extending along a first direction; a gate extending across the fin along a second direction, the second direction being perpendicular to the first direction, the gate also located on a portion of the sidewalls and top surface of the fin; a source / drain layer located within the fin on one or both sides of the gate; and a first etch stop layer located on the surface of the substrate, the surface of the source / drain layer, and the surface of the gate, the thickness of the first etch stop layer on the top surface of the gate being greater than the thickness of the first etch stop layer on the top surface of the gate. The thickness of the substrate and the source / drain layer surfaces, and the gate sidewall; a second etch stop layer located on the first etch stop layer, wherein the thickness of the second etch stop layer on the top surface of the gate is less than the thickness of the first etch stop layer on the substrate, the source / drain layer surfaces, and the gate sidewall, and the total thickness of the first etch stop layer and the second etch stop layer on the top surface of the gate is the same as the total thickness of the first etch stop layer and the second etch stop layer on the substrate and the source / drain layer surfaces; an interlayer dielectric layer located on the surface of the second etch stop layer, wherein the top surface of the interlayer dielectric layer is higher than the top surface of the gate.

[0008] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a base and a fin located on a portion of the base, the fin extending along a first direction; forming a gate spanning the fin, a source / drain layer located on one or both sides of the gate within the fin, a first etch stop layer located on the surface of the substrate and the surface of the gate, and an interlayer dielectric layer on the surface of the first etch stop layer, the top surface of the interlayer dielectric layer being higher than the top surface of the gate, the gate extending along a second direction, the second direction being perpendicular to the first direction, and the gate also located on a portion of the sidewalls and the top surface of the fin. An initial first trench is formed within the interlayer dielectric layer, the initial first trench exposing a first etch stop layer on the top surface of the source / drain layer; an initial second trench is formed within the interlayer dielectric layer, the initial second trench exposing a first etch stop layer on the gate surface, and the initial second trench is connected to the initial first trench; the first etch stop layers exposed by the initial first trench and the initial second trench are etched to form a first trench and a second trench, the first trench exposing the source / drain layer surface, and the second trench exposing the gate; a first conductive layer is formed within the first trench; and a second conductive layer is formed within the second trench.

[0009] Optionally, the method for forming the gate includes: forming a dummy gate spanning the fin, the dummy gate being located on a portion of the sidewall and top surface of the fin; forming a first dielectric material layer on the substrate surface, the first dielectric material layer being located on the sidewall and top surface of the dummy gate; employing a first planarization process to planarize the first dielectric material layer until the top surface of the dummy gate is exposed, forming a first dielectric layer; removing the dummy gate to form a gate recess within the first dielectric layer; and forming the gate within the gate recess.

[0010] Optionally, after forming the dummy gate and before forming the first dielectric layer, the source / drain layer is formed, and the source / drain layer is located in the fins on one or both sides of the dummy gate.

[0011] Optionally, the first etch stop layer includes: a protective layer located on the gate surface and a second etch stop layer located on the source / drain layer surface.

[0012] Optionally, the method for forming the first etch stop layer includes: after forming the source / drain layer and before forming the first dielectric material layer, forming an initial second etch stop layer on the surface of the source / drain layer and the surface of the dummy gate; the first planarization process causes the initial second etch stop layer to form the second etch stop layer; after forming the gate trench, forming a protective layer in the gate trench, the protective layer also being located on the gate surface.

[0013] Optionally, the interlayer dielectric layer includes a first dielectric layer located on the surface of the substrate and a second dielectric layer located on the first dielectric layer, wherein the second dielectric layer is also located on the surface of the first etch stop layer.

[0014] Optionally, the method for forming the gate and the protective layer includes: forming a gate material layer on the surface of the first dielectric layer and within the gate recess; employing a second planarization process to planarize the gate material layer until the surface of the first dielectric layer is exposed, forming an initial gate; etching back the initial gate to form an opening within the gate recess; and forming the protective layer within the opening.

[0015] Optionally, the first etch stop layer includes a first protective layer located on the gate surface, a second etch stop layer located on the source / drain layer surface, and a second protective layer located on the surfaces of the second etch stop layer and the first protective layer.

[0016] Optionally, the method for forming the first etch stop layer includes: after forming the source / drain layer and before forming the first dielectric material layer, forming an initial second etch stop layer on the substrate surface and the dummy gate surface; a first planarization process causing the initial second etch stop layer to form the second etch stop layer; after forming the gate trench, forming an initial first protective layer in the gate trench, the initial first protective layer also being located on the gate surface; after forming the initial first protective layer, employing a third planarization process to planarize the first dielectric layer and the initial first protective layer until the thickness of the initial first protective layer is the same as the thickness of the second etch stop layer on the source / drain layer surface, thereby forming the first protective layer with the initial first protective layer; after the third planarization process, removing the first dielectric layer to expose the second etch stop layer on the source / drain layer surface; after removing the first dielectric layer, forming a second protective layer on the surface of the second etch stop layer and the surface of the first protective layer.

[0017] Optionally, the method for forming the interlayer dielectric layer includes: after forming the first etch stop layer, forming a second dielectric material layer on the surface of the first etch stop layer, wherein the top surface of the second dielectric material layer is higher than the gate; planarizing the second dielectric material layer to form the interlayer dielectric layer.

[0018] Optionally, the method for forming the initial first groove includes: forming a third groove within the interlayer dielectric layer, the third groove extending along a second direction; and forming the initial first groove within the third groove.

[0019] Optionally, it also includes: after forming the first groove, forming a third conductive layer in the third groove.

[0020] Optionally, the material of the first etch stop layer is a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0021] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0022] In the semiconductor structure formation method provided by the present invention, the first etch stop layer exposed by the initial first groove and the initial second groove is etched to form a first groove and a second groove. The first groove exposes the source / drain layer surface, and the second groove exposes the gate. Since the first etch stop layer on the source / drain layer surface and the first etch stop layer on the gate surface can be opened simultaneously during the etching process, it is beneficial to control the etching depth, increase etching uniformity, and reduce the probability of over-etching the source / drain layer surface, thereby improving the performance of the formed device.

[0023] Furthermore, a third planarization process is employed to planarize the first dielectric layer and the initial first protective layer, making the thickness of the first protective layer on the gate surface the same as the thickness of the second etch stop layer on the source / drain layer surface. This results in uniform thickness of the first etch stop layer on the source / drain layer surface and the gate surface, allowing the first etch stop layers on both surfaces to open simultaneously. This facilitates control of the etching depth, increases etching uniformity, reduces the probability of over-etching the source / drain layer surface, and thus improves the performance of the formed device. Attached Figure Description

[0024] Figures 1 to 3 This is a schematic diagram of a semiconductor structure formation process;

[0025] Figures 4 to 13 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention;

[0026] Figures 14 to 17 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to another embodiment of the present invention.

[0027] Figure 18 This is a schematic diagram of a semiconductor structure in another embodiment of the present invention. Detailed Implementation

[0028] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0029] As described in the background section, the performance of semiconductor structures formed using existing static random access memory (SRAM) technology urgently needs improvement. This paper will now explain and analyze the formation process of a semiconductor structure.

[0030] Figures 1 to 3 This is a schematic diagram of the semiconductor structure formation process.

[0031] Please refer to Figure 1 A substrate is provided, the substrate including a base 100 and a fin 101 located on a portion of the base, the fin 101 extending along a first direction; a gate 102 is formed across the fin 101, the gate 102 extending along a second direction perpendicular to the first direction, the gate 102 also located on a portion of the sidewalls and top surface of the fin 101; source / drain layers 103 are formed in the fins 101 on both sides of the gate 102; after forming the source / drain layers 103, an etch stop layer 104 is formed on the substrate and the surface of the gate 102; an interlayer dielectric layer 105 is formed on the surface of the etch stop layer 104; the interlayer dielectric layer 105 and the etch stop layer 104 are etched, forming a first groove (not shown in the figure) and a first contact hole 106 located in the first groove in the interlayer dielectric layer 105, the first groove extending along a second direction, and the first contact hole 106 exposing the top surface of the source / drain layer 103.

[0032] Please refer to Figure 2 A spin-coated carbon layer 107 is formed on the surface of the interlayer dielectric layer 105, in the first groove, and in the first contact hole 106.

[0033] Please refer to Figure 3 After forming the spin-coated carbon layer 107, the interlayer dielectric layer 105 and the etching stop layer 104 are etched. A second groove 108 is formed in the interlayer dielectric layer 105. The second groove 108 extends along a first direction. The second groove 108 exposes the gate 102 and communicates with the first contact hole 106.

[0034] Subsequently, metal material is filled into the first groove, the first contact hole 106, and the second groove 108 to form a first conductive layer in the first groove, a shared contact in the first contact hole 106, and a second conductive layer in the second groove 108.

[0035] The above method is used to form a static random access memory (SRAM). As described in the background, to improve integration, the first conductive layer 110 and the second conductive layer 109 share the shared contact, thereby electrically connecting the active region 103 and the gate 102 through the shared contact. The spin-coated carbon layer 107 is an organic polymer material, and during the etching process forming the second groove 108, the spin-coated carbon layer 107 protects the surface of the source / drain layer 103 exposed by the first contact hole 106. However, on the one hand, the spin-coated carbon layer 107 is easily consumed during the etching process. On the other hand, when the structure is formed at the wafer edge, due to the difference in etching intensity uniformity between the wafer center and the wafer edge, the spin-coated carbon layer 107 on the wafer edge surface is easily less than that on the wafer center surface. Therefore, during the etching process of forming the second groove 108, the spin-coated carbon layer 107 does not provide sufficient protection for the surface of the source / drain layer 103 exposed by the first contact hole 106, which can easily lead to over-etching of the source / drain layer 103, causing the formed shared contact to be located within the source / drain layer 103, or even penetrating the source / drain layer 103, resulting in device leakage and seriously affecting the device performance.

[0036] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure by etching the first etch stop layer exposed by the initial first trench and the initial second trench to form a first trench and a second trench. The first trench exposes the source / drain layer surface, and the second trench exposes the gate. Since both the initial first contact hole and the initial second trench expose etch stop layers during the etching process, it is beneficial to control the etching depth, increase etching uniformity, and reduce the probability of over-etching the source / drain layer surface, thereby improving the performance of the formed device.

[0037] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Figures 4 to 13 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0039] Please refer to Figure 4 and Figure 5 , Figure 4 yes Figure 5 A top-view structural diagram. Figure 5 yes Figure 4 A cross-sectional structural schematic diagram along the DD1 direction is provided, the substrate including a base 200 and a fin 201 located on a portion of the base 200, the fin 201 extending along a first direction X.

[0040] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate is made of silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0041] In this embodiment, the fin 201 is made of silicon. In other embodiments, the fin 201 may be made of germanium-silicon.

[0042] Subsequently, a gate spanning the fin 201, a source / drain layer located on one or both sides of the gate within the fin 201, a first etch stop layer located on the substrate surface and the gate surface, and an interlayer dielectric layer on the surface of the first etch stop layer are formed. The top surface of the interlayer dielectric layer is higher than the top surface of the gate. The gate extends along a second direction Y, and the second direction Y is perpendicular to the first direction X. The gate is also located on a portion of the sidewall and top surface of the fin 201.

[0043] The method for forming the gate, the interlayer dielectric layer, and the first etch stop layer is referenced. Figures 4 to 8 .

[0044] Please continue to refer to this. Figure 4 and Figure 5 A pseudo gate 202 is formed across the fin 201, and the pseudo gate 202 is located on a portion of the sidewall and top surface of the fin 201.

[0045] In this embodiment, the dummy gate 202 is made of silicon. In other embodiments, the dummy gate 202 can be made of amorphous silicon, amorphous carbon, etc. The dummy gate 202 is used to occupy space for the subsequent formation of the gate.

[0046] In this embodiment, the interlayer dielectric layer includes a first dielectric layer located on the surface of the substrate and a second dielectric layer located on the first dielectric layer, wherein the second dielectric layer is also located on the surface of the first etch stop layer.

[0047] In this embodiment, after the dummy gate 202 is formed and before the first dielectric layer is formed, the source / drain layer 203 is formed, and the source / drain layer 203 is located in the fins 201 on one or both sides of the dummy gate 202.

[0048] The method for forming the source / drain layer 203 includes: forming a slot (not shown in the figure) in the fin 201 on one or both sides of the dummy gate 202; forming an epitaxial layer (not shown in the figure) in the slot; and implanting doped ions in the epitaxial layer, wherein the conductivity type of the doped ions is N-type or P-type.

[0049] In this embodiment, the source / drain layer 203 is located within the fins 201 on both sides of the dummy gate 202. In another embodiment, the source / drain layer is located within the fin on one side of the dummy gate.

[0050] Please refer to Figure 6 , Figure 6 The view direction is the same Figure 5 A first dielectric material layer 205 is formed on the surface of the substrate, and the first dielectric material layer 205 is located on the sidewall and top surface of the dummy gate 202.

[0051] In this embodiment, after the source / drain layer 203 is formed and before the first dielectric material layer 205 is formed, an initial second etch stop layer 204 is formed on the surface of the source / drain layer 203 and the surface of the dummy gate 202. Specifically, after the source / drain layer 203 is formed and before the first dielectric material layer 205 is formed, the initial second etch stop layer 204 is also formed on the surface of the substrate.

[0052] The initial second etch stop layer 204 is used to form a second etch stop layer, and the second etch stop layer is used to form a first etch stop layer. The material of the initial second etch stop layer 204 is the same as the material of the first etch stop layer.

[0053] The material of the first etch stop layer is a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride. In this embodiment, the material of the first etch stop layer is silicon nitride; the material of the initial second etch stop layer 204 is silicon nitride.

[0054] In this embodiment, the first etch stop layer includes a protective layer located on the surface of the gate 202 and a second etch stop layer located on the surface of the source / drain layer 203. For the method of forming the first etch stop layer, please refer to [reference needed]. Figures 7 to 8 .

[0055] Please refer to Figure 7 , Figure 7 The view direction is the same Figure 5 A first planarization process is used to planarize the first dielectric material layer 205 until the top surface of the dummy gate 202 is exposed, forming a first dielectric layer 206; the dummy gate 202 is removed, and a gate recess 207 is formed in the first dielectric layer 206.

[0056] The first planarization process causes the initial second etch stop layer 204 to form the second etch stop layer 208.

[0057] Please refer to Figure 8 , Figure 8The view direction is the same Figure 5 The gate 209 is formed within the gate groove 207.

[0058] The gate 209 is made of a metal, including tungsten, copper, or cobalt.

[0059] After the gate groove 207 is formed, a protective layer 210 is formed in the gate groove 207, and the protective layer 210 is also located on the surface of the gate 209.

[0060] In this embodiment, the method for forming the gate 209 and the protective layer 210 includes: forming a gate material layer (not shown in the figure) on the surface of the first dielectric layer 206 and in the gate recess 207; using a second planarization process to planarize the gate material layer until the surface of the first dielectric layer 206 is exposed to form an initial gate (not shown in the figure); etching back the initial gate to form an opening (not shown in the figure) in the gate recess 207; and forming the protective layer 210 in the opening.

[0061] The first etch stop layer includes a protective layer 210 located on the surface of the gate 202 and a second etch stop layer 208 located on the surface of the source / drain layer 203.

[0062] On one hand, the protective layer 210 is used to block the diffusion of ions within the gate 209, thereby improving device performance; on the other hand, the protective layer 210 is also used to form the first etch stop layer. Therefore, the material of the protective layer 210 is the same as the material of the first etch stop layer. In this embodiment, the material of the protective layer 210 is silicon nitride.

[0063] Please continue to refer to this. Figure 8 The interlayer dielectric layer includes a first dielectric layer 206 located on the surface of the substrate and a second dielectric layer 211 located on the first dielectric layer 206, wherein the second dielectric layer 211 is also located on the surface of the first etch stop layer.

[0064] The method for forming the second dielectric layer 211 includes: after forming the protective layer 210, forming a third dielectric material layer (not shown in the figure) on the surface of the first dielectric layer 206 and the first etch stop layer; planarizing the third dielectric material layer to form the second dielectric layer 211.

[0065] Please refer to Figure 9 and Figure 10 , Figure 9 for Figure 10 A top-view structural diagram. Figure 10 for Figure 9A cross-sectional view along the DD1 direction shows that an initial first groove 212 is formed in the interlayer dielectric layer, exposing a first etch stop layer on the top surface of the source / drain layer 203; an initial second groove 213 is formed in the interlayer dielectric layer, exposing a first etch stop layer on the surface of the gate 209, and the initial second groove 213 is connected to the initial first groove 212.

[0066] The method for forming the initial first groove 212 includes: forming a third groove 214 within the interlayer dielectric layer, the third groove 214 extending along a second direction Y; and forming the initial first groove 212 within the third groove 214.

[0067] In this embodiment, the initial first groove 212 is formed first, followed by the initial second groove 213. In other embodiments, the order in which the initial first groove 212 and the initial second groove 213 are formed is not required.

[0068] Please refer to Figure 11 , Figure 11 The view direction is the same Figure 5 The first etch stop layer exposed by the initial first groove 212 and the initial second groove 213 is etched to form a first groove 215 and a second groove 216, wherein the first groove 215 exposes the surface of the source / drain layer 203 and the second groove 216 exposes the gate 210.

[0069] During the etching process, the first etch stop layer on the surface of the source / drain layer 203 and the first etch stop layer on the surface of the gate 209 can be opened simultaneously, which helps to control the etching depth, increase the etching uniformity, and reduce the probability of over-etching the surface of the source / drain layer 203, thereby improving the performance of the formed device.

[0070] Please refer to Figure 12 and Figure 13 , Figure 12 yes Figure 13 A top-view structural diagram. Figure 13 yes Figure 12 A cross-sectional view along the DD1 direction shows that a first conductive layer 217 is formed in the first groove 215, and a second conductive layer 218 is formed in the second groove 216.

[0071] In this embodiment, after the first groove 215 is formed, a third conductive layer 219 is formed in the third groove 214.

[0072] The first conductive layer 217, the second conductive layer 218, and the third conductive layer 219 are used to form metal interconnects. The third conductive layer 219 and the first conductive layer 217 electrically interconnect the source / drain layer 203 and the gate 209 through the second conductive layer 218.

[0073] Figures 14 to 17 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to another embodiment of the present invention.

[0074] In this embodiment, the first etch stop layer includes a first protective layer located on the gate surface, a second etch stop layer located on the source / drain layer surface, and a second protective layer located on the surface of the second etch stop layer and the surface of the first protective layer. For the method of forming the first etch stop layer, please refer to [reference needed]. Figures 14 to 16 .

[0075] Please Figure 7 Based on this, continue to refer to Figure 14 After the gate groove 207 is formed, an initial first protective layer 301 is formed in the gate groove 207, and the initial first protective layer 301 is also located on the surface of the gate 300.

[0076] Please refer to the method for forming the gate 300 and the initial first protective layer 301. Figure 8 The methods for forming the gate 209 and the protective layer 210 will not be described in detail here.

[0077] Please refer to Figure 15 , Figure 15 The view direction is the same Figure 14 After the initial first protective layer 301 is formed, a third planarization process is used to planarize the first dielectric layer 206 and the initial first protective layer 301 until the thickness of the initial first protective layer 301 is the same as the thickness of the second etch stop layer 208 on the surface of the source / drain layer 203, and the first protective layer 302 is formed from the initial first protective layer 301.

[0078] The first protective layer 302 and the second etch stop layer 208 are used to form the first etch stop layer subsequently.

[0079] The first etch stop layer is made of a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the first etch stop layer is made of silicon nitride. Therefore, the materials of the first protective layer 302 and the second etch stop layer 208 are the same as the material of the first etch stop layer. In this embodiment, both the first protective layer 302 and the second etch stop layer 208 are made of silicon nitride.

[0080] The first protective layer 302 on the surface of the gate 300 has the same thickness as the second etch stop layer 208 on the surface of the source / drain layer 203, thereby making the thickness of the first etch stop layer on the surface of the source / drain layer 203 and the surface of the gate 300 uniform. This allows the first etch stop layers on the surface of the source / drain layer 203 and the surface of the gate 300 to be opened simultaneously, which is beneficial for controlling the etching depth, increasing etching uniformity, reducing the probability of over-etching the surface of the source / drain layer 203, and thus improving the performance of the formed device.

[0081] Please refer to Figure 16 , Figure 16 The view direction is the same Figure 14 After the third planarization process, the first dielectric layer 206 is removed, exposing the second etch stop layer 208 on the surface of the source / drain layer 203; after removing the first dielectric layer 206, a second protective layer 303 is formed on the surface of the second etch stop layer 208 and the surface of the first protective layer 302.

[0082] In this embodiment, the first etch stop layer is formed by the second etch stop layer 208, the first protective layer 302, and the second protective layer 303.

[0083] The material of the second protective layer 303 is the same as that of the first etch stop layer. In this embodiment, the material of the second protective layer 303 is silicon nitride.

[0084] The second protective layer 303 and the first protective layer 302 protect the surface of the gate 300. Simultaneously, the second protective layer 303 increases the thickness of the protective layer on the surface of the gate 300, improving its ability to block the outward diffusion of ions from within the gate 300, thereby enhancing the performance of the gate 300. Furthermore, because the second protective layer 303 is formed simultaneously on the surface of the gate 300 and the source / drain layer 203, it does not affect the uniformity of the thickness of the first etch stop layer on the surfaces of the gate 300 and the source / drain layer 203, thus reducing the probability of over-etching on the surface of the source / drain layer 203 and improving the performance of the formed device.

[0085] In this embodiment, please refer to the method for forming the interlayer dielectric layer. Figure 17 .

[0086] Please refer to Figure 17 , Figure 17 The view direction is the same Figure 14 After forming the first etch stop layer, a second dielectric material layer (not shown in the figure) is formed on the surface of the first etch stop layer, and the top surface of the second dielectric material layer is higher than the gate 300; the second dielectric material layer is planarized to form the interlayer dielectric layer 304.

[0087] For further details, please refer to [link / reference]. Figures 9 to 13 The description will not be repeated here.

[0088] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed using the above method. Please refer to [the original text]. Figure 17 The system includes: a substrate, the substrate including a base 200 and a fin 201 located on a portion of the base 200, the fin 201 extending along a first direction X; a gate 300 extending along a second direction Y across the fin 201, the second direction Y being perpendicular to the first direction X, the gate 300 also located on a portion of the sidewalls and top surface of the fin 201; a source / drain layer 203 located within the fin 201 on one or both sides of the gate 300; and a first etch stop layer located on the surface of the substrate and the surface of the gate 300. The first etch stop layer includes a first protective layer 302 located on the surface of the gate 300, a second etch stop layer 208 located on the surface of the source / drain layer 203, and a second protective layer 303 located on the surface of the second etch stop layer 208 and the surface of the first protective layer 302. The thickness of the first protective layer 302 is the same as the thickness of the second etch stop layer 208 on the surface of the source / drain layer 203. An interlayer dielectric layer 304 is located on the surface of the first etch stop layer, and the top surface of the interlayer dielectric layer 304 is higher than the top surface of the gate 300.

[0089] The first protective layer 302 on the surface of the gate 300 has the same thickness as the second etch stop layer 208 on the surface of the source / drain layer 203. This ensures that the thickness of the first etch stop layer on both the source / drain layer 203 and the gate 300 is uniform, allowing the first etch stop layers on both surfaces to open simultaneously. This facilitates control of the etching depth, increases etching uniformity, and reduces the probability of over-etching the source / drain layer 203, thereby improving the performance of the formed device. Simultaneously, the second protective layer 303 increases the thickness of the protective layer on the gate 300, enhancing its ability to prevent ion diffusion outward from the gate 300, thus improving the performance of the gate 300. In addition, since the second protective layer 303 is formed on both the surface of the gate 300 and the surface of the source / drain layer 203, it will not affect the uniformity of the thickness of the first etch stop layer on the surface of the gate 300 and the surface of the source / drain layer 203, thereby reducing the probability of over-etching the surface of the source / drain layer 203 and improving the performance of the formed device.

[0090] Figure 18 This is a schematic diagram of a semiconductor structure in another embodiment of the present invention.

[0091] Please refer to Figure 18 The semiconductor structure includes: a substrate, the substrate including a base 400 and a fin 401 located on a portion of the base 400, the fin 401 extending along a first direction; a gate 403 extending across the fin 401 along a second direction perpendicular to the first direction, the gate 403 also located on a portion of the sidewalls and top surface of the fin 401; a source / drain layer 402 located within the fin 401 on one or both sides of the gate 403; and a first etch stop layer 404 located on the surface of the substrate, the surface of the source / drain layer 402, and the surface of the gate 403, the thickness of the first etch stop layer 404 on the top surface of the gate 403 being greater than the thickness of the first etch stop layer 404 on the substrate and the source / drain layer 401. 2. The thickness of the surface of the gate 403 and the thickness of the sidewall of the gate 403; a second etch stop layer 405 located on the first etch stop layer 404, wherein the thickness of the second etch stop layer 405 on the top surface of the gate 403 is less than the thickness of the first etch stop layer 404 on the substrate, the surface of the source / drain layer 402, and the sidewall of the gate 403, and the total thickness of the first etch stop layer 404 and the second etch stop layer 405 on the top surface of the gate 403 is the same as the total thickness of the first etch stop layer 404 and the second etch stop layer 405 on the substrate and the surface of the source / drain layer 402; an interlayer dielectric layer 406 located on the surface of the second etch stop layer 405, wherein the top surface of the interlayer dielectric layer 406 is higher than the top surface of the gate 403.

[0092] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the substrate including a base and fins located on a portion of the base, the fins extending along a first direction; A gate spanning the fin, the gate extending along a second direction perpendicular to the first direction, the gate also being located on a portion of the sidewall and top surface of the fin; Source / drain layers located within fins on one or both sides of the gate; A first etch stop layer is located on the substrate surface and the gate surface. The first etch stop layer includes a first protective layer on the gate surface, a second etch stop layer on the source / drain layer surface, and a second protective layer on the surface of the second etch stop layer and the surface of the first protective layer. The thickness of the first protective layer is the same as the thickness of the second etch stop layer on the source / drain layer surface. An interlayer dielectric layer located on the surface of the first etch stop layer, wherein the top surface of the interlayer dielectric layer is higher than the top surface of the gate.

2. A semiconductor structure, characterized in that, include: A substrate, the substrate including a base and fins located on a portion of the base, the fins extending along a first direction; A gate spanning the fin, the gate extending along a second direction perpendicular to the first direction, the gate also being located on a portion of the sidewall and top surface of the fin; Source / drain layers located within fins on one or both sides of the gate; A first etch stop layer is located on the substrate surface, the source / drain layer surface, and the gate surface. The thickness of the first etch stop layer on the top surface of the gate is greater than the thickness of the first etch stop layer on the substrate and the source / drain layer surfaces, as well as on the gate sidewall. A second etch stop layer is located on the first etch stop layer. The thickness of the second etch stop layer on the top surface of the gate is less than the thickness of the first etch stop layer on the substrate, the source / drain layer surface, and the gate sidewall. The total thickness of the first etch stop layer and the second etch stop layer on the top surface of the gate is the same as the total thickness of the first etch stop layer and the second etch stop layer on the substrate and the source / drain layer surface. An interlayer dielectric layer located on the surface of the second etch stop layer, wherein the top surface of the interlayer dielectric layer is higher than the top surface of the gate.

3. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a base and fins located on a portion of the base, the fins extending along a first direction; A gate spanning the fin, a source / drain layer located within the fin on one or both sides of the gate, a first etch stop layer located on the substrate surface and the gate surface, and an interlayer dielectric layer on the surface of the first etch stop layer, wherein the top surface of the interlayer dielectric layer is higher than the top surface of the gate, the gate extends along a second direction and the second direction is perpendicular to the first direction, the gate is also located on a portion of the sidewall and top surface of the fin, and the first etch stop layer includes a first protective layer located on the gate surface, a second etch stop layer located on the source / drain layer surface, and a second protective layer located on the surfaces of the second etch stop layer and the first protective layer, wherein the thickness of the first protective layer is the same as the thickness of the second etch stop layer on the surface of the source / drain layer; An initial first groove is formed within the interlayer dielectric layer, the initial first groove exposing a first etch stop layer on the top surface of the source / drain layer; An initial second groove is formed within the interlayer dielectric layer, the initial second groove exposing a first etch stop layer on the gate surface, and the initial second groove is connected to the initial first groove; The first etch stop layer exposed by the initial first trench and the initial second trench is etched to form a first trench and a second trench, the first trench exposing the source / drain layer surface and the second trench exposing the gate; A first conductive layer is formed within the first groove; A second conductive layer is formed within the second groove.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The method of forming the gate includes: forming a dummy gate spanning the fin, the dummy gate being located on a portion of the sidewall and top surface of the fin; forming a first dielectric material layer on the surface of the substrate, the first dielectric material layer being located on the sidewall and top surface of the dummy gate; employing a first planarization process to planarize the first dielectric material layer until the top surface of the dummy gate is exposed, forming a first dielectric layer; removing the dummy gate to form a gate recess within the first dielectric layer; and forming the gate within the gate recess.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, After the dummy gate is formed, and before the first dielectric layer is formed, the source / drain layer is formed, the source / drain layer being located within the fins on one or both sides of the dummy gate.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The method for forming the first etch stop layer includes: after forming the source / drain layer and before forming the first dielectric material layer, forming an initial second etch stop layer on the substrate surface and the dummy gate surface; a first planarization process causing the initial second etch stop layer to form the second etch stop layer; after forming the gate trench, forming an initial first protective layer in the gate trench, the initial first protective layer also being located on the gate surface; after forming the initial first protective layer, employing a third planarization process to planarize the first dielectric layer and the initial first protective layer until the thickness of the initial first protective layer is the same as the thickness of the second etch stop layer on the source / drain layer surface, thereby forming the first protective layer; after the third planarization process, removing the first dielectric layer to expose the second etch stop layer on the source / drain layer surface; after removing the first dielectric layer, forming a second protective layer on the surface of the second etch stop layer and the surface of the first protective layer.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The method for forming the interlayer dielectric layer includes: after forming the first etch stop layer, forming a second dielectric material layer on the surface of the first etch stop layer, wherein the top surface of the second dielectric material layer is higher than the gate; and planarizing the second dielectric material layer to form the interlayer dielectric layer.

8. The method for forming a semiconductor structure as described in claim 3, characterized in that, The method for forming the initial first groove includes: forming a third groove within the interlayer dielectric layer, the third groove extending along a second direction; and forming the initial first groove within the third groove.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, Also includes: After the first groove is formed, a third conductive layer is formed in the third groove.

10. The method for forming a semiconductor structure as described in claim 3, characterized in that, The material of the first etch stop layer is a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

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