Vertical gate-all-around transistor and method of manufacturing the same

Abstract

The application discloses a vertical ring gate transistor and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for reducing the device size of a transistor and improving the integration of a semiconductor device. The vertical ring gate transistor comprises a substrate, an isolation medium layer, a stack structure and a gate stack structure. The isolation medium layer is formed on the substrate. The stack structure is formed on the isolation medium layer. In the thickness direction of the substrate, the stack structure comprises a first electrode layer, a channel layer and a second electrode layer which are sequentially arranged. The material of the channel layer is a two-dimensional material. The gate stack structure is formed on the isolation medium layer. The gate stack structure surrounds the outer periphery of the stack structure. The manufacturing method of the vertical ring gate transistor is used for manufacturing the vertical ring gate transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and particularly relates to a vertical gate-all-around transistor and a manufacturing method thereof. BACKGROUND

[0002] With the rapid development of semiconductor device manufacturing technology, semiconductor devices have deep submicron structures, and a large number of semiconductor elements are contained in integrated circuits. This requires that, when designing the layout of a transistor, the occupied size of the transistor should be reduced as much as possible without affecting the performance of the transistor, so as to improve the integration of semiconductor devices.

[0003] However, the size of the transistor in many current integrated circuits is still large, which is not conducive to improving the integration of semiconductor devices. SUMMARY

[0004] The present application aims to provide a vertical gate-all-around transistor and a manufacturing method thereof, which are used to reduce the device size of the transistor and are conducive to improving the integration of semiconductor devices.

[0005] In order to achieve the above-mentioned purpose, the present application provides a vertical gate-all-around transistor, which comprises a substrate, an isolation medium layer, a stack structure and a gate stack structure.

[0006] The isolation medium layer is formed on the substrate. The stack structure is formed on the isolation medium layer. In the thickness direction of the substrate, the stack structure comprises a first electrode layer, a channel layer and a second electrode layer which are sequentially stacked. The material of the channel layer is a two-dimensional material. The gate stack structure is formed on the isolation medium layer. The gate stack structure surrounds the outer periphery of the stack structure.

[0007] Compared with the prior art, in the vertical gate-all-around transistor provided by the application, along the thickness direction of the substrate, the stack structure comprises a first electrode layer, a channel layer and a second electrode layer which are sequentially stacked. One of the first electrode layer and the second electrode layer is the source electrode of the vertical gate-all-around transistor, and the other is the drain electrode. Based on this, compared with the horizontal gate-all-around transistor, the first electrode layer, the channel layer and the second electrode layer are distributed along the thickness direction of the substrate, so that the size of the vertical gate-all-around transistor on the substrate can be reduced. In addition, the material of the channel layer is a two-dimensional material. Based on this, when the vertical gate-all-around transistor is in the working state, the channel current can be formed along the thickness direction of the channel layer, the in-layer conduction or inter-layer conduction of the channel layer made of the two-dimensional material is fully utilized, the gate length of the vertical gate-all-around transistor is the same as the thickness of the nanoscale two-dimensional material, so that the extremely short gate length vertical gate-all-around transistor is realized, the size of the vertical gate-all-around transistor is further reduced, and the integration of the semiconductor device comprising the vertical gate-all-around transistor is improved. Secondly, the gate stack structure surrounds the outer periphery of the stack structure, so that the gate control capability of the device can be enhanced, and the electrical performance of the vertical gate-all-around transistor can be improved. Furthermore, the thickness of the channel layer is small, so when the gate stack structure surrounds the outer periphery of the first electrode layer, the channel layer and the second electrode layer, the manufacturing conditions and precision required for forming the gate stack structure only on the outer periphery of the channel layer with small thickness can be prevented, and the manufacturing difficulty of the gate stack structure is reduced.

[0008] The application further provides a manufacturing method of a vertical gate-all-around transistor, comprising:

[0009] A substrate is provided.

[0010] An isolation medium layer is formed on the substrate.

[0011] A stack structure is formed on the isolation medium layer. Along the thickness direction of the substrate, the stack structure comprises a first electrode layer, a channel layer and a second electrode layer which are sequentially stacked. The material of the channel layer is a two-dimensional material.

[0012] A gate stack structure is formed on the isolation medium layer. The gate stack structure surrounds the outer periphery of the stack structure.

[0013] Compared with the prior art, the manufacturing method of the vertical gate-all-around transistor provided by the application has the beneficial effects of the vertical gate-all-around transistor, which will not be described herein. BRIEF DESCRIPTION OF DRAWINGS

[0014] The drawings described herein are used to provide further understanding of the application, and form a part of the application. The schematic embodiments of the application and the descriptions thereof are used to explain the application, and do not constitute an improper limitation on the application. In the drawings:

[0015] Figure 1A structure schematic in a manufacturing process of a vertical ring gate transistor provided by an embodiment of the present application Figure 1 ;

[0016] Figure 2 A structure schematic in a manufacturing process of a vertical ring gate transistor provided by an embodiment of the present application Figure 2 ;

[0017] Figure 3 A structure schematic in a manufacturing process of a vertical ring gate transistor provided by an embodiment of the present application Figure 3 ;

[0018] Figure 4 A structure schematic in a manufacturing process of a vertical ring gate transistor provided by an embodiment of the present application Figure 4 ;

[0019] Figure 5 A structure schematic in a manufacturing process of a vertical ring gate transistor provided by an embodiment of the present application Figure 5 ;

[0020] Figure 6 A structure schematic in a manufacturing process of a vertical ring gate transistor provided by an embodiment of the present application Figure 6 ;

[0021] Figure 7 A structure schematic in a manufacturing process of a vertical ring gate transistor provided by an embodiment of the present application Figure 7 ;

[0022] Figure 8 A structure schematic in a manufacturing process of a vertical ring gate transistor provided by an embodiment of the present application Figure 8 ;

[0023] Figure 9 A structure schematic in a manufacturing process of a vertical ring gate transistor provided by an embodiment of the present application Figure 9 ;

[0024] Figure 10 A structure schematic in a manufacturing process of a vertical ring gate transistor provided by an embodiment of the present application Figure 10 ;

[0025] Figure 11 A structure schematic in a manufacturing process of a vertical ring gate transistor provided by an embodiment of the present application Figure 10 One

[0026] Figure 12 A structure schematic in a manufacturing process of a vertical ring gate transistor provided by an embodiment of the present application Figure 10 Two

[0027] Figure 13A structure diagram in a manufacturing process of a vertical ring gate transistor provided for an embodiment of the present application Figure 10 Three;

[0028] Figure 14 A structure diagram in a manufacturing process of a vertical ring gate transistor provided for an embodiment of the present application Figure 10 Four;

[0029] Figure 15 A structure diagram in a manufacturing process of a vertical ring gate transistor provided for an embodiment of the present application Figure 10 Five;

[0030] Figure 16 A structure diagram in a manufacturing process of a vertical ring gate transistor provided for an embodiment of the present application Figure 10 Six;

[0031] Figure 17 A structure diagram in a manufacturing process of a vertical ring gate transistor provided for an embodiment of the present application Figure 10 Seven;

[0032] Figure 18 A flow chart of a manufacturing method of a vertical ring gate transistor provided for an embodiment of the present application.

[0033] The figure marks: 11 is a substrate, 12 is an isolation medium layer, 13 is a stack structure, 131 is a first electrode layer, 132 is a channel layer, 133 is a second electrode layer, 14 is a gate stack structure, 141 is a gate medium layer, 142 is a gate, 15 is a two-dimensional material, 16 is a mask layer, 17 is a gate medium material, 18 is a gate material. DETAILED DESCRIPTION

[0034] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description is merely exemplary and is not intended to limit the scope of the present disclosure. Also, in the following description, the description of well-known structures and techniques is omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0035] In the drawings, various structure diagrams according to embodiments of the present disclosure are shown. These diagrams are not drawn to scale, in which certain details are exaggerated for clarity and others are omitted. The shapes of various regions, layers shown in the drawings, and their relative sizes and positional relationships are merely exemplary, and in actuality, they can deviate due to manufacturing tolerances or technical limitations, and a person skilled in the art can additionally design regions / layers with different shapes, sizes, relative positions according to actual needs.

[0036] In the context of the present disclosure, when one layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or there can be an intervening layer / element between them. In addition, if one layer / element is on another layer / element in one orientation, it can be under the other layer / element when the orientation is reversed. In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application and not to limit the present application.

[0037] In addition, the terms "first", "second", etc. are used only for descriptive purposes and should not be construed as indicating or implying relative importance or an indicated number of the technical features. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited. The meaning of "several" is one or more, unless otherwise explicitly specified and limited.

[0038] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0039] With the rapid development of semiconductor device manufacturing technology, semiconductor devices have deep sub-micron structures, and integrated circuits contain a large number of semiconductor elements. This requires that when designing the layout of transistors, the occupied size of the transistor should be reduced as much as possible without affecting the performance of the transistor, so as to improve the integration of semiconductor devices.

[0040] However, the size of the transistor in many current integrated circuits is still relatively large, which is not conducive to improving the integration of semiconductor devices.

[0041] To solve the above technical problems, the embodiment of the present application provides a vertical gate-all-around transistor and a manufacturing method thereof. In the vertical gate-all-around transistor provided by the embodiment of the present application, along the thickness direction of the substrate, the stack structure comprises a first electrode layer, a channel layer and a second electrode layer which are sequentially stacked. The material of the channel layer is a two-dimensional material, so that the gate length of the vertical gate-all-around transistor is the same as the nanoscale two-dimensional material thickness, thereby realizing an extremely short gate length vertical gate-all-around transistor and further reducing the size occupied by the vertical gate-all-around transistor.

[0042] The embodiment of the present application provides a vertical gate-all-around transistor. As shown in the figure, Figures 15 to 17 The vertical gate-all-around transistor comprises a substrate 11, an isolation dielectric layer 12, a stack structure 13 and a gate stack structure 14.

[0043] As shown in the figure, Figures 15 to 17 The isolation dielectric layer 12 is formed on the substrate 11. The stack structure 13 is formed on the isolation dielectric layer 12. Along the thickness direction of the substrate 11, the stack structure 13 comprises a first electrode layer 131, a channel layer 132 and a second electrode layer 133 which are sequentially stacked. The material of the channel layer 132 is a two-dimensional material. The gate stack structure 14 is formed on the isolation dielectric layer 12. The gate stack structure 14 surrounds the outer periphery of the stack structure 13.

[0044] Specifically, the substrate can be a semiconductor substrate such as a silicon substrate, a germanium-silicon substrate or a germanium substrate on which no structure is formed. Alternatively, the substrate can also be a semiconductor substrate on which some film layers are formed. In this case, the specific conditions of the film layers formed on the semiconductor substrate can be determined according to the actual application scenario, as long as they can be applied to the vertical gate-all-around transistor provided by the embodiment of the present application.

[0045] For the isolation medium layer, the isolation medium layer can be a single layer structure formed by an insulating material, or a multi-layer structure formed by at least two different insulating materials. The specific structure of the isolation medium layer can be set according to actual needs, which is not limited here. For example, the material of the isolation medium layer can be silicon oxide and / or aluminum oxide. For example, when the isolation medium layer is a single layer structure, the isolation medium layer can be a silicon oxide layer or an aluminum oxide layer. For example, when the isolation medium layer is a multi-layer structure, the isolation medium layer can be a composite layer composed of a silicon oxide layer and an aluminum oxide layer. In this case, the silicon oxide layer included in the isolation medium layer is formed on the substrate. The aluminum oxide layer is formed on the silicon oxide layer. At this time, because the lattice matching degree of the silicon oxide layer with the substrate is higher, it has a better surface morphology, so as to realize the adhesion of the superimposed aluminum oxide layer, and improve the structural stability of the vertical ring gate transistor. Moreover, compared with the silicon oxide layer, the dielectric constant of the aluminum oxide layer is higher, and the aluminum oxide layer is closer to the first electrode layer and the gate stack structure, so the existence of the aluminum oxide layer can ensure that the first electrode layer, the gate stack structure and the first electrode layer are isolated from each other by the isolation medium layer, prevent electric leakage, and improve the electrical performance of the vertical ring gate transistor.

[0046] The thickness of the isolation medium layer can be set according to actual needs, which is not limited here.

[0047] For the above-mentioned stack structure, in terms of material, the material of the channel layer included in the stack structure is a two-dimensional material. The specific type of the two-dimensional material can be set according to the actual application scenario, as long as it can be applied to the vertical ring gate transistor provided by the embodiment of the present application. For example, the above-mentioned two-dimensional material can be molybdenum disulfide, indium stannide or tin sulfide, etc.

[0048] One of the above-mentioned first electrode layer and the second electrode layer is a source electrode, and the other is a drain electrode. For example, the first electrode layer can be a source electrode, and the second electrode layer can be a drain electrode. For example, the first electrode layer can also be a drain electrode, and the second electrode layer can be a source electrode. As for the material of the first electrode layer and the second electrode layer, the materials of the two are conductive materials. For example, the material of the first electrode layer and / or the second electrode layer is a metal conductive material or a two-dimensional material with metal properties. For example, the above-mentioned metal conductive material can include one or more of gold, silver, platinum, copper and aluminum. The above-mentioned two-dimensional material with metal properties can include one or more of graphene, vanadium diselenide and niobium diselenide. In addition, the materials of the above-mentioned first electrode layer and the second electrode layer can be the same or different.

[0049] In terms of structure, as shown in FIG. 1, the vertical ring gate transistor includes a substrate 1, a gate stack structure 2, a channel layer 3, a first electrode layer 4 and a second electrode layer 5. Figure 15As shown, the stack structure 13 includes a first electrode layer 131, a channel layer 132 and a second electrode layer 133, which can be self-aligned. At this time, the boundaries of the three film layers coincide, so that the structure of the vertical ring gate transistor is more uniform. Alternatively, as shown in FIG. 2B, the boundaries of the three film layers do not coincide, so that the structure of the vertical ring gate transistor is not uniform. Figure 16 As shown, the cross-sectional area of the channel layer 132 can be smaller than the cross-sectional area of the first electrode layer 131. At this time, the projection of the channel layer 132 on the substrate 11 is located within the projection of the first electrode layer 131 on the substrate 11. In this case, in the thickness direction of the substrate 11, the channel layer 132 located above the first electrode layer 131 does not shield all the outer side of the first electrode layer 131, facilitating the accurate definition of the position of the first electrode layer 131 after the formation of the stack structure 13 in the manufacture of the vertical ring gate transistor, using the outer side of the channel layer 132 and the first electrode layer 131 which are staggered with each other in the thickness direction of the substrate 11, facilitating the lead-out of the metal lead, and reducing the difficulty of manufacturing the vertical ring gate transistor.

[0050] As shown, the cross-sectional area of the channel layer 132 can be smaller than the cross-sectional area of the first electrode layer 131. At this time, the projection of the channel layer 132 on the substrate 11 is located within the projection of the first electrode layer 131 on the substrate 11. In this case, in the thickness direction of the substrate 11, the channel layer 132 located above the first electrode layer 131 does not shield all the outer side of the first electrode layer 131, facilitating the accurate definition of the position of the first electrode layer 131 after the formation of the stack structure 13 in the manufacture of the vertical ring gate transistor, using the outer side of the channel layer 132 and the first electrode layer 131 which are staggered with each other in the thickness direction of the substrate 11, facilitating the lead-out of the metal lead, and reducing the difficulty of manufacturing the vertical ring gate transistor. Figure 16 As shown, the cross-sectional area of the channel layer 132 can be smaller than the cross-sectional area of the first electrode layer 131. At this time, the projection of the channel layer 132 on the substrate 11 is located within the projection of the first electrode layer 131 on the substrate 11. In this case, in the thickness direction of the substrate 11, the channel layer 132 located above the first electrode layer 131 does not shield all the outer side of the first electrode layer 131, facilitating the accurate definition of the position of the first electrode layer 131 after the formation of the stack structure 13 in the manufacture of the vertical ring gate transistor, using the outer side of the channel layer 132 and the first electrode layer 131 which are staggered with each other in the thickness direction of the substrate 11, facilitating the lead-out of the metal lead, and reducing the difficulty of manufacturing the vertical ring gate transistor.

[0051] As shown, the cross-sectional area of the channel layer 132 can be smaller than the cross-sectional area of the first electrode layer 131. At this time, the projection of the channel layer 132 on the substrate 11 is located within the projection of the first electrode layer 131 on the substrate 11. In this case, in the thickness direction of the substrate 11, the channel layer 132 located above the first electrode layer 131 does not shield all the outer side of the first electrode layer 131, facilitating the accurate definition of the position of the first electrode layer 131 after the formation of the stack structure 13 in the manufacture of the vertical ring gate transistor, using the outer side of the channel layer 132 and the first electrode layer 131 which are staggered with each other in the thickness direction of the substrate 11, facilitating the lead-out of the metal lead, and reducing the difficulty of manufacturing the vertical ring gate transistor. Figure 16

[0052] Further, in actual application, the channel layer includes at least one two-dimensional material layer. The thickness of each two-dimensional material layer is 0.6-0.8 nm. Specifically, the channel layer can include only one two-dimensional material layer. At this time, the thickness of the channel layer is the thickness of the two-dimensional material layer. Alternatively, the channel layer can include multiple two-dimensional material layers stacked along the thickness direction of the substrate. At this time, the thickness of the channel layer is the sum of the thicknesses of the multiple two-dimensional material layers.

[0053] ​It should be noted that the limit thickness of the two-dimensional material layer can be different for different types of two-dimensional materials, and thus the limit thickness value and the thickness of the channel layer can be determined according to the type of two-dimensional material used to manufacture the channel layer in the actual application scenario.

[0054] For the above-mentioned gate stack structure, as shown in Figures 15 to 17 , the gate stack structure 14 can include a gate dielectric layer 141 surrounding the outer periphery of the stack structure, and a gate electrode 142 formed on the gate dielectric layer 141. The material of the above-mentioned gate dielectric layer 141 can be an insulating material such as HfO2, ZrO2, TiO2 or Al2O3. The material of the above-mentioned gate electrode 142 can be a conductive material such as TiN, TaN or TiSiN. The thickness of the gate dielectric layer 141 and the gate electrode 142 can be determined according to actual needs, which is not specifically limited here.

[0055] From the above, as shown in Figures 15 to 17 , the vertical gate-all-around transistor provided by the embodiment of the present application includes a first electrode layer 131, a channel layer 132 and a second electrode layer 133 which are sequentially stacked along the thickness direction of the substrate 11. Based on this, compared with the horizontal gate-all-around transistor, the above-mentioned first electrode layer 131, channel layer 132 and second electrode layer 133 are distributed along the thickness direction of the substrate 11, which can reduce the size occupied by the vertical gate-all-around transistor on the substrate 11. In addition, the material of the channel layer 132 is a two-dimensional material. Based on this, when the vertical gate-all-around transistor is in a working state, a channel current can be formed along the thickness direction parallel to the channel layer 132, and the in-layer conduction or inter-layer conduction of the channel layer 132 made of two-dimensional material is fully utilized, so that the gate length of the vertical gate-all-around transistor is the same as the thickness of the nanoscale two-dimensional material, thereby realizing an extremely short gate length vertical gate-all-around transistor, further reducing the size occupied by the vertical gate-all-around transistor, and facilitating to improve the integration of the semiconductor device including the vertical gate-all-around transistor. Secondly, the gate stack structure 14 surrounds the outer periphery of the stack structure 13, which can enhance the gate control ability of the device, thereby facilitating to improve the electrical performance of the vertical gate-all-around transistor. Furthermore, as described above, the thickness of the channel layer 132 is small, and thus when the gate stack structure 14 surrounds the outer periphery of the first electrode layer 131, channel layer 132 and second electrode layer 133, it can also prevent the strict requirement of manufacturing conditions and precision for forming the gate stack structure 14 only on the outer periphery of the channel layer 132 with small thickness, thereby reducing the manufacturing difficulty of the gate stack structure 14.

[0056] As shown in Figure 18 , the embodiment of the present application also provides a manufacturing method of a vertical gate-all-around transistor. Hereinafter, the manufacturing process will be described according to the cross-sectional view of the operation shown in Figures 1 to 17 . Specifically, the manufacturing method of the vertical gate-all-around transistor includes:

[0057] First, as shown in Figure 1 a substrate 11 is provided. Specifically, the substrate 11 can refer to the structure and material as previously described, which will not be repeated here.

[0058] As shown in Figure 2 , an isolation medium layer 12 is formed on the substrate 11.

[0059] Specifically, the material and thickness of the isolation medium layer can refer to the previous description. In addition, the formation process of the isolation medium layer can be determined according to its material. For example, in the case of the isolation medium layer material is only silicon oxide, the above-mentioned isolation medium layer can be formed by using processes such as thermal oxidation or chemical vapor deposition.

[0060] As shown in Figure 8 , a stack structure 13 is formed on the isolation medium layer 12. Along the thickness direction of the substrate 11, the stack structure 13 includes the first electrode layer 131, the channel layer 132 and the second electrode layer 133 which are sequentially stacked.

[0061] For example, the above-mentioned formation of the stack structure on the isolation medium layer can include the following steps: as shown in Figures 3 to 8 , along the thickness direction of the substrate 11, the first electrode layer 131, the channel layer 132 and the second electrode layer 133 are sequentially stacked on the isolation medium layer 12.

[0062] In actual application process, a layer of first electrode material can be formed on the isolation medium layer by using processes such as chemical vapor deposition. Next, as shown in Figure 3 , the first electrode material can be patterned by using processes such as photolithography and etching, so that the remaining part of the first electrode material forms the first electrode layer 131. Then, as shown in Figure 4 , the two-dimensional material 15 covering the isolation medium layer 12 and the first electrode layer 131 can be formed by using processes such as mechanical peeling or chemical vapor deposition. Next, as shown in Figure 5 , a mask layer 16 is formed on the part of the two-dimensional material 15 corresponding to the first electrode layer 131. The material of the mask layer 16 can be photoresist, silicon nitride or spin-on carbon, etc. The formation process of the mask layer 16 can be determined according to the material of the mask layer 16. For example, in the case of the mask layer material is photoresist, the mask layer can be formed by using photolithography process. For example, in the case of the mask layer material is silicon nitride, the mask material covering the two-dimensional material can be formed by using deposition process. Then the mask material is patterned by using processes such as photolithography and etching to obtain the mask layer. After the mask layer is formed by using the above-mentioned method, as shown in Figure 6As shown, under the masking effect of the mask layer 16, dry etching or wet etching processes can be used to selectively etch the two-dimensional material so that the remaining part of the two-dimensional material forms the channel layer 132.

[0063] After the formation of the channel layer, such as Figure 7 As shown, wet or dry etching processes can be used to first remove the mask layer. Next, processes such as chemical vapor deposition can be used to form the second electrode material covering the isolation dielectric layer, the first electrode layer, and the channel layer. Finally, as... Figure 8 As shown, photolithography and etching processes can be used to pattern the second electrode material so that the remaining part of the second electrode material forms the second electrode layer 133, thereby obtaining the stacked structure 13.

[0064] Or, after the formation of the channel layer, such as Figure 11 As shown, a gate dielectric material 17 can be formed over the existing structure using processes such as chemical vapor deposition. The existing structure includes a substrate 11, an isolation dielectric layer 12, a first electrode layer 131, a channel layer 132, and a mask layer 16. Next, as... Figure 12 As shown, photolithography and etching processes can be used to remove the portion of the gate dielectric material covering the isolation dielectric layer 12 and the mask layer 16, so that the portion of the gate dielectric material surrounding the sidewalls of the first electrode layer 131, the channel layer 132, and the mask layer 16 forms the gate dielectric layer 141 included in the gate stack structure. Then, as... Figure 13 As shown, the mask layer can be removed using wet or dry etching processes. Finally, a second electrode layer 133 can be formed on the channel layer 132 in the manner described above to obtain the stacked structure 13.

[0065] like Figure 9 and Figure 10 ,as well as Figures 15 to 17 As shown, a gate stack structure 14 is formed on the isolation dielectric layer 12. The gate stack structure 14 surrounds the outer periphery of the stack structure 13.

[0066] In practical applications, the specific formation process of the gate stack structure can be determined based on the formation process of the stack structure described above. Specifically, the specific formation process of the gate stack structure can be divided into at least the following two cases:

[0067] The first type: such as Figures 3 to 8 As shown, after the first electrode layer 131, the channel layer 132, and the second electrode layer 133 are sequentially formed on the substrate 11 along the thickness direction of the substrate 11, the gate dielectric layer and the gate electrode included in the gate stack structure are formed. Forming the above-mentioned gate stack structure may include the following steps: Figure 9As shown, a process such as chemical vapor deposition can be used to form the gate dielectric material 17 and the gate material 18, which are sequentially formed on the stack structure 13 and the isolation medium layer 12. The gate dielectric material 17 is used to manufacture the gate dielectric layer 141 included in the gate stack structure 14. The gate material 18 is used to manufacture the gate electrode 142 included in the gate stack structure 14. Next, as shown in Figure 10 As shown, a process such as photolithography and etching can be used to sequentially pattern the gate material and the gate dielectric material, and only the portions of the gate material and the gate dielectric material that cover the sidewall of the stack structure 13 are reserved. The remaining portion of the gate material forms the gate electrode 142, and the remaining portion of the gate dielectric material forms the gate dielectric layer 141, and the gate stack structure 14 includes the gate dielectric layer 141 and the gate electrode 142.

[0068] The second one is as shown in Figures 11 to 14 If, after the first electrode layer 131 and the channel layer 132 are formed, the gate dielectric layer 141 included in the gate stack structure is formed, and the second electrode layer 133 is formed only after the gate dielectric layer 141 is formed, the formation of the above-mentioned gate stack structure can include the following steps: a process such as chemical vapor deposition can be used to form the gate material covering the isolation medium layer, the gate dielectric layer, and the stack structure. Next, as shown in Figure 15 and Figure 16 As shown, a process such as photolithography and etching can be used to selectively etch the gate material, and only the portion of the gate material formed on the sidewall of the gate dielectric layer 141 is reserved, to obtain the gate stack structure 14.

[0069] Compared with the prior art, the manufacturing method of the vertical gate-all-around transistor provided by the embodiments of the present application has the beneficial effects of the vertical gate-all-around transistor, which will not be described here.

[0070] In the above description, the patterning, etching, and other technical details of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions, and the like with the required shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0071] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A vertical ring gate transistor, characterized in that, include: Substrate, An isolation dielectric layer is formed on the substrate; A stacked structure is formed on the isolation dielectric layer; along the thickness direction of the substrate, the stacked structure includes a first electrode layer, a channel layer, and a second electrode layer stacked sequentially; the channel layer is made of a two-dimensional material; and a gate stack structure formed on the isolation dielectric layer; the gate stack structure surrounds the outer periphery of the stack structure; the gate length of the gate included in the gate stack structure is equal to the thickness of the channel layer.

2. The vertical ring gate transistor according to claim 1, characterized in that, The material of the first electrode layer and / or the second electrode layer is a metallic conductive material or a two-dimensional material with metallic properties.

3. The vertical ring gate transistor according to claim 1, characterized in that, The cross-sectional area of ​​the channel layer is smaller than the cross-sectional area of ​​the first electrode layer; and / or, The cross-sectional area of ​​the second electrode layer is smaller than that of the channel layer.

4. The vertical ring gate transistor according to claim 1, characterized in that, The channel layer includes at least one two-dimensional material layer; the maximum thickness of each two-dimensional material layer is 0.6 nm to 0.8 nm.

5. The vertical ring gate transistor according to claim 1, characterized in that, The gate stack structure includes a gate dielectric layer surrounding the outer periphery of the stack structure and a gate formed on the gate dielectric layer.

6. The vertical ring gate transistor according to claim 5, characterized in that, The material of the isolation medium layer is silicon oxide and / or aluminum oxide.

7. A method for manufacturing a vertical ring gate transistor, characterized in that, include: Provide a substrate; An isolation dielectric layer is formed on the substrate; A stacked structure is formed on the isolation medium layer; Along the thickness direction of the substrate, the stacked structure includes a first electrode layer, a channel layer, and a second electrode layer stacked sequentially; the channel layer is made of a two-dimensional material. A gate stack structure is formed on the isolation dielectric layer; the gate stack structure surrounds the outer periphery of the stack structure; the length of the gate included in the gate stack structure is equal to the thickness of the channel layer.

8. The method for manufacturing a vertical ring gate transistor according to claim 7, characterized in that, The formation of a stacked structure on the isolation medium layer includes: Along the thickness direction of the substrate, a first electrode layer, a channel layer, and a second electrode layer are formed and sequentially stacked on the isolation dielectric layer.

9. The method for manufacturing a vertical ring gate transistor according to claim 8, characterized in that, The formation of the channel layer includes: A two-dimensional material is formed covering the insulating dielectric layer and the first electrode layer; A mask layer is formed on the portion of the two-dimensional material corresponding to the first electrode layer; Under the masking effect of the mask layer, the two-dimensional material is selectively etched so that the remaining part of the two-dimensional material forms the channel layer.

10. The method for manufacturing a vertical ring gate transistor according to claim 9, characterized in that, The method for manufacturing the vertical gate ring transistor after forming the channel layer and before forming the second electrode layer includes: Forming a grid dielectric material covering the existing structure; The portion of the gate dielectric material covering the isolation dielectric layer and the mask layer is removed, such that the portion of the gate dielectric material surrounding the sidewalls of the first electrode layer, the channel layer and the mask layer forms the gate dielectric layer included in the gate stack structure; Remove the mask layer.

11. The method for manufacturing a vertical ring gate transistor according to claim 7, characterized in that, The formation of the gate stack structure on the isolation dielectric layer includes: A gate dielectric material and a gate material are formed sequentially covering the stacked structure and the isolation dielectric layer; The gate material and the gate dielectric material are patterned sequentially, leaving only the portions of the gate material and the gate dielectric material covering the sidewalls of the stacked structure; wherein the remaining portion of the gate material forms the gate, the remaining portion of the gate dielectric material forms the gate dielectric layer, and the gate stacked structure includes the gate dielectric layer and the gate.

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