Solar cell and method of manufacturing the same

Abstract

The application provides a solar cell and a preparation method thereof, and belongs to the technical field of solar cells. The solar cell comprises a silicon substrate with a first polarity or a second polarity, the silicon substrate comprises opposite first and second sides; a first passivation structure is arranged on the first side of the silicon substrate, the part farthest from the silicon substrate in the first passivation structure has the first polarity; the position of the first passivation structure is a first electrode area; a second passivation structure is arranged on the side of the first passivation structure far from the silicon substrate, the part farthest from the silicon substrate in the second passivation structure has the second polarity; the position of the second passivation structure is a second electrode area, the second electrode area does not overlap with the first electrode area, and the process temperature of the second passivation structure is lower than that of the first passivation structure; a first electrode is arranged on the side of the second passivation structure far from the silicon substrate and located in the first electrode area, and a second electrode is arranged on the side of the second passivation structure far from the silicon substrate and located in the second electrode area.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of solar cells, and particularly relates to a solar cell and a preparation method thereof. BACKGROUND

[0002] In a heterojunction back contact (HBC) solar cell, a silicon substrate back side (a side facing away from a light side) is provided with an intrinsic amorphous silicon (a-Si) layer, and a base and an emitter are both provided on a side of the intrinsic amorphous silicon layer away from the silicon substrate, and the intrinsic amorphous silicon layer surface is doped with different polarities at different electrode positions. SUMMARY

[0003] The present application provides a solar cell with a new structure and a preparation method thereof.

[0004] In a first aspect, an embodiment of the present application provides a solar cell, comprising:

[0005] a silicon substrate with a first polarity or a second polarity, the silicon substrate comprising opposite first and second sides; the first polarity being used for transmitting one of an electron and a hole, and the second polarity being used for transmitting the other of the electron and the hole;

[0006] a first passivation structure provided on the first side of the silicon substrate, a portion of the first passivation structure farthest from the silicon substrate having the first polarity; the first passivation structure being located at a first electrode region;

[0007] a second passivation structure provided on a side of the first passivation structure away from the silicon substrate, a portion of the second passivation structure farthest from the silicon substrate having the second polarity; the second passivation structure being located at a second electrode region, the second electrode region being non-overlapping with the first electrode region, and a process temperature of the second passivation structure being lower than a process temperature of the first passivation structure;

[0008] a first electrode provided on a side of the second passivation structure away from the silicon substrate and located at the first electrode region, and a second electrode provided on a side of the second passivation structure away from the silicon substrate and located at the second electrode region.

[0009] Optionally, the second passivation structure is located at the second electrode region.

[0010] Optionally, the first passivation structure comprises:

[0011] a tunneling passivation sublayer;

[0012] a first passivation sublayer provided on a side of the tunneling passivation sublayer away from the silicon substrate, the first passivation sublayer having the first polarity.

[0013] Optionally, the material of the tunneling passivation sub-layer comprises at least one of silicon oxide, aluminum oxide, silicon oxynitride, silicon carbide.

[0014] The material of the first passivation sub-layer comprises at least one of doped polysilicon, doped silicon carbide.

[0015] Optionally, the thickness of the tunneling passivation sub-layer is 1nm to 3nm.

[0016] The thickness of the first passivation sub-layer is 10nm to 200nm.

[0017] Optionally, the second passivation structure comprises:

[0018] a dielectric passivation sub-layer;

[0019] a second passivation sub-layer disposed on the side of the dielectric passivation sub-layer away from the silicon substrate, the second passivation sub-layer having a second polarity.

[0020] Optionally, the material of the dielectric passivation sub-layer comprises at least one of polysilicon, amorphous silicon, silicon oxide.

[0021] The material of the second passivation sub-layer comprises at least one of doped polysilicon, doped amorphous silicon, doped silicon carbide.

[0022] Optionally, the thickness of the dielectric passivation sub-layer is 1nm to 15nm.

[0023] The thickness of the second passivation sub-layer is 1nm to 20nm.

[0024] Optionally, the first electrode region comprises a plurality of spaced strip regions, the second electrode region comprises a plurality of spaced strip regions, the strip regions of the first electrode region and the strip regions of the second electrode region are alternately distributed.

[0025] Optionally, the process temperature of the first passivation structure is 300℃ to 650℃.

[0026] The process temperature of the second passivation structure is 150℃ to 200℃.

[0027] In a second aspect, an embodiment of the present application provides a preparation method of a solar cell, the solar cell being any one of the solar cells of the embodiments of the present application, the preparation method comprising:

[0028] forming a first passivation structure in the first electrode region of the first side of the silicon substrate through a patterning process;

[0029] forming a second passivation structure in the second electrode region of the first side of the silicon substrate through a patterning process;

[0030] A first electrode is formed in a first electrode region of the first side of the silicon substrate and a second electrode is formed in a second electrode region by a patterning process.

[0031] It can be seen that, in the embodiment of the present application, the two electrodes are arranged on the back side of the silicon substrate, and the silicon substrate corresponding to the two electrodes is respectively provided with passivation layers (first passivation structure and second passivation structure) of different polarities, so that a new form of 'hybrid' HBC solar cell is provided. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 Fig. 1 is a structural schematic diagram of an HBC solar cell in the prior art;

[0033] Figure 2 Fig. 2 is a sectional structure schematic diagram of a solar cell in an embodiment of the present application;

[0034] Figure 3 Fig. 3 is a sectional structure schematic diagram of another solar cell in an embodiment of the present application;

[0035] Figure 4 Fig. 4 is a distribution schematic diagram of electrode regions in a solar cell in an embodiment of the present application;

[0036] Figure 5 Fig. 5 is a flowchart of a preparation method of a solar cell in an embodiment of the present application;

[0037] Figure 6 Fig. 6 is a sectional structure schematic diagram of a silicon substrate in a preparation method of a solar cell in an embodiment of the present application;

[0038] Figure 7 Fig. 7 is a sectional structure schematic diagram after forming an antireflection layer in a preparation method of a solar cell in an embodiment of the present application;

[0039] Figure 8 Fig. 8 is a sectional structure schematic diagram after patterning a first passivation structure in a preparation method of a solar cell in an embodiment of the present application;

[0040] Figure 9 Fig. 9 is a sectional structure schematic diagram after patterning a second passivation structure in a preparation method of a solar cell in an embodiment of the present application;

[0041] In the drawings, 1 is a first passivation structure, 11 is a tunneling passivation sublayer, 12 is a first passivation sublayer, 2 is a second passivation structure, 21 is a dielectric passivation sublayer, 22 is a second passivation sublayer, 31 is a front dielectric passivation layer, 32 is an antireflection layer, 51 is an N-type doped region, 52 is a P-type doped region, 59 is an intrinsic amorphous silicon layer, 81 is a first electrode, 82 is a second electrode, 89 is a transparent conductive oxide layer, 9 is a silicon substrate, 91 is a first electrode region, and 92 is a second electrode region. DETAILED DESCRIPTION

[0042] In order to better understand the technical solutions of the present application, the present application will be further described in detail below in combination with the drawings and specific embodiments.

[0043] It can be understood that the specific embodiments and drawings described herein are only used to explain the present application, but not to limit the present application.

[0044] It can be understood that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0045] It can be understood that, for the convenience of description, only parts related to the embodiments of the present application are shown in the drawings of the present application, and parts unrelated to the embodiments of the present application are not shown in the drawings.

[0046] In the embodiments of the present application, the "first polarity and the second polarity" refer to the types of two kinds of semiconductors, i.e., the first polarity and the second polarity are respectively P-type (transmitting holes) and N-type (transmitting electrons) without repetition; for example, the first polarity can be P-type and the second polarity can be N-type, or the first polarity can be N-type and the second polarity can be P-type.

[0047] In the embodiments of the present application, "A is located on the side of B away from C" means that A and B are both formed on the same side of C, and A is formed after B, so that at the position where A and B are both present, A is covered on B; but it does not mean that A must be covered on B at all positions, nor does it mean that B is covered with A at all positions.

[0048] In the embodiments of the present application, "the process temperature of the structure" refers to the highest temperature required to be reached in the process of forming the structure.

[0049] In the embodiments of the present application, "the patterning process" refers to a process for forming a structure with a specific pattern, which can be a photolithography process, a laser process, a wet film etching process, etc.

[0050] Reference Figure 1 The HBC (Heterojunction Back Contact) solar cell includes a silicon substrate 9, the back side (first side) of the silicon substrate 9 is provided with an intrinsic amorphous silicon layer 59, and the surface of the intrinsic amorphous silicon layer 59 is respectively formed with alternatingly distributed N-type doped regions 51 and P-type doped regions 52 to respectively transmit holes and electrons, and the two kinds of doped regions are respectively provided with electrodes of different types on the side away from the silicon substrate 9, i.e., the first electrode 81 (such as a base electrode) and the second electrode 82 (such as an emitter electrode) in a "interdigital" shape.

[0051] On the light-incident side (second side) of the silicon substrate 9, a front surface medium passivation layer 31, a reflection-reducing layer 32, and the like can be further provided in sequence.

[0052] It can be seen that, in the HBC solar cell, the PN junction is located on the back side, and the base and the emitter are also located on the back side, so that there is no electrode on the light-incident side, and the light is not blocked by the electrode, thereby reducing the optical loss, increasing the short-circuit current density, and improving the efficiency and performance.

[0053] In a first aspect, referring to Figures 2 to 4 , the embodiment of the present application provides a solar cell, which comprises:

[0054] The silicon substrate 9 has a first side and a second side opposite to each other, and has a first polarity or a second polarity; the first polarity is used for transmitting one of an electron and a hole, and the second polarity is used for transmitting the other of the electron and the hole.

[0055] The first passivation structure 1 is provided on the first side of the silicon substrate 9, and the part of the first passivation structure 1 farthest from the silicon substrate 9 has the first polarity; the first passivation structure 1 is located in the first electrode area 91.

[0056] The second passivation structure 2 is provided on the side of the first passivation structure 1 farthest from the silicon substrate 9, and the part of the second passivation structure 2 farthest from the silicon substrate 9 has the second polarity; the second passivation structure 2 is located in the second electrode area 92, and the second electrode area 92 does not overlap with the first electrode area 91; the process temperature of the second passivation structure 2 is lower than the process temperature of the first passivation structure 1.

[0057] The first electrode 81 is provided on the side of the second passivation structure 2 farthest from the silicon substrate 9 and located in the first electrode area 91, and the second electrode 82 is provided on the side of the second passivation structure 2 farthest from the silicon substrate 9 and located in the second electrode area 92.

[0058] In a first aspect, referring to Figure 2 , the solar cell of the embodiment of the present application has a silicon substrate 9, and the silicon substrate 9 has a certain polarity (first polarity or second polarity), i.e., the silicon substrate is a P-type doped or N-type doped silicon-based semiconductor.

[0059] In a first aspect, referring to Figure 2 , the silicon substrate 9 has a first side and a second side opposite to each other, wherein the second side can be a “light-incident side” for light to enter, and the first side can be a “back side” opposite to the light-incident side.

[0060] In a first aspect, referring to Figure 2 , Figure 4 , the part of the surface of the first side of the silicon substrate 9 is a first electrode area 91 for providing the first electrode 81, and the other part is a second electrode area 92 for providing the second electrode 82.

[0061] It should be understood that the first electrode region 91 and the second electrode region 92 are different regions, that is, they can be non-overlapping; furthermore, the first electrode region 91 and the second electrode region 92 can "cover" the first side of the silicon substrate 9.

[0062] It should be understood that it is also feasible if the first electrode region 91 and the second electrode region 92 do not cover the first side of the silicon substrate 9.

[0063] Optionally, the first electrode region 91 includes a plurality of spaced strip regions, and the second electrode region 92 includes a plurality of spaced strip regions, with the strip regions of the first electrode region 91 and the strip regions of the second electrode region 92 being distributed alternately.

[0064] As one embodiment of the present invention, refer to Figure 4 The first electrode region 91 may include multiple parallel and spaced strips, and the second electrode region 92 also includes multiple parallel and spaced strips. The strips of the two electrode regions are also parallel to each other and are alternately distributed along the width direction of the strips (of course, the strips of the two electrode regions can be referenced). Figure 4 They may be in contact with each other on the sides, or they may have a certain gap; thus, the first electrode 81 and the second electrode 82, located in the first electrode region 91 and the second electrode region 92 respectively, are distributed in an "interdigital" shape.

[0065] Reference Figure 2 On the first side of the silicon substrate 9, a first passivation structure 1 (passivation layer) is provided in the first electrode region 91. That is, the first passivation structure 1 is "patterned" and its location is the first electrode region 91 (therefore, the first passivation structure 1 is distributed throughout and does not exceed the first electrode region 91); and the first passivation structure 1 has a certain polarity (first polarity) at least in the surface layer furthest from the silicon substrate 9. This polarity is the same as or opposite to the polarity of the silicon substrate 9.

[0066] Reference Figure 2 On the side of the first passivation structure 1 away from the silicon substrate 9, there is also a second passivation structure 2. The second passivation structure 2 is located in the second electrode region 92, that is, the second passivation structure 2 is also "patterned", and its location is the second electrode region 92 (therefore, the second passivation structure 2 is full and does not exceed the second electrode region 92).

[0067] Furthermore, since the first passivation structure 1 and the first passivation structure 2 are located in different electrode regions, they do not overlap. For example, if the first electrode region 91 and the second electrode region 92 are "covered" on the first side of the silicon substrate 9, then since the first passivation structure 1 and the second passivation structure 2 respectively fill the first electrode region 91 and the second electrode region 92, reference is made. Figure 2 The sides of the two objects can be in contact with each other.

[0068] Moreover, the second passivation structure 2 has a polarity opposite to the first passivation structure 1 (second polarity) at least in the surface layer farthest from the silicon substrate 9; for example, if the first passivation structure 1 is P-type, the second passivation structure 2 is N-type, and if the first passivation structure 1 is N-type, the second passivation structure 2 is P-type. Thus, in the first passivation structure 1 and the second passivation structure 2, the polarity of one is the same as that of the silicon substrate 9, and the polarity of the other is opposite to that of the silicon substrate 9.

[0069] That is, referring to Figure 2 , the first electrode region 91 and the second electrode region 92 on the first side of the silicon substrate 9 are respectively provided with the first passivation structure 1 and the second passivation structure 2, and the first passivation structure 1 and the second passivation structure 2 are respectively provided with the first electrode 81 and the second electrode 82; moreover, the polarities of the first passivation structure 1 and the second passivation structure 2 are opposite, and the polarity of one is the same as that of the silicon substrate 9, and the polarity of the other is opposite to that of the silicon substrate 9.

[0070] Thus, one of the first passivation structure 1 and the second passivation structure 2 can form a tunneling junction on the back side of the silicon substrate 9.

[0071] Among them, the first passivation structure 1 and the second passivation structure 2 are distinguished by the contrast of their process temperatures, that is, the process temperature of the second passivation structure 2 is lower than that of the first passivation structure 1. Thus, the first passivation structure 1 is a high-temperature passivation structure (high-temperature passivation layer) with a higher process temperature, and the second passivation structure 2 is a low-temperature passivation structure (low-temperature passivation layer) with a lower process temperature.

[0072] It should be understood that although the second passivation structure 2 and the first passivation structure 1 have no overlap (that is, the second passivation structure 2 is not "pressed" on the first passivation structure 1), the formation sequence of the second passivation structure 2 and the first passivation structure 1 in the structure of the solar cell product can be determined; because if the first passivation structure 1 is formed first, the heating in the subsequent process of forming the second passivation structure 2 will not affect the already formed first passivation structure 1; and if the second passivation structure 2 is formed first, the heating in the subsequent process of forming the first passivation structure 1 will destroy the already formed second passivation structure 2.

[0073] Optionally, the process temperature of the first passivation structure 1 is 300-650°C; the process temperature of the second passivation structure 2 is 150-200°C.

[0074] As a mode of the embodiment of the present application, the highest temperature (process temperature) during forming the first passivation structure 1 can be 300-650℃, further can be 400-600℃; correspondingly, the highest temperature (process temperature) during forming the second passivation structure 2 can be 150-200℃, further can be 170-190℃.

[0075] With reference to Figure 2 On the side of the second passivation structure 2 away from the silicon substrate 9, a first electrode 81 is provided, which does not exceed the first electrode area 91, i.e. the first electrode 81 is in communication with the silicon substrate 9 through the first passivation structure 1; and on the side of the second passivation structure 2 away from the silicon substrate 9, a second electrode 82 is also provided, which does not exceed the second electrode area 92, i.e. the second electrode 82 is in communication with the silicon substrate 9 through the second passivation structure 2.

[0076] Among the first electrode 81 and the second electrode 82, one is an emitter and the other is a base.

[0077] Further, the electrode on the passivation structure with the same polarity as the substrate 9 is the base, and the electrode on the passivation structure with the opposite polarity to the substrate 9 is the emitter.

[0078] It should be understood that the different kinds of electrodes cannot contact each other.

[0079] As can be seen, in the embodiment of the present application, the two kinds of electrodes are both provided on the back side of the silicon substrate 9, and the silicon substrate 9 corresponding to the two kinds of electrodes is respectively provided with passivation layers (the first passivation structure 1 and the second passivation structure 2) with different polarities, so that a new form of "hybrid" HBC solar cell is provided.

[0080] Optionally, the first passivation structure 1 comprises:

[0081] a tunneling passivation sublayer 11;

[0082] a first passivation sublayer 12 provided on the side of the tunneling passivation sublayer 11 away from the silicon substrate 9, the first passivation sublayer 12 having a first polarity.

[0083] With reference to Figure 3 As a mode of the embodiment of the present application, the first passivation structure 1 can specifically comprise two sublayers, i.e. a tunneling passivation sublayer 11 in contact with the silicon substrate 9 and a first passivation sublayer 12 provided on the tunneling passivation sublayer 11; wherein at least the first passivation sublayer 12 has a first polarity opposite to that of the second passivation structure 2, such as being doped as P type or N type.

[0084] It should be understood that the above tunneling passivation sublayer 11 and the first passivation sublayer 12 should both be patterned, and the patterns are the same.

[0085] Optionally, the material of the tunneling passivation sub-layer 11 comprises at least one of silicon oxide, aluminum oxide, silicon oxynitride, silicon carbide;

[0086] The material of the first passivation sub-layer 12 comprises at least one of doped polysilicon and doped silicon carbide.

[0087] As an embodiment of the present application, in the first passivation structure 1, the material of the tunneling passivation sub-layer 11 can be selected from a medium material such as silicon oxide (SiOx), aluminum oxide (AlOx), silicon oxynitride (SiNOx), and silicon carbide (SiCx). The tunneling passivation sub-layer 11 can be undoped and thus has no polarity.

[0088] The first passivation sub-layer 12 in the first passivation structure 1 has a first polarity opposite to that of the second passivation structure 2, which can be P-type or N-type doped polysilicon, silicon carbide, or the like.

[0089] For example, if the first polarity is P-type, the first passivation sub-layer 12 can be doped with a group III element, such as boron (B); if the first polarity is N-type, the first passivation sub-layer 12 can be doped with a group V element, such as phosphorus (P).

[0090] The use of doped polysilicon, silicon carbide, or the like in the first passivation sub-layer 12 can further reduce optical absorption, achieve a higher concentration of effective doping, reduce the contact resistance of the electrode, and improve the cell fill factor.

[0091] Optionally, the thickness of the tunneling passivation sub-layer 11 is 1 nm to 3 nm.

[0092] The thickness of the first passivation sub-layer 12 is 10 nm to 200 nm.

[0093] As an embodiment of the present application, the thickness (the size in the direction perpendicular to the first side of the silicon substrate 9) of the tunneling passivation sub-layer 11 in the first passivation structure 1 can be 1 nm to 3 nm, further 1.5 nm to 2 nm; and the thickness of the first passivation sub-layer 12 can be 10 nm to 200 nm, further 80 nm to 120 nm.

[0094] Optionally, the second passivation structure 2 comprises:

[0095] a medium passivation sub-layer 21;

[0096] a second passivation sub-layer 22 arranged on the side of the medium passivation sub-layer 21 away from the silicon substrate 9, the second passivation sub-layer 22 having a second polarity.

[0097] Reference Figure 3As a manner of the embodiment of the present application, the second passivation structure 2 can also include two sub-layers, i.e., a dielectric passivation sub-layer 21 close to the silicon substrate 9 and a second passivation sub-layer 22 arranged on the dielectric passivation sub-layer 21; wherein at least the second passivation sub-layer 22 has a second polarity opposite to the first passivation structure 1.

[0098] It should be understood that the above dielectric passivation sub-layer 21 and the second passivation sub-layer 22 should both be patterned and have the same pattern.

[0099] Optionally, the material of the dielectric passivation sub-layer 21 includes at least one of polycrystalline silicon, amorphous silicon, and silicon oxide.

[0100] The material of the second passivation sub-layer 22 includes at least one of doped polycrystalline silicon, doped amorphous silicon, and doped silicon carbide.

[0101] As a manner of the embodiment of the present application, the dielectric passivation sub-layer 21 can specifically use materials such as amorphous silicon, polycrystalline silicon (poly-Si, which can be specifically microcrystalline silicon or nanocrystalline silicon), etc., which can be a layer or a stacked structure of layers of different materials.

[0102] The dielectric passivation sub-layer 21 can be non-polar, i.e., an intrinsic undoped layer.

[0103] The second passivation sub-layer 22 has a polarity opposite to the first passivation structure 1, for example, the material thereof can be doped polycrystalline silicon, amorphous silicon, silicon carbide, etc., and the doping element can use Group III elements (such as boron) or Group V elements (such as phosphorus).

[0104] Optionally, the thickness of the dielectric passivation sub-layer 21 is 1 nm to 15 nm.

[0105] The thickness of the second passivation sub-layer 22 is 1 nm to 20 nm.

[0106] As a manner of the embodiment of the present application, in the second passivation structure 2, the thickness of the dielectric passivation sub-layer 21 can be 1 nm to 15 nm, and further can be 5 nm to 8 nm; and the thickness of the second passivation sub-layer 22 can be 1 nm to 20 nm, and further can be 5 nm to 15 nm.

[0107] It should be understood that the above is only an exemplary introduction to the partial structure of the solar cell of the embodiment of the present application, and the solar cell of the embodiment of the present application can also satisfy other characteristics.

[0108] For example, the silicon substrate 9 can be in the form of single crystal silicon or polycrystalline silicon, and is doped to produce a required polarity.

[0109] For another example, the second side (light-incident side) of the silicon substrate 9 can form a textured surface (light-trapping surface) to increase the absorption of light.

[0110] For example, referring to Figure 3 The second side of the silicon substrate 9 can be formed with a complete front surface medium passivation layer 31, which can specifically adopt the same material as the second passivation sub-layer 22 of the second passivation structure 2.

[0111] For example, referring to Figure 3 The second side of the silicon substrate 9 (e.g., outside the front surface medium passivation layer 31) can also be provided with an anti-reflection layer 32 for reducing light emission, which is also a protective layer (AR film), which can specifically adopt one or more of silicon oxide, silicon nitride, silicon oxynitride, etc., and can be a single layer or a stack structure of multiple layers with different refractive indexes.

[0112] For example, referring to Figure 3 A transparent conductive oxide (TCO) layer 89 for improving contact resistance can also be provided between the electrode and the second passivation structure 2, which can be a single layer of materials such as indium tin oxide (ITO), indium tungsten oxide (IWO), aluminum zinc oxide (AZO), indium cerium oxide (ICO), indium molybdenum oxide (IMO), indium hafnium oxide (IHO), zirconium titanium calcium doped indium oxide (SCOT), etc., or a stack structure of multiple layers of different materials.

[0113] For example, referring to Figure 3 To prevent the transparent conductive oxide layer 89 from conducting different electrodes, the transparent conductive oxide layer 89 in different electrode regions can have gaps between them.

[0114] For example, referring to Figure 3 The first electrode 81 and the second electrode 82 can be provided in the same layer (simultaneously prepared and made of the same material), which can adopt metal materials such as silver, copper, aluminum, copper-coated tin, silver-coated copper, etc., or composite electrodes of multiple materials such as nickel, copper, aluminum, and tin.

[0115] In a second aspect, referring to Figures 2 to 9 The present application embodiment provides a preparation method of a solar cell, wherein the solar cell is any one of the solar cells of the present application embodiments.

[0116] The preparation method of the present application embodiment is used to prepare the above solar cell.

[0117] For example, referring to Figure 5 The preparation method of the solar cell of the present application embodiment includes:

[0118] S101, forming a first passivation structure 1 in a first electrode region 91 on a first side of a silicon substrate 9 through a patterning process.

[0119] S102, forming the second passivation structure 2 in the second electrode area 92 on the first side of the silicon substrate 9 by a patterning process.

[0120] S103, forming the first electrode 81 in the first electrode area 91 and the second electrode 82 in the second electrode area 92 on the first side of the silicon substrate 9 by a patterning process.

[0121] To prepare the above solar cell, the first passivation structure 1 in the first electrode area 91 and the second passivation structure 2 in the second electrode area 92 can be formed on the first side of the silicon substrate 9 by a patterning process in sequence; then the first electrode 81 and the second electrode 82 can be formed in the first electrode area 91 and the second electrode area 92 respectively.

[0122] It should be understood that the above is only an exemplary introduction to the method for preparing the solar cell of the embodiment of the present application, and the method for preparing the solar cell of the embodiment of the present application can also satisfy other characteristics.

[0123] For example, the silicon substrate 9 can be formed by a Czochralski method (CZ), a zone melting method (FZ), a casting method, etc.

[0124] For another example, the silicon substrate 9 can be cleaned and polished before other steps are performed.

[0125] For another example, when the second side (light-incident side) of the silicon substrate 9 is textured, the texturing can be performed by a wet chemical texturing method, a dry reactive ion etching (RIE) texturing method, etc.

[0126] For another example, the above front-side dielectric passivation layer 31 can be formed on the second side of the silicon substrate 9 by a plasma enhanced chemical vapor deposition (PECVD) method or a hot wire chemical vapor deposition (HWCVD) method, etc.

[0127] For another example, the above anti-reflective layer 32 (protective layer) can be formed on the second side of the silicon substrate 9 by a PECVD method, etc.

[0128] For another example, when the above first passivation structure 1 is prepared, a complete first passivation structure 1 can be formed first, and then the complete first passivation structure 1 can be patterned to remove the first passivation structure 1 in the second electrode area 92; and the complete first passivation structure 1 can be formed by any one of the following methods:

[0129] (1) Utilize the low pressure chemical vapor deposition (LPCVD, Low Pressure Chemical Vapor Deposition) process to form the tunneling passivation sublayer 11 and intrinsic amorphous silicon layer in turn, and then dope the intrinsic amorphous silicon layer by high temperature diffusion (such as phosphorus diffusion or boron diffusion), to form the first passivation sublayer 12.

[0130] At this time, due to the oxygen-containing diffusion environment, a very thin PSG (phosphorus-containing silicon oxide) or BSG (boron-containing silicon oxide) structure will be formed on the surface of the first passivation sublayer 12 at the same time, which can be used as a mask in subsequent processes.

[0131] (2) Utilize the LPCVD process to form the tunneling passivation sublayer 11 and in-situ doped amorphous silicon layer in turn, and then utilize high temperature annealing or excimer laser annealing (ELA, Excimer Laser Annealing) to crystallize the amorphous silicon in the in-situ doped amorphous silicon layer into polycrystalline silicon, and activate the doping elements therein, so that the in-situ doped amorphous silicon layer forms the first passivation sublayer 12.

[0132] During the high temperature annealing process, an appropriate amount of oxygen (O2) can also be introduced synchronously, thereby also forming a PSG (or BSG) structure on the surface of the first passivation sublayer 12 synchronously, which is used as a mask in subsequent processes.

[0133] (3) Utilize the PECVD process to form the tunneling passivation sublayer 11, in-situ doped amorphous silicon layer, and silicon oxynitride layer in turn, and then utilize high temperature annealing or ELA to crystallize the amorphous silicon in the in-situ doped amorphous silicon layer into polycrystalline silicon, and activate the doping elements therein, so that the in-situ doped amorphous silicon layer forms the first passivation sublayer 12.

[0134] Among them, the silicon oxynitride layer does not belong to the first passivation structure 1, but is used as a mask in subsequent processes.

[0135] (4) Utilize the PECVD process to form the tunneling passivation sublayer 11 and in-situ doped amorphous silicon layer in turn, and then utilize high temperature annealing or ELA to crystallize the amorphous silicon in the in-situ doped amorphous silicon layer into polycrystalline silicon, and activate the doping elements therein, so that the in-situ doped amorphous silicon layer forms the first passivation sublayer 12.

[0136] Among them, this way does not form a mask.

[0137] For example, after forming the complete first passivation structure 1, it can be patterned by any of the following methods:

[0138] Method 1: When the first passivation structure 1 is formed by any one of the above methods (1) to (3), the mask with PSG (or BSG) structure, silicon oxynitride layer, etc. is formed, so the mask of the second electrode area 92 can be removed by laser opening, and then the first passivation structure 1 of the second electrode area 92 is removed by wet etching, while the first passivation structure 1 of the first electrode area 91 is protected by the mask and will not be etched, thereby completing the patterning of the first passivation structure 1; then, the mask of the first electrode area 91 is removed.

[0139] Method 2: When the first passivation structure 1 is formed by the above method (4) without a mask, then the ink can be printed on the first electrode area 91 as a mask by inkjet printing, and then the first passivation structure 1 of the second electrode area 92 is removed by wet etching; then, the ink mask of the first electrode area 91 is removed.

[0140] It can be seen that when the complete first passivation structure 1 is formed according to the above methods (1) and (2), it is equivalent to forming a mask (a mask for patterning the first passivation structure 1) at the same time as preparing the first passivation structure 1, so that it needs a separate step of preparing a mask, and the process is simple, and can further reduce the process of preparing a mask (such as forming ink).

[0141] It can be seen that when the complete first passivation structure 1 is formed according to the above method (1), the diffusion elements in the process of forming the first passivation sub-layer 12 can also form a phosphorus or boron diffusion layer on the second side of the silicon substrate 9 at the same time, which plays a role of phosphorus or boron gettering, and the diffusion layer will be naturally removed at the same time as the subsequent patterning (wet etching) of the first passivation structure 1, so that it neither needs to increase the process nor changes the structure of the second side of the silicon substrate 9.

[0142] For example, according to the requirements of the properties of the surface of the silicon substrate 9 of the second electrode area 92, a corresponding wet etching process can be selected to form a polished surface, a micro-textured surface, a textured surface, etc. on the surface of the second electrode area 92 of the silicon substrate 9 when patterning the first passivation structure 1.

[0143] For example, if the surface of the second electrode area 92 of the silicon substrate 9 is to be textured when the first passivation structure 1 is patterned, the textured surface on the second side of the silicon substrate 9 can also be formed at the same time.

[0144] For example, the second passivation structure 2 can also be formed by a physical vapor deposition (PVD) process, a rapid plasma deposition (RPD) process, or the like, and then ink is printed on the second electrode region 92 as a mask, and the second passivation structure 2 of the first electrode region 91 is removed by wet etching to obtain the patterned second passivation structure 2.

[0145] For example, when the second passivation sublayer 22 is doped (for example, boron-doped), oxygen (O), carbon (C), nitrogen (N), or the like can also be doped at the same time to further broaden the band gap, improve the doping quality, and reduce optical absorption.

[0146] For example, the above transparent conductive oxide layer 89 can also be formed on the first side of the silicon substrate 9 by a PVD process, an RPD process, or the like, and the transparent conductive oxide layer 89 of the first electrode region 91 and the second electrode region 92 is separated by a mask and wet etching, laser etching, etchant etching, or the like.

[0147] For example, when the second passivation sublayer 22 is amorphous silicon material, the transparent conductive oxide layer 89 of the first electrode region 91 can also be completely removed by laser etching, and the amorphous silicon of the second passivation sublayer 22 on the surface of the first electrode region 91 is crystallized by the energy of the laser to reduce the tunneling resistance of the tunnel junction.

[0148] For example, the above first electrode 81 and the second electrode 82 can be provided in the same layer and simultaneously formed by screen printing, electroplating, PVD (for example, evaporation), or the like.

[0149] Example 1:

[0150] The method for manufacturing a solar cell according to an embodiment of the present application specifically comprises the following steps.

[0151] A101, a silicon wafer (silicon substrate 9) of N type (first polarity) is cleaned and polished to obtain a structure as shown in FIG. 1. Figure 6

[0152] A102, a silicon oxide tunnel layer (tunnel passivation sublayer 11) and an intrinsic amorphous silicon layer are formed on the back side (first side) of the silicon wafer by LPCVD, and the intrinsic amorphous silicon layer is doped to form an N-type (first polarity) by subsequent high-temperature phosphorus diffusion, to obtain an N-type amorphous silicon layer (first passivation sublayer 12), and the surface is synchronously grown as a PSG mask.

[0153] The thickness of the silicon oxide tunnel layer is 1.5 nm, and the thickness of the N-type amorphous silicon layer is 120 nm.

[0154] ​It can be seen that the first passivation structure 1 and the silicon substrate 9 have the same polarity (the first polarity) in the embodiment of the present application. It should be understood that if the polarity of the first passivation structure 1 is opposite to the polarity of the silicon substrate 9, and the polarity of the second passivation structure 2 is the same as the polarity of the silicon substrate 9, it is also feasible.

[0155] A103, forming a rough surface by wet chemical texturing on the light-entering side (the second side) of the silicon wafer.

[0156] A104, forming a passivation layer of amorphous silicon (front surface medium passivation layer 31) by PECVD on the light-entering side of the silicon wafer.

[0157] A105, forming an AR film (antireflection layer 32) of a silicon oxide and silicon nitride stack by PECVD on the light-entering side of the silicon wafer, to obtain the structure as shown in FIG. 1. Figure 7

[0158] A106, removing the PSG mask on the surface of the N-type amorphous silicon layer of the second electrode area 92 by laser mask opening.

[0159] A107, removing the N-type amorphous silicon layer and the silicon oxide tunneling layer of the second electrode area 92 by wet etching, while forming a micro-rough surface on the surface of the second electrode area 92 on the back side of the silicon wafer, to obtain a patterned N-type amorphous silicon layer and a silicon oxide tunneling layer (the first passivation structure 1).

[0160] Then, the PSG mask is removed by wet etching, to obtain the structure as shown in FIG. 2. Figure 8

[0161] A108, forming an intrinsic amorphous silicon (medium passivation sublayer 21) and a boron-doped P-type (second polarity) amorphous silicon (second passivation sublayer 22) on the back side of the silicon wafer by RPD, in sequence, to obtain the second passivation structure 2.

[0162] The thickness of the intrinsic amorphous silicon layer can be 10 nm, and the thickness of the P-type amorphous silicon layer can be 12 nm.

[0163] A109, forming an ink as a mask on the surface of the P-type amorphous silicon of the second electrode area 92 by inkjet printing, and removing the intrinsic amorphous silicon and the P-type amorphous silicon of the first electrode area 91 by wet etching, to obtain the second passivation structure 2 located in the second electrode area 92, and then removing the ink of the second electrode area 92, to obtain the structure as shown in FIG. 3. Figure 9

[0164] A110, forming an ITO layer (transparent conductive oxide layer 89) on the back side of the silicon wafer by PVD.

[0165] ​​​A111, the ITO layer at the junction of the first electrode region 91 and the second electrode region 92 is removed by laser etching, i.e. the ITO layer corresponding to the first electrode 81 and the second electrode 82 is separated respectively.

[0166] A112, the silver electrodes (the first electrode 81 and the second electrode 82) in the first electrode region 91 and the second electrode region 92 respectively are formed by screen printing on the back side of the silicon wafer, obtaining the structure as shown in Figure 3 .

[0167] The solar cell of the embodiment of the present application is tested for performance, and the photoelectric conversion efficiency of the cell is measured to be 25.4%.

[0168] Therefore, the solar cell of the embodiment of the present application has excellent performance.

[0169] Example 2:

[0170] The method for preparing the solar cell of the embodiment of the present application is similar to that of Example 1.

[0171] The difference is that, in Example 2, the steps A106 and A107 are directly performed after the step A102.

[0172] In the patterning of the step A107, the second electrode region 92 on the back side of the silicon wafer is formed into a textured surface, and at the same time, the surface on the light-incident side of the silicon wafer is also formed into a textured surface, so that it is not necessary to specially texturize the light-incident side of the silicon wafer, i.e. the step A103 is not necessary, and the steps A104, A105, A108, A109, A110 and A111 can be sequentially performed.

[0173] The solar cell of the embodiment of the present application is tested for performance, and the photoelectric conversion efficiency of the cell is measured to be 25.5%.

[0174] Therefore, the solar cell of the embodiment of the present application has excellent performance, and the preparation process is further simplified.

[0175] It can be understood that the above embodiments are only exemplary embodiments for illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the present application, and these modifications and improvements are also considered to be within the protection scope of the present application.

Claims

1. A solar cell, characterized in that, include: A silicon substrate having a first polarity or a second polarity, the silicon substrate including opposing first and second sides; the first polarity is used to transport one of electrons and holes, and the second polarity is used to transport the other of electrons and holes; A first passivation structure is disposed on a first side of the silicon substrate, wherein the portion of the first passivation structure furthest from the silicon substrate has a first polarity; the location of the first passivation structure is a first electrode region; A second passivation structure is provided on the side of the first passivation structure away from the silicon substrate. The portion of the second passivation structure furthest from the silicon substrate has a second polarity. The location of the second passivation structure is a second electrode region. The second electrode region does not overlap with the first electrode region. The process temperature of the second passivation structure is lower than that of the first passivation structure. A first electrode is disposed on the side of the second passivation structure away from the silicon substrate and located in the first electrode region, and a second electrode is disposed on the side of the second passivation structure away from the silicon substrate and located in the second electrode region; The electrode located on the passivation structure with the same polarity as the silicon substrate is the base electrode, while the electrode located on the passivation structure with the opposite polarity to the silicon substrate is the emitter electrode. The first passivation structure is formed before the second passivation structure; When patterning the first passivation structure, the method further includes: forming a textured surface on the surface of the second electrode region of the silicon substrate and on the second side of the silicon substrate; The second passivation structure includes a dielectric passivation sublayer and a second passivation sublayer disposed on the side of the dielectric passivation sublayer away from the silicon substrate. The second passivation sublayer has a second polarity. The second passivation sublayer is doped with oxygen, carbon and nitrogen elements to widen the band gap of the second passivation sublayer.

2. The solar cell according to claim 1, characterized in that, The first passivation structure includes: Tunneling through the passivation sublayer; A first passivation sublayer is disposed on the side of the tunneling passivation sublayer away from the silicon substrate, and the first passivation sublayer has a first polarity.

3. The solar cell according to claim 2, characterized in that, The material of the tunneling passivation sublayer includes at least one of silicon oxide, aluminum oxide, silicon oxynitride, and silicon carbide; The material of the first passivation sublayer includes at least one of doped polycrystalline silicon and doped silicon carbide.

4. The solar cell according to claim 2, characterized in that, The thickness of the tunneling passivation sublayer is between 1 nm and 3 nm; The thickness of the first passivation sublayer is between 10 nm and 200 nm.

5. The solar cell according to claim 1, characterized in that, The material of the dielectric passivation sublayer includes at least one of polycrystalline silicon, amorphous silicon, and silicon oxide; The material of the second passivation sublayer includes at least one of doped polycrystalline silicon, doped amorphous silicon, and doped silicon carbide.

6. The solar cell according to claim 1, characterized in that, The thickness of the dielectric passivation sublayer is between 1 nm and 15 nm. The thickness of the second passivation sublayer is between 1 nm and 20 nm.

7. The solar cell according to claim 1, characterized in that, The first electrode region includes multiple spaced strip-shaped regions, and the second electrode region includes multiple spaced strip-shaped regions, with the strip-shaped regions of the first electrode region and the strip-shaped regions of the second electrode region being distributed alternately.

8. The solar cell according to claim 1, characterized in that, The process temperature for the first passivation structure is between 300°C and 650°C. The process temperature for the second passivation structure is between 150°C and 200°C.

9. A method for preparing a solar cell, characterized in that, The solar cell is a solar cell according to any one of claims 1 to 8, and the preparation method includes: A first passivation structure is formed in the first electrode region on the first side of the silicon substrate by a patterning process; A second passivation structure is formed in the second electrode region on the first side of the silicon substrate using a patterning process; A first electrode is formed in a first electrode region on a first side of the silicon substrate using a patterning process, and a second electrode is formed in a second electrode region.

Images