A high-precision fractional divider applied to a wideband phase-locked loop

Abstract

The application discloses a high-precision fractional divider applied to a wideband phase-locked loop and belonging to the field of digital circuits, comprising a 4 / 5 dual-mode frequency divider module, a 19bit programmable counter module and a programmable sigma-delta modulator module; the 4 / 5 dual-mode frequency divider module controls the switching of the 4 / 5 frequency division ratio according to the MC signal generated by the 19bit programmable counter module and performs pre-frequency division on the output signal of a VCO; the 19bit programmable counter module is connected with the 4 / 5 dual-mode pre-frequency division clock signal, generates a final frequency division signal through the 19bit configuration number control frequency division ratio; in the programmable sigma-delta modulator module, the 32bit fractional configuration input Fnum / Fden is modulated into a series of output sequences through the modulator, is added with an integer part PLL_N and enters the 19bit programmable counter module, generates a randomly changed instantaneous frequency division ratio, and the average value of the instantaneous frequency division ratio is the value of the final fractional frequency division ratio. The application can realize high-precision fractional frequency division on the input signal of 7.5GHz-15GHz, the step can reach 0.047Hz, and meanwhile, the phase-locked loop system has a lower fractional spur.

Description

Technical Field

[0001] This invention relates to the field of radio frequency circuit technology, and in particular to a high-precision fractional frequency divider for use in broadband phase-locked loops. Background Technology

[0002] Wireless communication technology plays a vital role in modern information exchange, and its development is closely related to phase-locked loops (PLLs), leading to increasing research into PLL technology. In wireless transceivers, PLLs provide local oscillation signals for modulation or demodulation, and they also provide clock signals for digital circuit systems. PLLs are crucial for the normal operation of the entire transceiver system. As an indispensable and important module in PLLs, the frequency divider's quality determines the overall performance of the PLL.

[0003] Phase-locked loops (PLLs) can be classified into integer and fractional frequency division based on their division ratios. Integer frequency division has a minimum step size that is an integer multiple of the reference frequency, and its frequency accuracy is limited by the reference frequency. Fractional frequency division can achieve fractional division ratios, resulting in higher frequency accuracy. Fractional frequency division is achieved by dynamically switching the instantaneous division ratio, but this can lead to fractional spurious signals, affecting the spectral purity of the output signal. A common method for eliminating fractional spurious signals is Σ-Δ modulation. With the rapid development of radar, millimeter-wave, and communication technologies, the requirements for key indicators such as operating frequency and phase noise of fractional frequency dividers are becoming increasingly stringent. Therefore, it is essential to design a fractional frequency divider with a wide frequency range, high accuracy, low phase noise, and low spurious performance in the system. Summary of the Invention

[0004] The purpose of this invention is to provide a high-precision fractional frequency divider for use in broadband phase-locked loops, in order to solve the problems in the background art.

[0005] To solve the above technical problems, the present invention provides a high-precision fractional frequency divider for broadband phase-locked loops, including a 4 / 5 dual-mode frequency divider module, a 19-bit programmable counter module, and a programmable Σ-Δ modulator module;

[0006] The 4 / 5 dual-mode frequency divider module controls the switching of the 4 / 5 division ratio based on the MC signal generated by the subsequent 19-bit programmable counter module, and pre-divides the output signal of the VCO.

[0007] The 19-bit programmable counter module is connected to a 4 / 5 dual-mode pre-division clock signal and generates the final division signal by controlling the division ratio through a 19-bit configuration number.

[0008] In the programmable Σ-Δ modulator module, the 32-bit fractional configuration input Fnum / Fden is modulated by the modulator and converted into a series of output sequences. These output sequences are added to the integer part PLL_N and fed into the 19-bit programmable counter module to generate randomly changing instantaneous division ratios. The average value of these instantaneous division ratios is the final fractional division ratio.

[0009] In one embodiment, the 4 / 5 dual-mode divider module includes three cascaded fully differential CML D flip-flops, the first and second being D flip-flops with embedded AND gate logic; the output signal finP of the VCO after passing through a buffer is connected to the clock CLK port of the three D flip-flops, and the inverted output signal finN of the VCO after passing through a buffer is connected to the inverted clock CLKn port of the three D flip-flops.

[0010] The input of the first D flip-flop is the AND of ports A and B. Port A is connected to the positive output Q of the third D flip-flop, and port B is connected to the control signal MC.

[0011] The input terminal A of the second D flip-flop is connected to the inverted output terminal QN of the third D flip-flop, and the input terminal B is connected to the inverted output terminal QN of the first D flip-flop.

[0012] The input D of the third D flip-flop is connected to the positive output Q of the second D flip-flop; the outputs Q and QN of the third D flip-flop are a pair of differential signals Fpre_p and Fpre_n after being divided by a 4 / 5 dual-mode frequency divider.

[0013] In one embodiment, the D flip-flop with embedded AND gate logic includes transistors Q1 to Q20 and resistors R1 to R8; wherein,

[0014] The bases of transistors Q1 and Q2 are connected to the positive input terminal A and the negative input terminal An, respectively. The bases of transistors Q3 and Q4 are connected to the positive input terminal B and the negative input terminal Bn, respectively. The emitters of transistors Q1 and Q2 are both connected to the collector of transistor Q3. The collector of transistor Q1 is simultaneously connected to the first terminal of resistor R1, the base of Q5, the collector of Q6, and the base of Q8. The collector of transistor Q2 is connected to the first terminal of resistor R2 and the base of Q4. The collector of transistor Q11, the collector of transistor Q5, the base of transistor Q6, and the base of transistor Q7 are all connected to the collector of transistor Q11; the emitters of transistors Q3 and Q4 are both connected to the collector of transistor Q11; the emitters of transistors Q5 and Q6 are both connected to the collector of transistor Q12; the collector of transistor Q7 is simultaneously connected to the first terminal of resistor R3, the base of transistor Q10, the collector of transistor Q9, and the base of transistor Q17; the collector of transistor Q8 is simultaneously connected to the first terminal of resistor R4, the base of transistor Q9, the collector of transistor Q10, and the base of transistor Q17. The base of transistor Q8 is connected to the collector of transistor Q13; the emitters of transistors Q9 and Q10 are connected to the collector of transistor Q14; the bases of transistors Q11 and Q14 are connected to the positive clock input CLK; the bases of transistors Q12 and Q13 are connected to the negative clock input CLKn; the emitters of transistors Q11 and Q12 are connected to the collector of transistor Q15; the emitters of transistors Q13 and Q14 are connected to the collector of transistor Q16. Collector; the collectors of transistors Q17 and Q18 and the second terminals of R1 to R4 are all connected to VCC; the emitter of transistor Q17 is connected to both the collector of Q19 and the positive output terminal Q; the emitter of transistor Q18 is connected to both the collector of Q20 and the inverted output terminal QN; the bases of transistors Q15, Q16, Q19, and Q20 are all connected to the bias voltage Vbias, and the emitters are grounded through resistors R5, R6, R7, and R8, respectively.

[0015] In one embodiment, the 19-bit programmable counter module includes a 17-bit pulse counter and a 2-bit synchronous programmable counter; wherein the 17-bit pulse counter is composed of 17 ECL2 dividers with set terminals and a counting termination detection circuit.

[0016] The dual-mode frequency divider signal Fpre enters the clock input of the first ECL2 frequency divider. Starting from the first stage, the output of each subsequent stage is connected to the clock input of the next stage in sequence. The programmable control bits DIV_N<18:2> are connected to the preset inputs PI of the 17 ECL2 frequency dividers in sequence. The inverted outputs QN of the 17 ECL2 frequency dividers are all connected to the input of the count termination detection logic circuit in sequence to detect the state of each QN. The output signal LD ​​of the count termination detection logic circuit is connected to the set input of the 17 ECL2 frequency dividers and the select input of the two 2-to-1 selectors in the 2-bit synchronous programmable counter.

[0017] Programmable control bit DIV_N <1> and DIV_N <0> The same or enters the A1 terminal of the first 2-to-1 selector, DIV_N <1> The signal enters the A0 terminal of the second 2-to-1 selector; the outputs of the two 2-to-1 selectors are respectively connected to the data D terminals of the two D flip-flops, and the dual-mode frequency divider signal Fpre is connected to the clock terminals of the two D flip-flops; the output Q terminal of the second D flip-flop is connected to the A0 terminal of the first 2-to-1 selector; the inverted output QN terminal of the first D flip-flop and the output Q terminal of the second D flip-flop are ANDed, and their output is connected to the A1 terminal of the second 2-to-1 selector; the output Q terminal of the first D flip-flop and the output Q terminal of the second D flip-flop are ORed to generate the MC signal to control the switching of the preceding 4 / 5 frequency divider.

[0018] In one embodiment, the ECL2 divider with a set terminal includes transistors Q21 to Q48, resistors R9 to R20, NMOS transistors M1 to M2, and an inverter; wherein,

[0019] The bases of transistors Q21, Q22, Q43, Q44, Q45, and Q46 are connected to a bias voltage Vbias; the emitters of transistors Q43, Q44, Q45, and Q46 are grounded through resistors R17, R18, R19, and R20, respectively; the collector of transistor Q21 is connected to the first terminal of resistor R9, the base of Q23, and the base of Q29; the collector of transistor Q22 is connected to the first terminal of resistor R10, the base of Q24, and the base of Q30; the emitters of transistors Q21 and Q22 are connected to the drains of NMOS transistors M1 and M2 through resistors R15 and R16, respectively; NMOS transistor M... The gate of transistor M1 is connected to the preset signal PI; an inverter connects the gate of transistor M2 to the preset signal PI; the sources of NMOS transistors M1 and M2 are both grounded; the emitters of transistors Q23 and Q24 are both connected to the collector of transistor Q39; the collector of transistor Q23 is simultaneously connected to the collector of Q25, the base of Q27, the collector of Q28, the first terminal of resistor R11, and the base of Q31; the collector of transistor Q24 is simultaneously connected to the collectors of Q26 and Q27, the base of Q28, the first terminal of resistor R12, and the base of Q32; the emitters of transistors Q25 and Q26 are both connected to the collector of Q35; the base of transistor Q25 is... The collectors of transistors Q28, Q32, and Q33, the base of Q34, the first terminal of resistor R14, and the base of Q48 are connected simultaneously. The base of transistor Q26 is also connected to the bases of transistors Q30, Q31, and Q33, the collector of Q34, the first terminal of resistor R13, and the base of Q47. The second terminals of resistors R11, R12, R13, and R14 are all connected to VCC. The collectors of transistors Q47 and Q48 are both connected to VCC, and their emitters are for positive output signal Q and negative output signal QN, respectively. The emitters of transistors Q27 and Q28 are both connected to the collector of Q36. The emitters of transistors Q29 and Q30 are connected to the collector of Q36. The emitters of transistors Q31 and Q32 are both connected to the collector of Q37; the emitters of transistors Q33 and Q34 are both connected to the collector of Q38; the bases of transistors Q35 and Q38 are both connected to the positive clock input signal CLK; the bases of transistors Q36 and Q37 are both connected to the negative clock input signal CLKn; the bases of transistors Q39 and Q41 are both connected to the positive set signal LD; the bases of transistors Q40 and Q42 are both connected to the negative set signal LDn; the emitters of transistors Q39 and Q40 are both connected to the collector of Q43; and the emitters of transistors Q41 and Q42 are both connected to the collector of Q44.

[0020] In one embodiment, the preset signal PI and the set control signal LD ​​are used to reset the preset state of the 17-bit pulse counter. When the set control signal LD ​​is low, the ECL2 divider is a divider by two. When the set control signal LD ​​is high, the divider function stops, the preset signal PI is fed into the input through a level conversion signal, and the output of the ECL2 divider is Q = PI, thus completing the preset operation.

[0021] In one embodiment, the programmable Σ-Δ modulator module includes four identical 32-bit accumulators, a clock generator, a ΔN operation module, and a random number generation module; the 32-bit accumulators perform accumulation operations on the inputs; the clock generator controls the order of the Σ-Δ modulator; the ΔN operation module includes a delay network that calculates ΔN using a formula on the overflow values ​​C1 to C4 of the four 32-bit accumulators; the random number generation module generates random 0s and 1s to increase the randomness of the modulator output sequence.

[0022] The sum of the numerator value PLL_NUM<31:0>, the initial value MASH_SEED<31:0>, and the PLL_NUM<31:0> value is fed into the input of the first 32-bit accumulator via a 2-to-1 selector, controlled by the control word MASH_SEED_EN; the denominator value PLL_DEN<31:0> is connected to the input of the four 32-bit accumulators; the clock CLK1 to 4 output from the clock generator are fed into the four 32-bit accumulators respectively, controlled by the register MASH_ORDER<2:0>, which can adjust the modulator order;

[0023] The output of the random number generation module enters the input of four 32-bit accumulators, controlled by the DITHER_EN register; the overflow values ​​C1 to C4 of the four 32-bit accumulators enter the ΔN operation module to generate an output sequence, which is added to the integer value PLL_N<18:0> and the result enters the SUM operation unit.

[0024] In one embodiment, the random number generation module consists of 24 D flip-flops, three XOR gates, and one NOT gate; D flip-flops D0 to D23 are connected in sequence to form a ring, and the output of D flip-flop D23 enters D flip-flop D0; the outputs of D flip-flops D0, D2, and D3 are XORed with the NOT output of D flip-flop D23, and then each enters the next stage; the final output sequence enters each accumulator from the output of D flip-flop D23.

[0025] The high-precision fractional frequency divider for broadband phase-locked loops provided in this invention includes a 4 / 5 dual-mode frequency divider module, a 19-bit programmable counter module, and a programmable Σ-Δ modulator module, which can be directly applied to broadband fractional PLLs ranging from 7.5 GHz to 15 GHz. Compared with the commonly used MASH1-1-1 type fractional frequency divider, the Σ-Δ modulator of this invention has a 32-bit programmable modulus, an adjustable order from 1 to 4, and a frequency division accuracy of up to f. PD / 2 32 Meanwhile, a random number generation module is added to break the randomness of the modulator output sequence and effectively suppress fractional spurious noise. The 4 / 5 dual-mode divider module and 19-bit programmable counter module with fully differential CML structure have lower phase noise performance, and the division ratio range can cover 16 to 524295, which can be applied to wideband fractional phase-locked loops from 7.5 GHz to 15 GHz. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of a high-precision fractional frequency divider structure applied to a broadband phase-locked loop, provided by the present invention.

[0027] Figure 2 This is a schematic diagram of the 4 / 5 dual-mode frequency divider module;

[0028] Figure 3 This is a schematic diagram of a D flip-flop circuit with embedded AND gate logic;

[0029] Figure 4 This is a schematic diagram of the structure of a 19-bit programmable counter module;

[0030] Figure 5 This is a schematic diagram of the ECL2 frequency divider with a set position.

[0031] Figure 6 This is a schematic diagram of the programmable Σ-Δ modulator module;

[0032] Figure 7 This is a schematic diagram of the random number generation module. Detailed Implementation

[0033] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a high-precision fractional frequency divider for use in broadband phase-locked loops. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0034] This invention provides a high-precision fractional frequency divider for use in broadband phase-locked loops, the structure of which is as follows: Figure 1As shown, it includes a 4 / 5 dual-mode frequency divider module, a 19-bit programmable counter module, and a programmable Σ-Δ modulator module, which can achieve high-precision fractional frequency division of input signals from 7.5GHz to 15GHz, with a step size of up to 0.047Hz; at the same time, it ensures that the phase-locked loop system has low fractional spurious noise.

[0035] The 4 / 5 dual-mode frequency divider module controls the switching of the 4 / 5 division ratio based on the MC signal generated by the subsequent 19-bit programmable counter module, pre-dividing the output signal of the VCO. The 19-bit programmable counter module receives the 4 / 5 dual-mode pre-division clock signal Fpre and controls the division ratio through a 19-bit configuration number to generate the final divided signal. In the programmable Σ-Δ modulator module, the 32-bit fractional configuration input Fnum / Fden is modulated by the modulator and converted into a series of output sequences. These output sequences are added to the integer part PLL_N and fed into the 19-bit programmable counter module to generate randomly changing instantaneous division ratios. The average value of these instantaneous division ratios is the final fractional division ratio.

[0036] The 4 / 5 dual-mode frequency divider module is as follows: Figure 2 As shown, the system includes three cascaded fully differential CML D flip-flops, with the first and second being D flip-flops with embedded AND gate logic. The 4 / 5 dual-mode divider module pre-divides the VCO output signal. The VCO's buffered output signal finP is connected to the clock CLK port of the three D flip-flops, and the buffered inverted output signal finN is connected to the inverted clock CLKn port of the three D flip-flops. The inputs of the first D flip-flop are ANDed with A and B; port A is connected to the positive output Q of the third D flip-flop, and port B is connected to the control signal MC. The input A of the second D flip-flop is connected to the inverted output QN of the third D flip-flop, and input B is connected to the inverted output QN of the first D flip-flop. The input D of the third D flip-flop is connected to the positive output Q of the second D flip-flop. The outputs Q and QN of the third D flip-flop are a pair of differential signals Fpre_p and Fpre_n after 4 / 5 dual-mode division.

[0037] The D flip-flop with embedded AND gate logic adopts a fully differential CML structure. Please refer to [link / reference]. Figure 3The system includes transistors Q1 to Q20 and resistors R1 to R8. The bases of transistors Q1 and Q2 are connected to the non-inverting input terminal A and the inverting input terminal An, respectively. The bases of transistors Q3 and Q4 are connected to the non-inverting input terminal B and the inverting input terminal Bn, respectively. The emitters of transistors Q1 and Q2 are both connected to the collector of transistor Q3. The collector of transistor Q1 is simultaneously connected to the first terminal of resistor R1, the base of Q5, the collector of Q6, and the base of Q8. The collector of transistor Q2 is connected to the first terminal of resistor R2, the collector of Q4, the collector of Q5, the base of Q6, and the base of Q7. The emitters of transistors Q3 and Q4 are both connected to the collector of Q11; the emitters of transistors Q5 and Q6 are both connected to the collector of Q12; the collector of transistor Q7 is simultaneously connected to the first terminal of resistor R3, the base of Q10, the collector of Q9, and the base of Q17. The collector of transistor Q8 is simultaneously connected to the first terminal of resistor R4, the base of Q9, the collector of Q10, and the base of Q18. The emitters of transistors Q7 and Q8 are both connected to the collector of Q13; the emitters of transistors Q9 and Q10 are both connected to the collector of Q14; the bases of transistors Q11 and Q14 are both connected to the positive clock input CLK; the bases of transistors Q12 and Q13 are both connected to the negative clock input CLKn; the emitters of transistors Q11 and Q12 are both connected to the collector of Q15; and the emitters of transistors Q13 and Q14 are both connected to the collector of Q16. Electrodes; the collectors of transistors Q17 and Q18 and the second terminals of resistors R1 to R4 are all connected to VCC; the emitter of transistor Q17 is simultaneously connected to the collector of transistor Q19 and the positive output terminal Q; the emitter of transistor Q18 is simultaneously connected to the collector of transistor Q20 and the inverted output terminal QN; the bases of transistors Q15, Q16, Q19, and Q20 are all connected to the signal Vbias, and their emitters are grounded through resistors R5, R6, R7, and R8, respectively. The fully differential structure has good anti-interference capabilities, effectively suppressing common-mode noise. Simultaneously, embedding AND gate logic within the D flip-flop reduces the number of circuit stages, further improving the circuit's operating speed. Vbias is a stable bias voltage generated by the bias circuit, providing a constant current source.

[0038] like Figure 4 As shown, the 19-bit programmable counter module includes a 17-bit pulse counter and a 2-bit synchronous programmable counter; the 17-bit pulse counter consists of 17 ECL2 dividers with set terminals and a counting termination detection circuit.

[0039] The dual-mode frequency divider signal Fpre enters the clock input of the first ECL2 frequency divider. Starting from the first stage, the output of each subsequent stage is connected to the clock input of the next stage in sequence. The programmable control bits DIV_N<18:2> are connected to the preset inputs PI of the 17 ECL2 frequency dividers in sequence. The inverted outputs QN of the 17 ECL2 frequency dividers are connected to the inputs of the count termination detection logic circuit in sequence to detect the state of each QN. The output signal LD ​​of the count termination detection logic circuit is connected to the set inputs of the 17 ECL2 frequency dividers and the select inputs of the two 2-to-1 selectors in the 2-bit synchronous programmable counter.

[0040] Programmable control bit DIV_N <1> and DIV_N <0> The same or enters the A1 terminal of the first 2-to-1 selector, DIV_N <1> The signal enters the A0 terminal of the second 2-to-1 selector; the outputs of the two 2-to-1 selectors are respectively connected to the data D terminals of the two D flip-flops, and the dual-mode frequency divider signal Fpre is connected to the clock terminals of the two D flip-flops; the output Q terminal of the second D flip-flop is connected to the A0 terminal of the first 2-to-1 selector; the inverted output QN terminal of the first D flip-flop and the output Q terminal of the second D flip-flop are ANDed, and their output is connected to the A1 terminal of the second 2-to-1 selector; the output Q terminal of the first D flip-flop and the output Q terminal of the second D flip-flop are ORed to generate the MC signal to control the switching of the preceding 4 / 5 frequency divider.

[0041] The ECL2 frequency divider with a set terminal can effectively improve the circuit's load-carrying capacity and operating speed, while also providing some protection against transistor breakdown. Its structure is as follows: Figure 5As shown, the circuit includes transistors Q21-Q48, resistors R9-R20, NMOS transistors M1-M2, and an inverter. The bases of transistors Q21, Q22, Q43, Q44, Q45, and Q46 are connected to the signal Vbias. The emitters of transistors Q43, Q44, Q45, and Q46 are grounded through resistors R17, R18, R19, and R20, respectively. The collector of transistor Q21 is simultaneously connected to the first terminal of resistor R9, the base of Q23, and the base of Q29. The collector of transistor Q22 is simultaneously connected to the first terminal of resistor R10, the base of Q24, and the base of Q30. The emitters of transistors Q21 and Q22 are connected through resistors R15 and R20, respectively. 16 is connected to the drains of NMOS transistors M1 and M2; the gate of NMOS transistor M1 is connected to the preset signal PI, and an inverter connects the gate of M2 to the preset signal PI; the sources of NMOS transistors M1 and M2 are both grounded; the emitters of transistors Q23 and Q24 are both connected to the collector of Q39; the collector of transistor Q23 is simultaneously connected to the collector of Q25, the base of Q27, the collector of Q28, the first terminal of resistor R11, and the base of Q31; the collector of transistor Q24 is simultaneously connected to the collectors of Q26 and Q27, the base of Q28, the first terminal of resistor R12, and the base of Q32; the emitters of transistors Q25 and Q26 are both connected to the collector of Q35; the transistor... The base of transistor Q25 is simultaneously connected to the collectors of transistors Q28, Q32, and Q33, the base of Q34, the first terminal of resistor R14, and the base of Q48; the base of transistor Q26 is simultaneously connected to the bases of transistors Q30, Q31, and Q33, the collector of Q34, the first terminal of resistor R13, and the base of Q47; the second terminals of resistors R11, R12, R13, and R14 are all connected to VCC; the collectors of transistors Q47 and Q48 are both connected to VCC, and their emitters are for positive output signal Q and for negative output signal QN, respectively; the emitters of transistors Q27 and Q28 are both connected to the collector of Q36; the emitters of transistors Q29 and Q30 are both connected to the collector of Q41. The emitters of transistors Q31 and Q32 are both connected to the collector of Q37; the emitters of transistors Q33 and Q34 are both connected to the collector of Q38; the bases of transistors Q35 and Q38 are both connected to the positive clock input signal CLK; the bases of transistors Q36 and Q37 are both connected to the negative clock input signal CLKn; the bases of transistors Q39 and Q41 are both connected to the positive set signal LD; the bases of transistors Q40 and Q42 are both connected to the negative set signal LDn; the emitters of transistors Q39 and Q40 are both connected to the collector of Q43; the emitters of transistors Q41 and Q42 are both connected to the collector of Q44; the preset signal PI and the set control signal LD ​​are used to reset the preset state of the counter.When the set control signal LD ​​is low, the ECL2 frequency divider circuit is a 2-divider; when the set control signal LD ​​is high, the frequency division function stops, the set signal PI is fed into the input through the level conversion signal, and the output terminal Q of the ECL2 frequency divider is Q=PI, and the circuit completes the set operation.

[0042] The programmable Σ-Δ modulator module, as shown in Figure 6 As shown, it includes four identical 32-bit accumulators (32-bit accumulator #1, 32-bit accumulator #2, 32-bit accumulator #3, and 32-bit accumulator #4), a clock generator CLK_BLOCK, a ΔN operation module, and a random number generation module. The 32-bit accumulators perform accumulation operations on the input. The clock generator controls the order of the Σ-Δ modulator. The ΔN operation module includes a delay network that calculates ΔN using formulas on the overflow values ​​C1 to C4 of the four 32-bit accumulators. The random number generation module generates random 0s and 1s to increase the randomness of the modulator output sequence and suppress fractional spurious signals. The numerator value PLL_NUM<31:0>, the initial value MASH_SEED<31:0>, and PLL... The sum of the values ​​_NUM<31:0> is fed into the input of 32-bit accumulator #1 via a 2-to-1 selector, controlled by the control word MASH_SEED_EN. The denominator value PLL_DEN<31:0> is connected to the inputs of accumulators #1 to #4. The clock generator CLK_BLOCK outputs CLK1 to #4, respectively, are fed into accumulators #1 to #4, controlled by the register MASH_ORDER<2:0>, which allows adjustment of the modulator's order. The output of the random number generation module is fed into the inputs of accumulators #1 to #4, controlled by the register DITHER_EN. The overflow values ​​C1 to C4 of accumulators #1 to #4 are fed into the ΔN operation module to generate an output sequence, which is then added to the integer value PLL_N<18:0>, and the resulting value is fed into the SUM operation unit. This programmable Σ-Δ modulator module has an adjustable order of 1 to 4, and both the numerator and denominator of the input decimal values ​​are 32-bit programmable. Compared to traditional Σ-Δ modulators, this modulator can meet the needs of different functional scenarios.

[0043] The random number generation module is as follows Figure 7 As shown, the system consists of 24 D flip-flops, three XOR gates, and one NOT gate. The D flip-flops D0 through D23 are connected sequentially to form a ring, with the output of D23 entering D0. A slight difference is that this structure performs logic processing at certain nodes: the outputs of D0, D2, and D3 are first XORed with the NOT output of D23, and then each enters the next stage. The final output sequence enters each accumulator from the output of D23. The addition of a random number generation module does not significantly increase power consumption, while making the modulator's output sequence more randomized and effectively suppressing fractional spurious signals.

[0044] This invention presents a programmable fractional frequency divider designed on a 0.13µm SiGeBiCMOS process platform. It comprises a 4 / 5 dual-mode frequency divider with a fully differential CML structure and a 19-bit programmable counter, offering advantages such as low phase noise and a wide division ratio range. The addition of a Σ-Δ modulator with adjustable order (1-4) and a 32-bit programmable modulus satisfies high-precision fractional frequency division and low spurious performance; further reduction of fractional spurious performance can be achieved through random dithering. Post-fabrication testing demonstrated that, with input signals ranging from 7.5GHz to 15GHz, an arbitrary division ratio of 16 to 524295 can be achieved. Under test conditions of a 7.5GHz sine wave input, a division ratio of 25, and an output signal frequency of 300MHz, the phase noise of the integer frequency divider is -150dBc / Hz@1kHz. With the third-order modulator and random dithering enabled, the fractional spurious performance can reach below -70dBc.

[0045] The high-precision fractional frequency divider of this invention is suitable for wideband fractional phase-locked loops from 7.5 GHz to 15 GHz. It can be based on a 0.13 μm SiGeBiCMOS process platform and achieves a trade-off between wideband, high precision, low phase noise, and low spurious performance.

[0046] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A high-precision fractional frequency divider for use in broadband phase-locked loops, characterized in that, Includes a 4 / 5 dual-mode frequency divider module, a 19-bit programmable counter module, and a programmable Σ-Δ modulator module; The 4 / 5 dual-mode frequency divider module controls the switching of the 4 / 5 division ratio based on the MC signal generated by the subsequent 19-bit programmable counter module, and pre-divides the output signal of the VCO. The 19-bit programmable counter module is connected to a 4 / 5 dual-mode pre-division clock signal and generates the final division signal by controlling the division ratio through a 19-bit configuration number. In the programmable Σ-Δ modulator module, the 32-bit fractional configuration input Fnum / Fden is modulated by the modulator and converted into a series of output sequences. These output sequences are added to the integer part PLL_N and fed into the 19-bit programmable counter module to generate randomly changing instantaneous frequency division ratios. The average value of these instantaneous frequency division ratios is the final fractional frequency division ratio. The 4 / 5 dual-mode frequency divider module includes three cascaded fully differential CML D flip-flops. The first and second are D flip-flops with embedded AND gate logic. The output signal finP of the VCO after passing through the buffer is connected to the clock CLK port of the three D flip-flops, and the inverted output signal finN of the VCO after passing through the buffer is connected to the inverted clock CLKn port of the three D flip-flops. The input of the first D flip-flop is the AND of ports A and B. Port A is connected to the positive output Q of the third D flip-flop, and port B is connected to the control signal MC. The input terminal A of the second D flip-flop is connected to the inverted output terminal QN of the third D flip-flop, and the input terminal B is connected to the inverted output terminal QN of the first D flip-flop. The input D of the third D flip-flop is connected to the positive output Q of the second D flip-flop; the outputs Q and QN of the third D flip-flop are a pair of differential signals Fpre_p and Fpre_n after being divided by a 4 / 5 dual-mode frequency divider. The 19-bit programmable counter module includes a 17-bit pulse counter and a 2-bit synchronous programmable counter; wherein the 17-bit pulse counter is composed of 17 ECL2 dividers with set terminals and a counting termination detection circuit. The dual-mode frequency divider signal Fpre enters the clock input of the first ECL2 frequency divider. Starting from the first stage, the output of each subsequent stage is connected to the clock input of the next stage in sequence. The programmable control bits DIV_N<18:2> are connected to the preset inputs PI of the 17 ECL2 frequency dividers in sequence. The inverted outputs QN of the 17 ECL2 frequency dividers are all connected to the input of the count termination detection logic circuit in sequence to detect the state of each QN. The output signal LD ​​of the count termination detection logic circuit is connected to the set input of the 17 ECL2 frequency dividers and the select input of the two 2-to-1 selectors in the 2-bit synchronous programmable counter. Programmable control bit DIV_N <1> and DIV_N <0> The same or enters the A1 terminal of the first 2-to-1 selector, DIV_N <1> The signal enters the A0 terminal of the second 2-to-1 selector; the outputs of the two 2-to-1 selectors are respectively connected to the data D terminals of the two D flip-flops, and the dual-mode frequency divider signal Fpre is connected to the clock terminals of the two D flip-flops; the output Q terminal of the second D flip-flop is connected to the A0 terminal of the first 2-to-1 selector; the inverted output QN terminal of the first D flip-flop and the output Q terminal of the second D flip-flop are ANDed, and their output is connected to the A1 terminal of the second 2-to-1 selector; the output Q terminal of the first D flip-flop and the output Q terminal of the second D flip-flop are ORed to generate the MC signal to control the switching of the preceding 4 / 5 frequency divider.

2. The high-precision fractional frequency divider applied to a broadband phase-locked loop as described in claim 1, characterized in that, The embedded AND gate logic D flip-flop includes transistors Q1~Q20 and resistors R1~R8; wherein, The bases of transistors Q1 and Q2 are connected to the positive input terminal A and the negative input terminal An, respectively. The bases of transistors Q3 and Q4 are connected to the positive input terminal B and the negative input terminal Bn, respectively. The emitters of transistors Q1 and Q2 are both connected to the collector of transistor Q3. The collector of transistor Q1 is simultaneously connected to the first terminal of resistor R1, the base of Q5, the collector of Q6, and the base of Q8. The collector of transistor Q2 is connected to the first terminal of resistor R2 and the base of Q4. The collector of transistor Q11, the collector of transistor Q5, the base of transistor Q6, and the base of transistor Q7 are all connected to the collector of transistor Q11; the emitters of transistors Q3 and Q4 are both connected to the collector of transistor Q11; the emitters of transistors Q5 and Q6 are both connected to the collector of transistor Q12; the collector of transistor Q7 is simultaneously connected to the first terminal of resistor R3, the base of transistor Q10, the collector of transistor Q9, and the base of transistor Q17; the collector of transistor Q8 is simultaneously connected to the first terminal of resistor R4, the base of transistor Q9, the collector of transistor Q10, and the base of transistor Q17. The base of transistor Q8 is connected to the collector of transistor Q13; the emitters of transistors Q9 and Q10 are connected to the collector of transistor Q14; the bases of transistors Q11 and Q14 are connected to the positive clock input CLK; the bases of transistors Q12 and Q13 are connected to the negative clock input CLKn; the emitters of transistors Q11 and Q12 are connected to the collector of transistor Q15; the emitters of transistors Q13 and Q14 are connected to the collector of transistor Q16. Collector; the collectors of transistors Q17 and Q18 and the second terminals of R1~R4 are all connected to VCC; the emitter of transistor Q17 is connected to both the collector of Q19 and the positive output terminal Q; the emitter of transistor Q18 is connected to both the collector of Q20 and the inverted output terminal QN; the bases of transistors Q15, Q16, Q19, and Q20 are all connected to the bias voltage Vbias, and the emitters are grounded through resistors R5, R6, R7, and R8, respectively.

3. The high-precision fractional frequency divider applied to a broadband phase-locked loop as described in claim 1, characterized in that, The ECL2 frequency divider with a set terminal includes transistors Q21~Q48, resistors R9~R20, NMOS transistors M1~M2, and an inverter; wherein, The bases of transistors Q21, Q22, Q43, Q44, Q45, and Q46 are connected to a bias voltage Vbias; the emitters of transistors Q43, Q44, Q45, and Q46 are grounded through resistors R17, R18, R19, and R20, respectively; the collector of transistor Q21 is connected to the first terminal of resistor R9, the base of Q23, and the base of Q29; the collector of transistor Q22 is connected to the first terminal of resistor R10, the base of Q24, and the base of Q30; the emitters of transistors Q21 and Q22 are connected to the drains of NMOS transistors M1 and M2 through resistors R15 and R16, respectively; NMOS transistor M... The gate of transistor M1 is connected to the preset signal PI; an inverter connects the gate of transistor M2 to the preset signal PI; the sources of NMOS transistors M1 and M2 are both grounded; the emitters of transistors Q23 and Q24 are both connected to the collector of transistor Q39; the collector of transistor Q23 is simultaneously connected to the collector of Q25, the base of Q27, the collector of Q28, the first terminal of resistor R11, and the base of Q31; the collector of transistor Q24 is simultaneously connected to the collectors of Q26 and Q27, the base of Q28, the first terminal of resistor R12, and the base of Q32; the emitters of transistors Q25 and Q26 are both connected to the collector of Q35; the base of transistor Q25 is... The collectors of transistors Q28, Q32, and Q33, the base of Q34, the first terminal of resistor R14, and the base of Q48 are connected simultaneously. The base of transistor Q26 is also connected to the bases of transistors Q30, Q31, and Q33, the collector of Q34, the first terminal of resistor R13, and the base of Q47. The second terminals of resistors R11, R12, R13, and R14 are all connected to VCC. The collectors of transistors Q47 and Q48 are both connected to VCC, and their emitters are for positive output signal Q and negative output signal QN, respectively. The emitters of transistors Q27 and Q28 are both connected to the collector of Q36. The emitters of transistors Q29 and Q30 are connected to the collector of Q36. The emitters of transistors Q31 and Q32 are both connected to the collector of Q37; the emitters of transistors Q33 and Q34 are both connected to the collector of Q38; the bases of transistors Q35 and Q38 are both connected to the positive clock input signal CLK; the bases of transistors Q36 and Q37 are both connected to the negative clock input signal CLKn; the bases of transistors Q39 and Q41 are both connected to the positive set signal LD; the bases of transistors Q40 and Q42 are both connected to the negative set signal LDn; the emitters of transistors Q39 and Q40 are both connected to the collector of Q43; and the emitters of transistors Q41 and Q42 are both connected to the collector of Q44.

4. The high-precision fractional frequency divider for broadband phase-locked loops as described in claim 3, characterized in that, The preset signal PI and the set control signal LD ​​are used to reset the preset state of the 17-bit pulse counter. When the set control signal LD ​​is low, the ECL2 frequency divider is a frequency divider by two. When the set control signal LD ​​is high, the frequency division function stops, the preset signal PI is fed into the input through a level conversion signal, and the output terminal of the ECL2 frequency divider Q=PI, thus completing the preset operation.

5. The high-precision fractional frequency divider applied to a broadband phase-locked loop as described in claim 1, characterized in that, The programmable Σ-Δ modulator module includes four identical 32-bit accumulators, a clock generator, a ΔN operation module, and a random number generation module. The 32-bit accumulators perform accumulation operations on the inputs. The clock generator controls the order of the Σ-Δ modulator. The ΔN operation module includes a delay network that calculates ΔN using formulas on the overflow values ​​C1~C4 of the four 32-bit accumulators. The random number generation module generates random 0s and 1s to increase the randomness of the modulator output sequence. The sum of the numerator value PLL_NUM<31:0>, the initial value MASH_SEED<31:0>, and the PLL_NUM<31:0> value is fed into the input of the first 32-bit accumulator via a 2-to-1 selector, controlled by the control word MASH_SEED_EN; the denominator value PLL_DEN<31:0> is connected to the input of the four 32-bit accumulators; the clock CLK1~4 output from the clock generator are fed into the four 32-bit accumulators respectively, controlled by the register MASH_ORDER<2:0>, which can adjust the modulator order; The output of the random number generation module enters the input of four 32-bit accumulators, controlled by the DITHER_EN register; the overflow values ​​C1~C4 of the four 32-bit accumulators enter the ΔN operation module to generate an output sequence, which is added to the integer value PLL_N<18:0> and the result enters the SUM operation unit.

6. The high-precision fractional frequency divider for broadband phase-locked loops as described in claim 5, characterized in that, The random number generation module consists of 24 D flip-flops, three XOR gates, and one NOT gate. D flip-flops D0 to D23 are connected in sequence to form a ring. The output of D flip-flop D23 enters D flip-flop D0. The outputs of D flip-flops D0, D2, and D3 are first XORed with the NOT output of D flip-flop D23, and then each enters the next stage. The final output sequence enters each accumulator from the output of D flip-flop D23.

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