Buried bit line structure, method for preparing buried bit line structure, and memory

Abstract

The present disclosure provides a buried bitline structure, a method for preparing the buried bitline structure, and a memory. The buried bitline structure includes: a substrate having a bitline trench; a bitline metal filled in the bitline trench; and a bitline contact filled in the bitline trench and located on the bitline metal, with an arc-shaped contact surface between the bitline contact and the bitline metal. The present disclosure increases the contact area between the bitline contact and the bitline metal by configuring the contact surface between the bitline contact and the bitline metal as an arc-shaped contact surface, thereby enhancing the conductivity of the bitline structure and preventing the collapse and damage of the bitline structure, thereby adapting to bitline structure failure caused by miniaturization of the bitline structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor manufacturing, and more particularly to a buried bit line structure, a method for preparing the buried bit line structure, and a memory. Background Art

[0002] As semiconductor device manufacturing processes shrink, bitline structures also shrink. Because photolithography and etching are required to form bitline trenches with smaller line widths to achieve this, existing bitline structures are prone to not only tilting and collapsing the material layers above the bitline trenches, but also damage and poor contact between these layers, leading to device failure.

[0003] Therefore, it is a technical problem to be solved to provide a bit line structure that is not easily damaged during the manufacturing process and has a large conductive contact area, and a method for manufacturing the bit line structure. Summary of the Invention

[0004] The technical problem to be solved by the embodiments of the present disclosure is to provide a buried bit line structure, a method for preparing the buried bit line structure, and a memory, so as to achieve the purpose of enhancing the conductivity and stability by increasing the contact area between the material layers of the bit line structure during the manufacturing process, so as to adapt to the miniaturization of the bit line structure.

[0005] In order to solve the above problems, an embodiment of the present disclosure provides a buried bit line structure, including: a substrate having a bit line groove; a bit line metal filled in the bit line groove; a bit line contact filled in the bit line groove and located on the bit line metal, and an arc-shaped contact surface is provided between the bit line contact and the bit line metal.

[0006] In some embodiments, the bit line trench includes: a first trench segment, in which the bit line metal is filled; a second trench segment, in which the bit line contact is filled, the second trench segment extending in the direction of the first trench segment, and a cross-sectional area of ​​the second trench segment being smaller than a cross-sectional area of ​​the first trench segment.

[0007] In some embodiments, the buried bit line structure further includes: a first barrier layer located in the bit line trench, and / or a second barrier layer located on a surface of the first barrier layer, and the bit line metal covers the bottom wall and side walls of the second barrier layer.

[0008] In some embodiments, the buried bit line structure further includes a sidewall spacer filled in the bit line trench and located on the bit line contact, wherein the sidewall spacer at least partially extends into the substrate.

[0009] In some embodiments, a projection of the bit line contact on the substrate is located within a projection of the bit line metal on the substrate.

[0010] An embodiment of the present disclosure also provides a method for preparing a buried bit line structure, comprising: providing a substrate and forming a bit line groove in the substrate; filling the bit line groove with a bit line metal; forming a bit line contact on the bit line metal, wherein an arc-shaped contact surface is provided between the bit line contact and the bit line metal.

[0011] In some embodiments, before filling the bit line metal in the bit line trench, the preparation method further includes: expanding a portion of the bit line trench to form a first trench segment; forming a second trench segment on the remaining bit line trench, wherein the second trench segment extends in the direction of the first trench segment, and the cross-sectional area of ​​the second trench segment is smaller than the cross-sectional area of ​​the first trench segment. In the case of the bit line structure shrinking caused by the shrinking of the dynamic random access memory process,

[0012] In some embodiments, the method for expanding a portion of the bit line trench and forming a first trench segment includes: depositing a first dielectric layer in the bit line trench, the first dielectric layer covering an inner wall of the bit line trench; depositing a second dielectric layer on the first dielectric layer; etching back a portion of the second dielectric layer and exposing a portion of the first dielectric layer; processing the exposed portion of the first dielectric layer to form a third dielectric layer, the third dielectric layer having different properties from the second dielectric layer; removing the remaining second dielectric layer and the first dielectric layer and exposing the substrate; and laterally etching the exposed portion of the substrate to expand a portion of the bit line trench and form the first trench segment.

[0013] In some embodiments, the exposed portion of the first dielectric layer is treated with oxygen plasma to form a third dielectric layer, the first dielectric layer is silicon nitride, and the third dielectric layer is silicon oxynitride.

[0014] In some embodiments, filling the bit line metal in the bit line trench includes: filling the first trench section and the second trench section of the bit line trench with metal material, whereby an air gap is formed in the filled metal material; and etching back a portion of the metal material to the air gap so that the remaining metal material has an arc-shaped surface, whereby the remaining metal material constitutes the bit line metal.

[0015] In some embodiments, before filling the bit line metal in the bit line trench, the preparation method also includes: forming a first barrier layer in the bit line trench, and / or forming a second barrier layer in the bit line trench, the second barrier layer is located on the surface of the first barrier layer, and the bit line metal covers the bottom wall and side walls of the second barrier layer.

[0016] In some embodiments, the first barrier layer is formed by nitriding the substrate in the bit line trench.

[0017] In some embodiments, the plasma nitriding gas used to nitridate the substrate is ammonia gas at a temperature of 600-800 degrees Celsius.

[0018] In some embodiments, sulfur hexafluoride, carbon tetrafluoride, trifluoromethane, oxygen, argon, or any combination thereof is used to remove the first dielectric layer or the second dielectric layer.

[0019] In some embodiments, the method further includes forming a sidewall spacer, wherein the sidewall spacer is filled in the bit line trench and is located on the bit line contact, and the sidewall spacer at least partially extends into the substrate.

[0020] An embodiment of the present disclosure also provides a memory, including: a buried bit line structure; the buried bit line structure includes: a substrate having a bit line groove; a bit line metal filled in the bit line groove; a bit line contact located on the bit line metal, and an arc-shaped contact surface between the bit line contact and the bit line metal contact.

[0021] The above technical solution, by configuring the contact surface between the bitline contact and the bitline metal as an arc-shaped contact surface, increases the contact area between the bitline contact and the bitline metal, thereby enhancing the conductivity of the bitline structure. Furthermore, embodiments of the present disclosure provide a buried bitline structure, which reduces the overall height of the bitline structure and increases stability. In some embodiments, the width of the first trench segment is increased, further widening the width of the bitline metal, effectively preventing the bitline structure from collapsing during subsequent etching processes. This provides a bitline structure that is not easily damaged during the manufacturing process and has a large conductive contact area, thereby adapting to bitline structure failures caused by miniaturization of the bitline structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 FIG. 1 is a schematic diagram of a buried bit line structure in an embodiment of the present disclosure.

[0023] Figure 2 FIG. 4 is a schematic diagram of a buried bit line structure in another embodiment of the present disclosure.

[0024] Figure 3 FIG. 4 is a schematic diagram of a buried bit line structure in another embodiment of the present disclosure.

[0025] Figure 4 FIG. 4 is a schematic diagram of a buried bit line structure in another embodiment of the present disclosure.

[0026] Figure 5 Schematic diagram of a method for preparing a buried bit line structure in an embodiment of the present disclosure.

[0027] Figure 6 FIG. 1 is a schematic diagram of a bit line trench in an embodiment of the present disclosure.

[0028] Figure 7 is a schematic diagram of a bit line trench in another embodiment of the present disclosure.

[0029] Figure 8 is a schematic diagram of a method for forming a first trench segment in an embodiment of the present disclosure.

[0030] Figure 9 FIG. 1 is a schematic diagram of a first dielectric layer and a second dielectric layer in one embodiment of the present disclosure.

[0031] Figure 10 is a schematic diagram of the third dielectric layer in one embodiment of the present disclosure.

[0032] Figure 11 Schematic diagram of a first trench segment in one embodiment of the present disclosure.

[0033] Figure 12 Schematic diagram of the first barrier layer and the second barrier layer in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The buried bit line structure, the method for preparing the buried bit line structure, and the specific implementation of the memory provided by the present invention are described in detail below with reference to the accompanying drawings.

[0035] Figure 1 This is a schematic diagram of a buried bitline structure in one embodiment of the present disclosure. The buried bitline structure includes: a substrate 1 having a bitline trench 2; a bitline metal 3 filling the bitline trench 2; and a bitline contact 4 filling the bitline trench 2 and located on the bitline metal 3. The bitline contact 4 and the bitline metal 3 have an arc-shaped contact surface. By increasing the contact area between the bitline contact 4 and the bitline metal 3, the conductivity of the bitline structure is enhanced.

[0036] In some embodiments, the substrate 1 can be, for example, a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulato). The semiconductor substrate can also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP or SiC. It can also be a stacked structure, such as Si / SiGe. It can also be other epitaxial structures, such as SGOI (Silicon Germanium On Insulator). The substrate 1 can be a single substrate structure, and of course it can also include other semiconductor structures, such as buried word lines, isolation structures, doping structures, etc. There is no special limitation, and the structure can be adjusted according to the needs.

[0037] In some embodiments, the bit line trenches 2 are multiple grooves formed by etching downward along the substrate 1. The etching width of these grooves can be 10nm to 20nm, for example, 10nm, 12nm, and 18nm. The etching depth of these grooves can be, for example, 1 to 2 times the groove width, for example, 1.5 or 2 times. Furthermore, for example, the etching depth when etching downward to form the bit line trenches 2 can be, for example, etching downward the substrate 1, for example, the Si silicon substrate and the insulating layer on the buried word line (not shown in the figure) to a position of 1 / 2 to 4 / 5 of the insulating layer, for example, a position of 1 / 2 or 3 / 5. When within the above range, the bit line metal 3 and the bit line contact 4 can be filled in the bit line trench 2, thereby forming a buried bit line structure in the substrate 1, reducing the height of the bit line structure, improving stability, and avoiding the subsequent material layer on the bit line trench 2 from extending too high outside the substrate 1 and collapsing. The material of the bit line metal 3 can be, for example, tungsten, copper, aluminum, nickel, cobalt, etc. The bit line contact 4 leads out the electrical signal of the bit line metal 3. The bit line contact 4 can be, for example, tungsten or polysilicon.

[0038] In some other embodiments, to avoid material layer collapse during the manufacturing process, the width of the bit line metal is further widened. Figure 2 This is a schematic diagram of a buried bitline structure in another embodiment of the present disclosure. The bitline trench 2 includes a first trench segment 21, which is filled with the bitline metal 3; and a second trench segment 22, which is filled with the bitline contact 4. The second trench segment 22 extends in the direction of the first trench segment 21 and has a smaller cross-sectional area than the first trench segment 21. The projection of the bitline contact 4 on the substrate 1 is located within the projection of the bitline metal 3 on the substrate 1.

[0039] Figure 3Figure 1 is a schematic diagram of a buried bitline structure in another embodiment of the present disclosure. The buried bitline structure includes: a substrate 1 having a bitline trench 2; a bitline metal 3 filling the bitline trench 2; and a bitline contact 4 filling the bitline trench 2 and located on the bitline metal 3. The bitline contact 4 and the bitline metal 3 have an arc-shaped contact surface. In this embodiment, the buried bitline structure further includes: a first barrier layer 6 located within the bitline trench; a second barrier layer 5 located on the surface of the first barrier layer 6; and the bitline metal 3 covers the bottom and sidewalls of the second barrier layer 5. Either or both barrier layers 5, 6, can be provided to prevent the bitline metal 3 from diffusing into the substrate 1. The first barrier layer 6 can be made of, for example, SiOx, SiN, SiON, or a low-k material. The second barrier layer 5 is located between the first barrier layer 6 and the bitline metal 3. Specifically, materials such as TiN, TaN, and other metal nitrides can be selected.

[0040] Figure 4 This is a schematic diagram of a buried bitline structure in another embodiment of the present disclosure. The buried bitline structure includes: a substrate 1 having a bitline trench 2; a bitline metal 3 filling the bitline trench 2; a bitline contact 4 filling the bitline trench 2 and located on the bitline metal 3, with an arc-shaped contact surface between the bitline contact 4 and the bitline metal 3; a first barrier layer 6 located in the bitline trench; a second barrier layer 5 located on the surface of the first barrier layer 6; and the bitline metal 3 covering the bottom and sidewalls of the second barrier layer 5. In this embodiment, the buried bitline structure further includes a spacer 7 filled within the bitline trench 2 and positioned above the bitline contact 4. The spacer 7 at least partially extends outside the substrate 1. The spacer 7 extends from the bitline trench 2 of the substrate 1 to the outside of the substrate 1. The spacer 7 serves as an isolation layer for the subsequent fabrication of a capacitor contact wire. The height of the spacer 7 extending outside the substrate 1 should not be too low to avoid affecting the fabrication of the capacitor contact wire, nor too high to prevent the spacer 7 from tilting and collapsing. The extension height a of the spacer 7 outside the substrate 1 can be 3 to 8 times, for example, 4 times, 6 times, or 8 times, of the spacer width b. Furthermore, it can be 1 to 2 times, for example, 1.5 times or 2 times, of the spacing c between adjacent spacers 7. In some embodiments, the width of the spacer 7 is greater than or equal to the width of the bitline contact 4 located thereunder. The material of the spacer 7 can be, for example, SiN. The spacer 7 will serve as an isolation layer for the subsequent fabrication of a capacitor contact wire.

[0041] The above technical solution, by configuring the contact surface between the bitline contact 4 and the bitline metal 3 as an arcuate contact surface, increases the contact area between the bitline contact 4 and the bitline metal 3, thereby enhancing the conductivity of the bitline structure. In some embodiments, the width of the first trench segment 21 is increased, further widening the width of the bitline metal 3, thereby preventing the collapse of the sidewall spacer 7 during the manufacturing process. This provides a bitline structure that is not easily damaged during the manufacturing process and has a large conductive contact area, thereby adapting to bitline structure failure caused by scaling.

[0042] Figure 5 The method for preparing the buried bit line structure in one embodiment of the present disclosure comprises: step S101, providing a substrate 1 (shown in FIG. Figure 4 ), and forming a bit line trench 2 in the substrate 1 (shown in Figure 4 ); Step S102, filling the bit line trench 2 with a bit line metal 3 (shown in FIG. Figure 4 ); Step S103, forming a bit line contact 4 on the bit line metal 3 (shown in Figure 4 ), an arc-shaped contact surface is provided between the bit line contact 4 and the bit line metal 3.

[0043] See also Figure 5 In step S101 , a substrate 1 is provided, and a bit line trench 2 is formed in the substrate 1 . Figure 6 This is a schematic diagram of the bit line trench 2 in one embodiment of the present disclosure. Figure 6 A substrate 1 is provided, and a mask layer (not shown in the figure), such as SiO2, is formed on the substrate 1. The mask layer is patterned using a photolithography process, and the substrate 1 is further etched downward along the patterned mask layer to provide a bit line trench 2 in the substrate 1. The bit line trench 2 serves as a bit line conductive layer to connect the bit line metal 3.

[0044] Figure 7 This is a schematic diagram of the bit line trench 2 in another embodiment of the present disclosure. Figure 7Before filling the bitline metal 3 in the bitline trench 2, the preparation method further includes: expanding a portion of the bitline trench 2 to form a first trench segment 21; and forming a second trench segment 22 in the remaining bitline trench 2. The second trench segment 22 extends in the direction of the first trench segment 21, and the cross-sectional area of ​​the second trench segment 22 is smaller than the cross-sectional area of ​​the first trench segment 21. The bitline trench 2 includes the first trench segment 21 and the second trench segment 22. The first trench segment 21 has a larger volume, allowing for more bitline metal 3 to be filled. An air gap is formed when the bitline metal 3 is filled, so that the bitline metal 3 is etched back to the air gap, forming a curved surface and improving conductivity. Furthermore, the first trench segment 21 and the second trench segment 22 can be used to deposit a wider sidewall spacer 7, preventing the sidewall spacer 7 from collapsing due to an excessively high aspect ratio.

[0045] Figure 8 FIG. 2 is a schematic diagram of a method for forming the first trench segment 21 in an embodiment of the present disclosure. Figure 9 Schematic diagram of the first dielectric layer 8 and the second dielectric layer 9 in one embodiment of the present disclosure. Figure 8 and Figure 9 , the bit line trench 2 is expanded to form a first trench segment 21 (shown in FIG. Figure 7 ) method comprises: step S201, depositing a first dielectric layer 8 in the bit line trench 2, wherein the first dielectric layer 8 covers the inner wall of the bit line trench 2; step S202, depositing a second dielectric layer 9 on the first dielectric layer 8; step S203, etching back a portion of the second dielectric layer 9 and exposing a portion of the first dielectric layer 8; step S204, processing the exposed portion of the first dielectric layer 8 to form a third dielectric layer 10, wherein the third dielectric layer 10 has different properties from the second dielectric layer 8; step S205, removing the remaining second dielectric layer 9 and the first dielectric layer 8 and exposing the substrate 1; step S206, side etching the exposed portion of the substrate 1 to expand a portion of the bit line trench 2 and form the first trench segment 21.

[0046] Please continue reading Figure 8 , step S201, in the bit line trench 2 (shown in Figure 9 ) is deposited within a first dielectric layer 8 (shown in FIG. Figure 9 ), the first dielectric layer 8 covers the inner wall of the bit line trench 2; step S202, depositing a second dielectric layer 9 (shown in FIG. 1 ) on the first dielectric layer 8 Figure 9 ). See below. Figure 9A substrate 1 has a bitline trench 2. A first dielectric layer 8 is deposited within the bitline trench 2. In this embodiment, the first dielectric layer 8 is, for example, a SiN layer. The thickness of the SiN layer is, for example, 3 to 5 nm, for example, 3 nm. The first dielectric layer 8 covers the inner wall of the bitline trench 2. A second dielectric layer 9 is deposited on the first dielectric layer 8. In this embodiment, the first dielectric layer 8 and the second dielectric layer 9 are formed using atomic layer deposition (ALD). The second dielectric layer 9 can be a SiO2 layer. The ALD method can precisely control the thickness of the first dielectric layer 8 and the second dielectric layer 9. When the first dielectric layer 8 is within the above range, it can effectively protect the substrate 1 and ensure that the subsequent processing of the first dielectric layer 8 can completely obtain the third dielectric layer 10, thereby obtaining a bitline trench 2 of the desired shape.

[0047] Please continue reading Figure 8 Step S203, etching back a portion of the second dielectric layer 9 and exposing a portion of the first dielectric layer. Step S204, processing the exposed portion of the first dielectric layer 8 to form a third dielectric layer 10 (shown in FIG. Figure 10 ), the third dielectric layer 10 has different properties from the second dielectric layer 9. The first dielectric layer 8 is formed into a third dielectric layer 10 having different properties, thereby separating and forming the first trench segment 21 and the second trench segment 22. In this case, the depth of the etched-back portion of the second dielectric layer 9 can be the predetermined height of the bit line metal 2, that is, the height of the first trench segment 21. Figure 10 is a schematic diagram of the third dielectric layer 10 in one embodiment of the present disclosure. Figure 10 , partially etch back the second dielectric layer 9, and process the exposed portion of the first dielectric layer 8 to form a third dielectric layer 10. In this embodiment, oxygen plasma is used to treat the exposed portion of the first dielectric layer 8 to form the third dielectric layer 10. The first dielectric layer 8 is a nitride, and after oxidation, a third dielectric layer 10 of nitride oxide is formed. For example, if the first dielectric layer 8 is a silicon nitride material, then the material of the third dielectric layer 10 is a silicon oxynitride material. In some embodiments, the temperature of the plasma oxygen reduction process is 800°C to 900°C, for example, 800°C, 852°C, the plasma intensity is 600W to 2000W, for example, 700W, 1200W, and the pressure is 1Pa to 10Pa, for example, 4Pa, 8Pa. Under the above environment, the exposed portion of the first dielectric layer 8 can be fully oxidized into a third dielectric layer 10 with different properties. The processing method used in the embodiments of the present disclosure is certainly not limited to this. For example, other suitable methods such as high-temperature furnace oxidation, inert ion implantation, and nitridation treatment can also be used. It should be understood that any method that can process the first dielectric layer 8 to form a third dielectric layer 10 with different properties should be included in the scope of protection required by the present disclosure.

[0048] Please continue reading Figure 8 , step S205, removing the remaining second dielectric layer 9 and the first dielectric layer 8, and exposing the substrate 1 (shown in Figure 11 ); Step S206, lateral etching is performed to expose a portion of the substrate 1 to expand a portion of the bit line trench 2 and form the first trench segment 21 (shown in FIG. Figure 11 ). Figure 11 This is a schematic diagram of the first groove segment 21 in one embodiment of the present disclosure. Figure 11 , the exposed portion of the substrate 1 is laterally etched to expand a portion of the bit line trench 2 and form the first trench segment 21. At this time, the remaining portion of the bit line trench 2 serves as the second trench segment 22 (shown in FIG. Figure 7 In some embodiments, sulfur hexafluoride, carbon tetrafluoride, trifluoromethane, oxygen, argon, or a mixture of these gases is used to remove the first dielectric layer 8 and the second dielectric layer 9, wherein argon can be used as a protective gas during the etching process.

[0049] Please return to Figure 5 , step S102 , filling the bit line trench 2 with a bit line metal 3 . Figure 12 Schematic diagram of the first barrier layer and the second barrier layer in one embodiment of the present disclosure. Figure 12 In some embodiments, before filling the bitline metal 3 in the bitline trench 2, the preparation method further includes: forming a first barrier layer 6 in the bitline trench 2, and / or forming a second barrier layer 5 in the bitline trench 2, wherein the second barrier layer 5 is located on the surface of the first barrier layer 6, and the bitline metal 3 covers the bottom and sidewalls of the second barrier layer 5. In some embodiments, the substrate 1 in the bitline trench 2 is nitrided to form the first barrier layer 6. The plasma nitriding gas used for nitriding the substrate 1 is ammonia gas, the temperature is 600°C to 800°C, for example, 620°C or 700°C, the plasma intensity is 600W to 2000W, for example, 600W or 720W, and the pressure is 1Pa to 10Pa, for example, 3Pa or 7Pa. In other embodiments, a portion of the substrate 1 can be oxidized to form a silicon oxide material as the first barrier layer 6. Of course, the first barrier layer 6 can also be formed directly by deposition. The second barrier layer 5 is then deposited on the surface of the first barrier layer 6 to form the second barrier layer 5. The second barrier layer 5 is, for example, a metal nitride layer. Of course, the first barrier layer 6 may not be provided and the second barrier layer 5 may be formed directly on the surface of the substrate 1 .

[0050] Please continue reading Figure 12In some embodiments, the filling of the bit line metal 3 in the bit line trench 2 includes: filling the first trench segment 21 and the second trench segment 22 of the bit line trench 2 with a metal material 11, whereby an air gap 12 is formed in the filled metal material 11; etching back a portion of the metal material 11 to the air gap 12 so that the remaining metal material 11 has an arc-shaped surface, and the remaining metal material 11 constitutes the bit line metal 3, for example, Figure 3 In the disclosed embodiment, the bit line trench 2 has a narrow upper portion and wide lower portion structure. An air gap 12 is formed during the deposition of the metal material 11. This air gap can be exposed during controlled etch-back, resulting in a concave circular surface on the surface of the ultimately formed bit line metal 3. This allows for a large contact area between the subsequent bit line contact 4 and the underlying conductive metal 3, facilitating electrical conductivity.

[0051] Please return to Figure 5 , step S103, forming a bit line contact 4 on the bit line metal 3, wherein an arc-shaped contact surface is formed between the bit line contact 4 and the bit line metal 3. Figure 12 and Figure 3 After removing the metal material 11 above, the third dielectric layer 10 on the sidewalls is also removed, and a bitline contact 4 is deposited on the bitline metal 3. The bitline contact 4 is electrically conductive between the bitline metal 3 and the substrate 1. In some embodiments, for example, the bitline contact 4 can be made of polysilicon, for example, by LPCVD deposition, where the reaction gas may be silane (SiH4) and phosphine (PH3) doping deposition at a temperature of 480°C to 520°C, for example, 5000°C. The SiH4 and PH3 are mixed and decomposed by LPCVD heating to form P-doped polysilicon, which is thus electrically conductive.

[0052] In some embodiments, the method for preparing the buried bit line structure further includes: forming a sidewall 7 (shown in FIG. Figure 4 ), the sidewall 7 is filled in the bit line trench 2 (shown in Figure 4 ) and located within the bit line contact 4 (shown in Figure 4 ), the side wall 7 at least partially extends to the base 1 (shown in Figure 4 )Inside. Figure 4 FIG is a schematic diagram of a buried bit line structure in an embodiment of the present disclosure. Figure 4The buried bitline structure includes: a substrate 1 having a bitline trench 2; a bitline metal 3 filled in the bitline trench 2; a bitline contact 4 filled in the bitline trench 2 and located on the bitline metal 3, with an arc-shaped contact surface between the bitline contact 4 and the bitline metal 3; a first barrier layer 6 located in the bitline trench, and / or a second barrier layer 5 located on the surface of the first barrier layer, with the bitline metal 3 covering the bottom wall and sidewalls of the second barrier layer 5. In this embodiment, the buried bitline structure further includes: a sidewall spacer 7 filled in the bitline trench 2 and located on the bitline contact 4, with the sidewall spacer 7 at least partially extending outside the substrate 1. The bit line contact 4 in the bit line trench 2 does not completely fill the second trench section 22 of the bit line trench 2, or a portion of the bit line contact 4 is etched back, thereby depositing an insulating material, such as SiN material, in the remaining bit line trench 2. The SiN material is also formed in the trench of the upper mask layer (not shown). After removing the upper mask layer, a spacer 7 is formed. Figure 4 As shown. Afterwards, for example, a sidewall layer such as SiN-SiO2-SiN can be formed on the surface of the sidewall 7 (not shown in the figure). Since the material of the SiN-SiO2-SiN structure has the characteristic of low dielectric constant, it can be used to prepare a sidewall with low dielectric constant to enhance the sidewall's anti-puncture capability.

[0053] The above technical solution, by configuring the contact surface between the bitline contact 4 and the bitline metal 3 as an arc-shaped contact surface, increases the contact area between the bitline contact 4 and the bitline metal 3, thereby enhancing the conductivity of the bitline structure. In some embodiments, the width of the first trench segment 21 is increased, further widening the width of the bitline metal, thereby preventing the bitline structure from collapsing during subsequent etching processes. This provides a bitline structure that is not easily damaged during the manufacturing process and has a large conductive contact area, thereby adapting to bitline structure failure caused by scaling.

[0054] An embodiment of the present disclosure also provides a memory, including: a buried bit line structure; the buried bit line structure includes: a substrate having a bit line groove; a bit line metal filled in the bit line groove; a bit line contact located on the bit line metal, and an arc-shaped contact surface between the bit line contact and the bit line metal contact.

[0055] The above-disclosed technical solution increases the contact area between the bitline contact and the bitline metal by configuring the contact surface between the bitline contact and the bitline metal as an arc-shaped contact surface, thereby enhancing the conductivity of the bitline structure. In some embodiments, the width of the first trench segment is increased, further widening the width of the bitline metal, thereby preventing the bitline structure from collapsing during subsequent etching processes. This provides a bitline structure that is resistant to damage during the manufacturing process and has a large conductive contact area. This adapts to bitline structure failures caused by bitline structure miniaturization, reduces memory failures and damage caused by bitline structure failures, and extends the memory's service life.

[0056] The above description is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A buried bit line structure, characterized in that: include: a substrate having a bit line trench; A bit line metal is filled in the bit line trench; The bit line contact is filled in the bit line trench and is located on the bit line metal. An arc-shaped contact surface is formed between the bit line contact and the bit line metal.

2. The buried bit line structure according to claim 1, wherein: The bit line trench comprises: a first trench section, wherein the bit line metal is filled in the first trench section; The bit line contact is filled in the second trench segment, the second trench segment extends in the direction of the first trench segment, and the cross-sectional area of ​​the second trench segment is smaller than the cross-sectional area of ​​the first trench segment.

3. The buried bit line structure according to claim 1, wherein: The buried bit line structure further includes: a first barrier layer located in the bit line trench, and / or The second barrier layer is located on the surface of the first barrier layer, and the bit line metal covers the bottom wall and side walls of the second barrier layer.

4. The buried bit line structure according to claim 1, wherein: The buried bit line structure further includes: A sidewall is filled in the bit line trench and is located on the bit line contact. The sidewall is at least partially extended out of the substrate.

5. The buried bit line structure according to claim 1, wherein: The projection of the bit line contact on the substrate is located within the projection of the bit line metal on the substrate.

6. A method for preparing a buried bit line structure, characterized in that: The preparation method comprises: Providing a substrate and forming a bit line trench in the substrate; filling the bit line trench with a bit line metal; A bit line contact is formed on the bit line metal, and an arc-shaped contact surface is formed between the bit line contact and the bit line metal.

7. The method for preparing a buried bit line structure according to claim 6, wherein: Before filling the bit line metal in the bit line trench, the preparation method further includes: enlarging a portion of the bit line trench to form a first trench segment; A second trench segment is formed on the remaining bit line trenches, wherein the second trench segment extends in the direction of the first trench segment, and a cross-sectional area of ​​the second trench segment is smaller than a cross-sectional area of ​​the first trench segment.

8. The method for preparing a buried bit line structure according to claim 7, wherein: The method of expanding a portion of the bit line trench and forming a first trench segment includes: depositing a first dielectric layer in the bit line trench, wherein the first dielectric layer covers an inner wall of the bit line trench; depositing a second dielectric layer on the first dielectric layer; Etching back a portion of the second dielectric layer and exposing a portion of the first dielectric layer; processing the exposed portion of the first dielectric layer to form a third dielectric layer, the third dielectric layer having different properties from the second dielectric layer; removing the remaining second dielectric layer and the first dielectric layer to expose the substrate; The exposed portion of the substrate is laterally etched to expand a portion of the bit line trench and form the first trench segment.

9. The method for preparing a buried bit line structure according to claim 8, wherein: The exposed portion of the first dielectric layer is treated with oxygen plasma to form a third dielectric layer, wherein the first dielectric layer is silicon nitride and the third dielectric layer is silicon oxynitride.

10. The method for preparing a buried bit line structure according to claim 7, wherein: The step of filling the bit line trench with bit line metal comprises: Filling the first trench section and the second trench section of the bit line trench with metal material, wherein the filled metal material has air gaps; A portion of the metal material is etched back to the air gap, so that the remaining metal material has an arc-shaped surface, and the remaining metal material constitutes the bit line metal.

11. The method for preparing a buried bit line structure according to claim 7, wherein: Before filling the bit line trench with a bit line metal, the preparation method further includes: forming a first barrier layer in the bit line trench, and / or, A second barrier layer is formed in the bit line trench, the second barrier layer is located on the surface of the first barrier layer, and the bit line metal covers the bottom wall and side walls of the second barrier layer.

12. The method for preparing a buried bit line structure according to claim 11, wherein: The substrate in the bit line trench is nitrided to form the first barrier layer.

13. The method for preparing a buried bit line structure according to claim 12, wherein: The plasma nitriding gas used in nitriding the substrate is ammonia gas, and the temperature is 600 to 800 degrees Celsius.

14. The method for preparing a buried bit line structure according to claim 8, wherein: The first dielectric layer or the second dielectric layer is removed by using sulfur hexafluoride, carbon tetrafluoride, trifluoromethane, oxygen, argon, or any combination thereof.

15. The method for preparing a buried bit line structure according to claim 6, wherein: Also includes: A sidewall is formed, the sidewall is filled in the bit line trench and is located on the bit line contact, and the sidewall at least partially extends out of the substrate.

16. A memory, characterized in that: include: buried bit line structure; The buried bit line structure comprises: a substrate having a bit line trench; A bit line metal is filled in the bit line trench; The bit line contact is located on the bit line metal, and an arc-shaped contact surface is formed between the bit line contact and the bit line metal contact.

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