Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The structure includes: a channel structure layer comprising a plurality of first channel layers spaced apart from bottom to top, the first channel layers extending laterally, with a longitudinal direction parallel to the substrate and perpendicular to the lateral direction; a gate structure spanning the channel structure layer and surrounding the first channel layers; source / drain structures located on both sides of the gate structure, including first source / drain doped layers located on the sidewalls of the first channel layers; and source / drain plugs contacting the top of the source / drain structures and also contacting at least one sidewall of the first source / drain doped layers along the longitudinal direction and opposite to the gate structure, along a first lateral sidewall, and along a second lateral sidewall. The source / drain plugs contact at least one sidewall of the first source / drain doped layers, allowing current to flow directly through the source / drain plugs to each of the first channel layers, reducing the voltage drop consumed in the path of current flow to each of the first channel layers, increasing the channel current value within each of the first channel layers, and enhancing the drive current of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration, and semiconductor process nodes are continuously shrinking in accordance with Moore's Law. Transistors, as the most basic semiconductor devices, are currently widely used. Therefore, as the component density and integration of semiconductor devices increase, the channel length of transistors must be continuously shortened to adapt to the shrinking process nodes.

[0003] To better adapt to the requirements of proportionally shrinking device dimensions, semiconductor technology has gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors. In a GAA transistor, the gate surrounds the channel area from all sides. Compared with planar transistors, GAA transistors have stronger control over the channel and can better suppress short-channel effects.

[0004] However, the performance of fully enclosed gate transistors still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which enhances the driving current of the device and optimizes the performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate; a channel structure layer located on the substrate, the channel structure layer comprising a plurality of first channel layers spaced apart sequentially from bottom to top, the first channel layers extending laterally, the direction parallel to the substrate and perpendicular to the lateral direction being the longitudinal direction; a gate structure spanning the channel structure layer and surrounding the first channel layers, and the gate structure filling between adjacent first channel layers and between the substrate and the first channel layers adjacent to the substrate; a source / drain structure located on both sides of the gate structure and covering the sidewalls of the channel structure layer, the source / drain structure comprising a first source / drain doped layer located on the sidewall of the first channel layer along the lateral direction; and source / drain plugs located on both sides of the gate structure and contacting the top of the source / drain structure, and the source / drain plugs also contacting at least one of the following sidewalls of the first source / drain doped layer along the longitudinal direction and opposite to the gate structure, along a first lateral side, and along a second lateral side.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a stacked structure is formed on the substrate, including a plurality of channel stacks stacked sequentially from bottom to top, each channel stack including a sacrificial layer and a first channel layer located on the sacrificial layer, the first channel layer extending laterally, and the direction parallel to the substrate and perpendicular to the lateral direction being the longitudinal direction; forming a pseudo-gate structure spanning the stacked structure on the substrate; forming grooves in the stacked structures on both sides of the pseudo-gate structure; and forming a source / drain structure in the grooves, including a first source / drain doped layer covering the sidewalls of the first channel layer exposed in the grooves. Remove the dummy gate structure to form a gate opening, exposing the channel stack; remove the sacrificial layer in the channel stack through the gate opening, so that the adjacent first channel layer, the substrate, and the first channel layer adjacent to the substrate form a through trench; form a gate structure in the gate opening and the through trench, surrounding the first channel layer; form source / drain plugs on both sides of the gate structure, contacting the top of the source / drain structure, and the source / drain plugs also contact at least one of the following sidewalls of the first source / drain doped layer: a sidewall along the longitudinal direction and opposite to the gate structure, a sidewall along the first transverse side, and a sidewall along the second transverse side.

[0008] Compared with the prior art, the technical solution of the present invention has the following advantages: In the semiconductor structure provided by the present invention, the source-drain plug is in contact with the top of the source-drain structure, and the source-drain plug is also in contact with at least one of the sidewalls of the first source-drain doped layer along the longitudinal direction and opposite to the gate structure, the sidewall along the first transverse side, and the sidewall along the second transverse side. Compared to the scheme where the source / drain plug only contacts the top of the source / drain doped layer, the source / drain plug provided in this invention also has a contact surface along a direction perpendicular to the substrate surface. The source / drain plug can contact the first source / drain doped layers located on the sidewalls of each first channel layer. When the device is operating, the current can flow directly through the source / drain plug through the sidewalls of the first source / drain doped layer to each first channel layer, which is beneficial to bypass the current flow in the source / drain structure along the direction perpendicular to the substrate. Since the resistivity of the source / drain plug material is usually significantly smaller than that of the source / drain structure material, the current flowing directly through the source / drain plug to each first channel layer helps to reduce parasitic resistance, thereby reducing the voltage drop consumed by the current in the path to each first channel layer, increasing the channel current value in each first channel layer, especially significantly increasing the channel current value in the first channel layer closer to the substrate, thereby enhancing the device's drive current and optimizing the performance of the semiconductor structure.

[0009] In the semiconductor structure formation method provided by the present invention, source and drain plugs are formed on both sides of the gate structure and are in contact with the top of the source and drain structure. The source and drain plugs are also in contact with at least one of the following sidewalls of the first source and drain doped layer: a sidewall along the longitudinal direction and opposite to the gate structure, a sidewall along the first transverse side, and a sidewall along the second transverse side. Compared to the scheme where the source / drain plug only contacts the top of the source / drain doped layer, the source / drain plug formed in this invention also has a contact surface along a direction perpendicular to the substrate surface. The source / drain plug can contact the first source / drain doped layer located on the sidewall of each first channel layer. When the device is working, the current can flow directly through the source / drain plug through the sidewall of the first source / drain doped layer to each first channel layer, which is beneficial to bypass the current flow in the source / drain structure along the direction perpendicular to the substrate. Since the resistivity of the source / drain plug material is usually significantly smaller than that of the source / drain structure material, the current flowing directly through the source / drain plug to each first channel layer helps to reduce parasitic resistance, thereby reducing the voltage drop consumed by the current in the path to each first channel layer, increasing the channel current value in each first channel layer, especially significantly increasing the channel current value in the first channel layer closer to the substrate, thereby enhancing the device drive current and optimizing the performance of the semiconductor structure. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a partial three-dimensional structure of a semiconductor structure.

[0011] Figures 2 to 3 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0012] Figures 4 to 20 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0013] As the background technology shows, the performance of fully enclosed gate transistors still needs improvement. This paper analyzes the reasons why the performance of fully enclosed gate transistors needs further improvement, using a specific semiconductor structure as an example. Figure 1 This is a schematic diagram of a partial three-dimensional structure of a semiconductor structure.

[0014] The semiconductor structure includes: a substrate 10; a channel structure layer 11 located on the substrate 10, the channel structure layer 11 including a plurality of channel layers 12 arranged sequentially from bottom to top; a gate structure 13 spanning the channel structure layer 11 and covering the top of the channel structure layer 11, the gate structure 13 filling between adjacent first channel layers 12 and surrounding the channel layers 12; source / drain doped layers 14 located on both sides of the gate structure 13 and covering the sidewalls of the channel structure layer 11; a dielectric layer 15 located on the substrate 10 and covering the source / drain doped layers 14; and a source / drain plug 16 located in the dielectric layer 15 on top of the source / drain doped layers 14 and in contact with the top of the source / drain doped layers 14.

[0015] The semiconductor structure is a fully enclosed gate transistor. When the fully enclosed gate transistor is working, the external current flows sequentially through the source / drain plug 16 on the first side of the gate structure 13, the source / drain doped layer 14 on the first side of the gate structure 13, the channel layer 12, the source / drain doped layer 14 on the second side of the gate structure 13, and the source / drain plug 16 on the second side of the gate structure 13, and finally flows out of the device.

[0016] For the channel layers 12 that are far from the source / drain plugs 16, such as the bottom channel layer 12(a) (i.e. the channel layer 12 closest to the substrate 10), the current needs to flow through the source / drain doped layers 14 for a longer path along the direction perpendicular to the substrate 10. The parasitic resistance of the source / drain doped layers 14 is large along this longer flow path, which will consume more voltage drop. As a result, the channel current flowing through these channel layers 12 that are far from the source / drain plugs 16 is small, which is not conducive to improving the drive current of the device.

[0017] To address these issues, one approach is to increase the ion doping concentration of the source / drain doped layer to reduce its resistance. However, in semiconductor manufacturing, the source / drain doped layer is typically formed using epitaxial growth, and increasing the ion doping concentration can negatively impact the growth quality of the epitaxial layer, ultimately leading to a decrease in the film quality of the source / drain doped layer.

[0018] Another approach is to increase the projected area of ​​the source / drain doped layer on the substrate. This correspondingly increases the cross-sectional area of ​​the conductive region, which helps reduce the resistance of the source / drain doped layer and the source / drain plug. However, increasing the projected area of ​​the source / drain doped layer on the substrate leads to an increase in design size, which is detrimental to reducing manufacturing costs and device size.

[0019] Therefore, neither of the above two methods can solve the problem of low channel current in the channel layer that is far from the source-drain contact plug.

[0020] To address the aforementioned technical problem, embodiments of the present invention provide a semiconductor structure in which a source / drain plug contacts the top of the source / drain structure, and the source / drain plug also contacts at least one of the following sidewalls of the first source / drain doped layer: a sidewall along the longitudinal direction and opposite to the gate structure, a sidewall along the first transverse side, and a sidewall along the second transverse side. Compared to the scheme where the source / drain plug only contacts the top of the source / drain doped layer, the source / drain plug provided in this invention also has a contact surface along a direction perpendicular to the substrate surface. The source / drain plug can contact the first source / drain doped layers located on the sidewalls of each first channel layer. When the device is operating, the current can flow directly through the source / drain plug through the sidewalls of the first source / drain doped layer to each first channel layer, which is beneficial to bypass the current flow in the source / drain structure along the direction perpendicular to the substrate. Since the resistivity of the source / drain plug material is usually significantly smaller than that of the source / drain structure material, the current flowing directly through the source / drain plug to each first channel layer helps to reduce parasitic resistance, thereby reducing the voltage drop consumed by the current in the path to each first channel layer, increasing the channel current value in each first channel layer, especially significantly increasing the channel current value in the first channel layer closer to the substrate, thereby enhancing the device's drive current and optimizing the performance of the semiconductor structure.

[0021] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figures 2 to 3 , Figure 2 This is a schematic diagram of a partial three-dimensional structure. Figure 3 (a) is Figure 2 A sectional view along the xx direction. Figure 3 (b) is Figure 2 A cross-sectional view along the yy direction shows a schematic diagram of an embodiment of the semiconductor structure of the present invention.

[0022] like Figures 2 to 3 As shown, in this embodiment, the semiconductor structure includes: a substrate 100; a channel structure layer 400 located on the substrate 100, the channel structure layer 400 including a plurality of first channel layers 30 arranged sequentially from bottom to top, the first channel layers 30 being arranged laterally (e.g., ...). Figure 2 Extending in the X direction (as shown), the longitudinal direction is parallel to the base 100 and perpendicular to the said transverse direction (e.g., as shown in the X direction). Figure 2(As shown in the Y direction); Gate structure 410, spanning the channel structure layer 400 and surrounding the first channel layer 30, and the gate structure 410 filling between adjacent first channel layers 30, and between the substrate 100 and the first channel layer 30 adjacent to the substrate 100; Source / drain structure 300, located on both sides of the gate structure 410 and covering the sidewalls of the channel structure layer 400, the source / drain structure 300 including a first source / drain doped layer 310 located on the sidewalls of the first channel layer 30 along the transverse direction; Source / drain plug 350, located on both sides of the gate structure 410 and contacting the top of the source / drain structure 300, and the source / drain plug 350 also contacting at least one of the following sidewalls of the first source / drain doped layer 310: a longitudinal sidewall 35 opposite to the gate structure 410, a sidewall 36 along a first transverse direction, and a sidewall (not shown) along a second transverse direction.

[0023] The source / drain plug 350 contacts the top of the source / drain structure 300, and the source / drain plug 350 also contacts at least one of the following sidewalls of the first source / drain doped layer 310: a longitudinal sidewall 35 opposite to the gate structure 410, a sidewall 36 along a first transverse side, and a sidewall along a second transverse side. Compared to a solution where the source / drain plug only contacts the top of the source / drain doped layer, the source / drain plug 350 provided in this embodiment also has a contact with the first source / drain doped layer 310 along a direction perpendicular to the surface of the substrate 100 (e.g., ...). Figure 2 The source / drain plug 350 (as shown in the Z-direction) can contact the first source / drain doped layers 310 located on the sidewalls of each first channel layer 30. When the device is working, the current can flow directly through the source / drain plug 350 through the sidewalls of the first source / drain doped layers 310 to each first channel layer 30. This is beneficial for bypassing the current flow in the source / drain structure 300 along the direction perpendicular to the substrate 100. Since the resistivity of the source / drain plug 350 material is usually significantly smaller than that of the source / drain structure material, the current flowing directly through the source / drain plug 350 to each first channel layer 30 helps to reduce parasitic resistance, thereby reducing the voltage drop consumed by the current in the path to each first channel layer 30, increasing the channel current value in each first channel layer 30, especially significantly increasing the channel current value in the first channel layer 30 closer to the substrate 100, thereby enhancing the device's drive current and optimizing the performance of the semiconductor structure.

[0024] The substrate 100 serves as a process platform for the formation of semiconductor structures. In this embodiment, a gate-all-around (GAA) transistor is used as an example of the semiconductor structure. In other embodiments, the semiconductor structure may also be a forksheet transistor or a complementary field-effect transistor (CFET).

[0025] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, etc., and the substrate may also be other types of substrates such as silicon on insulator or germanium on insulator.

[0026] The channel structure layer 400 is used to provide a conductive channel for the field-effect transistor.

[0027] As an example, the channel structure layer 400 is a fin-like structure extending along the lateral direction.

[0028] The stacking direction of multiple first channel layers 30 arranged sequentially from bottom to top at intervals (e.g.) Figure 2 (As shown in the Z direction) is perpendicular to the surface of the substrate 100.

[0029] In this embodiment, the semiconductor structure is an NMOS transistor, and the material of the first channel layer 30 is Si. In other embodiments, when the semiconductor structure is a PMOS transistor, SiGe channel technology can be used to improve the performance of the PMOS transistor, and the material of the first channel layer is SiGe.

[0030] As an example, in the channel structure layer 400, the number of first channel layers 30 is three. In other embodiments, the number of first channel layers may also be different.

[0031] As an example, the channel structure layer 400 further includes a second channel layer 40, located between the substrate 100 and the first channel layer 30 and spaced apart from the first channel layer 30. The second channel layer 40 also serves to provide a conductive channel for the field-effect transistor.

[0032] In this embodiment, the material of the second channel layer 40 is the same as that of the first channel layer 30, and the material of the second channel layer 40 is silicon.

[0033] In this embodiment, the semiconductor structure further includes an isolation structure 110 located in a portion of the thickness of the substrate 100 on the side of the channel structure layer 400. The isolation structure 110 serves to isolate adjacent channel structure layers 400.

[0034] In this embodiment, the material of the isolation structure 110 is silicon oxide. The isolation structure 110 can also be other insulating materials.

[0035] Specifically, the substrate 100 includes a substrate (not shown) and a protrusion (not shown) extending from the substrate. The isolation structure 110 is located on the substrate on the side of the protrusion, and the isolation structure 110 exposes the channel structure layer 400. Accordingly, the isolation structure 110 is also used to define the active area (AA) and isolation area of ​​the substrate 100.

[0036] As an example, the protrusion and the second channel layer 40 are an integral structure.

[0037] It should be noted that this embodiment is illustrated by the example of the channel structure layer 400 also including the second channel layer 40. In other embodiments, depending on actual process requirements, the channel structure layer may only include the first channel layer. Correspondingly, the top surface of the isolation structure is flush with the top surface of the protrusion.

[0038] When the device is in operation, the gate structure 410 is used to control the opening and closing of the conductive channel.

[0039] In this embodiment, the gate structure 410 is filled between adjacent first channel layers 30, and between the second channel layer 40 and the first channel layer 30 adjacent to the second channel layer 40.

[0040] In this embodiment, the gate structure 410 is a metal gate structure, which includes a high-k gate dielectric layer (not shown), a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer.

[0041] The high-k gate dielectric layer is used to achieve electrical isolation between the work function layer, the gate electrode layer, and the channel. The material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can also be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0042] The work function layer is used to adjust the work function of the gate structure 410, thereby adjusting the threshold voltage of the field-effect transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon tantalum nitride, silicon titanium nitride, and tantalum carbide.

[0043] The gate electrode layer serves as the external electrode for electrical connection between the gate structure 410 and external circuitry. The gate electrode layer is made of a conductive material, such as W, Al, Cu, Ag, Au, Pt, Ni, or Ti.

[0044] In this embodiment, the gate structure 410 includes a first portion (not shown) that spans the channel structure layer 400, and a second portion (not shown) that fills the spaces between adjacent first channel layers 30 and between the second channel layer 40 and adjacent first channel layers 30.

[0045] In this embodiment, along the lateral direction, the sidewalls of the first portion and the second portion are recessed relative to the sidewall on the same side of the first channel layer 30 to provide space for the gate sidewall and the inner sidewall.

[0046] In this embodiment, along the lateral direction, the sidewall of the first portion is recessed relative to the sidewall on the same side of the first channel layer 30 to provide space for the gate sidewall; the semiconductor structure further includes: a gate sidewall 130, located on the sidewall of the first portion and covering a portion of the top of the channel structure layer 400.

[0047] The gate sidewall 130 is used to define the formation location of the source-drain structure 300, and the gate sidewall 130 is also used to protect the sidewall of the gate structure 410.

[0048] In this embodiment, the material of the gate sidewall 130 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material, and the gate sidewall 130 is a single-layer or multi-layer structure. As an example, the gate sidewall 130 is a single-layer structure, and the material of the gate sidewall 130 is silicon nitride.

[0049] In this embodiment, along the lateral direction, the sidewall of the second portion is recessed relative to the sidewall on the same side of the first channel layer 30 to provide space for the inner sidewall; the semiconductor structure further includes: an inner sidewall 150, filling the region enclosed by the second portion and the adjacent first channel layer 30, and the region enclosed by the second portion, the substrate 100 and the first channel layer 30 adjacent to the substrate 100.

[0050] Specifically, the inner wall 150 fills the area enclosed by the second part and the adjacent first channel layer 30, as well as the area enclosed by the second part, the second channel layer 40, and the first channel layer 30 adjacent to the second channel layer 40.

[0051] The inner wall 150 is used to isolate the source-drain structure 300 from the gate structure 410, and also increases the distance between the gate structure 410 and the source-drain structure 300, which helps to reduce the parasitic capacitance between the gate structure 410 and the source-drain structure 300.

[0052] In this embodiment, the inner wall 150 is made of an insulating material to achieve isolation between the source / drain structure 300 and the gate structure 410. In this embodiment, the material of the inner wall 150 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material. As an example, the material of the inner wall 150 is silicon nitride.

[0053] In this embodiment, the semiconductor structure further includes an etch stop layer 420 located on top of the gate structure 410. The etch stop layer 420 is used to protect the top of the gate structure 410 to prevent accidental etching of the gate structure 410 during the formation of the source / drain plug 350, thereby helping to prevent short circuit between the source / drain plug 350 and the gate structure 410.

[0054] In this embodiment, the gate sidewall 130 covers the first portion and the sidewall of the etch stop layer 420.

[0055] The etching stop layer 420 is made of a material that has etching selectivity with the material of the interlayer dielectric layer 160, so as to ensure that the etching process for forming the source / drain plug 350 is not likely to cause erroneous etching of the etching stop layer 420.

[0056] In this embodiment, the material of the etch stop layer 420 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the etch stop layer 420 is silicon carbide.

[0057] The source-drain structure 300 is used as the source or drain of the field-effect transistor. When the field-effect transistor is working, the source-drain structure 300 is used to provide a source of charge carriers.

[0058] In this embodiment, it is not necessary to reduce the resistance of the source / drain structure by increasing the ion doping concentration of the source / drain structure in order to increase the channel current in the channel layer. This is beneficial to ensuring the epitaxial growth quality of the epitaxial process forming the source / drain structure 300, thereby improving the film formation quality of the source / drain structure 300 and optimizing the performance of the semiconductor structure.

[0059] Furthermore, in this embodiment, it is not necessary to reduce the resistance of the source / drain structure in order to increase the channel current in the channel layer by increasing the projected area of ​​the source / drain structure on the substrate. This is beneficial for miniaturization of the device size and also helps to reduce manufacturing costs.

[0060] In this embodiment, the source-drain structure 300 includes an ion-doped stress layer, which provides stress to the channel region to improve carrier mobility.

[0061] Specifically, the first source / drain doped layer 310 is used to provide stress for the first channel layer 30.

[0062] In this embodiment, when forming a PMOS transistor, the source-drain structure 300 includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe; when forming an NMOS transistor, the source-drain structure 300 includes a stress layer doped with N-type ions, and the material of the stress layer is Si or SiC.

[0063] As an embodiment, the first source / drain doped layers 310 located on adjacent sidewalls of the first channel layer 30 are spaced apart. When the source / drain plug 350 is in contact with at least one of the following sidewalls of the first source / drain doped layers 310: the sidewall along the longitudinal direction and opposite to the gate structure 410, the sidewall along the first transverse side, and the sidewall along the second transverse side, since the first source / drain doped layers 310 on adjacent sidewalls of the first channel layer 30 are not in contact, current can be prevented from flowing in the source / drain structure 300 along a direction perpendicular to the substrate 100 (e.g., ...) during device operation. Figure 2 The flow (as shown in the Z direction) allows the current to flow only through the source-drain plug 350 to each first channel layer 30, which significantly reduces the voltage drop consumed by the current in the path to each first channel layer 30, and increases the channel current value in each first channel layer 30, especially significantly increasing the channel current value in the first channel layer 30 closer to the substrate 100.

[0064] In other embodiments, the first source / drain doped layers located on the sidewalls of adjacent first channel layers may also be in contact with each other. When the semiconductor structure typically includes an interlayer dielectric layer covering the source / drain structure, the interlayer dielectric layer does not need to fill the gaps between the first source / drain doped layers located on the sidewalls of adjacent first channel layers. This helps to reduce the process difficulty of forming the interlayer dielectric layer and correspondingly improves process compatibility and film quality of the interlayer dielectric layer.

[0065] In this embodiment, the first source / drain doped layer 310 is opposite to the sidewall 36 along the first transverse side and the sidewall (not shown) along the second transverse side in the longitudinal direction.

[0066] In this embodiment, the source / drain structure 400 further includes: a second source / drain doped layer 320 located on the sidewall of the second channel layer 40 along the lateral direction, the second source / drain doped layer 320 also located on the top surface of the substrate 100 on both sides of the second channel layer 40, and the end of the second source / drain doped layer 320 protrudes from the end of the first source / drain doped layer 310 along the lateral direction.

[0067] The second source / drain doped layer 320 is used to provide stress to the second channel layer 40, thereby improving the carrier mobility within the second channel layer 40.

[0068] In this embodiment, the material of the second source / drain doped layer 320 is the same as that of the first source / drain doped layer 310, and the doping type of the second source / drain doped layer 320 is also the same as that of the first source / drain doped layer 310.

[0069] In this embodiment, the end of the second source / drain doped layer 320 protrudes beyond the end of the first source / drain doped layer 310 along the lateral direction. This leaves space in the area enclosed by the top of the second source / drain doped layer 320 and the side of the first source / drain doped layer 310 for forming the source / drain plug 350. This also allows the source / drain plug 350 to have a smaller lateral dimension, reducing the lateral area occupied by the source / drain plug 350 and thus reducing the size of the semiconductor structure. Furthermore, the second source / drain doped layer 320 is located on the top surface of the substrate 100 on both sides of the second channel layer 40. The plug 350 can contact the top of the second source / drain doped layer 320, which not only realizes the electrical connection between the source / drain plug 350 and the second source / drain doped layer 320, but also prevents the source / drain plug 350 from contacting the substrate 100. In addition, the source / drain plug 350 can contact the longitudinal sidewall of the first source / drain doped layer 310 that is opposite to the gate structure 410. Compared with the transverse sidewall of the first source / drain doped layer 310, the longitudinal sidewall of the first source / drain doped layer 310 has a larger area, thereby increasing the contact area between the source / drain plug 350 and the first source / drain doped layer 310.

[0070] It should be noted that, along the lateral direction, the width of the first source / drain doped layer 310 should not be too small or too large. If the width of the first source / drain doped layer 310 along the lateral direction is too small, the volume of the first source / drain doped layer 310 will be correspondingly too small, which can easily affect the stress of the first source / drain doped layer 310. Moreover, the semiconductor structure usually also includes a silicide layer located between the first source / drain doped layer 310 and the source / drain plug 350. The formation process of the silicide layer usually consumes part of the first source / drain doped layer 310. If the width of the first source / drain doped layer 310 along the lateral direction is too small, it can easily lead to a smaller volume of the remaining first source / drain doped layer 310 after the formation of the silicide layer, which will further affect the semiconductor structure. This can negatively impact performance. If the width of the first source / drain doped layer 310 is too large in the lateral direction, the top area of ​​the second source / drain doped layer 320 exposed by the first source / drain doped layer 310 will be too small. The space enclosed by the top of the second source / drain doped layer 320 and the side of the first source / drain doped layer 310 will be too small. When the source / drain plug 350 is formed within this space, the formation space for the source / drain plug 350 will be too small, thus increasing the difficulty of forming the source / drain plug 350. Therefore, in this embodiment, the width of the first source / drain doped layer 310 in the lateral direction is 10% to 90% of the width of the second source / drain doped layer 320.

[0071] In one embodiment, the second source / drain doped layer 320 is spaced apart from the first source / drain doped layer 310. Correspondingly, when the source / drain plug 350 contacts at least the tops of the first source / drain doped layer 310 and the second source / drain doped layer 320, and the longitudinal sidewall of the first source / drain doped layer 310 opposite to the gate structure 410, since the second source / drain doped layer 320 and the first source / drain doped layer 310 are not in contact, current can be prevented from flowing in the source / drain structure 300 along a direction perpendicular to the substrate 100 (e.g., ...) during device operation. Figure 2 The current flows to the second channel layer 40 (as shown in the Z direction), so that the current flows directly to the second channel layer 40 through the source-drain plug 350, which significantly reduces the voltage drop consumed by the current in the path to the second channel layer 40 and significantly increases the channel current value in the second channel layer 40.

[0072] In other embodiments, the second source / drain doped layer and the first source / drain doped layer can also be in contact, so that the interlayer dielectric layer does not need to fill the gap between the second source / drain doped layer and the first source / drain doped layer, which helps to reduce the difficulty of forming the interlayer dielectric layer and correspondingly improves process compatibility and film quality of the interlayer dielectric layer.

[0073] It should be noted that this embodiment is illustrated by the example that the channel structure layer 400 also includes the second channel layer 40, and the source / drain structure 300 correspondingly includes a second source / drain doped layer 320 located on the sidewall of the second channel layer 40. In other embodiments, when the channel structure layer only includes a plurality of channel stacks arranged sequentially from bottom to top, the source / drain structure correspondingly includes only a first source / drain doped layer located on the sidewall of the first channel layer.

[0074] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 160 located on the substrate 100 on the side of the gate structure 410. The interlayer dielectric layer 160 covers the source / drain structure 300 and also fills the space between adjacent first channel layers 30.

[0075] The interlayer dielectric layer 160 is used to isolate adjacent devices. In this embodiment, the material of the interlayer dielectric layer 160 is silicon oxide. The material of the interlayer dielectric layer 160 can also be other insulating materials.

[0076] In this embodiment, the first source / drain doped layers 310 located on the sidewalls of adjacent first channel layers 30 are spaced apart, and the interlayer dielectric layer 160 is correspondingly filled between adjacent first source / drain doped layers 310. In this embodiment, the source / drain structure 300 further includes a second source / drain doped layer 320, and the second source / drain doped layer 320 is spaced apart from the adjacent first source / drain doped layers 310, and the interlayer dielectric layer 160 is correspondingly filled between the second source / drain doped layer 320 and the adjacent first source / drain doped layer 310.

[0077] In this embodiment, the semiconductor structure further includes a metal dielectric layer 190, located on the interlayer dielectric layer 160 and covering the top of the gate structure 410. Specifically, the metal dielectric layer 190 covers the etch stop layer 420 located on top of the gate structure 410.

[0078] The metal dielectric layer 190 is used to achieve isolation between the source and drain plugs 350. The material of the metal dielectric layer 190 is a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, low-k dielectric materials, and ultra-low-k dielectric materials.

[0079] The source / drain plug 350 is used to establish an electrical connection between the source / drain structure 300 and an external circuit or other interconnection structure. The source / drain plug 350 is made of a conductive material, such as one or more of Cu, Co, Ru, RuN, W, and Al.

[0080] As an example, along the lateral direction, the end of the second source / drain doped layer 320 protrudes beyond the end of the first source / drain doped layer 310, and correspondingly, the source / drain plug 350 contacts at least the top of the first source / drain doped layer 310 and the second source / drain doped layer 320, as well as the longitudinal sidewall of the first source / drain doped layer 310 opposite to the gate structure 410.

[0081] In this configuration, the second channel layer 40 is closer to the substrate 100 than the first channel layer 30. The second channel layer 40 is the bottommost channel layer in the channel structure layer 400. The source / drain plug 350 is in contact with the top of the second source / drain doped layer 320. This not only enables the source / drain plug 350 to be electrically connected to the second source / drain doped layer 320, allowing current to flow directly through the source / drain plug 350 to the second channel layer 40, thereby significantly increasing the channel current in the second channel layer 40, but also prevents the source / drain plug 350 from contacting the substrate 100 at the bottom of the second source / drain doped layer 320.

[0082] Furthermore, compared to the first source / drain doped layer 310 along the first or second transverse sidewall, the first source / drain doped layer 310 has a larger area along the longitudinal sidewall opposite to the gate structure 410. The source / drain plug 350 contacts the first source / drain doped layer 310 along the longitudinal sidewall opposite to the gate structure 410, which helps to increase the contact area between the source / drain plug 350 and the first source / drain doped layer 310 while ensuring that the volume of the source / drain plug 350 is not too large, thereby reducing the contact resistance between the source / drain plug 350 and the first source / drain doped layer 310.

[0083] As an example, the source / drain plug 350 also contacts at least one of the sidewalls of the second source / drain doped layer 320 along the first transverse side 38 and the second transverse side (not shown), which helps to increase the contact area between the source / drain plug 350 and the second source / drain doped layer 320 and correspondingly reduce the contact resistance between the source / drain plug 350 and the second source / drain doped layer 320.

[0084] As one embodiment, the source / drain plug 350 is in contact with the top of the first source / drain doped layer 310 and the second source / drain doped layer 320, the longitudinal sidewall 35 of the first source / drain doped layer 310 opposite to the gate structure 410, the sidewall of the first source / drain doped layer 310 along the first transverse sidewall 36 and the second transverse sidewall, and the sidewall of the second source / drain doped layer 320 along the first transverse sidewall 36 and the second transverse sidewall. This allows the source / drain plug 350 to contact the exposed top and sidewalls of the first source / drain doped layer 310 and the exposed top and sidewalls of the second source / drain doped layer 320. This significantly increases the contact area between the source / drain plug 350 and the first source / drain doped layer 310, and between the source / drain plug 350 and the second source / drain doped layer 320, thereby significantly reducing the contact resistance between the source / drain plug 350 and the source / drain structure 300 and improving the performance of the semiconductor structure.

[0085] In this embodiment, the source / drain plug 350 penetrates the interlayer dielectric layer 160 at the top of the source / drain structure 300. Specifically, the source / drain plug 350 also penetrates the metal dielectric layer 190 above the source / drain structure 300.

[0086] In this embodiment, when the source / drain plug 350 covers the lateral sidewall of the second source / drain doped layer 320, and along the longitudinal direction, the source / drain plug 350 is located on the portion of the isolation structure 110 adjacent to the corresponding sidewall of the second source / drain doped layer 320.

[0087] In this embodiment, the semiconductor structure further includes a silicide layer 360 located between the source / drain plug 350 and the surface of the source / drain structure 300.

[0088] The silicide layer 360 is used to reduce the contact resistance between the source / drain plug 350 and the source / drain structure 300. During device operation, current flows through the source / drain plug 350 and across the surface of the silicide layer 360. In other words, current can flow across the surface of the source / drain structure 300 in contact with the source / drain plug 350, and then to each channel layer. In this embodiment, current can flow across the surface of the source / drain structure 300 in contact with the source / drain plug 350, and then to the second channel layer 40 and each of the first channel layers 30.

[0089] In this embodiment, the material of the silicide layer 360 can be a nickel silicon compound, a cobalt silicon compound, or a titanium silicon compound.

[0090] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 4 to 20 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0091] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0092] refer to Figure 4 The diagram shows a partial three-dimensional structure, providing a substrate 100 on which a stacked structure 200 is formed, including a plurality of channel stacks 210 stacked sequentially from bottom to top. Each channel stack 210 includes a sacrificial layer 20 and a first channel layer 30 located on the sacrificial layer 20. The first channel layer 30 is lateral (e.g., ...). Figure 4 Extending in the X direction (as shown), the longitudinal direction is parallel to the base 100 and perpendicular to the said transverse direction (e.g., as shown in the X direction). Figure 4 shown in the Y direction).

[0093] The substrate 100 serves as a process platform for subsequent processes. In this embodiment, the formation of a gate-all-around (GAA) transistor is used as an example. In other embodiments, the formation method can also be used to form a forksheet transistor or a complementary field-effect transistor (CFET).

[0094] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, etc., and the substrate may also be other types of substrates such as silicon on insulator or germanium on insulator.

[0095] As an example, the stacked structure 200 is a fin-like structure extending along the lateral direction.

[0096] In the stacked structure 200, the stacking direction of the multiple channel stacks 210 (e.g.) Figure 4(As shown in the Z direction) is perpendicular to the surface of the substrate 100.

[0097] The channel stack 210 provides a process basis for the subsequent formation of the first channel layer 30 with a suspended arrangement. Specifically, the first channel layer 30 is used to provide a conductive channel for the field-effect transistor, and the sacrificial layer 20 is used to support the first channel layer 30, thereby providing a process basis for the subsequent realization of the suspended arrangement of the first channel layer 30. The sacrificial layer 20 is also used to occupy space for the subsequent formation of the gate structure.

[0098] In this embodiment, an NMOS transistor is formed, with the first channel layer 30 made of Si and the sacrificial layer 20 made of SiGe. During the subsequent removal of the sacrificial layer 20, the etching selectivity of SiGe and Si is relatively high. Therefore, by setting the material of the sacrificial layer 20 to SiGe and the material of the first channel layer 30 to Si, the impact of the sacrificial layer 20 removal process on the first channel layer 30 can be effectively reduced, thereby improving the quality of the first channel layer 30 and thus contributing to improved device performance. In other embodiments, when forming a PMOS transistor, SiGe channel technology can be used to improve the performance of the PMOS transistor, with the first channel layer made of SiGe and the sacrificial layer made of Si.

[0099] As an example, the number of channel stacks 210 is three. In other embodiments, the number of channel stacks may also be other.

[0100] As an example, the stacked structure 200 further includes a second channel layer 40 located between the substrate 100 and the channel stack 210. The second channel layer 40 also serves to provide a conductive channel for the field-effect transistor.

[0101] In this embodiment, the material of the second channel layer 40 is the same as that of the first channel layer 30, and the material of the second channel layer 40 is silicon.

[0102] In this embodiment, an isolation structure 110 is also formed in the base 100 on the side of the stacked structure 200. The isolation structure 110 is used to isolate adjacent stacked structures 200.

[0103] In this embodiment, the material of the isolation structure 110 is silicon oxide. The isolation structure 110 can also be other insulating materials.

[0104] Specifically, the substrate 100 includes a substrate (not shown) and a protrusion (not shown) extending from the substrate. The isolation structure 110 is located on the substrate on the side of the protrusion, and the isolation structure 110 exposes the stacked structure 200. Accordingly, the isolation structure 110 is also used to define the active area (AA) and isolation area of ​​the substrate 100.

[0105] As an example, the protrusion and the second channel layer 40 are an integral structure. The protrusion is also a fin-like structure extending laterally.

[0106] It should be noted that this embodiment uses the example of the laminated structure 200 further including the second channel layer 40 for illustration. In other embodiments, depending on actual process requirements, the laminated structure may also include only multiple channel layers stacked sequentially from bottom to top. Correspondingly, the top surface of the isolation structure is flush with the top surface of the protrusion.

[0107] As one embodiment, the step of providing the substrate 100 includes: providing a semiconductor layer (not shown) and a plurality of channel stack materials (not shown) stacked sequentially from bottom to top on the semiconductor layer, the channel stack materials including an initial sacrificial layer and an initial first channel layer located on the initial sacrificial layer; patterning the channel stack materials and a portion of the semiconductor layer to form a substrate, a protrusion structure protruding from the substrate, and a plurality of channel stacks 210 stacked sequentially from bottom to top on the protrusion structure, the protrusion structure including the protrusion portion and a second channel layer 40 located on the protrusion portion, the second channel layer 40 and the plurality of stacked channel stacks 210 constituting the stack structure 200; forming an isolation structure 110 on the substrate at the side of the stack structure 200, the isolation structure 110 exposing the second channel layer 40 and the channel stack 210.

[0108] refer to Figure 5 The diagram shows a partial three-dimensional structural schematic, in which a pseudo-gate structure 120 is formed on the substrate 100, spanning the stacked structure 200. Specifically, the pseudo-gate structure 120 is located on the isolation structure 11 and covers a portion of the top and sidewalls of the stacked structure 200. The pseudo-gate structure 120 extends along the longitudinal direction.

[0109] The pseudo-gate structure 120 is used to pre-reserve space for the subsequent formation of the gate structure.

[0110] The dummy gate structure 120 can be a stacked structure or a single-layer structure. In this embodiment, the dummy gate structure 120 is a stacked structure, including a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) located on the dummy gate oxide layer. Specifically, the dummy gate structure 120 is a polysilicon gate structure, the material of the dummy gate oxide layer can be silicon oxide or silicon oxynitride, and the material of the dummy gate layer can be polysilicon.

[0111] refer to Figure 6 The diagram shows a partial perspective view. The formation method further includes forming a gate sidewall 130 on the sidewall of the dummy gate structure 120. The gate sidewall 130, together with the dummy gate structure 120, serves as an etching mask for a subsequent etching process to form a recess, defining the formation location of the source / drain structure. The gate sidewall 130 also protects the sidewalls of the dummy gate structure 120 and the subsequent gate structure.

[0112] In this embodiment, the material of the gate sidewall 130 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material, and the gate sidewall 130 is a single-layer or multi-layer structure. As an example, the gate sidewall 130 is a single-layer structure, and the material of the gate sidewall 130 is silicon nitride.

[0113] refer to Figures 7 to 8 , Figure 7 This is a partial 3D image. Figure 8 for Figure 7 A cross-sectional view along the xx direction shows that grooves 140 are formed in the stacked structures 200 on both sides of the pseudo-gate structure 130.

[0114] The groove 140 provides space for forming the source / drain structure. The sidewalls of the groove 140 expose the stacked structure 200 to facilitate the subsequent etching of a portion-thickness sacrificial layer 20 in the lateral direction, and also to facilitate the subsequent formation of the source / drain structure on the sidewalls of the first channel layer 30 and the second channel layer 40 exposed by the groove 140 through epitaxial processes.

[0115] In this embodiment, the bottom of the groove 140 exposes the substrate 100. Specifically, the bottom of the groove 140 exposes the top surface of the protrusion.

[0116] In this embodiment, an anisotropic etching process (e.g., anisotropic dry etching process) is used to etch the stacked structure 200 on both sides of the pseudo gate structure 120 and the gate sidewall 130, which is beneficial to improve the cross-sectional morphology quality of the groove 140.

[0117] As an example, the stacked structures 200 on both sides of the pseudo-gate structure 120 and the gate sidewall 130 are removed to form the groove 140.

[0118] Reference Figures 9 to 10 , Figure 9This is a partial 3D image. Figure 10 for Figure 9 In this embodiment, after forming the groove 140, the forming method further includes: etching a portion of the thickness of the sacrificial layer 20 along the transverse direction to form a trench (not shown), the trench being surrounded by an adjacent first channel layer 30 and the sacrificial layer 20, or by a substrate 100, a first channel layer 30 adjacent to the substrate 100, and the sacrificial layer 20; and filling the trench with an inner spacer 150.

[0119] Specifically, the trench is formed by an adjacent first trench layer 30 and a sacrificial layer 20, or by a second trench layer 40, a first trench layer 30 adjacent to the second trench layer 40, and a sacrificial layer 20.

[0120] The trench is used to provide space for the formation of the inner sidewall.

[0121] In this embodiment, a vapor etching process is used to etch the sacrificial layer 20, representing a portion of the sidewall thickness of the groove 140, along the lateral direction. Vapor etching is an isotropic etching process, enabling the sacrificial layer 20 to be etched along the lateral direction. Furthermore, vapor etching easily achieves a large etching selectivity, which helps reduce the difficulty of etching the sacrificial layer 20 and decreases the probability of damage to other film structures (e.g., the first trench layer 30 and the second trench layer 40).

[0122] In this embodiment, the sacrificial layer 20 is made of SiGe, and the first channel layer 30 and the second channel layer 40 are made of Si. The sacrificial layer 20 on the sidewall of the groove 140 is etched by HCl vapor. The etching rate of HCl vapor on SiGe material is much greater than that on Si material, which can effectively reduce the probability of damage to the first channel layer 30 and the second channel layer 40.

[0123] In other embodiments, when the materials of the first and second channel layers are SiGe and the material of the sacrificial layer is Si, a dry etching process can be used to etch the sacrificial layer on the sidewall of the trench along the transverse direction. The etchant for the dry etching process may include a mixture of plasmas of CF4, O2, and N2. The difference between the etching rate of Si and the etching rate of SiGe in the plasma mixture is relatively large, which can effectively reduce the probability of the first and second channel layers being damaged.

[0124] Subsequently, a source-drain structure is formed in the groove 140, and a gate structure is formed at the positions of the dummy gate structure 120 and the sacrificial layer 20. The inner wall 150 is used to achieve isolation between the source-drain structure and the gate structure, and also increases the distance between the gate structure and the source-drain structure, which is beneficial to reduce the parasitic capacitance between the gate structure and the source-drain structure.

[0125] In this embodiment, the inner wall 150 is made of an insulating material to achieve isolation between the source / drain structure and the gate structure. In this embodiment, the material of the inner wall 150 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material. As an example, the material of the inner wall 150 is silicon nitride.

[0126] refer to Figures 11 to 12 , Figure 11 This is a partial 3D image. Figure 12 (a) is Figure 11 A sectional view along the xx direction. Figure 12 (b) is Figure 11 A cross-sectional view along the yy direction shows that a source / drain structure 300 is formed in the groove 140, including a first source / drain doped layer 310 covering the sidewall of the first channel layer 30 exposed in the groove 140.

[0127] The source-drain structure 300 is used as the source or drain of the field-effect transistor. When the field-effect transistor is working, the source-drain structure 300 is used to provide a source of charge carriers.

[0128] In this embodiment, it is not necessary to reduce the resistance of the source / drain structure by increasing the ion doping concentration of the source / drain structure in order to increase the channel current in the channel layer. This is beneficial to ensuring the epitaxial growth quality of the epitaxial process forming the source / drain structure 300, thereby improving the film formation quality of the source / drain structure 300 and optimizing the performance of the semiconductor structure.

[0129] Furthermore, in this embodiment, it is not necessary to reduce the resistance of the source / drain structure in order to increase the channel current in the channel layer by increasing the projected area of ​​the source / drain structure on the substrate. This is beneficial for miniaturization of the device size and also helps to reduce manufacturing costs.

[0130] In this embodiment, the source-drain structure 300 includes an ion-doped stress layer, which provides stress to the channel region to improve carrier mobility.

[0131] Specifically, the first source / drain doped layer 310 is used to provide stress for the first channel layer 30.

[0132] In this embodiment, when forming a PMOS transistor, the source-drain structure 300 includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe; when forming an NMOS transistor, the source-drain structure 300 includes a stress layer doped with N-type ions, and the material of the stress layer is Si or SiC.

[0133] In this embodiment, along the lateral direction, the width of the first source / drain doped layer 310 is smaller than the opening width of the groove 140, so the first source / drain doped layer 310 does not completely fill the groove 140. A portion of the sidewall of the first source / drain doped layer 310 remains in the groove 140. This remaining space in the groove 140 can provide space for the subsequent formation of source / drain plugs, allowing the source / drain plugs to contact the longitudinal sidewall of the first source / drain doped layer 310 opposite to the gate structure. Compared to the lateral sidewall of the first source / drain doped layer 310, the longitudinal sidewall has a larger area, thereby increasing the contact area between the source / drain plug and the first source / drain doped layer 310. Furthermore, the source / drain plug filling the remaining space in the groove 140 also helps to make the lateral dimension of the source / drain plug smaller, which helps to reduce the lateral area occupied by the source / drain plug, and thus helps to reduce the size of the semiconductor structure.

[0134] It should be noted that the width of the first source / drain doped layer 310 along the lateral direction should not be too small or too large. If the width of the first source / drain doped layer 310 along the lateral direction is too small, the volume of the first source / drain doped layer 310 will be correspondingly too small, which will easily affect the stress of the first source / drain doped layer 310. Moreover, a silicide layer is usually formed between the first source / drain doped layer 310 and the source / drain plug afterward. The process of forming the silicide layer will usually consume part of the thickness of the first source / drain doped layer 310. If the width of the first source / drain doped layer 310 along the lateral direction is too small, the remaining volume of the first source / drain doped layer 310 after the formation of the silicide layer will be even smaller, which will have an adverse effect on the performance of the semiconductor structure. If the width of the first source / drain doped layer 310 along the lateral direction is too large, the remaining space of the groove 140 will be too small. When the source / drain plug is subsequently formed in the remaining space of the groove 140, the formation space of the source / drain plug will be too small, which will easily increase the difficulty of forming the source / drain plug. Therefore, in this embodiment, along the lateral direction, the width of the first source / drain doped layer 310 is 10% to 90% of the width of the groove 140.

[0135] As an embodiment, the first source / drain doped layers 310 located on adjacent sidewalls of the first channel layer 30 are spaced apart. During the subsequent formation of the source / drain plug, when the source / drain plug is in contact with at least one of the sidewalls of the first source / drain doped layers 310 along the longitudinal direction and opposite to the gate structure, along the sidewall along the first transverse side, and along the second transverse side, since the first source / drain doped layers 310 on adjacent sidewalls of the first channel layer 30 are not in contact with each other, during device operation, current can be prevented from flowing in the source / drain structure 300 along the direction perpendicular to the substrate 100 (e.g., ...). Figure 11The flow (as shown in the Z direction) allows the current to flow only through the source and drain plugs to each first channel layer 30, which significantly reduces the voltage drop consumed by the current in the path to each first channel layer 30, and increases the channel current value in each first channel layer 30, especially significantly increasing the channel current value in the first channel layer 30 closer to the substrate 100.

[0136] In other embodiments, based on the actual process of forming the source and drain structure, the first source and drain doped layers located on the sidewalls of adjacent first channel layers can also be in contact with each other. Thus, when the interlayer dielectric layer covering the source and drain structure is subsequently formed, the interlayer dielectric layer does not need to fill the gaps between the first source and drain doped layers on the sidewalls of adjacent first channel layers. This helps to reduce the process difficulty of forming the interlayer dielectric layer and correspondingly improves process compatibility.

[0137] In this embodiment, the stacked structure 200 further includes a second channel layer 40; the step of forming the source / drain structure 300 in the groove 140 includes: forming a first source / drain doped layer 310 located on the sidewall of the first channel layer 30 exposed in the groove 140, and a second source / drain doped layer 320 located on the sidewall of the second channel layer 40 exposed in the groove 140. The second source / drain doped layer 320 is also formed on the substrate 100 at the bottom of the groove 140, and the end of the second source / drain doped layer 320 protrudes from the end of the first source / drain doped layer 310 in the transverse direction.

[0138] The second source / drain doped layer 320 is used to provide stress to the second channel layer 40, thereby improving the carrier mobility within the second channel layer 40.

[0139] In this embodiment, the width of the first source / drain doped layer 310 in the transverse direction is smaller than the opening width of the groove 140, and the second source / drain doped layer 320 is also formed on the substrate 100 at the bottom of the groove 140. The end of the second source / drain doped layer 320 in the transverse direction protrudes from the end of the first source / drain doped layer 310, so that the groove 140 still has space to provide a forming space for the subsequent formation of source / drain plugs. Furthermore, the subsequent source / drain plugs can contact the top of the second source / drain doped layer 320, which not only realizes the electrical connection between the source / drain plugs and the second source / drain doped layer 320, but also prevents the source / drain plugs from contacting the substrate 100 at the bottom of the groove 140.

[0140] In this embodiment, the material of the second source / drain doped layer 320 is the same as that of the first source / drain doped layer 310, and the doping type of the second source / drain doped layer 320 is also the same as that of the first source / drain doped layer 310.

[0141] In one embodiment, the second source / drain doped layer 320 is spaced apart from the first source / drain doped layer 310. Correspondingly, during the subsequent formation of the source / drain plug, when the source / drain plug contacts at least the tops of the first source / drain doped layer 310 and the second source / drain doped layer 320, and the longitudinal sidewall of the first source / drain doped layer 310 opposite to the gate structure, since the second source / drain doped layer 320 and the first source / drain doped layer 310 are not in contact, current can be prevented from flowing in the source / drain structure 300 along a direction perpendicular to the substrate 100 (e.g., ...). Figure 11 The current flows to the second channel layer 40 (as shown in the Z direction), so that the current flows directly to the second channel layer 40 through the source-drain plug, which significantly reduces the voltage drop consumed by the current in the path to the second channel layer 40 and significantly increases the channel current value in the second channel layer 40.

[0142] In other embodiments, based on the actual process of forming the source / drain structure, the second source / drain doped layer and the first source / drain doped layer can also be in contact. Therefore, when the interlayer dielectric layer covering the source / drain structure is subsequently formed, the interlayer dielectric layer does not need to fill the gap between the second source / drain doped layer and the first source / drain doped layer, which helps to reduce the process difficulty of forming the interlayer dielectric layer and improves the process compatibility accordingly.

[0143] It should be noted that this embodiment uses the stacked structure 200 further including the second channel layer 40 as an example for illustration. The source / drain structure 300 correspondingly also includes a second source / drain doped layer 320 located on the sidewall of the second channel layer 40. In other embodiments, when the stacked structure only includes a plurality of channel layers stacked sequentially from bottom to top, the source / drain structure correspondingly includes only a first source / drain doped layer located on the sidewall of the first channel layer.

[0144] In this embodiment, an epitaxial process is used to form the source / drain structure 300. Specifically, epitaxial growth is performed based on the first channel layer 30, the second channel layer 40, and the substrate 100 exposed by the groove 140.

[0145] In this embodiment, the epitaxial process parameters include: a process temperature of 550°C to 800°C, a gas flow rate of 10 sccm to 200 sccm, and a time of 60 seconds to 3600 seconds. By setting the epitaxial process parameters within the above range, the first source / drain doped layer 310 is ensured not to be too thick, so that there is still remaining space in the groove 140 for forming source / drain plugs.

[0146] refer to Figure 13 and Figure 14 , Figure 13 This is a partial 3D image. Figure 14 for Figure 13In this embodiment, the forming method further includes, after forming the source / drain structure 300, forming an interlayer dielectric layer 160 on the substrate 100 on the side of the pseudo-gate structure 120 to cover the source / drain structure 300.

[0147] The interlayer dielectric layer 160 is used to isolate adjacent devices and also to support the first channel layer 30 during the subsequent removal of the dummy gate structure 120 and the sacrificial layer 20, thereby achieving a suspended space arrangement of the first channel layer 30. In this embodiment, the material of the interlayer dielectric layer 160 is silicon oxide. The material of the interlayer dielectric layer 160 can also be other insulating materials.

[0148] In this embodiment, the interlayer dielectric layer 160 also exposes the top of the pseudo-gate structure 120 to facilitate subsequent removal of the pseudo-gate structure 120.

[0149] In this embodiment, the first source / drain doped layers 310 located on the sidewalls of adjacent first channel layers 30 are spaced apart, and the interlayer dielectric layer 160 is correspondingly filled between adjacent first source / drain doped layers 310. In this embodiment, the source / drain structure 300 further includes a second source / drain doped layer 320, and the second source / drain doped layer 320 is spaced apart from the adjacent first source / drain doped layers 310, and the interlayer dielectric layer 160 is correspondingly filled between the second source / drain doped layer 320 and the adjacent first source / drain doped layer 310.

[0150] In this embodiment, the process for forming the interlayer dielectric layer 160 includes at least one of flow chemical vapor deposition (FCVD) and atomic layer deposition (ALD). Both FCVD and ALD have high gap-filling capabilities, which helps to ensure that the interlayer dielectric layer 160 can fill the gaps between adjacent first source / drain doped layers 310 and between the second source / drain doped layer 320 and adjacent first source / drain doped layers 310, thereby improving the film quality of the interlayer dielectric layer 160.

[0151] Specifically, the step of forming the interlayer dielectric layer 160 includes: using a deposition process to form a dielectric material layer (not shown) covering the source / drain structure 300 and the pseudo-gate structure 120 on the substrate 100; using a planarization process to remove the dielectric material layer located on top of the pseudo-gate structure 120, and the remaining dielectric material layer is used as the interlayer dielectric layer 160.

[0152] The deposition process can be at least one of flow chemical vapor deposition (FCVD) and atomic layer deposition (ALD).

[0153] Continue to refer to Figure 13 and Figure 14 , Figure 13 This is a partial 3D image. Figure 14 for Figure 13 A cross-sectional view along the xx direction shows the removal of the pseudo-gate structure 120, forming a gate opening 170, which exposes the channel stack 210.

[0154] The gate opening 170 provides space for forming the gate structure. The gate opening 170 exposes the channel stack 210 to facilitate subsequent removal of the sacrificial layer 20 through the gate opening 170.

[0155] In this embodiment, the gate opening 170 spans the stacked structure 200 and is located in the interlayer dielectric layer 160.

[0156] Continue to refer to Figure 14 and Figure 15 The sacrificial layer 20 in the channel stack 210 is removed through the gate opening 170, so that the adjacent first channel layer 30, the substrate 100 and the first channel layer 30 adjacent to the substrate 100 form a through groove 180.

[0157] In this embodiment, the sacrificial layer 20 in the channel stack 210 is removed, so that the adjacent first channel layer 30, the second channel layer 40 and the first channel layer 30 adjacent to the second channel layer 40 form the through groove 180.

[0158] The through-slot 180 and the gate opening 170 together provide space for forming the gate structure. The through-slot 180 is connected to the gate opening 170.

[0159] The sacrificial layer 20 is removed after the source / drain structure 300 is formed. Therefore, after the sacrificial layer 20 is removed, the two ends of the first channel layer 30 are connected to the first source / drain doped layer 310 along the lateral direction and are suspended in the gate opening 170 so that the subsequent gate structure can surround the first channel layer 30.

[0160] In this embodiment, after removing the sacrificial layer 20, the first channel layers 30 are spaced apart, and the multiple spaced first channel layers 30 are used to form the channel structure layer 400. In this embodiment, the channel structure layer 400 further includes a second channel layer 40 located between the substrate 100 and the first channel layers 30 and spaced apart from the first channel layers 30.

[0161] In this embodiment, a vapor etching process is used to remove the sacrificial layer 20. Specifically, the first channel layer 30 and the second channel layer 40 are made of Si, and the sacrificial layer 20 is made of SiGe. Therefore, the sacrificial layer 20 exposed by the gate opening 170 is removed by HCl vapor.

[0162] refer to Figure 15A partial perspective view is shown, in which a gate structure 410 is formed in the gate opening 170 and the through-slot 180, surrounding the first channel layer 30.

[0163] When the device is in operation, the gate structure 410 is used to control the opening and closing of the conductive channel.

[0164] In this embodiment, the gate structure 410 is a metal gate structure. The gate structure 410 includes a high-k gate dielectric layer (not shown), a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer and filling the through-slot 180 and the gate opening 170.

[0165] The high-k gate dielectric layer is used to achieve electrical isolation between the work function layer, the gate electrode layer, and the channel. The material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can also be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0166] The work function layer is used to adjust the work function of the gate structure 410, thereby adjusting the threshold voltage of the field-effect transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon tantalum nitride, silicon titanium nitride, and tantalum carbide.

[0167] The gate electrode layer serves as the external electrode for electrical connection between the gate structure 410 and external circuitry. The gate electrode layer is made of a conductive material, such as W, Al, Cu, Ag, Au, Pt, Ni, or Ti.

[0168] In this embodiment, a metal gate structure 410 is used as an example for illustration. In other embodiments, based on actual process requirements, the gate structure can also be other types of gate structures, such as polycrystalline silicon gate structures or amorphous silicon gate structures.

[0169] refer to Figures 16 to 20 Source / drain plugs 350 are formed on both sides of the gate structure 410, which are in contact with the top of the source / drain structure 300. The source / drain plugs 350 are also in contact with at least one of the following sidewalls of the first source / drain doped layer 310: the sidewall along the longitudinal direction and opposite to the gate structure 410, the sidewall along the first transverse side, and the sidewall along the second transverse side.

[0170] The source / drain plug 350 is used to establish an electrical connection between the source / drain structure 300 and an external circuit or other interconnection structure. The source / drain plug 350 is made of a conductive material, such as one or more of Cu, Co, Ru, RuN, W, and Al.

[0171] Compared to the scheme where the source / drain plug only contacts the top of the source / drain doped layer, the source / drain plug 350 formed in this embodiment also has a contact surface along a direction perpendicular to the surface of the substrate 100 with the first source / drain doped layer 310. The source / drain plug 350 can contact all the first source / drain doped layers 310 located on the sidewalls of each first channel layer 30. When the device is working, the current can flow directly through the source / drain plug 350 through the sidewalls of the first source / drain doped layer 310 to each first channel layer 30, which is beneficial to bypass the current flow along the direction perpendicular to the substrate in the source / drain structure 300. The flow in the 100-degree direction, since the resistivity of the source / drain plug 350 material is generally significantly smaller than that of the source / drain structure 300 material, allows the current to flow directly through the source / drain plug 350 to each first channel layer 30, which helps to reduce parasitic resistance. This reduces the voltage drop consumed by the current in the path to each first channel layer 30, increases the channel current value in each first channel layer 30, especially significantly increases the channel current value in the first channel layer 30 closer to the substrate 100, thereby enhancing the drive current of the device and optimizing the performance of the semiconductor structure.

[0172] As an example, along the lateral direction, the end of the second source / drain doped layer 320 protrudes beyond the end of the first source / drain doped layer 310, and correspondingly, the source / drain plug 350 contacts at least the top of the first source / drain doped layer 310 and the second source / drain doped layer 320, as well as the longitudinal sidewall of the first source / drain doped layer 310 opposite to the gate structure 410.

[0173] Compared to the first channel layer 30, the second channel layer 40 is closer to the substrate 100. The second channel layer 40 is the bottommost channel layer in the channel structure layer 400. The source / drain plug 350 and the top of the second source / drain doped layer 320 not only realize the electrical connection between the source / drain plug 350 and the second source / drain doped layer 320, so that the current can flow directly through the source / drain plug 350 to the second channel layer 40, thereby significantly improving the channel current in the second channel layer 40, but also prevent the source / drain plug 350 from contacting the substrate 100 at the bottom of the groove 140.

[0174] Furthermore, compared to the first source / drain doped layer 310 along the first or second transverse sidewall, the first source / drain doped layer 310 has a larger area along the longitudinal sidewall opposite to the gate structure 410. The source / drain plug 350 contacts the first source / drain doped layer 310 along the longitudinal sidewall opposite to the gate structure 410, which helps to increase the contact area between the source / drain plug 350 and the first source / drain doped layer 310 while ensuring that the volume of the source / drain plug 350 is not too large, thereby reducing the contact resistance between the source / drain plug 350 and the first source / drain doped layer 310.

[0175] As an example, the source / drain plug 350 is also in contact with at least one of the sidewalls of the second source / drain doped layer 320 along the first transverse side and the second transverse side, which helps to increase the contact area between the source / drain plug 350 and the second source / drain doped layer 320 and correspondingly reduce the contact resistance between the source / drain plug 350 and the second source / drain doped layer 320.

[0176] As one embodiment, the source / drain plug 350 is in contact with the top of the first source / drain doped layer 310 and the second source / drain doped layer 320, the longitudinal sidewall 35 of the first source / drain doped layer 310 opposite to the gate structure 410, the first transverse sidewall 36 and the second transverse sidewall of the first source / drain doped layer 310, and the second transverse sidewall 38 and the second transverse sidewall of the second source / drain doped layer 320. This allows the source / drain plug 350 to contact the exposed top and sidewalls of the first source / drain doped layer 310 and the exposed top and sidewalls of the second source / drain doped layer 320. This significantly increases the contact area between the source / drain plug 350 and the first source / drain doped layer 310, and between the source / drain plug 350 and the second source / drain doped layer 320, thereby significantly reducing the contact resistance between the source / drain plug 350 and the source / drain structure 300 and improving the performance of the semiconductor structure.

[0177] In this embodiment, the source / drain plug 350 penetrates the interlayer dielectric layer 160 at the top of the source / drain structure 300.

[0178] The steps for forming the source / drain plug 350 in this embodiment will be described in detail below with reference to the accompanying drawings.

[0179] like Figures 16 to 18 As shown, source / drain contact holes 340 are formed on both sides of the gate structure 410, exposing the top of the source / drain structure 300, and also exposing at least one of the following sidewalls of the first source / drain doped layer 310: a sidewall along the longitudinal direction and opposite to the gate structure 410, a sidewall along the first transverse side, and a sidewall along the second transverse side. The source / drain contact holes 340 are used to provide space for forming source / drain plugs.

[0180] As an example, the source / drain contact hole 340 exposes the top of the source / drain structure 300, and also exposes the sidewall 35 of the first source / drain doped layer 310 along the longitudinal direction and opposite to the gate structure 410, the sidewall 36 along the first transverse side, and the sidewall along the second transverse side (not shown), thereby increasing the surface area of ​​the exposed source / drain structure 300 in order to increase the contact area between the source / drain structure 300 and the subsequent source / drain plug.

[0181] In this embodiment, the source / drain contact hole 340 also exposes the top of the second source / drain doped layer 320 so that the subsequent source / drain plug can contact the top of the second source / drain doped layer 320, so that the current can flow directly through the source / drain plug to the second channel layer 40.

[0182] As an example, the source / drain contact hole 340 also exposes the sidewall 38 of the second source / drain doped layer 320 along the first transverse side and the sidewall along the second transverse side, thereby increasing the surface area of ​​the exposed second source / drain doped layer 320 and thus increasing the contact area between the second source / drain doped layer 320 and the source / drain plug.

[0183] In other embodiments, depending on actual process requirements, the source / drain contact holes may expose only one of the sidewalls of the second source / drain doped layer along the first transverse side and the second transverse side.

[0184] It should be noted that, as Figure 16 As shown in the partial perspective view, in this embodiment, before forming the source / drain contact hole 340, the forming method further includes: removing a portion of the thickness material at the top of the gate structure 410; forming an etch stop layer 420 on the top of the gate structure 410; and forming a metal dielectric layer 190 on the interlayer dielectric layer 160 to cover the etch stop layer 420.

[0185] The etching stop layer 420 is used to protect the top of the gate structure 410 to prevent accidental etching of the gate structure 410 during the formation of the source / drain contact hole 340, thereby helping to prevent the source / drain plug from short-circuiting with the gate structure 410.

[0186] The etching stop layer 420 is made of a material that has etching selectivity with the material of the metal dielectric layer 190 or the interlayer dielectric layer 160, so as to ensure that the etching process for forming the source / drain contact hole 340 is not likely to cause erroneous etching of the etching stop layer 420.

[0187] In this embodiment, the material of the etch stop layer 420 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the etch stop layer 420 is silicon carbide.

[0188] The metal dielectric layer 190 is used to achieve electrical isolation between the source and drain plugs. The material of the metal dielectric layer 190 is a dielectric material, such as one or more of the following: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, low-k dielectric materials, and ultra-low-k dielectric materials.

[0189] Therefore, as Figures 17 to 18 As shown, Figure 17 A partial 3D view is shown. Figure 18 (a) is Figure 17 A sectional view along the xx direction. Figure 18 (b) is Figure 17 In the cross-sectional view along the yy direction, in this embodiment, during the step of forming the source / drain contact hole 340, the source / drain contact hole 340 penetrates the interlayer dielectric layer 160 and the metal dielectric layer 190 above the source / drain structure 300.

[0190] like Figures 19 to 20 As shown, Figure 19 This is a partial 3D image. Figure 20 (a) is Figure 19 A sectional view along the xx direction. Figure 20 (b) is Figure 19 A cross-sectional view along the yy direction, showing the source / drain plug 350 filling the source / drain contact hole 340.

[0191] In this embodiment, the process for forming the source / drain plug 350 includes chemical vapor deposition.

[0192] Specifically, as an example, the step of filling the source / drain contact hole 340 with the source / drain plug 350 includes: filling the source / drain contact hole 340 with source / drain plug material (not shown), the source / drain plug material also being formed on the metal dielectric layer 190; removing the source / drain plug material located on the metal dielectric layer 190, and using the remaining source / drain plug material filling the source / drain contact hole 340 as the source / drain plug 350.

[0193] In this embodiment, the process of filling the source / drain contact hole 340 with source / drain plug material includes a chemical vapor deposition process. This process of filling the source / drain plug material has good gap-filling capability, which is beneficial for improving the filling capacity and quality of the source / drain plug material in the source / drain contact hole 340.

[0194] In this embodiment, a planarization process (e.g., chemical mechanical planarization) is used to remove the source / drain plug material located on the metal dielectric layer 190, which helps to improve the removal efficiency of the source / drain plug material located on the metal dielectric layer 190, and at the same time improves the flatness of the top surface of the source / drain plug 350 and the metal dielectric layer 190.

[0195] In this embodiment, the forming method further includes: after forming the source / drain contact hole 340 and before filling the source / drain plug 350 into the source / drain contact hole 340, forming a silicide layer 360 on the surface of the source / drain structure 300 exposed in the source / drain contact hole 340.

[0196] The silicide layer 360 is used to reduce the contact resistance between the source / drain plug 350 and the source / drain structure 300. During device operation, current flows through the source / drain plug 350 and across the surface of the silicide layer 360. In other words, current can flow across the surface of the source / drain structure 300 in contact with the source / drain plug 350, and then to each channel layer. In this embodiment, current can flow across the surface of the source / drain structure 300 in contact with the source / drain plug 350, and then to the second channel layer 40 and each of the first channel layers 30.

[0197] In this embodiment, the material of the silicide layer 360 can be a nickel silicon compound, a cobalt silicon compound, or a titanium silicon compound.

[0198] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A channel structure layer is located on the substrate. The channel structure layer includes a plurality of first channel layers arranged sequentially from bottom to top. The first channel layers extend laterally, and the direction parallel to the substrate and perpendicular to the lateral direction is the longitudinal direction. A gate structure that spans the channel structure layer and surrounds the first channel layer, and the gate structure fills between adjacent first channel layers and between the substrate and the first channel layer adjacent to the substrate; A source / drain structure is located on both sides of the gate structure and covers the sidewalls of the channel structure layer. The source / drain structure includes a first source / drain doped layer located along the lateral direction on the sidewall of the first channel layer. The source / drain plugs are located on both sides of the gate structure and in contact with the top of the source / drain structure. The source / drain plugs are also in contact with at least one of the following sidewalls of the first source / drain doped layer: a sidewall along the longitudinal direction and opposite to the gate structure, a sidewall along the first transverse side, and a sidewall along the second transverse side. The channel structure layer further includes: a second channel layer located between the substrate and the first channel layer and spaced apart from the first channel layer; the gate structure fills the spaces between adjacent first channel layers, and between the second channel layer and the first channel layer adjacent to the second channel layer; The source / drain structure further includes: a second source / drain doped layer located on the sidewall of the second channel layer along the lateral direction; the second source / drain doped layer is also located on the top surface of the substrate on both sides of the second channel layer, and the end of the second source / drain doped layer protrudes beyond the end of the first source / drain doped layer along the lateral direction; the source / drain plug is in contact with at least the top of the first source / drain doped layer and the second source / drain doped layer, and the sidewall of the first source / drain doped layer along the longitudinal direction and opposite to the gate structure.

2. The semiconductor structure as described in claim 1, characterized in that, The source / drain plug is also in contact with at least one of the sidewalls of the second source / drain doped layer along the first transverse side and the second transverse side.

3. The semiconductor structure as described in claim 1, characterized in that, Along the lateral direction, the width of the first source / drain doped layer is 10% to 90% of the width of the second source / drain doped layer.

4. The semiconductor structure as described in claim 1, characterized in that, The second source / drain doped layer is spaced apart from the first source / drain doped layer, or the second source / drain doped layer is in contact with the first source / drain doped layer.

5. The semiconductor structure as described in claim 1, characterized in that, The first source / drain doped layers located on adjacent sidewalls of the first channel layer are spaced apart, or the first source / drain doped layers located on adjacent sidewalls of the first channel layer are in contact.

6. The semiconductor structure as described in claim 5, characterized in that, The semiconductor structure further includes: an interlayer dielectric layer located on a substrate on the side of the gate structure, the interlayer dielectric layer covering the source / drain structure and also filling the spaces between adjacent first channel layers; wherein, when the first source / drain doped layers located on the sidewalls of adjacent first channel layers are spaced apart, the interlayer dielectric layer also fills the spaces between adjacent first channel layers. Between the first source and drain doped layers; The source / drain plug penetrates the interlayer dielectric layer at the top of the source / drain structure.

7. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a silicide layer located between the source / drain plug and the surface of the source / drain structure.

8. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which a stacked structure is formed, including a plurality of channel stacks stacked sequentially from bottom to top. Each channel stack includes a sacrificial layer and a first channel layer located on the sacrificial layer. The first channel layer extends laterally, and the direction parallel to the substrate and perpendicular to the lateral direction is the longitudinal direction. A pseudo-gate structure is formed on the substrate that spans the stacked structure; Grooves are formed in the stacked structures on both sides of the pseudo-gate structure; A source / drain structure is formed in the groove, including a first source / drain doped layer covering the exposed sidewall of the first channel layer in the groove; Remove the pseudo-gate structure to form a gate opening and expose the channel stack; The sacrificial layer in the channel stack is removed through the gate opening, so that the adjacent first channel layer, the substrate, and the first channel layer adjacent to the substrate form a through trench. A gate structure is formed in the gate opening and the through slot, surrounding the first channel layer; Source / drain plugs are formed on both sides of the gate structure and are in contact with the top of the source / drain structure. The source / drain plugs are also in contact with at least one of the following sidewalls of the first source / drain doped layer: the sidewall along the longitudinal direction and opposite to the gate structure, the sidewall along the first transverse side, and the sidewall along the second transverse side. The laminated structure further includes a second channel layer located between the substrate and the channel laminate; in the step of forming the groove, the bottom of the groove exposes the substrate; The step of forming a source / drain structure in the groove includes: forming a first source / drain doped layer located on the sidewall of the first channel layer exposed in the groove, and a second source / drain doped layer located on the sidewall of the second channel layer exposed in the groove, wherein the second source / drain doped layer is also formed on a substrate at the bottom of the groove, and the end of the second source / drain doped layer protrudes from the end of the first source / drain doped layer in the transverse direction. In the process of removing the sacrificial layer in the trench stack, the adjacent first trench layer, the second trench layer, and the first trench layer adjacent to the second trench layer form the through trench. In the step of forming the source / drain plug, the source / drain plug is in contact with at least the top of the first source / drain doped layer and the second source / drain doped layer, and the sidewall of the first source / drain doped layer along the longitudinal direction and opposite to the gate structure.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of forming the source / drain plug, the source / drain plug is also in contact with at least one of the sidewalls of the second source / drain doped layer along the first transverse side and the second transverse side.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, The step of forming the source / drain plug includes: forming source / drain contact holes on both sides of the gate structure to expose the top of the source / drain structure, and also exposing at least one of the following sidewalls of the first source / drain doped layer: a sidewall along the longitudinal direction and opposite to the gate structure, a sidewall along the first transverse side, and a sidewall along the second transverse side; and filling the source / drain plug into the source / drain contact holes.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The method for forming the semiconductor structure further includes: after forming the source / drain contact hole, and before filling the source / drain plug into the source / drain contact hole, forming a silicide layer on the surface of the source / drain structure exposed by the source / drain contact hole.

12. The method for forming a semiconductor structure as described in claim 8, characterized in that, The source-drain structure is formed using an epitaxial process.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The parameters of the epitaxial process include: a process temperature of 550°C to 800°C, a gas flow rate of 10 sccm to 200 sccm, and a time of 60 seconds to 3600 seconds.

14. The method for forming a semiconductor structure as described in claim 8, characterized in that, The second source / drain doped layer is spaced apart from the first source / drain doped layer, or the second source / drain doped layer is in contact with the first source / drain doped layer.

15. The method for forming a semiconductor structure as described in claim 8, characterized in that, Along the transverse direction, the width of the first source / drain doped layer is smaller than the opening width of the groove.

16. The method for forming a semiconductor structure as described in claim 8, characterized in that, Along the lateral direction, the width of the first source / drain doped layer is 10% to 90% of the width of the groove opening.

17. The method for forming a semiconductor structure as described in claim 8, characterized in that, The first source / drain doped layers located on adjacent sidewalls of the first channel layer are spaced apart, or the first source / drain doped layers located on adjacent sidewalls of the first channel layer are in contact.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The method for forming the semiconductor structure further includes: after forming the source / drain structure and before removing the dummy gate structure, forming an interlayer dielectric layer on the substrate on the side of the dummy gate structure to cover the source / drain structure; wherein, when the first source / drain doped layers located on the sidewalls of adjacent first channel layers are spaced apart, the interlayer dielectric layer also fills the space between adjacent first source / drain doped layers. In the step of forming the source / drain plug, the source / drain plug penetrates the interlayer dielectric layer at the top of the source / drain structure.

Images