Transmitter systems and electronic equipment

Abstract

The present application provides a transmitter system and electronic device, relating to the field of transmitters, capable of improving the problem of performance degradation of the transmitter system due to leakage of radio frequency feedback signals. The transmitter system includes: a feedback channel and a first transmission channel; the first transmission channel includes a first transmission mixer, the first transmission mixer is used to convert a received baseband transmission signal into a radio frequency transmission signal; the radio frequency transmission signal is amplified by a first power amplifier and output to a first coupler for coupling before being transmitted through an antenna; the feedback channel receives the radio frequency feedback signal coupled from the first coupler; the feedback channel includes a feedback mixer, the feedback mixer converts the radio frequency feedback signal into a baseband feedback signal; the feedback mixer is coupled to a first local oscillator via a first local oscillator path; the first local oscillator path is used to receive a differential local oscillator signal of the first local oscillator, and convert it into an in-phase orthogonal signal with common-mode rejection characteristics before outputting it to the feedback mixer.

Description

Technical Field

[0001] The present application relates to the field of transmitters, and in particular to a transmitter system and electronic equipment. Background Art

[0002] As an important component of electronic equipment, the transmitter system's main task is to complete the modulation of the high-frequency carrier by useful intermediate frequency signals (including zero intermediate frequency signals and low intermediate frequency signals), converting it into an electromagnetic wave with a certain bandwidth at a certain center frequency and suitable for transmission through the antenna.

[0003] The transmitter system includes a transmission channel and a feedback channel. The feedback channel is provided with a feedback mixer and a local oscillator (LO), and the feedback mixer and the local oscillator are connected via a local oscillator path (LO path). Typically, the RF feedback signal received by the feedback channel has a large amount of energy and is prone to leakage, resulting in a degradation of the transmitter system's performance. Summary of the Invention

[0004] Embodiments of the present application provide a transmitter system and electronic equipment, which can improve the problem of transmitter system performance degradation caused by leakage of radio frequency feedback signals.

[0005] An embodiment of the present application provides a transmitter system, including a feedback channel and a first transmitting channel; the first transmitting channel includes a first transmitting mixer, which is used to convert a received baseband transmitting signal into a radio frequency transmitting signal; the radio frequency transmitting signal is amplified by a first power amplifier, output to a first coupler for coupling, and then transmitted through an antenna; the feedback channel is used to receive a radio frequency feedback signal coupled from the first coupler; the feedback channel includes a feedback mixer, which is used to convert the radio frequency feedback signal into a baseband feedback signal; the feedback mixer is coupled to a first local oscillator through a first local oscillator path; the first local oscillator path is used to receive a differential local oscillator signal of the first local oscillator, and convert it into a local oscillator in-phase and quadrature signal with common-mode rejection characteristics, and then output it to the feedback mixer.

[0006] Compared with the transmitter system of the related art, which is prone to leakage due to the large energy of the RF feedback signal received in the feedback channel, resulting in common-mode interference, the transmitter system of the present application converts the received differential local oscillator signal of the first local oscillator into an in-phase orthogonal signal with common-mode rejection characteristics by setting a first local oscillator path and outputs it to the feedback mixer, thereby reducing the common-mode interference problem caused by the leakage of the RF feedback signal, that is, improving the problem of transmitter system performance degradation caused by the leakage of the RF feedback signal, and improving the performance of the transmitter system.

[0007] In some possible implementations, the first local oscillator path includes an in-phase and quadrature signal generator (i.e., an IQ signal generator) and a common-mode rejection circuit. The common-mode rejection circuit is coupled between the first local oscillator and the in-phase and quadrature signal generator, or the common-mode rejection circuit is coupled between the in-phase and quadrature signal generator and a feedback mixer. The common-mode rejection circuit performs common-mode rejection on a transmission signal on the first local oscillator path.

[0008] In some possible implementations, the in-phase and quadrature signal generator includes a first forward input terminal, a second reverse input terminal, an in-phase forward output terminal (i.e., an I+ output terminal), an in-phase reverse output terminal (i.e., an I- output terminal), a quadrature forward output terminal (i.e., a Q+ output terminal), and a quadrature reverse output terminal (i.e., a Q- output terminal); the common-mode suppression circuit includes a first forward input terminal, a second reverse input terminal, a first forward output terminal, and a second reverse output terminal; the first forward input terminal and the second reverse input terminal of the common-mode suppression circuit are respectively coupled to the two differential output terminals of the first local oscillator, and the first forward output terminal and the second reverse output terminal of the common-mode suppression circuit are respectively coupled to the first forward input terminal and the second reverse input terminal of the in-phase and quadrature signal generator; the in-phase forward output terminal, the in-phase reverse output terminal, the quadrature forward output terminal, and the quadrature reverse output terminal of the in-phase and quadrature signal generator are coupled to the feedback mixer.

[0009] In this case, the common-mode suppression circuit performs common-mode elimination and differential-mode amplification (i.e., common-mode suppression) on the differential local oscillator signal received from the first local oscillator, and then outputs it to the first positive input terminal and the second negative input terminal of the in-phase orthogonal signal generator. The in-phase orthogonal signal generator evenly decomposes the signal into four groups according to the phase and outputs them to the feedback mixer.

[0010] In some possible implementations, the IQ signal generator uses a divide-by-2 circuit to generate the IQ signal; in this case, the IQ signal generator may include a first latch and a second latch, wherein the D input of the first latch is connected to the Q- output, the C input of the first latch is connected to the first positive input of the IQ signal generator, the Q output of the first latch is connected to the I+ output, and the QB output of the first latch is connected to the I- output; the D input of the second latch is connected to the I+ output, the C input of the second latch is connected to the second negative input of the IQ signal generator, the Q output of the second latch is connected to the Q+ output, and the QB output of the second latch is connected to the Q- output.

[0011] In some possible implementations, the IQ signal generator uses a polyphase filter (PPF) to generate the IQ signal. In this case, the IQ signal generator may include a first resistor, a first capacitor, a second resistor, a second capacitor, a third resistor, a third capacitor, a fourth resistor, and a fourth capacitor. The first resistor has two terminals connected to a first positive input terminal and an I+ output terminal of the IQ signal generator, respectively; the first capacitor has two terminals connected to a first positive input terminal and a Q+ output terminal of the IQ signal generator, respectively; the second resistor has two terminals connected to a ground terminal and a Q+ output terminal, respectively; the second capacitor has two terminals connected to a ground terminal and an I- output terminal, respectively; the third resistor has two terminals connected to a second negative input terminal and an I- output terminal of the IQ signal generator, respectively; the third capacitor has two terminals connected to a second negative input terminal and a Q- output terminal of the IQ signal generator, respectively; the fourth resistor has two terminals connected to a ground terminal and a Q- output terminal, respectively; and the fourth capacitor has two terminals connected to a ground terminal and an I+ output terminal, respectively.

[0012] In some possible implementations, the first local oscillator path includes two common-mode suppression circuits; the two common-mode suppression circuits are respectively a first common-mode suppression circuit and a second common-mode suppression circuit; the in-phase and quadrature signal generator includes a first positive input terminal, a second negative input terminal, an in-phase positive output terminal, an in-phase negative output terminal, a quadrature positive output terminal, and a quadrature negative output terminal; the common-mode suppression circuit includes a first positive input terminal, a second negative input terminal, a first positive output terminal, and a second negative output terminal; the first positive input terminal and the second negative input terminal of the in-phase and quadrature signal generator are respectively connected to the first Two differential output terminals of a local oscillator are coupled; the in-phase positive output terminal and the in-phase negative output terminal of the in-phase and quadrature signal generator are respectively coupled to the first positive input terminal and the second negative input terminal of the first common-mode suppression circuit; the quadrature positive output terminal and the quadrature negative output terminal of the in-phase and quadrature signal generator are respectively coupled to the first positive input terminal and the second negative input terminal of the second common-mode suppression circuit; the first positive output terminal and the second negative output terminal of the first common-mode suppression circuit and the first positive output terminal and the second negative output terminal of the second common-mode suppression circuit are coupled to the feedback mixer.

[0013] In this case, the in-phase and quadrature signal generator decomposes the differential local oscillator signal received from the first local oscillator into four groups of signals evenly according to the phase. Two groups of differential signals in the four groups of signals are respectively subjected to common-mode elimination and differential-mode amplification (i.e., common-mode suppression) by the first common-mode suppression circuit and the second common-mode suppression circuit, and then output to the feedback mixer.

[0014] In some possible implementations, the in-phase forward output, in-phase reverse output, quadrature forward output, and forward reverse output of the in-phase and quadrature signal generator are coupled to the feedback mixer via separate drive circuits. The drive circuits are configured to adjust the output signals of the in-phase and quadrature signal generator to a standard voltage and output them to the feedback mixer.

[0015] In some possible implementations, the in-phase positive output and the in-phase negative output of the in-phase and quadrature signal generator are coupled to the first positive input and the second negative input of the first common-mode suppression circuit through different driving circuits, respectively. The first positive output and the second negative output of the first common-mode suppression circuit are coupled to the feedback mixer through the driving circuits, respectively. The quadrature positive output and the quadrature negative output of the in-phase and quadrature signal generator are coupled to the first positive input and the second negative input of the second common-mode suppression circuit through different driving circuits, respectively. The first positive output and the second negative output of the second common-mode suppression circuit are coupled to the feedback mixer through the driving circuits, respectively. By providing driving circuits on the paths between the input and output of the first and second common-mode suppression circuits, the inputs of the first and second common-mode suppression circuits receive a standard voltage adjusted by the driving circuits, and the signals output by the outputs of the first and second common-mode suppression circuits are adjusted to the standard voltage by the driving circuits and then output to the feedback mixer.

[0016] In some possible implementations, the common-mode suppression circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the gate of the first NMOS transistor is coupled to the first positive input terminal of the common-mode suppression circuit, the drain of the first NMOS transistor is coupled to the first voltage terminal, and the source of the first NMOS transistor is coupled to the first positive output terminal of the common-mode suppression circuit; the gate of the second NMOS transistor is coupled to the second negative input terminal of the common-mode suppression circuit, the drain of the second NMOS transistor is coupled to the first positive output terminal of the common-mode suppression circuit, and the source of the second NMOS transistor is coupled to the second voltage terminal; the gate of the third NMOS transistor is coupled to the second negative input terminal of the common-mode suppression circuit, the drain of the third NMOS transistor is coupled to the first voltage terminal, and the source of the third NMOS transistor is coupled to the second negative output terminal of the common-mode suppression circuit; the gate of the fourth NMOS transistor is coupled to the first positive input terminal of the common-mode suppression circuit, the drain of the fourth NMOS transistor is coupled to the second negative output terminal of the common-mode suppression circuit, and the source of the fourth NMOS transistor is coupled to the second voltage terminal.

[0017] In this common-mode suppression circuit, the input signal can be split into common-mode and differential-mode signals. For the common-mode signal, the first and second NMOS transistors have the same input signal and opposite output polarity, thereby canceling out the common-mode signals at the first positive output terminal. For the differential-mode signal, the first and second NMOS transistors have opposite input signals and the same output polarity, thereby adding the differential-mode signals at the output terminal. Similarly, the third and fourth NMOS transistors achieve common-mode signal cancellation and differential-mode signal addition.

[0018] In some possible implementations, the common-mode suppression circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; the gate of the first PMOS transistor is coupled to the first positive input terminal of the common-mode suppression circuit, the source of the first PMOS transistor is coupled to the first voltage terminal, and the drain of the first PMOS transistor is coupled to the first positive output terminal of the common-mode suppression circuit; the gate of the second PMOS transistor is coupled to the second negative input terminal of the common-mode suppression circuit, the source of the second PMOS transistor is coupled to the first positive output terminal of the common-mode suppression circuit, and the drain of the second PMOS transistor is coupled to the second voltage terminal; the gate of the third PMOS transistor is coupled to the second negative input terminal of the common-mode suppression circuit, the source of the third PMOS transistor is coupled to the first voltage terminal, and the drain of the third PMOS transistor is coupled to the second negative output terminal of the common-mode suppression circuit; the gate of the fourth PMOS transistor is coupled to the first positive input terminal of the common-mode suppression circuit, the source of the fourth PMOS transistor is coupled to the second negative output terminal of the common-mode suppression circuit, and the drain of the fourth PMOS transistor is coupled to the second voltage terminal.

[0019] In some possible implementations, the common-mode suppression circuit includes a first differential input tube, a second differential input tube, a current source (also called a tail current source), a first resistor, and a second resistor; one end of the first resistor is connected to the first voltage terminal, and the other end of the first resistor is connected to the second reverse output terminal of the common-mode suppression circuit; the gate of the first differential input tube is connected to the first positive input terminal of the common-mode suppression circuit, the drain of the first differential input tube is connected to the second reverse output terminal of the common-mode suppression circuit, and the source of the first differential input tube is connected to the second voltage terminal (such as the ground terminal) through the current source. One end of the second resistor is connected to the first voltage terminal, and the other end of the second resistor is connected to the first positive output terminal of the common-mode suppression circuit; the gate of the second differential input tube is connected to the second negative input terminal of the common-mode suppression circuit, the drain of the second differential input tube is connected to the first positive output terminal of the common-mode suppression circuit, and the source of the second differential input tube is connected to the second voltage terminal (such as the ground terminal) through the current source; that is, the first differential input tube and the second differential input tube are common-mode current sources; wherein, the first differential input tube and the second differential input tube are both NMOS tubes.

[0020] In some possible implementations, the transmitter system further includes a second transmit channel, which includes a second transmit mixer configured to convert a received baseband transmit signal into a second RF transmit signal. The second RF transmit signal is amplified by a second power amplifier and then output to a second coupler for coupling before being transmitted via an antenna. A first local oscillator is configured to provide a local oscillator signal to the first transmit mixer and / or the second transmit mixer. In this case, the first local oscillator can provide a local oscillator signal to one or both of the first transmit mixer and the second transmit mixer; that is, the first transmit mixer and the second transmit mixer can reuse the first local oscillator.

[0021] In some possible implementations, the second coupler and the first coupler are coupled to the feedback mixer via a selector, so that the RF feedback signal coupled by the second coupler or the first coupler is transmitted to the feedback mixer through the control of the selector.

[0022] In some possible implementations, the first local oscillator further includes a phase-locked loop, a first frequency divider, a second frequency divider, and a selector; the inputs of the first frequency divider and the second frequency divider are coupled to the phase-locked loop, and the outputs of the first frequency divider and the second frequency divider are coupled to the first local oscillator path via the selector. In this case, the first local oscillator can select one of the first frequency divider and the second frequency divider to be connected to the first local oscillator path via the selector, thereby providing in-phase and quadrature signals to the feedback mixer via the first local oscillator path.

[0023] In some possible implementations, the in-phase and quadrature signal generator is a polyphase filter.

[0024] In some possible implementations, the driving circuit includes an inverter to invert the phase of the received signal at the input end by 180° through the inverter and adjust the phase to a standard voltage to be output through the output end.

[0025] In some possible implementations, the feedback channel further includes an attenuator coupled between the first coupler and the feedback mixer, so as to attenuate the coupled high-energy RF feedback signal through the attenuator to prevent the feedback channel from entering a saturation state.

[0026] In some possible implementations, the first transmit channel further includes an amplifier coupled between the first transmit mixer and the first power amplifier to further increase the amplification factor of the radio frequency transmit signal.

[0027] In some possible implementations, the first transmit channel further includes a filter coupled to the output end of the amplifier and a filter coupled to the output end of the first power amplifier, so as to filter the amplified RF transmit signal through the filter.

[0028] In some possible implementations, the first transmitting channel also includes a duplexer coupled between the first power amplifier and the antenna, so as to separate the transmitting channel and the receiving channel through the duplexer, and while transmitting a portion of the signal to the antenna, a portion of the signal can be coupled from the antenna to the receiving channel.

[0029] In some possible implementations, the duplexer is a frequency division duplexer that implements frequency division duplexing by using filters in different frequency bands.

[0030] In some possible implementations, the duplexer is a time division duplexer, so as to implement time division duplexing through a switch.

[0031] An embodiment of the present application also provides an electronic device, comprising the transmitter system in any of the aforementioned possible implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic structural diagram of a transmitter system provided in an embodiment of the present application;

[0033] Figure 2 A schematic structural diagram of a transmitter system provided in an embodiment of the present application;

[0034] Figure 3 A schematic diagram of the structure of a local oscillator provided in an embodiment of the present application;

[0035] Figure 4 A schematic structural diagram of a local oscillator path provided in an embodiment of the present application;

[0036] Figure 5 A schematic structural diagram of a local oscillator path provided in an embodiment of the present application;

[0037] Figure 6 A schematic diagram of the structure of an IQ signal generator provided in an embodiment of the present application;

[0038] Figure 7 A schematic diagram of the structure of an IQ signal generator provided in an embodiment of the present application;

[0039] Figure 8 A schematic structural diagram of a common-mode suppression circuit provided in an embodiment of the present application;

[0040] Figure 9 A schematic structural diagram of a common-mode suppression circuit provided in an embodiment of the present application;

[0041] Figure 10 A schematic diagram of the common-mode signal principle of a common-mode suppression circuit provided in an embodiment of the present application;

[0042] Figure 11A schematic diagram of the differential mode signal principle of a common mode suppression circuit provided in an embodiment of the present application;

[0043] Figure 12 A schematic diagram of the connection relationship in a local oscillator path provided in an embodiment of the present application;

[0044] Figure 13 A schematic diagram of the connection relationship in a local oscillator path provided in an embodiment of the present application;

[0045] Figure 14 A schematic diagram of the connection relationship in a local oscillator path provided in an embodiment of the present application;

[0046] Figure 15 A schematic structural diagram of a driving circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0048] The terms "first", "second", etc. in the specification, embodiments, claims and drawings of this application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order; the size of the sequence number of each process does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of this application. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products or devices are not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. "Connected", "coupled" and similar words are used to express the intercommunication or interaction between different components, which may include direct connection or indirect connection through other components.

[0049] An embodiment of the present application provides an electronic device, in which a transmitter system is provided. The present application does not limit the specific form of the electronic device, and the electronic device may be a wireless communication device, such as a mobile phone, a computer, etc.

[0050] The transmitter system used in the electronic device can improve the problem of system performance degradation caused by leakage of radio frequency feedback signals, thereby improving the stability of the electronic device.

[0051] The transmitter system provided in the embodiment of the present application is described in detail below.

[0052] The embodiment of the present application provides a transmitter system, such as Figure 1 As shown, the transmitter system includes a feedback channel f1 and a first transmission channel t1. The first transmission channel t1 includes a first transmission mixer 1.1, which is used to convert a received baseband transmission signal into a radio frequency transmission signal. The radio frequency transmission signal is amplified by a first power amplifier a1 (PA) and then output to a first coupler 2.1. After coupling by the first coupler 2.1, the signal is transmitted through an antenna 3.

[0053] Of course, in some specific embodiments, such as Figure 1 As shown, the RF transmission signal output by the first transmission mixer 1.1 can be amplified and filtered in sequence by the front-stage amplifier (AMP) and filter, and then output to the first power amplifier a1 and the back-stage filter for amplification and filtering in sequence, and then coupled by the first coupler 2.1 and transmitted through the antenna 3.

[0054] In addition, in some possible implementations, such as Figure 1 As shown, the first transmission channel t1 can also be provided with a duplexer; wherein the duplexer can be coupled between the antenna and the first power amplifier a1 to separate the transmission channel and the receiving channel (i.e., the RX channel) through the duplexer, so that a portion of the signal can be transmitted to the antenna while a portion of the signal can be coupled from the antenna to the receiving channel. Of course, the present application does not impose any specific restrictions on the duplexer; for example, in some possible implementations, the duplexer can adopt a frequency division duplexer to achieve frequency division duplexing by filtering signals in different frequency bands; for another example, in some possible implementations, the duplexer can also adopt a time division duplexer to achieve time division duplexing through a single-pole multi-throw switch or multiple parallel switches.

[0055] On this basis, in this transmitter system, reference Figure 1 As shown, the feedback channel f1 is used to receive the radio frequency feedback signal coupled from the first coupler 2.1; the feedback channel f1 includes a feedback mixer 4, which is used to convert the radio frequency feedback signal into a baseband feedback signal.

[0056] Among some possible implementations, Figure 1 As shown, an attenuator 6 may be further provided in the feedback channel f1 , and the attenuator 6 is coupled between the first coupler 2 . 1 and the feedback mixer 4 , so as to attenuate the coupled excessive RF feedback signal through the attenuator 6 to prevent the feedback channel from entering a saturation state.

[0057] In addition, reference Figure 1 As shown, the feedback mixer 4 is coupled to the first local oscillator 5 via a first local oscillator path (i.e., a first LO path) LO1. The first local oscillator path LO1 is used to receive the differential local oscillator signal of the first local oscillator 5 and convert it into an in-phase and quadrature signal (abbreviated as IQ signal) with common-mode rejection characteristics, and then output it to the feedback mixer 4. Wherein, I stands for in-phase and Q stands for quadrature. Schematically, in some possible implementations, the IQ signal can be an IQ clock signal.

[0058] It should be noted that as a transmitter system, it also has other modules and devices inside, such as Figure 1 The transmit baseband filter connected to the first transmit mixer 1.1, the feedback baseband filter connected to the feedback mixer 4, the amplifier (AMP) connected between the attenuator 6 and the feedback mixer 4, etc., can be specifically referred to the relevant technology and will not be described here one by one.

[0059] Compared with the transmitter system of the related art, which is prone to leakage due to the large energy of the RF feedback signal received in the feedback channel, resulting in common-mode interference, the transmitter system of the present application converts the received differential local oscillator signal of the first local oscillator into an in-phase orthogonal signal with common-mode rejection characteristics by setting a first local oscillator path and outputs it to the feedback mixer, thereby reducing the common-mode interference problem caused by the leakage of the RF feedback signal, that is, improving the problem of transmitter system performance degradation caused by the leakage of the RF feedback signal, and improving the performance of the transmitter system.

[0060] also, Figure 1 The example in which the transmitter system is provided with one transmission channel (ie, the first transmission channel t1) is used for illustration only, but the present application is not limited thereto. In some possible implementations, the transmitter system may be provided with multiple transmission channels; for example, Figure 2 As shown, the transmitter system, in addition to including the aforementioned first transmission channel t1, may further include a second transmission channel t2; the second transmission channel t2 includes a second transmission mixer 1.2, which is used to convert the received baseband transmission signal into a second RF transmission signal; the second RF transmission signal is amplified by a second power amplifier a2, output to a second coupler 2.2, and transmitted through an antenna 3 after being coupled by the second coupler 2.2.

[0061] In addition, if Figure 2As shown, the second coupler 2.2 and the first coupler 2.1 can be coupled to the feedback mixer 4 via a selector (MUX), so that the RF feedback signal coupled by the second coupler or the first coupler is transmitted to the feedback mixer 4 through the selector control. In addition, when the transmitter system adopts the first coupler 2.1 and the second coupler 2.2, the first coupler 2.1 and the second coupler 2.2 can be coupled to the same antenna or to different antennas. This application does not impose any specific restrictions on this. In practice, the setting can be selected as needed.

[0062] For other related settings in the second transmit channel t2 (such as amplifier, duplexer, filter, transmit baseband filter, etc.), reference may be made to the aforementioned description of the first transmit channel t1 and will not be repeated here.

[0063] On this basis, if Figure 2 As shown, the first local oscillator 5 is coupled to one or both of the first transmit mixer 1.1 and the second transmit mixer 1.2 to provide a local oscillator signal to one or both of the first transmit mixer 1.1 and the second transmit mixer 1.2. For example, in some possible implementations, the first local oscillator 5 is coupled to the first transmit mixer 1.1 to provide a local oscillator signal to the first transmit mixer 1.1; for another example, in some possible implementations, the first local oscillator 5 is coupled to the second transmit mixer 1.2 to provide a local oscillator signal to the second transmit mixer 1.2; for another example, in some possible implementations, the first local oscillator 5 is coupled to both the first transmit mixer 1.1 and the second transmit mixer 1.2 to provide a local oscillator signal to both the first transmit mixer 1.1 and the second transmit mixer 1.2, that is, the first local oscillator 5 is multiplexed by the first transmit mixer 1.1 and the second transmit mixer 1.2.

[0064] In addition, reference Figure 1 and Figure 3 As shown, in some possible implementations, the first local oscillator 5 may include a phase-locked loop 50, a first frequency divider 51, a second frequency divider 52, and a selector 53. The first frequency divider 51 and the second frequency divider 51 have different frequency division ratios, and the inputs of the first frequency divider 51 and the second frequency divider 52 are coupled to the phase-locked loop 50, while the outputs of the first frequency divider 51 and the second frequency divider 52 are coupled to the first local oscillation path LO1 via the selector 53. In this case, the first local oscillator 5 can select one of the first frequency divider 51 and the second frequency divider 52 to be connected to the first local oscillation path LO1 through the selector 53, so as to provide an IQ signal to the feedback mixer 4 via the first local oscillation path LO1.

[0065] It should be noted that the present application does not limit the specific configuration of the phase-locked loop 50. For example, in some possible implementations, the phase-locked loop 50 may include: Figure 3 The phase detector 501, charge pump 502, loop filter 503, voltage controlled oscillator 504, and frequency divider 505 shown in FIG. 5 ; in addition, the phase detector 501 in the phase-locked loop 50 can be connected to the crystal oscillator module ( Figure 3 The phase-locked loop 50 is connected to the first frequency divider 51 and the second frequency divider 52 through the voltage-controlled oscillator 504.

[0066] As described above, the transmitter system of the present application converts the differential local oscillator signal output by the first local oscillator 5 into an IQ signal with common-mode rejection characteristics through the first local oscillator path LO1, and outputs the converted signal to the feedback mixer 4 to improve the problem of transmitter system performance degradation caused by RF feedback signal leakage. The following further details the relevant settings of the first local oscillator path LO1 for achieving IQ signal conversion with common-mode rejection characteristics.

[0067] In some possible implementations, refer to Figure 4 and Figure 5 As shown, the first local oscillator path LO1 may include an in-phase and quadrature signal generator (hereinafter referred to as IQ signal generator) 100 and a common-mode suppression circuit 200 ; the common-mode suppression circuit 200 is used to perform common-mode suppression on the transmission signal on the first local oscillator path LO1 .

[0068] Indicative, such as Figure 4 As shown, the common mode rejection circuit 200 may be coupled between the first local oscillator 5 and the IQ signal generator 100 , that is, the common mode rejection circuit 200 may be provided at the input end side of the IQ signal generator 100 .

[0069] Indicative, such as Figure 5 As shown, the common-mode suppression circuit 200 may be coupled between the IQ signal generator 100 and the feedback mixer 4 ; that is, the common-mode suppression circuit 200 may be provided at the output end side of the IQ signal generator 100 .

[0070] The specific configuration of the IQ signal generator 100 and the common-mode suppression circuit 200 is further described below.

[0071] refer to Figure 6 and Figure 7As shown, the IQ signal generator 100 includes a first positive input terminal Vin+, a second negative input terminal Vin-, an in-phase positive output terminal I+ (hereinafter referred to as I+ output terminal), an in-phase negative output terminal I- (hereinafter referred to as I- output terminal), an orthogonal positive output terminal Q+ (hereinafter referred to as Q+ output terminal), and an orthogonal negative output terminal Q- (hereinafter referred to as Q- output terminal); the IQ signal generator 100 is used to decompose a group of differential signals input by the first positive input terminal Vin+ and the second negative input terminal Vin- into four groups of signals (I+ signal, Q+ signal, I- signal) according to the phase. In other words, the output signal of the I+ output terminal has the same vector direction as the input signal of the first positive input terminal Vin+, the output signal of the I- output terminal has a vector direction opposite to the input signal of the first positive input terminal Vin+ (i.e., a phase difference of 180°), the output signal of the Q+ output terminal intersects with the vector direction of the input signal of the first positive input terminal Vin+ (i.e., a phase difference of 90°), and the output signal of the Q- output terminal has a vector direction different from the input signal of the first positive input terminal Vin+ by 270°.

[0072] As an example, in some possible implementations, the IQ signal generator 100 may use a polyphase filter (PPF) to generate the IQ signal; Figure 6 As shown, the IQ signal generator 100 (i.e., a polyphase filter) may include a first resistor R1, a first capacitor C1, a second resistor R2, a second capacitor C2, a third resistor R3, a third capacitor C3, a fourth resistor R4, and a fourth capacitor C4. The first resistor R1 has two terminals connected to the first positive input terminal Vin+ and the I+ output terminal, respectively; the first capacitor C1 has two terminals connected to the first positive input terminal Vin+ and the Q+ output terminal, respectively; the second resistor R2 has two terminals connected to the ground terminal and the Q+ output terminal, respectively; the second capacitor C2 has two terminals connected to the ground terminal and the I- output terminal, respectively; the third resistor R3 has two terminals connected to the second negative input terminal Vin- and the I- output terminal, respectively; the third capacitor C3 has two terminals connected to the second negative input terminal Vin- and the Q- output terminal, respectively; the fourth resistor R4 has two terminals connected to the ground terminal and the Q- output terminal, respectively; and the fourth capacitor C4 has two terminals connected to the ground terminal and the I+ output terminal, respectively.

[0073] For example, in some other possible implementations, the IQ signal generator 100 may use a divide-by-2 circuit to generate the IQ signal; Figure 7As shown, the IQ signal generator 100 (i.e., a divide-by-2 circuit) may include a first latch and a second latch. The D input of the first latch is connected to the Q- output, the C input of the first latch is connected to the first positive input Vin+, the Q output of the first latch is connected to the I+ output, and the QB output of the first latch is connected to the I- output; the D input of the second latch is connected to the I+ output, the C input of the second latch is connected to the second negative input Vin-, the Q output of the second latch is connected to the Q+ output, and the QB output of the second latch is connected to the Q- output.

[0074] refer to Figure 8 and Figure 9 As shown, the common-mode suppression circuit 200 includes a first positive input terminal in1, a second negative input terminal in2, a first positive output terminal out1, a second negative output terminal out2, a first voltage terminal VDD, and a second voltage terminal (e.g., a ground terminal). The input signal of the first positive input terminal in1 is in phase with the output signal of the first positive output terminal out1, and the input signal of the second negative input terminal in2 is in phase with the output signal of the second negative output terminal out2. The common-mode suppression circuit 200 can suppress the common-mode voltage of a set of differential signals input through the first positive input terminal in1 and the second negative input terminal in2, generating a new set of differential signals with common-mode suppression characteristics and outputting them through the first positive output terminal out1 and the second negative output terminal out2.

[0075] For example, in some possible implementations, the common mode suppression circuit 200 may use a cross-coupled buffer circuit; Figure 8 As shown, the common-mode suppression circuit 200 (i.e., a cross-coupled buffer circuit) may include a first MOS transistor T1, a second MOS transistor T2, a third MOS transistor T3, and a fourth MOS transistor T4. The first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3, and the fourth MOS transistor T4 may be NMOS transistors or PMOS transistors; this is not limited in this application. The following description of the common-mode suppression circuit 200 is based on an example in which the first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3, and the fourth MOS transistor T4 are all NMOS transistors, the voltage at the first voltage terminal VDD is a high-level voltage, and the voltage at the second voltage terminal is a low-level voltage (e.g., a ground voltage).

[0076] like Figure 8As shown, in the common-mode suppression circuit 200, the gate of the first MOS transistor T1 is connected to the first positive input terminal in1 of the common-mode suppression circuit 200, the drain of the first MOS transistor T1 is connected to the first voltage terminal VDD, and the source of the first MOS transistor T1 is connected to the first positive output terminal out1 of the common-mode suppression circuit 200. The gate of the second MOS transistor T2 is connected to the second negative input terminal in2 of the common-mode suppression circuit 200, the drain of the second MOS transistor T2 is connected to the first positive output terminal out1 of the common-mode suppression circuit 200, and the source of the second MOS transistor T2 is connected to the second voltage terminal (e.g., ground). The gate of the third MOS transistor T3 is connected to the second negative input terminal in2 of the common-mode suppression circuit 200, the drain of the third MOS transistor T3 is connected to the first voltage terminal VDD, and the source of the third MOS transistor T3 is connected to the second negative output terminal out2 of the common-mode suppression circuit 200. The gate of the fourth MOS transistor T4 is connected to the first positive input terminal in1 of the common-mode suppression circuit 200, the drain of the fourth MOS transistor T4 is connected to the second negative output terminal out2 of the common-mode suppression circuit 200, and the source of the fourth MOS transistor T4 is connected to the second voltage terminal (e.g., the ground terminal). Of course, when the first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3, and the fourth MOS transistor T4 are all PMOS transistors, the connection relationship between the source and drain of the aforementioned NMOS transistors can be interchanged.

[0077] In some possible implementations, for example, Figure 9 As shown, the common-mode suppression circuit 200 may include a resistor Ra, a resistor Rb, a differential input transistor Ta, a differential input transistor Tb, and a current source (also referred to as a tail current source) S. The differential input transistors Ta and Tb may be NMOS transistors or PMOS transistors, and this application does not impose any restrictions thereto. The following description of the common-mode suppression circuit 200 is based on the example that the differential input transistors (Ta, Tb) may be NMOS transistors, the voltage at the first voltage terminal VDD is a high-level voltage, and the voltage at the second voltage terminal is a low-level voltage (e.g., a ground voltage).

[0078] like Figure 9As shown, in the common-mode suppression circuit 200, one end of the resistor Ra is connected to the first voltage terminal VDD, and the other end of the resistor Ra is connected to the second reverse output terminal out2; the gate of the differential input transistor Ta is connected to the first positive input terminal in1, the drain of the differential input transistor Ta is connected to the second reverse output terminal out2, and the source of the differential input transistor Ta is connected to the second voltage terminal (e.g., ground) via a current source S. One end of the resistor Rb is connected to the first voltage terminal VDD, and the other end of the resistor Rb is connected to the first positive output terminal out1; the gate of the differential input transistor Tb is connected to the second reverse input terminal in2, the drain of the differential input transistor Tb is connected to the first positive output terminal out1, and the source of the differential input transistor Tb is connected to the second voltage terminal (e.g., ground) via a current source S; that is, the differential input transistors Ta and Tb share a common-mode current source S. Of course, when the differential input transistors Ta and Tb are both PMOS transistors, the connection relationship between the source and drain of the differential input transistors Ta and Tb of the NMOS transistors can be interchanged.

[0079] for Figure 9 As for the common-mode suppression circuit 200 shown in FIG, it uses differential input transistors (Ta, Tb) to suppress the common-mode signal of the differential input signal at the input terminals (in1, in2). When the output impedance of the tail current source S is infinite, for the differential input signal, the common node of the differential input transistors (Ta, Tb) is virtually connected to the ground, so it can be equivalent to a common-source amplifier. For the common-mode signal, the common node of the differential input transistors (Ta, Tb) is connected from the output impedance of the tail current source S to the ground, which is equivalent to a source-level negative feedback amplifier. When the output impedance of the tail current source S is infinite, the gain approaches 0. However, in actual circuits, the output impedance of the tail current source S is limited, which limits the common-mode suppression capability of the common-mode suppression circuit 200. At the same time, due to the presence of the tail current source, a certain voltage domain is occupied, resulting in a limited effective amplitude of the differential input signal.

[0080] for Figure 8 As for the common-mode suppression circuit 200 shown in FIG, it adopts a fully differential circuit. Since the common-mode suppression circuit 200 adopts a left-right symmetrical circuit structure, the common-mode suppression capability of the common-mode suppression circuit 200 is specifically described below using the left half circuit as an example. In the common-mode suppression circuit 200, the input signal can be split into two signals, common mode and differential mode. For the common-mode signal, refer to Figure 10 As shown, the input signals of the first NMOS transistor T1 and the second NMOS transistor T2 are the same, and the output signals have opposite polarities, thereby achieving common-mode signal cancellation at the first positive output terminal out1; for differential-mode signals, refer to Figure 11The first NMOS transistor T1 and the second NMOS transistor T2 have opposite input signals and the same output polarity, thus achieving differential-mode signal addition at the output. Similarly, the third NMOS transistor T3 and the fourth NMOS transistor T4 in the right half of the circuit achieve common-mode signal cancellation and differential-mode signal addition.

[0081] Compared to Figure 7 The common-mode suppression circuit in the circuit mainly relies on source-level negative feedback and is limited by the output impedance value of the tail current source. Figure 8 Since the common-mode suppression circuit 200 shown in the figure does not have a tail current source, the maximum swing of the input signal is relatively larger, and by superimposing signals of opposite polarity, the common-mode signal can be eliminated while ensuring that the gains of the two paths are consistent, thereby making the common-mode suppression capability of the common-mode suppression circuit stronger.

[0082] The following adopts Figure 8 Taking the common mode rejection circuit 200 shown in FIG. 2 as an example, Figure 4 and Figure 5 The specific connection method of the IQ signal generator 100 and the common mode suppression circuit 200 located in the first local oscillation path LO1 is further described.

[0083] refer to Figure 4 As shown, in the case where the common mode suppression circuit 200 is provided on the input side of the IQ signal generator 100, as shown in FIG. Figure 12 As shown, the first positive input terminal in1 and the second negative input terminal in2 of the common-mode suppression circuit 200 are respectively coupled to the two differential output terminals of the first local oscillator 5, the first positive output terminal out1 of the common-mode suppression circuit 200 is coupled to the first positive input terminal Vin+ of the IQ signal generator 100, and the second negative output terminal out2 of the common-mode suppression circuit 200 is coupled to the second negative input terminal Vin- of the IQ signal generator 100; the I+ output terminal, Q+ output terminal, I- output terminal, and Q- output terminal of the IQ signal generator 100 are coupled to the feedback mixer 4.

[0084] Regarding the connection between the I+ output terminal, Q+ output terminal, I- output terminal, and Q- output terminal of the IQ signal generator 100 and the feedback mixer 4, in some possible implementations, for example, Figure 12 As shown, the I+ output terminal, Q+ output terminal, I− output terminal, and Q− output terminal of the IQ signal generator 100 can be coupled to the feedback mixer 4 through different driving circuits ( 300 . 1 , 300 . 2 , 300 . 3 , and 300 . 4 ) respectively.

[0085] In this case, the common-mode suppression circuit 200 performs common-mode cancellation and differential-mode amplification (i.e., common-mode suppression) on the differential local oscillator signal received from the first local oscillator 5, and then outputs the signal to the first positive input terminal Vin+ and the second negative input terminal Vin- of the IQ signal generator 100. The IQ signal generator 100 evenly decomposes the differential signal input from the first positive input terminal Vin+ and the second negative input terminal Vin- into four signals (I+ signal, Q+ signal, I- signal, Q- signal) according to phase, and outputs the signals through the I+ output terminal, Q+ output terminal, I- output terminal, and Q- output terminal, respectively. The four signals (I+ signal, Q+ signal, I- signal, Q- signal) are then adjusted to standard voltages (e.g., full-swing IQ clock signals) through the driver circuits (300.1, 300.2, 300.3, 300.4) and output to the feedback mixer 4.

[0086] refer to Figure 5 As shown, in the case where the common mode suppression circuit 200 is provided at the output end side of the IQ signal generator 100, as shown in FIG. Figure 13 As shown, the first local oscillator path LO1 includes two common-mode rejection circuits: a first common-mode rejection circuit 200.1 and a second common-mode rejection circuit 200.2. The first positive input terminal Vin+ and the second negative input terminal Vin+ of the IQ signal generator 100 are respectively coupled to the two differential output terminals of the first local oscillator 5. The I+ output and I- output terminals of the IQ signal generator 100 are respectively coupled to the first positive input terminal in1 and the second negative input terminal in2 of the first common-mode rejection circuit 200.1. The Q+ output and Q- output terminals of the IQ signal generator 100 are respectively coupled to the first positive input terminal in1 and the second negative input terminal in2 of the second common-mode rejection circuit 200.2. The first positive output terminal out1 and the second negative output terminal out2 of the first common-mode rejection circuit 200.1, as well as the first positive output terminal out1 and the second negative output terminal out2 of the second common-mode rejection circuit 200.2, are respectively coupled to the feedback mixer 4.

[0087] Regarding the first positive output terminal out1 and the second negative output terminal out2 of the first common-mode suppression circuit 200.1 and the first positive output terminal out1 and the second negative output terminal out2 of the second common-mode suppression circuit 200.2 being coupled to the feedback mixer 4, in some possible implementations, such as Figure 13 As shown, the first positive output terminal out1 and the second negative output terminal out2 of the first common-mode suppression circuit 200.1 and the first positive output terminal out1 and the second negative output terminal out2 of the second common-mode suppression circuit 200.2 can be coupled to the feedback mixer 4 through different driving circuits (300.1, 300.2, 300.3, 300.4) respectively.

[0088] Among some possible implementations, Figure 14 As shown, the I+ output terminal and the I- output terminal of the IQ signal generator 100 can be coupled to the first positive input terminal in1 and the second negative input terminal in2 of the first common-mode suppression circuit 200.1 through different driving circuits (300.5, 300.6), respectively. The Q+ output terminal and the Q- output terminal of the IQ signal generator 100 can be coupled to the first positive input terminal in1 and the second negative input terminal in2 of the second common-mode suppression circuit 200.2 through different driving circuits (300.7, 300.8), respectively. The first positive output terminal out1 and the second negative output terminal out2 of the first common-mode suppression circuit 200.1 and the first positive output terminal out1 and the second negative output terminal out2 of the second common-mode suppression circuit 200.2 are coupled to the feedback mixer 4 through different driving circuits (300.1, 300.2, 300.3, 300.4), respectively. That is, driving circuits are respectively provided on the paths of the input end and the output end of the first common-mode suppression circuit 200.1 and the second common-mode suppression circuit 200.2.

[0089] by Figure 14 Taking the first local oscillator path LO1 shown in FIG as an example, the IQ signal generator 100 decomposes the differential local oscillator signal received from the first local oscillator 5 into four groups of signals (I+ signal, Q+ signal, I- signal, Q- signal) according to the phase uniformity. The I+ signal at the I+ output terminal and the I- signal at the I- output terminal are respectively adjusted to the standard voltage by the driving circuits (300.5 and 300.6). After that, the common mode is eliminated and the differential mode is amplified (i.e., common mode suppression is performed) by the first common mode suppression circuit 200.1. After being adjusted to a standard voltage by driving circuits (300.1, 300.2), the signals are output to the feedback mixer 4. The Q+ signal at the Q+ output terminal and the Q- signal at the Q- output terminal are adjusted to a standard voltage by driving circuits (300.7, 300.8), respectively. After being adjusted to a standard voltage by the second common-mode suppression circuit 200.2, the signals undergo common-mode elimination and differential-mode amplification (i.e., common-mode suppression) and are again adjusted to a standard voltage by driving circuits (300.3, 300.4), respectively, and are output to the feedback mixer 4.

[0090] For any of the aforementioned drive circuits (300.1, 300.2, 300.3, 300.4, 300.5, 300.6, 300.7, 300.8), in some possible implementations, the drive circuit may use one or more cascaded inverters. Figure 15As shown, it includes two transistors (M1 and M2), transistor M1 is an N-type transistor (i.e., NMOS tube), called a driver tube; transistor M2 is a P-type transistor (i.e., PMOS tube), called a load tube; the inverter can reverse the phase of the received signal at the input end by 180° and adjust it to a standard voltage and output it through the output end.

[0091] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A transmitter system, characterized in that: including a feedback channel and a first transmitting channel; The first transmit channel includes a first transmit mixer, and the first transmit mixer is used to convert a received baseband transmit signal into a radio frequency transmit signal; The radio frequency transmission signal is amplified by the first power amplifier, output to the first coupler for coupling, and then transmitted through the antenna; The feedback channel is used to receive the radio frequency feedback signal coupled from the first coupler; The feedback channel includes a feedback mixer, and the feedback mixer is used to convert the radio frequency feedback signal into a baseband feedback signal; The feedback mixer is coupled to a first local oscillator via a first local oscillation path; The first local oscillator path is used to receive the differential local oscillator signal of the first local oscillator, convert it into an in-phase and quadrature signal with a common-mode rejection characteristic, and then output it to the feedback mixer.

2. The transmitter system according to claim 1, wherein The first local oscillator path includes an in-phase and quadrature signal generator and a common mode suppression circuit; The common-mode rejection circuit is coupled between the first local oscillator and the in-phase and quadrature signal generator; or, the common-mode rejection circuit is coupled between the in-phase and quadrature signal generator and the feedback mixer.

3. The transmitter system according to claim 2, characterized in that The in-phase and quadrature signal generator includes a first positive input terminal, a second negative input terminal, an in-phase positive output terminal, an in-phase negative output terminal, a quadrature positive output terminal, and a quadrature negative output terminal; The common mode suppression circuit includes a first positive input terminal, a second negative input terminal, a first positive output terminal, and a second negative output terminal; The first positive input terminal and the second negative input terminal of the common mode suppression circuit are respectively coupled to the two differential output terminals of the first local oscillator, and the first positive output terminal and the second negative output terminal of the common mode suppression circuit are respectively coupled to the first positive input terminal and the second negative input terminal of the in-phase and quadrature signal generator; The in-phase positive output terminal, the in-phase negative output terminal, the quadrature positive output terminal, and the quadrature negative output terminal of the in-phase and quadrature signal generator are coupled to the feedback mixer.

4. The transmitter system according to claim 2, wherein The first local oscillator path includes two common-mode suppression circuits; the two common-mode suppression circuits are respectively a first common-mode suppression circuit and a second common-mode suppression circuit; The in-phase and quadrature signal generator includes a first positive input terminal, a second negative input terminal, an in-phase positive output terminal, an in-phase negative output terminal, a quadrature positive output terminal, and a quadrature negative output terminal; the common-mode suppression circuit includes a first positive input terminal, a second negative input terminal, a first positive output terminal, and a second negative output terminal; The first positive input terminal and the second negative input terminal of the in-phase and quadrature signal generator are respectively coupled to the two differential output terminals of the first local oscillator; The in-phase positive output terminal and the in-phase negative output terminal of the in-phase and quadrature signal generator are respectively coupled to the first positive input terminal and the second negative input terminal of the first common-mode suppression circuit, and the quadrature positive output terminal and the quadrature negative output terminal of the in-phase and quadrature signal generator are respectively coupled to the first positive input terminal and the second negative input terminal of the second common-mode suppression circuit; The first positive output terminal and the second negative output terminal of the first common-mode suppression circuit and the first positive output terminal and the second negative output terminal of the second common-mode suppression circuit are coupled to the feedback mixer.

5. The transmitter system according to claim 3 or 4, characterized in that The in-phase positive output terminal, the in-phase negative output terminal, the quadrature positive output terminal, and the positive negative output terminal of the in-phase and quadrature signal generator are respectively coupled to the feedback mixer through different driving circuits.

6. The transmitter system according to claim 4, characterized in that The in-phase positive output terminal and the in-phase negative output terminal of the in-phase and quadrature signal generator are respectively coupled to the first positive input terminal and the second negative input terminal of the first common-mode suppression circuit through different driving circuits, and the first positive output terminal and the second negative output terminal of the first common-mode suppression circuit are respectively coupled to the feedback mixer through driving circuits; The orthogonal positive output terminal and the orthogonal negative output terminal of the in-phase orthogonal signal generator are respectively coupled to the first positive input terminal and the second negative input terminal of the second common-mode suppression circuit through different driving circuits, and the first positive output terminal and the second negative output terminal of the second common-mode suppression circuit are respectively coupled to the feedback mixer through driving circuits.

7. The transmitter system according to any one of claims 2 to 4 and 6, characterized in that: The common mode suppression circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; The gate of the first NMOS transistor is coupled to the first positive input terminal of the common-mode suppression circuit, the drain of the first NMOS transistor is coupled to the first voltage terminal, and the source of the first NMOS transistor is coupled to the first positive output terminal of the common-mode suppression circuit; The gate of the second NMOS transistor is coupled to the second inverting input terminal of the common-mode suppression circuit, the drain of the second NMOS transistor is coupled to the first positive output terminal of the common-mode suppression circuit, and the source of the second NMOS transistor is coupled to the second voltage terminal; The gate of the third NMOS transistor is coupled to the second inverting input terminal of the common-mode suppression circuit, the drain of the third NMOS transistor is coupled to the first voltage terminal, and the source of the third NMOS transistor is coupled to the second inverting output terminal of the common-mode suppression circuit; The gate of the fourth NMOS transistor is coupled to the first positive input terminal of the common-mode suppression circuit, the drain of the fourth NMOS transistor is coupled to the second negative output terminal of the common-mode suppression circuit, and the source of the fourth NMOS transistor is coupled to the second voltage terminal.

8. The transmitter system according to any one of claims 1 to 4 and 6, characterized in that: The transmitter system further includes a second transmit channel, the second transmit channel including a second transmit mixer, the second transmit mixer being configured to convert a received baseband transmit signal into a second radio frequency transmit signal; The second radio frequency transmission signal is amplified by the second power amplifier, output to the second coupler for coupling, and then transmitted through the antenna; The first local oscillator is used to provide a local oscillator signal for the first transmit mixer and / or the second transmit mixer.

9. The transmitter system according to any one of claims 1 to 4 and 6, characterized in that: The first local oscillator further includes a phase-locked loop, a first frequency divider, a second frequency divider, and a selector; Input terminals of the first frequency divider and the second frequency divider are coupled to the phase-locked loop, and output terminals of the first frequency divider and the second frequency divider are coupled to the first local oscillator path through the selector.

10. The transmitter system according to any one of claims 1 to 4 and 6, characterized in that: The in-phase and quadrature signal generator is a polyphase filter.

11. The transmitter system according to claim 5, characterized in that The driving circuit includes an inverter.

12. The transmitter system according to any one of claims 1 to 4, 6 and 11, characterized in that: The feedback path further includes an attenuator coupled between the first coupler and the feedback mixer.

13. An electronic device, characterized in that: Comprising a transmitter system as claimed in any one of claims 1 to 12.

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