Three-dimensional memory and its manufacturing method

Abstract

This application provides a three-dimensional memory and a method for manufacturing the same. The three-dimensional memory includes a stacked structure comprising a first stacked layer and a second stacked layer. The first stacked layer includes alternately stacked control gate layers and a first dielectric layer, and the second stacked layer includes alternately stacked top select gate layers and second dielectric layers. It also includes multiple channel structures that penetrate the stacked structure and include charge storage layers. Each charge storage layer includes multiple charge storage portions discontinuously disposed along the stacking direction of the stacked structure, with the charge storage portions located between adjacent first dielectric layers. Finally, it includes at least one isolation structure that penetrates the top select gate layer and is located between adjacent channel structures. The three-dimensional memory and manufacturing method provided by this application maintain the process window of the top select gate tangent line unchanged, reducing storage density loss.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology. Specifically, this application relates to a three-dimensional memory and a method for manufacturing the same. Background Technology

[0002] As the number of stacked layers in 3D memory increases, it is often necessary to thin the gate and dielectric layers in the stack to reduce the overall stack height and thus alleviate the load caused by deep via etching. However, thinning the gate and dielectric layers can create coupling effects between memory cells and weaken the data retention capability of the 3D memory.

[0003] It should be understood that the background section is intended to provide some useful background for understanding the technology; however, this content is not necessarily what was known or understood by a person skilled in the art prior to the filing date of this application. Summary of the Invention

[0004] One aspect of this application provides a three-dimensional memory, comprising: a stacked structure including a first stacked layer and a second stacked layer, wherein the first stacked layer includes alternately stacked control gate layers and first dielectric layers, and the second stacked layer includes alternately stacked top select gate layers and second dielectric layers; a plurality of channel structures extending through the stacked structure and including charge storage layers, wherein the charge storage layers include a plurality of charge storage portions discontinuously disposed along the stacking direction of the stacked structure, the charge storage portions being disposed between adjacent first dielectric layers; and at least one isolation structure extending through the top select gate layer and located between adjacent channel structures.

[0005] In one embodiment of this application, the top select gate layer and the control gate layer are made of different materials.

[0006] In one embodiment of this application, the top selected gate layer comprises a semiconductor material.

[0007] In one embodiment of this application, the semiconductor material includes polycrystalline silicon or metal nitride.

[0008] In one embodiment of this application, the semiconductor material comprises boron-doped polycrystalline silicon.

[0009] In one embodiment of this application, the control gate layer comprises metal.

[0010] In one embodiment of this application, the metal includes tungsten.

[0011] In one embodiment of this application, the channel structure includes: a plurality of first portions surrounded by the control gate layer and a plurality of second portions surrounded by the second stacked layer and the first dielectric layer, wherein a first radial dimension of the first portions is greater than a second radial dimension of the second portions.

[0012] In one embodiment of this application, each of the first portions includes a first charge blocking portion and the charge storage portion, wherein, between adjacent first dielectric layers, the charge storage portion covers the sidewall of the first charge blocking portion.

[0013] In one embodiment of this application, the first part further includes a tunneling layer, a channel layer, and a dielectric core sequentially disposed on the sidewall of the charge storage portion.

[0014] In one embodiment of this application, the first charge blocking portion covers the inner wall surrounded by the adjacent first dielectric layer and the control gate layer therebetween.

[0015] In one embodiment of this application, the second portion includes a plurality of second charge blocking portions disposed on the sidewalls of the second stacked layer and the first dielectric layer, wherein the tunneling layer, the channel layer and the dielectric core extend sequentially on the second charge blocking portions, and the first charge blocking portions and the second charge blocking portions form a continuous blocking layer.

[0016] In one embodiment of this application, the first portion includes a charge blocking portion and a charge storage portion, wherein the charge blocking portion covers the sidewall of the control gate layer.

[0017] In one embodiment of this application, the tunneling layer, the trench layer, and the dielectric core are sequentially disposed on the sidewalls of the second stacked layer and the first dielectric layer.

[0018] In one embodiment of this application, the charge blocking portion and the charge storage portion have the same size in the stacking direction.

[0019] In one embodiment of this application, the charge blocking portion and the control gate layer have the same dimensions in the stacking direction.

[0020] In one embodiment of this application, the first charge blocking portion comprises silicon oxynitride or silicon oxide, and the charge storage portion comprises silicon nitride.

[0021] Another aspect of this application provides another three-dimensional memory, comprising: a stacked structure including a first stacked layer and a second stacked layer, wherein the first stacked layer includes alternately stacked first dielectric layers and control gate layers, the second stacked layer includes alternately stacked second dielectric layers and top selected gate layers, wherein the control gate layers include metal, and the top selected gate layers include semiconductor material; a plurality of channel structures extending through the stacked structure and a charge storage layer, wherein the charge storage layer includes a plurality of charge storage portions discontinuously disposed along the direction of the stack, the charge storage portions being disposed between adjacent first dielectric layers; and at least one isolation structure extending through the top selected gate layer and located between adjacent channel structures.

[0022] Another aspect of this application provides a method for manufacturing a three-dimensional memory, the method comprising: sequentially forming a first stacked layer consisting of alternating first dielectric layers and sacrificial layers, and a second stacked layer consisting of alternating second dielectric layers and conductive layers; forming a channel via through the first stack and the second stack; removing at least a portion of each of the sacrificial layers in the first stack through the channel via, such that a recess is formed between adjacent first dielectric layers in the first stack; forming a channel structure in the recess and the channel via; and forming an isolation structure in the second stack, wherein the isolation structure penetrates the conductive layer and is located between adjacent channel structures.

[0023] In one embodiment of this application, the method further includes: forming a gate slit through the first stacked layer and the second stacked layer; removing the remainder of the sacrificial layer via the gate slit; and forming a conductor layer in the sacrificial space formed after the remainder has been removed.

[0024] In one embodiment of this application, the isolation structure is formed before the channel hole is formed.

[0025] In one embodiment of this application, the isolation structure is formed after the channel structure is formed.

[0026] In one embodiment of this application, the isolation structure is formed after the conductor layer is formed.

[0027] In one embodiment of this application, forming the isolation structure includes: forming an opening through the second stacked layer, the opening being located between adjacent channel structures; and filling the opening with an insulating material.

[0028] In one embodiment of this application, forming the channel structure includes: forming a continuous barrier layer along the sidewall of the channel hole on the inner wall of the recess, the second stacked layer, and the first dielectric layer; and forming a charge storage portion in each of the recesses.

[0029] In one embodiment of this application, forming the channel structure further includes:

[0030] A tunneling layer, a channel layer, and a dielectric core are sequentially formed on the portion of the barrier layer along the sidewall of the channel hole and on the charge storage portion.

[0031] In one embodiment of this application, forming the channel structure includes forming a plurality of intermittent charge storage portions and a plurality of intermittent charge blocking portions in the recess.

[0032] In one embodiment of this application, forming a plurality of discontinuous charge storage portions and a plurality of discontinuous charge blocking portions in each of the recesses includes: forming a plurality of initial charge storage portions in each of the recesses; removing the remainder of the sacrificial layer to expose the initial charge storage portions on a side opposite to the channel aperture; and oxidizing at least a portion of the exposed initial charge storage portions into the charge blocking portions.

[0033] In one embodiment of this application, before forming the intermittent charge storage portion, the method further includes forming an etch stop layer located on the sidewall of the sacrificial layer in each of the recesses.

[0034] In one embodiment of this application, removing the remaining portion of the sacrificial layer includes: etching the remaining portion of the sacrificial layer and stopping at the etch stop layer; and removing the etch stop layer.

[0035] In one embodiment of this application, forming the channel structure further includes: sequentially disposing a tunneling layer, a channel layer, and a dielectric core on the sidewall of the second stacked layer, the charge storage portion, and the sidewall of the first dielectric layer. Attached Figure Description

[0036] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. In the drawings,

[0037] Figure 1 A flowchart of a method for manufacturing a three-dimensional memory according to some embodiments of this application;

[0038] Figure 2This is a partial schematic diagram of the device structure after the stacked structure is formed according to a method for manufacturing a three-dimensional memory according to some embodiments of this application;

[0039] Figure 3 This is a partial schematic diagram of the device structure after the formation of the channel via in a method for manufacturing a three-dimensional memory according to some embodiments of this application.

[0040] Figure 4 This is a partial schematic diagram of a device structure formed after removing at least a portion of the sacrificial layer according to a method for manufacturing a three-dimensional memory according to some embodiments of this application.

[0041] Figure 5 This is a partial schematic diagram of the device structure after the formation of a continuous barrier layer according to the manufacturing method of a three-dimensional memory according to Embodiment 1 of this application.

[0042] Figure 6 This is a partial schematic diagram of the device structure after the formation of continuous storage layers according to the manufacturing method of a three-dimensional memory according to Embodiment 1 of this application.

[0043] Figure 7 This is a partial schematic diagram of the device structure after forming multiple charge storage portions according to the manufacturing method of a three-dimensional memory according to Embodiment 1 of this application.

[0044] Figure 8 This is a partial schematic diagram of the device structure formed after the formation of the channel structure according to the manufacturing method of the three-dimensional memory according to Embodiment 1 of this application;

[0045] Figure 9 This is a partial schematic diagram of the device structure after the opening is formed according to the manufacturing method of the three-dimensional memory according to Embodiment 1 of this application;

[0046] Figure 10 This is a partial schematic diagram of the device structure after the isolation structure is formed according to the manufacturing method of the three-dimensional memory according to Embodiment 1 of this application;

[0047] Figure 11 This is a partial schematic diagram of the method for manufacturing a three-dimensional memory according to Embodiment 1 of this application, showing the formation of an isolation structure before the formation of a channel hole;

[0048] Figure 12 This is a partial schematic diagram of the device structure after the conductor layer is formed according to the manufacturing method of the three-dimensional memory according to Embodiment 1 of this application;

[0049] Figures 13-16 This is a partial schematic diagram of the device structure after the top selection gate tangent is formed, according to a method for manufacturing a three-dimensional memory according to some embodiments of this application.

[0050] Figure 17 This is a partial schematic diagram showing the formation of an opening after the conductor layer is formed in the manufacturing method of a three-dimensional memory according to Embodiment 1 of this application;

[0051] Figure 18 This is a flowchart illustrating the steps of forming a plurality of discontinuous charge storage portions and a plurality of discontinuous charge blocking portions in a recess in a manufacturing method of a three-dimensional memory according to Embodiment 2 of this application.

[0052] Figure 19 This is a partial schematic diagram of the device structure after the formation of continuous storage layers in the manufacturing method of the three-dimensional memory according to Embodiment 2 of this application.

[0053] Figure 20 This is a partial schematic diagram of the device structure after multiple initial memory structures have been formed according to the manufacturing method of the three-dimensional memory according to Embodiment 2 of this application;

[0054] Figure 21 This is a partial schematic diagram of the device structure formed after filling the channel holes according to the manufacturing method of the three-dimensional memory according to Embodiment 2 of this application;

[0055] Figure 22 This is a partial schematic diagram of the device structure after exposing multiple initial charge storage portions according to the manufacturing method of the three-dimensional memory according to Embodiment 2 of this application;

[0056] Figure 23 This is a partial schematic diagram of the device structure after the formation of the initial etch stop layer according to the manufacturing method of the three-dimensional memory according to Embodiment 2 of this application;

[0057] Figure 24 This is a partial schematic diagram of the device structure after the etch stop layer is formed according to the manufacturing method of the three-dimensional memory according to Embodiment 2 of this application;

[0058] Figure 25 This is a partial schematic diagram of the device structure after forming multiple initial charge storage portions on the etch stop layer according to the manufacturing method of the three-dimensional memory according to Embodiment 2 of this application;

[0059] Figure 26 This is a partial schematic diagram of the device structure formed after forming multiple charge blocking portions according to the manufacturing method of the three-dimensional memory of Embodiment 2 of this application.

[0060] Figure 27 This is a partial schematic diagram of the device structure formed after the formation of the conductor layer according to the three-dimensional memory manufacturing method of Embodiment 2 of this application;

[0061] Figure 28This is a partial schematic diagram of the device structure after the opening of the isolation structure is formed according to the manufacturing method of the three-dimensional memory of Embodiment 2 of this application; and

[0062] Figure 29 This is a partial schematic diagram of the device structure after forming the isolation structure according to the three-dimensional memory manufacturing method of Embodiment 2 of this application. Detailed Implementation

[0063] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements.

[0064] Note that references to "one embodiment," "implementation," "example embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly stated or not, implementing that feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0065] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0066] It should be readily understood that the meanings of “above,” “on top,” and “above” in this disclosure should be interpreted in the broadest sense, such that “above” means not only “directly on something” but also includes “on something” with an intermediate feature or layer therebetween, and that “on top” or “above” means not only “above” or “above” something but also includes “above” or “above” something without an intermediate feature or layer therebetween (i.e., directly on something).

[0067] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for ease of description to describe the relationship between one element or feature and another element(s)(s)(s) as shown in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and accordingly, the spatial relative descriptors used herein may be interpreted similarly.

[0068] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire upper or lower structure, or may have a extent smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers.

[0069] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the terms “approximately,” “about,” and similar terms used herein are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0070] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising," when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0071] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0072] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0073] It should be understood that, in describing specific embodiments of this application, for ease of explanation, the cross-sectional views showing the device structure may be partially enlarged without adhering to the general scale, and the cross-sectional views are merely schematic structural diagrams illustrating some steps and components of this application and the relationships between the components, and should not limit the scope of protection of this application.

[0074] Implementation Method 1

[0075] like Figure 1 The diagram shows a flowchart of a three-dimensional memory manufacturing method 200 according to some embodiments of this application. Embodiment 1 includes various operations of method 200, which will be described below with reference to... Figures 2-17 The following partial schematic diagrams illustrate the device structure formed at each stage of the manufacturing method of the three-dimensional memory, describing this embodiment. For ease of explanation, the schematic diagrams showing the device structure are partially enlarged, not to scale, and are merely examples; they should not limit the scope of protection of this application. Furthermore, in actual fabrication, a three-dimensional spatial scale including length, width, and depth should be included. It should be understood that the operations shown in the method are not exhaustive, and other operations may be performed before, after, or between any of the described operations.

[0076] Reference Figure 1 According to some embodiments of the present application, the three-dimensional memory manufacturing method 200 can sequentially form a first stacked layer 110 consisting of an alternating first dielectric layer and a sacrificial layer in operation S210. Figure 2 ), and a second stacked layer 120 consisting of a second dielectric layer and a conductive layer and alternating stacked layers ( Figure 2 ).like Figure 2As shown, a stacked structure consisting of a first stacked layer 110 and a second stacked layer 120 is sequentially formed on a substrate (not shown). The substrate can be made of any suitable semiconductor material, such as single-crystal silicon, polycrystalline silicon, single-crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide and other III-V compounds.

[0077] In some embodiments, a first stacked layer 110 may be formed via a plurality of alternately stacked first dielectric layers 111 and sacrificial layers 112. The first stacked layer 110 may include a plurality of first dielectric layer 111 / sacrificial layer 112 pairs, the number of which may be selected depending on various application scenarios. In some examples, the material of the first dielectric layer 111 includes silicon oxide, silicon nitride, silicon oxynitride, organosilicon glass (OSG), spin-coated dielectric materials, dielectric metal oxides (e.g., alumina, hafnium oxide, etc.) and their silicates, commonly referred to as high dielectric constant (high k) dielectric oxides, dielectric metal oxynitrides and their silicates, and organic insulating materials. Under the same etching process, the first dielectric layer 111 has a high etching selectivity to the sacrificial layer 112 to ensure that the first dielectric layer 111 is hardly removed during subsequent removal of the sacrificial layer 112. As an example, the first dielectric layer 111 may include silicon oxide, and the sacrificial layer 112 may include silicon nitride. In some embodiments, a first stacked layer 110 can be formed over a substrate by repeatedly and alternately performing a deposition process of a first dielectric layer 111 and a sacrificial layer 112. The deposition process may include, for example, a thin film deposition process of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0078] On the first stacked layer 110, a plurality of second dielectric layers 121 and conductive layers 122 may be alternately stacked along a stacking direction in which first dielectric layers 111 and sacrificial layers 112 are alternately stacked to form a second stacked layer 120. Exemplarily, the second stacked layer 120 may include at least one pair of second dielectric layer 121 / conductive layer 122, and the number of pairs of second dielectric layer 121 / conductive layer 122 may be less than the number of pairs of first dielectric layer 111 / sacrificial layer 112. As an example, the number of pairs of second dielectric layer 121 / conductive layer 122 may be, for example, 1, 2, 4 or more. In some examples, the second dielectric layer 121 and conductive layer 122 may be alternately deposited to form the second stacked layer 120 using thin film deposition processes including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some embodiments, due to increasingly higher requirements for the number of stacked layers, deposition processes with higher deposition rates, such as chemical vapor deposition, are typically employed to increase deposition time and productivity.

[0079] In some examples, the material of the conductive layer 122 may include any suitable conductive material, wherein the sacrificial layer 112 has a high etch selectivity relative to the conductive layer 122 to retain the conductive layer 122 when at least a portion of the sacrificial layer 112 is removed. Exemplarily, the process for removing at least a portion of the sacrificial layer 112 may include isotropic wet etching, in which the sacrificial layer 112 has a high etch selectivity relative to the conductive layer 122, to ensure that the conductive layer 122 is hardly removed during subsequent removal of the sacrificial layer 112.

[0080] In some examples, the conductive material of the conductive layer 122 may include a semiconductor material, such as polysilicon or metal silicide. Alternatively, the conductive layer 122 may include P-type doped (e.g., boron doped) polysilicon such that when the conductive layer 122 is used as a top-select gate layer, the threshold voltage of the top-select gate transistor is positive, thereby turning off the controlled channel.

[0081] In some examples, the conductive material of the conductive layer 122 may include metals such as W, Co, Cu, Al, Ti, Ta, and Ni, and the work function of the metal satisfies the following: when the conductive layer 122 is used as a top-select gate layer, the threshold voltage of the top-select gate transistor is positive, thereby turning off the controlled channel.

[0082] In some examples, to simplify the manufacturing process, the material of the second dielectric layer 121 may be the same as that of the first dielectric layer 111.

[0083] In some embodiments, stepped structures may be formed on both sides or near the middle of the stacked structure (not in Figure 2 (As shown), to facilitate the routing of word lines. The formation of the stepped structure can be achieved by repeatedly etching the second dielectric layer 121 and conductive layer 122, as well as the sacrificial layer 112 and first dielectric layer 111, over the stacked structure using a mask layer (e.g., patterned photoresist). Exemplarily, the mask layer can be trimmed to expose portions of the second dielectric layer 121 and conductive layer 122, as well as the sacrificial layer 112 and first dielectric layer 111, to be etched, so that the exposed portions can be etched using a suitable etching process. It should be understood that the stepped structure can be formed at any suitable stage of the method of manufacturing the three-dimensional memory device without departing from the teachings of the invention.

[0084] Back Figure 1 The three-dimensional memory manufacturing method 200 according to some embodiments of this application continues to operation S220, in which a plurality of channel holes 130 are formed through the first stack 110 and the second stack layer 120. Figure 3 ).

[0085] like Figure 3As shown, vias 130 can be formed in a stacked structure (first stacked layer 110 and second stacked layer 120). In some embodiments, a plurality of vias 130 are arranged in an array in the stacked structure, and each via 130 extends vertically into a substrate (not shown). Furthermore, the vias 130 may have a high aspect ratio and can be formed by etching the stacked structure. Exemplarily, the vias 130 can be formed by forming a mask layer (not shown) on the stacked structure and patterning the mask layer using, for example, a photolithography process, and then performing a suitable etching process, such as wet etching, dry etching, or a combination thereof, to etch the first stacked layer 110 and the second stacked layer 120. In some embodiments, the mask layer may be removed after the plurality of vias 130 have been formed.

[0086] Continue back Figure 1 The three-dimensional memory manufacturing method 200 according to some embodiments of this application further includes operation S230 to remove at least a portion of each sacrificial layer 112 in the first stacked layer 110 via a channel via 130, such that a recess 103 is formed between each adjacent first dielectric layer 111 in the first stacked layer 110. Figure 4 ).

[0087] like Figure 4 As shown, at least a portion of each sacrificial layer 112 can be removed via via aperture 130 to form a recess 103, wherein the recess 103 may communicate perpendicularly or substantially perpendicularly to the via aperture 130. In some embodiments, a portion of each sacrificial layer 112 parallel to the stack direction and perpendicular or substantially perpendicular to the stack direction can be removed via via aperture 130 by an isotropic wet etching process to expose a portion of the top and bottom surfaces of each first dielectric layer 111, and may also expose the sidewalls of the sacrificial layer 112 to form the recess 103.

[0088] Refer again Figure 4 In the second stacked layer 120, adjacent channel holes 130 have a wall thickness D2. Due to the formation of recesses 103 between adjacent first dielectric layers 111 that are perpendicular or substantially perpendicular to the channel holes 130, adjacent channel holes 130 in the first stacked layer 110 have different and alternating wall thicknesses. At the first dielectric layer 111, adjacent channel holes 130 may have a wall thickness D2, while at the sacrificial layer 112, adjacent channel holes 130 have a wall thickness D1, wherein D2 is greater than D1.

[0089] like Figure 1 As shown, the three-dimensional memory manufacturing method 200 according to some embodiments of this application further includes operation S240 to form a channel structure 139 in the recess 103 and the channel hole 130. Figure 8 ). Figures 5-8A schematic diagram of the various stages in forming the channel structure is shown.

[0090] like Figure 5 As shown, in some embodiments, a continuous barrier layer 131 may be formed along the sidewalls of the channel via 130 on the inner wall of the recess 103, the second stacked layer 120, and the first dielectric layer 111 using a suitable deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some examples, the material used for the barrier layer 131 may include silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material such as aluminum oxide or hafnium oxide.

[0091] Refer again Figure 5 In the example shown, the barrier layer 131 may include a first charge-blocking portion 131-1 and a second charge-blocking portion 131-2, wherein the first charge-blocking portion 131-1 may cover a portion of the sidewalls of the sacrificial layer 112 and the bottom and top surfaces of its adjacent first dielectric layer 111 within the recess 103. The second charge-blocking portion 131-2 may cover the sidewalls of the second stacked layer 120 and the first dielectric layer 111 along the channel via 130.

[0092] like Figure 6 As shown, after forming the barrier layer 131, a continuous storage layer 132 can be formed on the first charge-blocking portion 131-1 in each recess 103 and the second charge-blocking portion 131-2 on the sidewall of the channel via 130 using a suitable deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Exemplarily, in the recess 103, the storage layer 132 can fill the space defined by the first charge-blocking portion 131-1. Then, the portion of the storage layer 132 located on the second charge-blocking portion 131-2 can be removed using, for example, an anisotropic dry etching process, leaving its portion in the recess 103, thereby forming a continuous storage layer 132. Figure 7 The diagram shows multiple discontinuous charge storage sections 132-1. During the operation of the three-dimensional memory, the multiple discontinuous charge storage sections 132-1 can reduce charge loss caused by the diffusion of stored charge in adjacent memory cells, thereby improving the data retention capability of the memory. Furthermore, the discontinuous charge storage sections 132-1 can mitigate the coupling effect of memory cells due to uneven electric field distribution, thus improving the reliability of the three-dimensional memory.

[0093] like Figure 8As shown, after forming multiple storage structures 132-1, the channel holes 130 can be filled to form a channel structure 139. Exemplarily, a tunneling layer 133, a channel layer 134, and a dielectric core 135 can be sequentially formed along the sidewall of the channel holes 130 on the second charge blocking portion 131-2 and the charge storage portion 132-1, wherein the charge captured by the storage structure 132-1 can tunnel through the tunneling layer 133 into the channel layer 134 and be transported in the channel layer 134.

[0094] Exemplary examples show that the material used for the tunneling layer 133 may include silicon oxide, silicon nitride, or silicon oxynitride, and the material used for the channel layer 134 may include one or more semiconductor materials, such as single-element semiconductor materials, III-V compound semiconductor materials, II-VI compound semiconductor materials, and / or organic semiconductor materials. In some embodiments, the channel layer 134 may include a polysilicon layer for facilitating charge transport. In some examples, the dielectric core 135 may include a suitable dielectric material, such as silicon oxide. As an example, the channel structure 139 corresponding to the first stacked layer 110 may include a silicon oxide-silicon nitride-silicon oxide-silicon nitride-polysilicon (ONOP) structure.

[0095] Alternatively, a tunneling layer 133, a channel layer 134, and a dielectric core 135 may be sequentially deposited radially toward the center of the channel hole 130 via a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, wherein the dielectric core 135 may fill the space defined by the channel layer 134.

[0096] like Figure 8 As shown, due to the removal of a portion of the sacrificial layer 112 of the first stacked layer 110, a structure is formed between adjacent first dielectric layers 111 as follows: Figure 4 The recess 103 is shown, but a similar operation is not performed on the second stacked layer 120, so there is no difference between the recess 103 and the channel hole 130. Figure 4 After the channel structure 139 is formed in the first stacked layer 110 and the second stacked layer 120, the channel structure 139 surrounded by the first stacked layer 110 and the second stacked layer 120 may have alternating and different radial dimensions.

[0097] Refer again Figure 8 In some examples, the first portion 139-1 of the channel structure 139 surrounded by the sacrificial layer 112 has a first radial dimension L1, and the second portion 139-2 of the channel structure 139 surrounded by the second stacked layer 120 and the first dielectric layer 111 has a second radial dimension L2, wherein L1 is greater than L2.

[0098] It should be noted that, for the purpose of clarity, the first part 139-1 and the second part 139-2 of the channel structure 139 are... Figure 8In the example, the markings are on two identical channel structures 139. For the same purpose, the first part 139-1 and the second part 139-2 are also marked in the same way in other exemplary figures. This does not have any material effect on the scope of protection of this application.

[0099] It is understood that the channel structure 139 surrounded by the second stacked layer 120 may not include a storage layer for storing charge. Alternatively, when the barrier layer 131 and the tunneling layer 133 comprise silicon oxide, the barrier layer 131 and the tunneling layer 133 may serve as the gate oxide layer of a MOS transistor.

[0100] In some embodiments, a channel plug 136 may also be formed on the top of the channel hole 130 away from the substrate, which can increase the contact area and process window for bit line contact landing.

[0101] In some embodiments, a gate slit may also be formed in the stacked structure after the channel structure 139 is formed. Figure 8 (Not shown), for example, a gate slit can be formed vertically through the stacked structure by, for example, an anisotropic dry etching process.

[0102] In some examples, the gate slit ( Figure 8 (Not shown) may include a first gate slit and a second gate slit, wherein the first gate slit may divide the stacked structure into multiple block regions, and the second gate slit may divide the block regions into multiple finger regions between adjacent first gate slits.

[0103] It is readily understood that the gate slit can be formed at any suitable stage of the method of manufacturing the three-dimensional memory without departing from the teachings of the present invention.

[0104] Back Figure 1 The memory manufacturing method according to some embodiments of this application continues to operation S250, wherein an isolation structure 124 may be formed in the second stacked layer 120, the isolation structure 124 penetrating the conductive layer 122 and passing between adjacent channel structures 139. Figure 10 The corresponding structure is shown.

[0105] like Figure 9 In the embodiment shown, after the trench structure 139 is formed, an opening 123 can be formed in the second stacked layer 120 by means of an anisotropic dry etching process or an isotropic wet etching process. The opening 123 can pass through the second stacked layer 120 and stop in the second dielectric layer 121 that is in contact with the first stacked layer 110.

[0106] Compared to two-dimensional memories, three-dimensional memories typically consist of a three-dimensional stacked structure formed by alternating layers of gate and dielectric layers. An array of channel structures can be formed within this stacked structure, with memory cells formed at the intersections of the channel structures and gate layers. Multiple memory cells form a memory string along the stacking direction.

[0107] In some implementations, such as Figure 11 As shown, the three-dimensional memory may include a stacked structure 400, which includes alternating dielectric layers 211 and gate layers 212 and a channel structure 339 formed through the dielectric layers 211 and gate layers 212. Alternatively, at least one gate layer 212 located on top of the stacked structure 400 may serve as a top selected gate layer. The top selected gate layer can be partitioned by setting a top selected gate tangent 233, thereby enabling more precise control over the memory strings of each partition.

[0108] In some examples, it is possible to use two adjacent second gate slits ( Figure 11 A 9-row channel structure 339 (the "rows" are parallel to the gate slits) is provided in the finger region (not shown), which may also be called a "9-hole array". The "9-hole array" is controlled by the top selection gate of the finger region.

[0109] Within a storage plane of the same area, if channel structure 339 ( Figure 11 Increasing the number of rows can significantly reduce the number of second gate slits, increasing the number of channel structures 339 with storage function. Figure 11 This increases the number of [items], thereby increasing storage density.

[0110] The inventors discovered that increasing the "9-hole array" to a "12 / 15 / 16 / 19 / 24-hole array" or more not only increases the second gate slit ( Figure 11 The number of (not shown) decreases, and the second gate slit ( Figure 11 The spacing between (not shown) means that if the top select gate tangent 233 is formed first, it will hinder the diffusion of the gate material during the gate replacement step, thus affecting the formation of the gate layers 212 on both sides of the top select gate tangent. Therefore, the fabrication step of the top select gate tangent 233 usually needs to be moved after the gate replacement step. Since the step of forming the gate layer 212 usually involves depositing multiple layers of different types of materials that are significantly different from the dielectric layer materials, such as high-k dielectric, TiN, and W, etching is required when forming the opening of the top select gate tangent 233. Due to the significant material differences between the layers, the variety of materials, and the large number of stacked layers, selective etching is difficult, making the fabrication process of the top select gate tangent challenging.

[0111] In some examples, such as Figure 11As shown, the channel structure 339 typically includes an ONOP (oxide-nitride-oxide-polysilicon) composite layer, which can form at least a portion of the memory layer (not shown) of the channel structure 339 between adjacent dielectric layers 211. This allows the memory layer to be bent or broken to reduce or block the diffusion of stored charge in the stacking direction, improving the data retention capability of the memory. However, because a portion of the space is occupied between the dielectric layers 212, the wall thickness W at some locations between adjacent channel structures 339 becomes correspondingly thinner, resulting in a reduction in the process window of the top select gate tangent 233.

[0112] like Figure 12 As shown, in some embodiments, in order to increase the process window of the top selected gate tangent 233, a portion of two adjacent rows of channel structures 339 may be occupied, which will not be electrically connected during subsequent 3D memory operations.

[0113] like Figure 13 As shown, in some embodiments, an additional row of dummy channel structures 239 (without storage function) may be formed for use by the top selection gate tangent 233.

[0114] like Figure 14 As shown, in some embodiments, the wall thickness between adjacent storage channel structures 339 can also be increased, for example, the wall thickness can be increased from... Figure 11 The W shown increases to Figure 14 W' is shown in the diagram.

[0115] The inventors discovered that the method of increasing the process window of the top selected gate tangent 233 leads to a reduction in the number of channel structures 339, resulting in a loss of storage density.

[0116] As mentioned above, for example Figure 9 In some embodiments including a first stacked layer 110 and a second stacked layer 120, the wall thickness of adjacent channel structures 139 is thinned at the sacrificial layer 112 of the first stacked layer 110, with the thinned wall thickness being D1. In the second stacked layer 120, the wall thickness D2 of adjacent channel structures 139 is almost preserved. When an opening 123 is formed through the second stacked layer 120 with a wall thickness of D2, its process window is hardly reduced. Under certain process conditions, it is not necessary to enlarge the process window of the isolation structure 124, which can reduce the occurrence of channel structures 139 occupying a portion of the space, adding an extra row of dummy channel structures, or increasing the wall thickness between adjacent channel structures 139. Therefore, to a certain extent, the loss of storage density can be reduced.

[0117] Because the second stacked layer 120 is thin, with a thickness range of, for example, in the nanometer range, it is relatively easy to form the opening 123 by etching the second stacked layer 120.

[0118] In some examples, insulating material can be filled into the opening 123 to form a shape such as Figure 10 The isolation structure 124 is shown. The filling insulating material may include one or more of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and oxynitride (e.g., silicon oxynitride) materials. Alternatively, the top surface of the isolation structure 124 may be planarized using chemical mechanical polishing. In some examples, the isolation structure 124 may be disposed as a top select gate tangent between adjacent second gate slits to divide the finger region into multiple sub-regions, facilitating more precise control over the memory strings of the sub-regions.

[0119] like Figure 15 As shown, in some embodiments, the isolation structure 124 can be formed in the second stacked layer 120 after the first stacked layer 110 and the second stacked layer 120 are formed and before the channel via 130 is formed. In some embodiments, to simplify the process, the channel via 130 and the opening 123 can also be formed simultaneously by a suitable etching process.

[0120] like Figure 16 As shown, in some embodiments, the remainder of the sacrificial layer 112 may be removed via a gate slit, and then a conductor layer 112' may be formed in the space created by removing the remainder of the sacrificial layer 112. In some examples, the material of the conductor layer 112' may be different from the material of the conductive layer 122. For example, the material of the conductor layer 112' may include metals such as W, Co, Cu, Al, Ti, Ta, and Ni, while the conductive layer may include semiconductor materials such as p-type doped polysilicon or metal silicides. In other examples, the material of the conductor layer 112' may be the same as the material of the conductive layer 122, for example, both may include metals.

[0121] In some examples, such as when the material of conductor layer 112' and the material of conductive layer 122 both include metals, when forming opening 123, the second dielectric layer 121 and conductive layer 122 can be etched alternately by selecting different etching gases and controlling the etching time so that the etching can stop in the second dielectric layer 121 that is in contact with the first stacked layer 110.

[0122] In some embodiments, at least one dielectric layer may be formed before the conductor layer 112' is formed to reduce leakage current of word lines and impurity diffusion of the conductor layer 112'. For example, at least one TiN layer and at least one high-k dielectric layer may be formed, and then the conductor layer 112' is formed on the high-k dielectric layer.

[0123] In some implementations, such as Figure 17 As shown, an isolation structure 124 can be formed in the second stacked layer 120 after the conductor layer 112' is formed. Figure 16 ) opening 123.

[0124] In some embodiments, an insulating layer may be filled in the gate slit and a conductive channel may be formed in the space defined by the insulating layer in a suitable step to form a gate slit structure, wherein the insulating layer may be used to electrically isolate the conductive layer 122 and the conductor layer 112' from the conductive channel, and the conductive channel may serve as a lead-out channel for electrical connection of a common source line.

[0125] The manufacturing method provided in this application, since the conductive layer 122 used as the top select gate layer is formed by a direct deposition process, can form the isolation structure 124 in any suitable step in a porous array structure with more than "9 holes", thus avoiding the limitation on the formation process of the isolation structure 124 caused by forming the conductive layer 122 by the gate replacement process.

[0126] Another aspect of this embodiment of the application also provides a three-dimensional memory 100. For example... Figure 16 As shown, the three-dimensional memory 100 includes: a substrate (not shown), a stacked structure 102 formed on the substrate, a plurality of channel structures 139 formed in the stacked structure 102, and an isolation structure 124, wherein the isolation structure 124 may be disposed between adjacent channel structures 139.

[0127] In some examples, the substrate can be made of any suitable semiconductor material, such as single-crystal silicon, polycrystalline silicon, single-crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide and other group III-V compounds.

[0128] like Figure 16 As shown, in some embodiments, the stacked structure 102 includes a first stacked layer 110 and a second stacked layer 120 sequentially formed on a substrate. The first stacked layer 110 includes an alternately stacked first dielectric layer 111 and a conductor layer 112' (also referred to as a "control gate layer"). The second stacked layer 120 includes an alternately stacked second dielectric layer 121 and a conductor layer 122 (also referred to as a "top select gate layer"). The second stacked layer 120 and the first stacked layer 110 have the same stacking orientation.

[0129] In some examples, the first stacked layer 110 may include multiple pairs of first dielectric layer 111 / sacrificial layer 112, the number of which can be selected according to various application scenarios. In some examples, the material of the first dielectric layer 111 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, organosilicon glass (OSG), spin-coated dielectric materials, dielectric metal oxides (e.g., alumina, hafnium oxide, etc.) commonly referred to as high dielectric constant (high k) dielectric oxides and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. As an example, the first dielectric layer 111 may include silicon oxide, and the sacrificial layer 112 may include silicon nitride.

[0130] In some examples, the second stacked layer 120 may include at least one pair of second dielectric layer 121 / conductive layer 122, the number of which may be less than the number of pairs of first dielectric layer 111 / sacrificial layer 112. As an example, the number of pairs of second dielectric layer 121 / conductive layer 122 may be, for example, 1, 2, 4 or more.

[0131] In some examples, the second stacked layer 120 is thinner, with a thickness range, for example, in the nanometer scale.

[0132] In some examples, conductive layer 122 may comprise a semiconductor material, such as polysilicon or metal silicide. Alternatively, conductive layer 122 may comprise, for example, p-type doped (e.g., boron doped) polysilicon such that when conductive layer 122 is used as a top-select gate layer, the threshold voltage of the top-select gate transistor is positive, thereby turning off the controlled channel.

[0133] In some examples, the conductive material of the conductive layer 122 may include metals such as W, Co, Cu, Al, Ti, Ta, and Ni, and the work function of the metal satisfies the following: when the conductive layer 122 is used as a top-select gate layer, the threshold voltage of the top-select gate transistor is positive, thereby turning off the controlled channel.

[0134] In some examples, the material of conductor layer 112' may be different from that of conductor layer 122. For example, the material of conductor layer 112' may include metals such as W, Co, Cu, Al, Ti, Ta, Ni, etc., while conductor layer 122 may include semiconductor materials such as P-type doped polycrystalline silicon, metal silicide, etc.

[0135] In other examples, the material of conductor layer 112' may be the same as that of conductor layer 122, for example, both may include metal.

[0136] In some examples, the material of the second dielectric layer 121 may be the same as that of the first dielectric layer 111.

[0137] In some embodiments, a stepped structure may be formed on both sides or near the middle of the stacked structure 102 (not in...). Figure 16 (as shown), so that the word lines can be drawn out.

[0138] like Figure 16 As shown, in some embodiments, the channel structure 139 includes a plurality of first portions 139-1 formed by a conductive layer 122 surrounding a plurality of second portions 139-2 formed by a second stacked layer 120 and a first dielectric layer 111 surrounding a plurality of first portions 139-1 in the circumferential direction.

[0139] In some examples, between adjacent first dielectric layers 111, each first portion 139-1 includes a first charge-blocking portion 131-1 and a charge-storing portion 132-1. Exemplarily, each first charge-blocking portion 131-1 may cover the inner wall surrounded by the adjacent first dielectric layers 111 and the conductor layer 112' between them. Alternatively, multiple charge-storing portions 132-1 may be intermittently arranged along the stacking direction, wherein each charge-storing portion 132-1 may cover the sidewall of the first charge-blocking portion 131-1.

[0140] During the operation of the three-dimensional memory, multiple discontinuous charge storage sections 132-1 can reduce charge loss caused by the diffusion of stored charge in adjacent memory cells, thereby improving the data retention capability of the three-dimensional memory. Furthermore, the discontinuous charge storage sections 132-1 can mitigate the coupling effect of memory cells due to uneven electric field distribution, thus improving the reliability of the three-dimensional memory.

[0141] In some embodiments, the second portion 139-2 may include a plurality of second charge-blocking portions 131-2 sequentially disposed on the sidewalls of the second stacked layer 120 and the first dielectric layer 111, wherein the first charge-blocking portion 131-1 of the first portion 139-1 and the second charge-blocking portions 131-2 of the second portion 139-2 constitute a continuous barrier layer 131. Exemplarily, the material used for the barrier layer 131 may include silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material such as aluminum oxide or hafnium oxide.

[0142] In some embodiments, the first portion 139-1 and the second portion 139-2 may further include a tunneling layer 133, a channel layer 134, and a dielectric core 135 sequentially disposed on the sidewalls of the charge storage portion 132-1 and the second charge blocking portion 131-2, respectively. The dielectric core 135 may fill the space defined by the channel layer 134, wherein the charge captured by the charge storage portion 132-1 may tunnel through the tunneling layer 133 into the channel layer 134 and be transported in the channel layer 134.

[0143] Exemplary examples show that the material used for the tunneling layer 133 may include silicon oxide, silicon nitride, or silicon oxynitride, and the material used for the channel layer 134 may include one or more semiconductor materials, such as single-element semiconductor materials, III-V compound semiconductor materials, II-VI compound semiconductor materials, and / or organic semiconductor materials. In some embodiments, the channel layer 134 may include a polysilicon layer for facilitating charge transport. In some examples, the dielectric core 135 may include a suitable dielectric material, such as silicon oxide. As an example, the channel structure 139 corresponding to the first stacked layer 110 may include a silicon oxide-silicon nitride-silicon oxide-silicon nitride-polysilicon (ONOP) structure.

[0144] It is understood that the channel structure 139 surrounded by the second stacked layer 110 may not include a storage layer for storing charge. Alternatively, when the barrier layer 131 and the tunneling layer 133 comprise silicon oxide, the barrier layer 131 and the tunneling layer 133 may serve as the gate oxide layer of a MOS transistor.

[0145] For example, a channel plug 136 may also be formed on the top of the channel structure 139 away from the substrate, which can increase the contact area and process window for bit line contact landing.

[0146] Refer again Figure 16 In some embodiments, a plurality of first portions 139-1 of the channel structure 139 surrounded by the conductor layer 112' have a first radial dimension L1, and a second portion 139-2 of the channel structure 139 surrounded by the second stacked layer 120 and the first dielectric layer 111 has a second radial dimension L2, wherein the first radial dimension L1 is greater than the second radial dimension L2. Thus, in the second stacked layer 120, adjacent channel structures 139 have a wall thickness D2, and in the first stacked layer 110, adjacent channel structures 139 have different and alternating wall thicknesses; for example, at the first dielectric layer 111, adjacent channel structures may have a wall thickness D2, while at the conductor layer 112', adjacent channel structures 139 have a wall thickness D1, wherein D2 is greater than D1.

[0147] In some embodiments, the three-dimensional memory 100 further includes a gate slit structure ( Figure 16 (Not shown), which extends through the second stacked layer 120 and the first stacked layer 110. In some examples, the gate slit structure includes an insulating layer filling the gate slit extending through the second stacked layer 120 and the first stacked layer 110, and a conductive channel formed in the space defined by the insulating layer, wherein the insulating layer can be used to electrically isolate the conductive layer 122 and the conductor layer 112' from the conductive channel, respectively, and the conductive channel can serve as a lead-out channel for electrical connection of a common source line.

[0148] In some embodiments, the isolation structure 124 may extend through the conductive layer 122 and be located between adjacent channel structures 139, ending in a second dielectric layer 121 in contact with the first stacked layer 110. As an example, the isolation structure 124 may include an insulating material filling an opening formed through the second stacked layer 120, the filling insulating material including one or more of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and oxynitride (e.g., silicon oxynitride) materials.

[0149] In some examples, the isolation structure 124 may be disposed as a top selected gate tangent in an adjacent second gate slit. Figure 16 (Not shown) to divide the finger-shaped region into multiple sub-regions, which facilitates more precise control over the storage strings of the sub-regions.

[0150] Implementation Method 2

[0151] The memory manufacturing method according to this second embodiment includes operations S210, S220, and S230, such as... Figure 1 As shown. Operations S210, S220, and S230 in this second embodiment are the same as those in the first embodiment described above for forming the first stacked layer 110 and the second stacked layer 120. Figure 2 The processing of the first stack 110 and the second stack 120 forms a channel hole 130. Figure 3 The steps include removing at least a portion of each sacrificial layer 112 in the first stacked layer 110 via the channel via 130, such that a recess 103 is formed between each adjacent first dielectric layer 111 in the first stacked layer 110. Figure 4 The process is the same as that of the other two, so a detailed description of it is omitted.

[0152] Similarly, such as Figure 1 As shown, the method for manufacturing a three-dimensional memory according to this embodiment further includes operation S240 to create a recess 103 ( Figure 4 ) and channel hole 130 ( Figure 19 ) forms a channel structure 139 ( Figures 19-26 In operation S240, multiple discontinuous charge storage portions 142' can be formed in each recess 103. Figure 26 ) and multiple intermittent charge blocking sections 131-3 ( Figure 26 ). Figure 18 A flowchart of step 300, which involves forming a plurality of discontinuous charge storage portions and a plurality of discontinuous charge blocking portions in a recess 103, is shown. Figures 19-26 A schematic diagram of the various stages of forming multiple charge storage portions 142' and charge blocking portions 131-3 is shown.

[0153] Reference Figure 19 For operation S310 in step 300, multiple initial charge storage portions can be formed in each recess. Figure 20 The corresponding structure is shown.

[0154] like Figure 19 As shown, in some embodiments, suitable deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to deposit thin film on the recess 103 ( Figure 4 A continuous storage layer 142 is formed within the second stacked layer 120 and the first dielectric layer 111 along the sidewall of the channel hole 130. A portion of the storage layer 142 along the sidewall of the channel hole 130 can then be removed to form a structure as shown in the image. Figure 20 The diagram shows multiple initial charge storage sections 142-1 that are discontinuous with each other. Exemplarily, storage layer 132 may be filled by recesses 103 (…). Figure 4 (A space that is limited by space.)

[0155] During the operation of the three-dimensional memory, multiple discontinuous initial charge storage sections 142-1 can reduce charge loss caused by the diffusion of stored charge in adjacent memory cells, thereby improving the data retention capability of the memory. Furthermore, the discontinuous initial charge storage sections 142-1 can mitigate the coupling effect of memory cells due to uneven electric field distribution, thus improving the reliability of the three-dimensional memory.

[0156] The initial charge storage section 142-1 is capable of storing charge to perform storage operations, therefore, the film quality requirements for 142-1 are high. In some examples, atomic-level deposition processes, such as atomic layer deposition (ALD), are typically employed to form a storage layer with low roughness and high density.

[0157] like Figure 21 As shown, in some embodiments, after the initial charge storage portion 142-1 is formed, a tunneling layer 133, a channel layer 134, and a dielectric core 135 may be sequentially deposited along the sidewall of the channel hole 130 toward the center of the channel hole 130. The dielectric core 135 may fill the space defined by the channel layer 134, wherein the charge captured by the charge storage portion 132-1 may tunnel through the tunneling layer 133 into the channel layer 134 and be transported in the channel layer 134.

[0158] For example, the tunneling layer 133, the channel layer 134 and the dielectric core 135 can be formed using the same deposition process and materials as in Embodiment 1, which will not be described in detail here.

[0159] like Figure 21 As shown, in some embodiments, the channel hole 130 ( Figure 20A channel plug 136 is formed on the top of the bit line contact away from the substrate. The channel plug 136 can increase the contact area and process window of the bit line contact landing.

[0160] In some embodiments, a gate slit (not shown) parallel to the channel via 130 may be formed in the stacked structure simultaneously with a suitable step, such as when forming the channel via 130, and the gate slit may pass perpendicularly through the stacked structure. It will be readily understood that the gate slit may be formed at any suitable stage of the method of manufacturing the three-dimensional memory without departing from the teachings of the invention.

[0161] Back Figure 18 For operation S320 in step 300, the remainder of the sacrificial layer may be removed to expose the initial charge storage portion on the side opposite to the channel aperture. Figure 22 The corresponding structure is shown.

[0162] like Figure 22 As shown, in some embodiments, the channel slit can be used after filling the channel via 130. Figure 22 (Not shown) Remove the remainder of the sacrificial layer 112, thereby removing the portion away from the channel hole 130 ( Figure 20 The sidewalls of multiple initial memory structures 142-1 are exposed on one side. At the same time, the remaining portions of the top and bottom surfaces of the first dielectric layer 111 may also be exposed, so that adjacent first dielectric layers 111 and the initial memory structures 142-1 between them form a sacrificial space that is perpendicular to and communicates with the gate slit.

[0163] In some embodiments, the sacrificial layer 112 has a higher etch selectivity relative to the initial charge storage portion 142-1 to preserve the initial charge storage portion 142-1 when the remainder of the sacrificial layer 112 is removed. Exemplarily, the process for removing the remainder of the sacrificial layer 112 may include isotropic wet etching, in which the sacrificial layer 112 has a higher etch selectivity than the initial charge storage portion 142-1 under the same wet etching process, so that the initial charge storage portion 142-1 is barely damaged.

[0164] In some embodiments, the sacrificial layer 112 and the initial charge storage portion 142-1 may both include silicon nitride. While ensuring that the nitrogen-silicon ratio of the initial charge storage portion 142-1 can achieve better storage performance, the ratio of nitrogen and silicon in the sacrificial layer 112 can be adjusted to make it significantly different from the nitrogen-silicon ratio of the initial charge storage portion 142-1, thereby enabling selective etching.

[0165] In some examples, the silicon nitride included in the sacrificial layer 112 and the initial charge storage portion 142-1 may also be doped to change the elemental composition, thereby enabling selective etching.

[0166] In some embodiments, an etch stop layer, made of a different material than the initial charge storage portion 142-1 and the sacrificial layer 112, may also be formed between them. Alternatively, the sacrificial layer 112 may have a higher etch selectivity than the etch stop layer, thereby stopping at the etch stop layer when the remaining portion of the sacrificial layer 112 is etched away, reducing the loss of the initial charge storage portion 142-1.

[0167] like Figure 23 As shown, in some examples, to form the aforementioned etch stop layer, an initial etch stop layer 152' can be first formed in the recess 103 and the via 130. Then, the portion of the initial etch stop layer 152' located on the sidewall of the via 130 is removed, and a portion of the initial etch stop layer 152' is removed in the recess, while the portion of the initial etch stop layer 152' located on the inner wall of the sacrificial layer 112 is retained, thereby forming the etch stop layer 152'. Figure 24 The etching stop layer 152 is shown.

[0168] like Figure 25 As shown, in some examples, after the etch stop layer 152 is formed, an initial charge storage portion 142-1 covering the sidewalls of the etch stop layer 152 can be formed in the recessed remaining space, and multiple initial charge storage portions 142-1 are intermittently arranged along the stacking direction.

[0169] Back Figure 18 Step 300 continues to operation S330, where at least a portion of the exposed initial charge storage portion can be oxidized into a discontinuous charge-blocking portion. Figure 26 The corresponding structure is shown.

[0170] In some implementations, for example, Figure 22 In the example shown, after the sacrificial space is formed, a portion of the opposite channel aperture of the plurality of initial charge storage portions 142-1 can be oxidized into a plurality of charge blocking portions 131-3, thereby forming as shown in the example. Figure 26 The channel structure 139 shown includes a portion where the remainder of the initial charge storage portion 142-1 can serve as the final charge storage portion 142'. Exemplarily, this can be achieved via a gate slit ( Figure 26 (Not shown), a portion of the initial charge storage portions 142-1 (e.g., silicon nitride) away from the channel via is oxidized into multiple charge blocking portions 131-3 (e.g., silicon oxide or silicon oxynitride) through thermal oxidation and / or chemical oxidation processes, forming discontinuous charge storage portions 142'. For example, thermal oxidation may include an in-situ steam method that uses oxygen and hydrogen to generate water in the form of steam. Alternatively, the channel structure 139 may include a silicon-oxide-nitride-oxide (SONO) structure.

[0171] In some implementations, for example, Figure 25 In the example shown, which includes an etch stop layer 152, a suitable etching process can be used to sequentially remove the remainder of the sacrificial layer 112 and the etch stop layer 152, thereby exposing the side facing away from the via 130 as... Figure 22 The sidewalls of the multiple initial storage structures 142-1 shown.

[0172] like Figure 26 As shown, due to the removal of the sacrificial layer 112 of the first stacking layer 110 ( Figure 4 As part of the first dielectric layer 111, a recess 103 is formed between adjacent first dielectric layers 111. Figure 4 ), and no similar operation was performed on the second stacked layer 120, therefore in the recess 103 ( Figure 4 ) and channel hole 130 ( Figure 4 After the channel structure 139 is formed in the first stacked layer 110 and the second stacked layer 120, the channel structure 139 may have alternating and different radial dimensions. (See again...) Figure 26 In some examples, the channel structure 139 may have alternating first radial dimension L1 and second radial dimension L2, wherein L1 is greater than L2.

[0173] It is understood that the channel structure 139 surrounded by the second stacked layer 110 may not include a storage layer for storing charge. Alternatively, when the charge blocking portions 131-3 and the tunneling layer 133 comprise silicon oxide, the plurality of charge blocking portions 131-3 and the tunneling layer 133 may serve as the gate oxide layer of a MOS transistor.

[0174] like Figure 27 As shown, in some embodiments, a conductor layer 112' may be formed in the sacrificial space via a gate slit. In some examples, the material of the conductor layer 112' may be different from the material of the conductive layer 122. For example, the material of the conductor layer 112' may include metals such as W, Co, Cu, Al, Ti, Ta, and Ni, while the conductive layer may include semiconductor materials such as p-type doped polysilicon or metal silicides. In other examples, the material of the conductor layer 112' may be the same as the material of the conductive layer 122, for example, both may include metals.

[0175] The charge blocking portion 131-3 formed in this embodiment does not occupy the space of the conductor layer 112' along the stacking direction. At the same stacking height, more layers of the first dielectric layer 111 and conductor layer 112' can be stacked, thereby increasing the storage capacity. Moreover, the charge blocking portion 131-3 formed by oxidizing the initial charge storage portion 142-1 has better film density and uniformity, which can effectively reduce charge leakage.

[0176] In some embodiments, at least one dielectric layer may be formed before the conductor layer 112' is formed to reduce leakage current of word lines and impurity diffusion of the conductor layer 112'. For example, at least one TiN layer and at least one high-k dielectric layer may be formed, and then the conductor layer 112' is formed on the high-k dielectric layer.

[0177] In some embodiments, an insulating layer may be filled in the gate slit and a conductive channel may be formed in the space defined by the insulating layer in a suitable step to form a gate slit structure, wherein the insulating layer may be used to electrically isolate the conductive layer 122 and the conductor layer 112' from the conductive channel, and the conductive channel may serve as a lead-out channel for electrical connection of a common source line.

[0178] The method for manufacturing a three-dimensional memory according to this embodiment includes operation S250, similarly, as... Figure 1 As shown, an isolation structure 124 can be formed in the second stacked layer 120, wherein the isolation structure 124 can penetrate the conductive layer 122 and is located between adjacent channel structures 139. Figure 29 The corresponding structure is shown.

[0179] like Figure 28 As shown, in some embodiments, after the conductor layer 112' is formed, the opening 123 may be formed in the second stacked layer 120 by a dry etching process such as anisotropic etching.

[0180] In some examples, because the second stacked layer 120 is thin, for example in the nanometer range, it is relatively easy to form an opening 123 by etching the second stacked layer 120, wherein the opening 123 can pass through the second stacked layer 120 and stop in the second dielectric layer 121 in contact with the first stacked layer 110.

[0181] As previously mentioned, at the sacrificial layer 112 of the first stacked layer 110, the wall thickness of the adjacent channel structure 139 is thinned to D2. In the second stacked layer 120, the wall thickness D2 of the adjacent channel structure 139 is almost entirely preserved. When an opening 123 is formed through the second stacked layer 120 with a wall thickness of D1, its process window is hardly reduced. Under certain process conditions, it is not necessary to increase the process window of the isolation structure 124, which can reduce the occurrence of channel structures 139 occupying a portion of the space, adding an extra row of dummy channel structures, or increasing the wall thickness between adjacent channel structures 139. Therefore, to a certain extent, the loss of storage density can be reduced.

[0182] In some examples, insulating material can be filled into the opening 123 to form a shape such as Figure 29The isolation structure 124 is shown. The filling insulating material includes one or more of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and oxynitride (e.g., silicon oxynitride) materials. Alternatively, the top surface of the isolation structure 124 may be planarized using chemical mechanical polishing. In some examples, the isolation structure 124 may be disposed as a top select gate tangent between adjacent second gate slits to divide the finger region into multiple sub-regions, facilitating more precise control over the memory strings of the sub-regions.

[0183] In some examples, such as when the material of the conductor layer 112' and the material of the conductive layer 122 both include metals, the second dielectric layer 121 and the conductive layer 122 can be etched alternately by selecting different etching gases and controlling the etching time so that the etching can stop in the second dielectric layer 121 that is in contact with the first stacked layer 110.

[0184] In some embodiments, the isolation structure 124 may be formed in the second stacked layer 120 after the first stacked layer 110 and the second stacked layer 120 are formed and before the via 130 is formed. In some embodiments, to simplify the process, the via 130 and the top selected gate opening 123 may be formed simultaneously by a suitable etching process.

[0185] In some embodiments, an isolation structure 124 may also be formed in the second stacked layer 120 after the channel structure 139 has been formed.

[0186] The manufacturing method provided in this application, since the conductive layer 122 used as the top select gate layer is formed by a direct deposition process, can form the isolation structure 124 in any suitable step in a porous array structure with more than "9 holes", thus avoiding the limitation on the formation process of the isolation structure 124 caused by forming the conductive layer 122 by the gate replacement process.

[0187] Another aspect of the embodiments of this application provides a three-dimensional memory 100'. Figure 29 A partial schematic structure of the three-dimensional memory 100' is shown, as follows: Figure 29 As shown, the three-dimensional memory 100 includes: a substrate (not shown), a stacked structure 102 formed on the substrate, a plurality of channel structures 139 formed in the stacked structure 102, and an isolation structure 124, wherein the isolation structure 124 may be disposed between adjacent channel structures 139.

[0188] In some examples, the substrate can be made of any suitable semiconductor material, such as single-crystal silicon, polycrystalline silicon, single-crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide and other group III-V compounds.

[0189] like Figure 29 As shown, in some embodiments, the stacked structure 102 includes a first stacked layer 110 and a second stacked layer 120 sequentially formed on a substrate. The first stacked layer 110 includes an alternately stacked first dielectric layer 111 and a conductor layer 112' (also referred to as a "control gate layer"). The second stacked layer 120 includes an alternately stacked second dielectric layer 121 and a conductor layer 122 (also referred to as a "top select gate layer"). The second stacked layer 120 and the first stacked layer 110 have the same stacking orientation.

[0190] In some examples, the first stacked layer 110 may include multiple pairs of first dielectric layer 111 / sacrificial layer 112, the number of which can be selected according to various application scenarios. In some examples, the material of the first dielectric layer 111 includes silicon oxide, silicon nitride, silicon oxynitride, organosilicon glass (OSG), spin-coated dielectric materials, dielectric metal oxides (e.g., alumina, hafnium oxide, etc.) commonly referred to as high dielectric constant (high k) dielectric oxides and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. As an example, the first dielectric layer 111 may include silicon oxide, and the sacrificial layer 112 may include silicon nitride.

[0191] In some examples, the second stacked layer 120 may include at least one pair of second dielectric layer 121 / conductive layer 122, the number of which may be less than the number of pairs of first dielectric layer 111 / sacrificial layer 112. As an example, the number of pairs of second dielectric layer 121 / conductive layer 122 may be, for example, 1, 2, 4 or more.

[0192] In some examples, the second stacked layer 120 is thinner, with a thickness range, for example, in the nanometer scale.

[0193] In some examples, conductive layer 122 may comprise a semiconductor material, such as polysilicon or metal silicide. Alternatively, conductive layer 122 may comprise p-type doped (e.g., boron doped) polysilicon such that when conductive layer 122 is used as a top-select gate layer, the threshold voltage of the top-select gate transistor is positive, thereby turning off the controlled channel.

[0194] In some examples, the conductive material of the conductive layer 122 may include metals such as W, Co, Cu, Al, Ti, Ta, and Ni, and the work function of the metal satisfies the following: when the conductive layer 122 is used as a top-select gate layer, the threshold voltage of the top-select gate transistor is positive, thereby turning off the controlled channel.

[0195] In some examples, the material of conductor layer 112' may be different from that of conductor layer 122. For example, the material of conductor layer 112' may include metals such as W, Co, Cu, Al, Ti, Ta, Ni, etc., and the conductor layer may include semiconductor materials such as P-type doped polycrystalline silicon, metal silicide, etc.

[0196] In other examples, the material of conductor layer 112' may be the same as that of conductor layer 122, for example, both may include metal.

[0197] In some examples, the material of the second dielectric layer 121 may be the same as that of the first dielectric layer 111.

[0198] In some embodiments, a stepped structure may be formed on both sides or near the middle of the stacked structure 102 (not in...). Figure 29 (as shown in the image) so that the word lines can be drawn out.

[0199] like Figure 29 As shown, in some embodiments, the channel structure 139 includes a plurality of first portions 139-1 formed by a conductive layer 122 surrounding a plurality of second portions 139-2 formed by a second stacked layer 120 and a first dielectric layer 111 surrounding a plurality of first portions 139-1 in the circumferential direction.

[0200] In some examples, between adjacent first dielectric layers 111, each first portion 139-1 includes a plurality of charge-blocking portions 131-3 and a plurality of charge-storing portions 142', wherein each first charge-blocking portion 131-1 may cover the sidewall of the conductor layer 112'. Alternatively, the plurality of charge-storing portions 142' may be intermittently arranged along the stacking direction, wherein each charge-storing portion 142' may cover the sidewall of the charge-blocking portion 131-3. Exemplarily, the material for the charge-blocking portion 131-3 may include silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material such as aluminum oxide or hafnium oxide.

[0201] During the operation of the three-dimensional memory, multiple discontinuous charge storage sections 142' can reduce charge loss caused by the diffusion of stored charge in adjacent memory cells, thereby improving the data retention capability of the three-dimensional memory. Furthermore, the discontinuous charge storage sections 142' can mitigate the coupling effect of memory cells due to uneven electric field distribution, thus improving the reliability of the three-dimensional memory.

[0202] In some embodiments, the first portion 139-1 and the second portion 139-2 may further include a tunneling layer 133, a channel layer 134, and a dielectric core 135 sequentially disposed on the sidewall of the charge storage portion 142', the sidewall of the second stacked layer 120, and the sidewall of the first dielectric layer 111, respectively. The dielectric core 135 may fill the space defined by the channel layer 134, wherein the charge captured by the charge storage portion 142' may tunnel through the tunneling layer 133 into the channel layer 134 and be transported in the channel layer 134.

[0203] In some examples, each charge blocking portion 131-3 and the corresponding charge storage portion 142' and conductor layer 112' may have the same size along the stacking direction. Therefore, the charge blocking portion 131-3 formed in the embodiments of this application may not occupy the space of conductor layer 112' along the stacking direction. At the same stacking height, more layers of first dielectric layer 111 and conductor layer 112' can be stacked, thereby increasing the storage capacity.

[0204] For example, the material used for the charge blocking portion 131-3 may include silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material such as aluminum oxide or hafnium oxide.

[0205] Exemplary examples show that the material used for the tunneling layer 133 may include silicon oxide, silicon nitride, or silicon oxynitride, and the material used for the channel layer 134 may include one or more semiconductor materials, such as single-element semiconductor materials, III-V compound semiconductor materials, II-VI compound semiconductor materials, and / or organic semiconductor materials. In some embodiments, the channel layer 134 may include a polysilicon layer for facilitating charge transport. In some examples, the dielectric core 135 may include a suitable dielectric material, such as silicon oxide. As an example, the channel structure 139 corresponding to the first stacked layer 110 may include a silicon oxide-silicon nitride-silicon oxide-silicon nitride-polysilicon (ONOP) structure.

[0206] It is understood that the channel structure 139 surrounded by the second stacked layer 110 may not include a storage layer for storing charge. Alternatively, when the barrier layer 131 and the tunneling layer 133 comprise silicon oxide, the barrier layer 131 and the tunneling layer 133 may serve as the gate oxide layer of a MOS transistor.

[0207] For example, a channel plug 136 may also be formed on the top of the channel structure 139 away from the substrate, which can increase the contact area and process window for bit line contact landing.

[0208] like Figure 29As shown, in some embodiments, a first portion 139-1 of the channel structure 139 surrounded by the conductor layer 112' has a first radial dimension L1, and a second portion 139-2 surrounded by the second stacked layer 120 and the first dielectric layer 111 has a second radial dimension L2, wherein the first radial dimension L1 is greater than the second radial dimension L2. Thus, in the second stacked layer 120, adjacent channel structures 139 have a wall thickness D2, and in the first stacked layer 110, adjacent channel structures 139 have different and alternating wall thicknesses. At the first dielectric layer 111, adjacent channel structures may have a wall thickness D2, while at the conductor layer 112', adjacent channel structures 139 have a wall thickness D1, wherein D2 is greater than D1.

[0209] In some embodiments, the three-dimensional memory 100' further includes a gate slit structure ( Figure 28 (Not shown), it extends through the second stacked layer 120 and the first stacked layer 110 to divide the stacked structure 102 into a plurality of finger-like regions. In some examples, the gate slit structure includes an insulating layer filling the gate slit extending through the second stacked layer 120 and the first stacked layer 110, and a conductive channel formed in the space defined by the insulating layer, wherein the insulating layer can be used to electrically isolate the conductive layer 122 and the conductor layer 112' from the conductive channel, respectively, and the conductive channel can serve as a lead-out channel for a common source line electrical connection.

[0210] In some embodiments, the isolation structure 124 may extend through the conductive layer 122 and be located between adjacent channel structures 139, ending in a second dielectric layer 121 in contact with the first stacked layer 110. As an example, the isolation structure 124 may include an insulating material filling an opening formed through the second stacked layer 120, the filling insulating material including one or more of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and oxynitride (e.g., silicon oxynitride) materials.

[0211] In some examples, the isolation structure 124 can be disposed as a top select gate tangent between adjacent second gate slits to divide the finger region into multiple sub-regions, facilitating more precise control over the memory strings of the sub-regions.

[0212] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above are merely specific embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A three-dimensional memory, characterized in that, include: A stacked structure, the stacked structure including a first stacked layer and a second stacked layer, wherein the first stacked layer includes an alternately stacked control gate layer and a first dielectric layer, and the second stacked layer includes an alternately stacked top select gate layer and a second dielectric layer; Multiple channel structures, each channel structure penetrating the stacked structure and including a charge-trapping type charge storage layer, wherein the charge storage layer includes multiple charge storage portions discontinuously disposed along the stacking direction of the stacked structure, the charge storage portions being located between adjacent first dielectric layers; and At least one isolation structure extends through the top selected gate layer and is located between adjacent channel structures, the isolation structure being spaced apart from the channel structures; The channel structure includes: a plurality of first portions surrounded by the control gate layer and a plurality of second portions surrounded by the second stacked layer and the first dielectric layer, wherein a first radial dimension of the first portions is larger than the second radial dimension of the second portions as a whole.

2. The three-dimensional memory according to claim 1, characterized in that, The top select gate layer and the control gate layer are made of different materials.

3. The three-dimensional memory according to claim 1, characterized in that, The top selected gate layer comprises a semiconductor material.

4. The three-dimensional memory according to claim 3, characterized in that, The semiconductor material includes polycrystalline silicon or metal nitride.

5. The three-dimensional memory according to claim 3, characterized in that, The semiconductor material includes boron-doped polycrystalline silicon.

6. The three-dimensional memory according to claim 1, characterized in that, The control gate layer comprises metal.

7. The three-dimensional memory according to claim 6, characterized in that, The metal includes tungsten.

8. The three-dimensional memory according to claim 1, characterized in that, Each of the first portions includes a first charge blocking portion and a charge storage portion, wherein, between adjacent first dielectric layers, the charge storage portion covers the sidewall of the first charge blocking portion.

9. The three-dimensional memory according to claim 8, characterized in that, The first part also includes a tunneling layer, a channel layer and a dielectric core sequentially disposed on the sidewall of the charge storage part.

10. The three-dimensional memory according to claim 9, characterized in that, The first charge blocking portion covers the inner wall surrounded by the adjacent first dielectric layer and the control gate layer between them.

11. The three-dimensional memory according to claim 10, characterized in that, The second part includes a plurality of second charge blocking portions disposed on the sidewalls of the second stacked layer and the first dielectric layer, wherein the tunneling layer, the channel layer and the dielectric core are sequentially disposed on the second charge blocking portions, and the first charge blocking portions and the second charge blocking portions form a continuous blocking layer.

12. The three-dimensional memory according to claim 1, characterized in that, The first part includes a charge blocking portion and a charge storage portion, wherein the charge blocking portion covers the sidewall of the control gate layer.

13. The three-dimensional memory according to claim 12, characterized in that, The trench structure further includes a tunneling layer, a trench layer, and a dielectric core; the tunneling layer, the trench layer, and the dielectric core are sequentially disposed on the sidewalls of the second stacked layer and the first dielectric layer.

14. The three-dimensional memory according to claim 12, characterized in that, In the stacking direction, the charge blocking portion and the charge storage portion have the same dimensions.

15. The three-dimensional memory according to claim 12 or 14, characterized in that, In the stacking direction, the charge blocking portion and the control gate layer have the same dimensions.

16. The three-dimensional memory according to any one of claims 8-11, characterized in that, The first charge-blocking portion comprises silicon oxynitride or silicon oxide, and the charge-storing portion comprises silicon nitride.

17. A three-dimensional memory, characterized in that, include: A stacked structure, the stacked structure including a first stacked layer and a second stacked layer, wherein the first stacked layer includes an alternately stacked first dielectric layer and a control gate layer, the second stacked layer includes an alternately stacked second dielectric layer and a top selected gate layer, wherein the control gate layer includes a metal, and the top selected gate layer includes a semiconductor material; Multiple channel structures, each channel structure penetrating the stacked structure and including a charge-trapping type charge storage layer, wherein the charge storage layer includes multiple charge storage portions discontinuously disposed along the stacking direction of the stacked structure, the charge storage portions being located between adjacent first dielectric layers; and At least one isolation structure extends through the top selected gate layer and is located between adjacent channel structures, the isolation structure being spaced apart from the channel structures; The channel structure includes: a plurality of first portions surrounded by the control gate layer and a plurality of second portions surrounded by the second stacked layer and the first dielectric layer, wherein a first radial dimension of the first portions is larger than the second radial dimension of the second portions as a whole.

18. The three-dimensional memory according to claim 17, characterized in that, The semiconductor material includes polycrystalline silicon or metal nitride.

19. The three-dimensional memory according to claim 18, characterized in that, The semiconductor material includes boron-doped polycrystalline silicon.

20. The three-dimensional memory according to claim 19, characterized in that, The control gate layer comprises tungsten.

21. The three-dimensional memory according to claim 17, characterized in that, Each of the first portions includes a first charge blocking portion and a charge storage portion, wherein, between adjacent first dielectric layers, the charge storage portion covers the sidewall of the first charge blocking portion.

22. The three-dimensional memory according to claim 21, characterized in that, The first part also includes a tunneling layer, a channel layer and a dielectric core sequentially disposed on the sidewall of the charge storage part.

23. The three-dimensional memory according to claim 22, characterized in that, The first charge blocking portion covers the inner wall surrounded by the adjacent first dielectric layer and the control gate layer between them.

24. The three-dimensional memory according to claim 23, characterized in that, The second part includes a plurality of second charge blocking portions disposed on the sidewalls of the second stacked layer and the first dielectric layer, wherein the tunneling layer, the channel layer and the dielectric core are sequentially disposed on the second charge blocking portions, and the first charge blocking portions and the second charge blocking portions form a continuous blocking layer.

25. The three-dimensional memory according to claim 17, characterized in that, The first part includes a charge blocking portion and a charge storage portion, wherein the charge blocking portion covers the sidewall of the control gate layer.

26. The three-dimensional memory according to claim 25, characterized in that, The trench structure further includes a tunneling layer, a trench layer, and a dielectric core; the tunneling layer, the trench layer, and the dielectric core are sequentially disposed on the sidewalls of the second stacked layer and the first dielectric layer.

27. The three-dimensional memory according to claim 25, characterized in that, In the stacking direction, the charge blocking portion and the charge storage portion have the same dimensions.

28. The three-dimensional memory according to claim 25 or 27, characterized in that, In the stacking direction, the charge blocking portion and the control gate layer have the same dimensions.

29. The three-dimensional memory according to any one of claims 21-24, characterized in that, The first charge-blocking portion comprises silicon oxynitride or silicon oxide, and the charge-storing portion comprises silicon nitride.

30. A method for manufacturing a three-dimensional memory, comprising: A first stacked layer consisting of alternating first dielectric layers and sacrificial layers, and a second stacked layer consisting of alternating second dielectric layers and conductive layers are sequentially formed; A channel hole is formed through the first stack and the second stack layer; At least a portion of each of the sacrificial layers is removed in the first stacked layer via the channel holes, such that a recess is formed between adjacent first dielectric layers in the first stacked layer; A channel structure is formed in the recess and the channel hole; as well as An isolation structure is formed in the second stacked layer, wherein the isolation structure extends through the conductive layer and is located between adjacent channel structures.

31. The manufacturing method according to claim 30, characterized in that, The method further includes: A gate slit is formed that extends through the first stacked layer and the second stacked layer; The remaining portion of the sacrificial layer is removed via the gate slit; and A conductor layer is formed in the sacrificial space created by removing the remaining portion.

32. The manufacturing method according to claim 30, characterized in that, The isolation structure is formed before the channel holes are formed.

33. The manufacturing method according to claim 30, characterized in that, After the channel structure is formed, the isolation structure is formed.

34. The manufacturing method according to claim 31, characterized in that, After the conductor layer is formed, the isolation structure is formed.

35. The manufacturing method according to claim 30, characterized in that, Forming the isolation structure includes: An opening is formed through the second stacked layer, the opening being located between adjacent channel structures; and The opening is filled with insulating material.

36. The manufacturing method according to any one of claims 30-35, characterized in that, The formation of the channel structure includes: A continuous barrier layer is formed along the sidewall of the channel hole on the inner wall of the recess, the second stacked layer, and the first dielectric layer; and A charge storage portion is formed in each of the depressions.

37. The manufacturing method according to claim 36, characterized in that, The formation of the channel structure also includes: A tunneling layer, a channel layer, and a dielectric core are sequentially formed on the portion of the barrier layer along the sidewall of the channel hole and on the charge storage portion.

38. The manufacturing method according to any one of claims 30-35, characterized in that, The formation of the channel structure includes: Multiple intermittent charge storage portions and multiple intermittent charge blocking portions are formed in the depression.

39. The manufacturing method according to claim 38, characterized in that, The formation of multiple intermittent charge storage portions and multiple intermittent charge blocking portions in each of the recesses includes: Multiple initial charge storage portions are formed in each of the aforementioned recesses; Remove the remainder of the sacrificial layer to expose the initial charge storage portion on the side opposite to the channel aperture; and At least a portion of the exposed initial charge storage portion is oxidized into the charge blocking portion.

40. The manufacturing method according to claim 39, characterized in that, Before forming the intermittent charge storage portion, the method further includes: An etching stop layer is formed in each of the recesses, located on the sidewall of the sacrificial layer.

41. The manufacturing method according to claim 40, characterized in that, The removal of the remaining portion of the sacrificial layer includes: Etch the remaining portion of the sacrificial layer and stop at the etch stop layer; and Remove the etching stop layer.

42. The manufacturing method according to claim 39, characterized in that, The formation of the channel structure also includes: A tunneling layer, a channel layer, and a dielectric core are sequentially disposed on the sidewall of the second stacked layer, the charge storage portion, and the sidewall of the first dielectric layer.

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