Graph processing apparatus and method

Abstract

The application discloses a graph processing device and method, relates to the field of data processing, and improves the throughput of data processing. The graph processing device comprises at least one core, a topology-aware traversal path regularization (TATR) circuit and a prefetch index (PI) circuit. The TATR circuit is used for obtaining a common traversal path according to a vertex accessed by the at least one core in a graph structure, and the common traversal path is used for indicating the sequence in which the vertex is accessed by the at least one core. The PI circuit is used for sending information of the vertex to the at least one core according to the sequence indicated by the common traversal path.

Description

Technical Field

[0001] This application relates to the field of data processing, and more particularly to a graph processing apparatus and method. Background Technology

[0002] A graph is a data structure consisting of vertices and edges, and is uniformly described as a graph structure in this application. In data centers, there are typically a large number of concurrent iterative graph processing tasks (referred to as concurrent graph processing tasks in this application) analyzing the same graph structure. The inherent irregular access characteristics of concurrent graph processing tasks lead to underutilization of system memory, resulting in low data processing throughput. Summary of the Invention

[0003] This application provides a graph processing apparatus and method for improving data processing throughput.

[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0005] In a first aspect, a graph processing apparatus is provided, comprising: at least one kernel, a topology-aware traversal path regularization (TATR) circuit, and a prefetch indexing (PI) circuit; the TATR circuit is used to obtain a common traversal path based on vertices in the graph structure accessed by at least one kernel, the common traversal path being used to indicate the order in which vertices are accessed by at least one kernel; the PI circuit is used to send vertex information to at least one kernel according to the order indicated by the common traversal path.

[0006] The graph processing apparatus and method provided in this application provide a common traversal path to at least one kernel, instructing these kernels to access vertices in the graph structure in the same order. This enables at least one kernel to access vertices in a regular manner, avoiding irregular access to vertices by at least one kernel, thereby improving data processing throughput and also improving memory bandwidth utilization and cache capacity utilization.

[0007] In one possible implementation, the TATR circuit is specifically used to: first add the first source vertex that has not yet been added to the common traversal path to the common traversal path, and then add the first neighbor vertex of the first source vertex that has not yet been added to the common traversal path to the common traversal path. Here, the first source vertex and the first neighbor vertex are two vertices of an edge in the graph structure, and both the first source vertex and the first neighbor vertex are vertices in the graph structure that are visited by at least one kernel. For directed graphs, the kernel visits the source vertex first and then the neighbor vertex, so generating the common traversal path in this order means that the kernel does not need to jump back to the source vertex after visiting the neighbor vertex, thus improving the efficiency of the kernel in processing the graph structure.

[0008] In one possible implementation, for each kernel, the PI circuit is specifically used to: obtain the unsent second source vertex in the order of the common traversal path; obtain the unsent second neighbor vertices of the second source vertex; and send the information of the second source vertex and the information of the second neighbor vertices to each kernel. Here, the second source vertex and the second neighbor vertex are two vertices of an edge in the graph structure, and both the second source vertex and the second neighbor vertex are vertices visited by each kernel in the graph structure. For directed graphs, the kernel visits the source vertex first and then the neighbor vertices, so sending vertex information to the kernel in this order eliminates the need for the kernel to jump back to the source vertex after visiting the neighbor vertices, thus improving the efficiency of the kernel in processing the graph structure.

[0009] In one possible implementation, at least one kernel runs multiple graph processing tasks; at least one kernel is also used to merge and store the states of the same vertex from different graph processing tasks. Typically, the amount of data for the state of a single vertex is not large, and the inherent irregular access characteristics of concurrent graph processing tasks can lead to wasted memory bandwidth and cache capacity. Therefore, merging and storing the states of the same vertex from different graph processing tasks can improve memory bandwidth utilization and cache capacity utilization.

[0010] In one possible implementation, at least one kernel is specifically used to merge and store the states of the same vertex from different graph processing tasks according to the size of the cache line. Since the granularity of data prefetching is the cache line, it facilitates direct data prefetching.

[0011] In one possible implementation, vertices with more than a threshold number of neighboring vertices are considered. Vertices with high activity levels are more likely to be accessed by at least one kernel; merging and storing these vertices maximizes storage space and avoids increasing the complexity of data processing.

[0012] In one possible implementation, the graph processing apparatus further includes a buffer; the TATR circuit is further configured to divide the common traversal path into blocks according to the size of the buffer lines; and the PI circuit is further configured to store vertex information into the buffer according to the blocks. This facilitates the storage of vertex information into the buffer through data prefetching.

[0013] In one possible implementation, the graph processing device is at least one of a system-on-a-chip, a general-purpose processor, a special-purpose processor, an application-specific integrated circuit, a programmable logic device, a standalone system, a distributed system, or a cloud computing platform. This application does not limit the specific application scenario.

[0014] Secondly, a graph processing method is provided, comprising: obtaining a common traversal path based on vertices in a graph structure that are accessed by at least one kernel, wherein the common traversal path is used to indicate the order in which vertices are accessed by at least one kernel; and sending vertex information to at least one kernel according to the order indicated by the common traversal path.

[0015] In one possible implementation, a common traversal path is obtained based on the vertices in the graph structure that are accessed by at least one kernel. This includes: first adding the first source vertex that has not been added to the common traversal path to the common traversal path, and then adding the first neighbor vertex of the first source vertex that has not been added to the common traversal path to the common traversal path. Here, the first source vertex and the first neighbor vertex are two vertices of an edge in the graph structure, and both the first source vertex and the first neighbor vertex belong to the vertices in the graph structure that are accessed by at least one kernel.

[0016] In one possible implementation, for each kernel, vertex information is sent to at least one kernel in the order indicated by the common traversal path, including: obtaining the unsent second source vertex in the order of the common traversal path; obtaining the unsent second neighbor vertex of the second source vertex; sending the information of the second source vertex and the information of the second neighbor vertex to each kernel; wherein the second source vertex and the second neighbor vertex are two vertices of an edge in the graph structure, and both the second source vertex and the second neighbor vertex belong to the vertices in the graph structure that are visited by each kernel.

[0017] In one possible implementation, at least one kernel runs multiple graph processing tasks; the method further includes merging and storing the states of the same vertex from different graph processing tasks.

[0018] In one possible implementation, merging and storing the state of the same vertex from different graph processing tasks includes: merging and storing the state of the same vertex from different graph processing tasks according to the size of the buffer line.

[0019] In one possible implementation, the number of vertices whose neighboring vertices are the same vertex is greater than a threshold.

[0020] In one possible implementation, the method further includes: dividing the common traversal path into blocks according to the size of the cache line; and storing vertex information into a cache according to the blocks.

[0021] Thirdly, a computer-readable storage medium is provided, which stores instructions that, when executed on a graph processing apparatus, cause the graph processing apparatus to perform the method as described in the second aspect and any embodiment thereof.

[0022] Fourthly, a computer program product comprising instructions is provided, which, when executed on a graph processing apparatus, cause the graph processing apparatus to perform the method as described in the second aspect and any embodiment thereof.

[0023] The technical effects of the second to fourth aspects are the same as those of the first aspect and any of its embodiments. Attached Figure Description

[0024] Figure 1 A schematic diagram of a directed graph, adjacency matrix, and compressed sparse row (CSR) matrix provided for embodiments of this application;

[0025] Figure 2 This is a schematic diagram of the structure of an image processing device provided in an embodiment of this application;

[0026] Figure 3 A schematic flowchart of an image processing method provided in an embodiment of this application;

[0027] Figure 4 This is a schematic diagram of a data structure involved in a graph processing apparatus provided in an embodiment of this application;

[0028] Figure 5 A schematic flowchart illustrating another graph processing method provided in an embodiment of this application;

[0029] Figure 6 A schematic diagram of the structure of a topology-aware traversal regularization (TATR) circuit provided in an embodiment of this application;

[0030] Figure 7 A schematic flowchart illustrating another graph processing method provided in an embodiment of this application;

[0031] Figure 8 A schematic diagram illustrating a prefetching and indexing (PI) circuit sending information to the kernel, provided in an embodiment of this application;

[0032] Figure 9 This is a schematic diagram illustrating the merging and storage of the states of the same vertex from different graph processing tasks, as provided in an embodiment of this application.

[0033] Figure 10 A schematic flowchart illustrating another image processing method provided in an embodiment of this application;

[0034] Figure 11 This is a schematic diagram illustrating how to access the state of merged vertices, as provided in an embodiment of this application. Detailed Implementation

[0035] It should be noted that the terms "first" and "second" used in the embodiments of this application are only used to distinguish features of the same type and should not be construed as indicating relative importance, quantity, order, etc.

[0036] The terms "exemplary" or "for example" used in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0037] The terms "coupling" and "connection" used in the embodiments of this application should be interpreted broadly. For example, they can refer to a physical direct connection or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0038] First, let me describe some of the concepts involved in this application:

[0039] A graph is a data structure consisting of vertices and edges, uniformly described as a graph structure in this application. Graphs can include directed graphs and undirected graphs. In a directed graph, a source vertex is connected to a target vertex via a directed edge; the target vertex is a neighboring vertex of the source vertex. That is, the source vertex refers to the starting vertex of an edge in the graph structure, and the target vertex refers to the ending vertex of the edge. In an undirected graph, two vertices connected by an edge are neighbors; one of these vertices is the source vertex, and the other is the target vertex. Each vertex and edge can have a state. The state of a vertex and the state of an edge connected to that vertex can be used to update the state of the neighboring vertices at the other end of that edge. Vertices accessed by graph processing tasks running in the kernel are called active vertices, and vertices not accessed by such tasks are called inactive vertices. Each vertex can be represented by a vertex identifier (ID). The identifiers of the vertices in the graph structure are ordered by natural numbers (e.g., starting from 0). Therefore, by knowing the identifier of the first and last vertex, it is possible to traverse all vertices in the graph structure. For example, Figure 1 Figure A shows a directed graph, where the edge from vertex 0 to vertex 1 is A, the edge from vertex 0 to vertex 3 is B, the edge from vertex 1 to vertex 2 is C, the edge from vertex 1 to vertex 3 is D, the edge from vertex 2 to vertex 0 is E, and the edge from vertex 3 to vertex 2 is F.

[0040] Information about vertices in a graph can be stored as an array of structures. Information about edges can be stored as an adjacency matrix, where rows and columns are indexed by vertex identifiers, and 0 (invalid value) represents no edge between two vertices. The adjacency matrix for an undirected graph is a symmetric matrix, while the adjacency matrix for a directed graph can be either symmetric or asymmetric. For example... Figure 1 Figure B shows the adjacency matrix form of the edges of a directed graph. Each row of the adjacency matrix corresponds to the identifier of the source vertex, and each column of the adjacency matrix corresponds to the identifier of the target vertex.

[0041] As can be seen from the adjacency matrix above, it contains a large number of 0s (invalid values), which consumes a significant amount of storage space. Therefore, the storage space of the adjacency matrix can be compressed using a compressed sparse row (CSR) matrix. A CSR matrix is ​​a way to represent non-zero items in a two-dimensional matrix using a one-dimensional array. In this embodiment, the edge information is stored using a CSR matrix obtained by compressing the adjacency matrix. It is understood that other methods can also be used for storage, and this application does not limit this.

[0042] For example, Figure 1 Figure C shows that when the above adjacency matrix is ​​represented as a CSR matrix, it can be obtained as three one-dimensional arrays, including: non-zero items [AB CDEF], column indices [1 3 2 3 0 2], and row offsets [0 2 4 5 6]. Among them, non-zero items represent non-zero items in the adjacency matrix, i.e., edges.

[0043] The column index indicates which column of the adjacency matrix the corresponding non-zero item belongs to. The number of column indices is the same as the number of non-zero items, and they correspond one-to-one. Especially for directed graphs, the column index represents the identifier of the target vertex. For example, non-zero item A is located in row 0, column 1, with a column index of 1, indicating that the target vertex 1 is reached from the source vertex 0 via edge A; B is located in row 0, column 3, with a column index of 3, indicating that the target vertex 3 is reached from the source vertex 0 via edge B; C is located in row 1, column 2, with a column index of 2, indicating that the target vertex 2 is reached from the source vertex 1 via edge C; D is located in row 1, column 3, with a column index of 3, indicating that the target vertex 3 is reached from the source vertex 1 via edge D; E is located in row 2, column 0, with a column index of 0, indicating that the target vertex 0 is reached from the source vertex 2 via edge E; F is located in row 3, column 2, with a column index of 2, indicating that the target vertex 2 is reached from the source vertex 3 via edge F.

[0044] Row offsets represent the start and end positions of non-zero items in the same row of the original adjacency matrix. Row offsets are key information for matrix compression. For example, assuming each non-zero item has an offset on both sides, six non-zero items can have seven positions from 0 to 6. Then, the start position of non-zero items A and B in the first row is 0 and the end position is 2; the start position of non-zero items C and D in the second row is 2 and the end position is 4; the start position of non-zero item E in the third row is 4 and the end position is 5; and the start position of non-zero item F in the fourth row is 5 and the end position is 6.

[0045] Memory access in concurrent graph processing tasks exhibits two types of locality: temporal locality between tasks, where different tasks frequently access the same graph structure in the short term as they synchronously traverse the same path along active vertices; and spatial locality between tasks, where a large number of state accesses by different tasks are confined to a relatively small set of vertices when they access the state of the same vertex.

[0046] Therefore, this application proposes a graph processing apparatus and method that fully utilizes the temporal and spatial locality of concurrent graph processing tasks. When multiple graph processing tasks access the same graph structure, by providing a common traversal path to the kernels running multiple graph processing tasks, these kernels are instructed to access the vertices in the graph structure in the same order, thus avoiding irregular access to vertices and improving the throughput of data processing.

[0047] This application provides a graph processing device that can be at least one of a system-on-chip (SoC) chip, a general-purpose processor (e.g., a central processing unit (CPU)), a dedicated processor (e.g., a graphics processing unit (GPU)), an application-specific integrated circuit (ASIC), a programmable logic device (e.g., a field-programmable gate array (FPGA)), a standalone system, a distributed system, or a cloud computing platform.

[0048] For example, taking the graph processing device as a processor, one possible structure of the graph processing device will be described. Figure 2As shown, this application embodiment provides a graph processing device including a processor 11 and memory 12. The processor 11 includes at least one core 111, a cache 112 (e.g., static random access memory (SRAM)), a topology-aware traversal regularization (TATR) circuit 113, and at least one prefetching and indexing (PI) circuit 114. The cache 112 may include a first-level cache (FLC) 1121, a second-level cache (MLC) 1122, and a third-level cache (LLC) 1123, and may also include at least one prefetch cache 1124. The prefetch cache 1124 may be a separate cache or located in the first-level cache 1121 or the second-level cache 1122. The number of PI circuits 114 and prefetch caches 1124 can be the same as the number of kernels 111, and each set of PI circuits 114 and prefetch caches 1124 can correspond to one kernel 111. That is, each set of PI circuits 114 and prefetch caches 1124 can interact with the corresponding kernel, but will not interact with other non-corresponding kernels 111.

[0049] Each kernel 111 can independently run graph processing tasks (i.e., run concurrent graph processing tasks) to read and write data stored in memory 12, such as graph structures, through the memory controller (not shown in the diagram). However, due to the significant speed difference between kernel 111 and memory 12, a cache 112 is set between processor 11 and memory 12 to store data exchanged between kernel 111 and memory 12, such as graph structures. The cache 112 has a small capacity but its operating speed is close to that of processor 11. The operating speeds of the L1 cache 1121, L2 cache 1122, and L3 cache 1123 in cache 112 decrease sequentially, but their capacities increase sequentially. The L1 cache 1121 in cache 112 is used to cache the most frequently hit instructions and data of kernel 111. The L1 cache 1121 operates in the same clock cycle as kernel 111 and has a fast operating speed, but its capacity is generally very small due to its high cost. Each kernel 111 corresponds to a L2 cache 1122, which can cache data exclusive to each kernel 111. There is typically one L3 cache 1123. The data stored in L3 cache 1123 is shared by at least one kernel 111, and is mainly used to reduce the latency of data between kernel 111 and memory 12. The prefetch cache 1124 is used to cache data that kernel 111 may access in the future (i.e., data prefetching) to reduce the latency of kernel 111 accessing data. The granularity of data prefetching is a cache line.

[0050] like Figure 3 As shown, the TATR circuit 113 and PI circuit 114 described above are used to perform the processing method shown in the figure below:

[0051] S101 and TATR circuit 113 obtain a common traversal path based on the vertices in the graph structure that are accessed by at least one kernel 111 (multiple graph processing tasks running).

[0052] The common traversal path indicates the order in which the vertices mentioned above are visited by at least one kernel 111 (multiple graph processing tasks running). The common traversal path is empty by default. The TATR circuit 113 generates the common traversal path according to the following principle: first, the source vertex that has not been added to the common traversal path is added to the common traversal path; then, the neighboring vertices of the source vertex that have not been added to the common traversal path (called the target vertex) are added to the common traversal path. Both the source vertex and the target vertex are vertices in the graph structure that are visited by at least one kernel 111 (multiple graph processing tasks running). The following example, using edge information stored in CSR matrix form, illustrates how the common traversal path is obtained.

[0053] Figure 4Table 1 shows the data structures that the TATR circuit 113 may involve. These data structures can be stored in memory 12 or other storage areas. The TATR circuit 113 can store the starting address and size of these data structures.

[0054] Table 1

[0055]

[0056]

[0057] like Figure 5 As shown, step S101 may include steps S1011-S1015, where step S1015 is optional. As mentioned above, the identifiers of each vertex in the graph structure are sorted according to natural numbers (e.g., starting from 0). By knowing the identifier of the first vertex and the identifier of the last vertex, each vertex in the graph structure can be traversed. After the TATR circuit 113 completes steps S1011-S1014, steps S1011-S1014 are executed again until each vertex in the graph structure has been traversed according to the identifier of the first vertex and the identifier of the last vertex.

[0058] S1011 and TATR circuit 113 obtain the source vertex and add the source vertex to the common traversal path.

[0059] TATR circuit 113 can first determine whether the intermediate result queue array is empty:

[0060] If the intermediate queue array is empty, then an active vertex is obtained as the source vertex based on all active vertex bitvectors. The identifier of this source vertex is added to the worklist array (i.e., added to the common traversal path), and the source vertex is changed to inactive in all active vertex bitvectors. Figure 1 Taking C as an example, assuming that the TATR circuit 113 determines that vertex 0 is the source vertex, then the identifier "0" of vertex 0 is added to the worklist array, and vertex 0 is changed to an inactive vertex in all active vertex bit vectors.

[0061] If the intermediate result queue array is not empty, a vertex is taken from the intermediate result queue array as the source vertex, and the vertex is deleted from the intermediate result queue array. Since the source vertex has already been added to the worklist array, that is, it has already been added to the common traversal path, the source vertex will not be added to the worklist array again, that is, it will not be added to the common traversal path again. The specific reason is described in step S1014.

[0062] S1012, TATR circuit 113 obtains the row offset corresponding to the source vertex.

[0063] The TATR circuit 113 can obtain the row offset (including start and end offset) corresponding to the source vertex from the vertex array. Figure 1 Taking C as an example, the starting position of the row offset corresponding to the source vertex 0 is 0 and the ending position is 2, that is, the row offset corresponding to the source vertex 0 is [0 2].

[0064] S1013 and TATR circuit 113 obtain the target vertex based on the column index and the row offset corresponding to the source vertex, and add the target vertex to the common traversal path.

[0065] The TATR circuit 113 can obtain the identifiers of all neighboring vertices from the column indices stored in the edges array based on the row offset corresponding to the source vertex, and determine the neighboring vertex belonging to the active vertex from all neighboring vertices based on the active_all bitvector as the target vertex. The identifier of the target vertex is added to the worklist array, that is, the target vertex is added to the common traversal path.

[0066] by Figure 1Taking C as an example, the column index corresponding to the edge is [1 3 2 3 0 2]. The column index between the row offset

[02] corresponding to the source vertex 0 is [1 3]. That is, the neighboring vertices of the source vertex 0 are vertex 1 and vertex 3. And in all active vertex bit vectors, vertex 1 and vertex 3 are active vertices. Therefore, vertex 1 and vertex 3 are both target vertices of the source vertex 0. The TATR circuit 113 adds the identifier "1" of vertex 1 and the identifier "3" of vertex 3 to the worklist array and the intermediate result queue array. At this time, since the worklist array has already stored the identifier "0" of vertex 0, plus the identifier "1" of vertex 1 and the identifier "3" of vertex 3 added in sequence, it indicates that the common traversal path is vertex 0 -> vertex 1 -> vertex 3, which is used to indicate that at least one kernel 111 accesses vertex 0, vertex 1 and vertex 3 in the graph structure in sequence.

[0067] In addition, the target vertices are added to the intermediate result queue array. When step S1011 is executed next, these target vertices will be used as new source vertices, thus continuously exploring and forming a connected common traversal path.

[0068] S1014, TATR circuit 113 changes the target vertex to an inactive vertex.

[0069] If the target vertex is an active vertex in all active vertex bitvectors, then the target vertex is changed to an inactive vertex to avoid repeatedly adding the target vertex to the common traversal path in step S1011. Figure 1 Taking A as an example, since vertex 3 has already been added to the worklist array and the intermediate queue array as a neighboring vertex of vertex 0, when searching for the neighboring vertex of vertex 1 next time, vertex 3 will not be added to the worklist array and the intermediate queue array again.

[0070] S1015 and TATR circuit 113 can divide the common traversal path into multiple sub-paths.

[0071] The TATR circuit 113 can partition the common traversal path according to the partition size to obtain multiple sub-paths with the same number of vertices, or it can partition the common traversal path in other ways to obtain multiple sub-paths. The TATR circuit 113 can store multiple sub-paths in a partition table array. The TATR circuit 113 can also further divide the common traversal path or sub-paths into chunks according to the size of the buffer lines, which facilitates the storage of vertex information in the buffer 112 through data prefetching.

[0072] It should be noted that, as Figure 6 As shown, the TATR circuit 113 may include multiple pipelines 1131, and optionally, a merging circuit 1132. Each pipeline 1131 is used to execute steps S1011-S1014, and the merging circuit 1132 is used to execute step S1015. For the multiple pipelines 1131, all active vertex bitvectors can be divided into multiple consecutive ranges and assigned to the multiple pipelines 1131 respectively. Each pipeline 1131 is responsible for retrieving all active vertex bitvectors within a range, thereby achieving parallel processing of step S101.

[0073] S102, PI circuit 114 sends vertex information to at least one kernel 111 according to the order indicated by the common traversal path.

[0074] For each kernel 111, the PI circuit 114 follows the following principle to send vertex information: the PI circuit 114 first obtains the unsent vertices as source vertices according to the order of the common traversal path, then obtains the unsent neighbor vertices of the source vertex (called target vertices), and sends the information of the source vertex and the information of the target vertex to the kernel. The vertex information may include the vertex's identifier and the vertex's state.

[0075] Figure 4 Table 2 shows the data structures that the PI circuit 114 may involve. These data structures can be stored in memory 12 or other storage areas. The PI circuit 114 can store the starting address and size of these data structures.

[0076] Table 2

[0077]

[0078] like Figure 7 As shown, step S102 may include steps S1021-S1025:

[0079] S1021 and PI circuit 114 obtain the source vertex in the order of the common traversal path.

[0080] PI circuit 114 can obtain a vertex as a source vertex according to the order of the entire common traversal path; or, PI circuit 114 can obtain a vertex as a source vertex according to the order of a sub-path in the common traversal path until all sub-paths have been traversed; or, PI circuit 114 can obtain a vertex as a source vertex according to the order of the block until all blocks have been traversed.

[0081] It should be noted that the next sub-path is only processed by the PI circuit 114 after one sub-path has been processed by all PI circuits 114, so that the PI circuits 114 can be synchronized, and so that the graph processing tasks running by each kernel 111 can be synchronized.

[0082] S1022 and PI circuit 114 determine whether the source vertex is an active vertex.

[0083] Since the common traversal path includes active vertices visited by at least one graph processing task running in kernel 111, and each kernel 111 may only process a portion of these active vertices, the PI circuit 114 can search the active vertex bitvector to determine whether the source vertex is an active vertex. Here, an active vertex refers to the vertex visited by the graph processing task running in the kernel 111 corresponding to this PI circuit 114. If the source vertex is not an active vertex, step S1011 is re-executed; if the source vertex is an active vertex, it is updated as an inactive vertex in the active vertex bitvector, and step S1023 is executed.

[0084] S1023 and PI circuit 114 obtain the row offset corresponding to the source vertex.

[0085] This step is the same as step S1012 and will not be repeated here.

[0086] S1024 and PI circuit 114 obtain the target vertex based on the column index and the row offset corresponding to the source vertex.

[0087] Similar to step S1013, the PI circuit 114 can obtain the identifiers of all neighboring vertices from the column indices stored in the edges array based on the row offset corresponding to the source vertex, and determine the neighboring vertex belonging to the active vertex from all neighboring vertices based on the active vertex bit vector as the target vertex.

[0088] by Figure 1Taking C as an example, the column index corresponding to the edge is [1 3 2 3 0 2]. The column index between the row offset

[02] corresponding to the source vertex 0 is [1 3]. That is, the neighboring vertices of the source vertex 0 are vertex 1 and vertex 3. In the active vertex bit vector, vertex 1 and vertex 3 are both active vertices. Therefore, vertex 1 and vertex 3 are both target vertices of the source vertex 0.

[0089] S1025 and PI circuit 114 send the source vertex identifier, the target vertex identifier, the source vertex state, and the target vertex state to kernel 111.

[0090] like Figure 8 As shown, kernel 111 can send a state update command to PI circuit 114. PI circuit 114 can store the source vertex identifier (e.g., 4 bytes), the target vertex identifier (e.g., 4 bytes), the source vertex state (e.g., 8 bytes), and the target vertex state (e.g., 8 bytes) in prefetch cache 1124 so that kernel 111 can retrieve this information from cache 1124 via fetch command.

[0091] It's important to note that while multiple graph processing tasks share the same common traversal path, this only means that each task visits vertices in the same order. The vertex states remain private to each task and are not shared among them. Typically, the state data for a single vertex is not large, and the inherent irregular access characteristics of concurrent graph processing tasks can lead to wasted memory bandwidth and cache capacity. Therefore, the states of the same vertex from different graph processing tasks can be merged and stored to improve memory bandwidth and cache capacity utilization. For example, ... Figure 9 As shown, assuming graph processing task 0 visits vertices 1, 2, and 3 sequentially, and graph processing task 1 visits vertices 0, 1, 2, 3, and 4 sequentially, the states of vertex 1, 2, and 3 for these two tasks can be merged and stored in memory 12. When prefetching the states of these vertices from memory 12 to cache 112, they are prefetched using the same storage format, thereby improving memory bandwidth utilization and cache capacity utilization. In particular, since the granularity of data prefetching is the cache line, the granularity of merging and storing in memory 12 can also be the cache line. That is, the states of the same vertex from different graph processing tasks can be merged and stored according to the size of the cache line, so as to facilitate direct data prefetching.

[0092] In addition, merging the states of all vertices would incur high management overhead. Therefore, it is possible to merge only the states of the same vertex that have high popularity (popularity greater than a threshold) in different graph processing tasks. The popularity of a vertex can refer to the number of its neighboring vertices.

[0093] Optional, such as Figure 10 As shown, the image processing method also includes step S103. It should be noted that step S103 does not depend on steps S101-S102, that is, step S103 can be executed independently.

[0094] S103, at least one kernel 111 merges and stores the state of the same vertex of different graph processing tasks.

[0095] In particular, software running in at least one kernel 111 can merge and store the states of the same vertex from different graph processing tasks according to the size of the cache line, so as to facilitate direct data prefetching.

[0096] Figure 4 Table 3 shows the data structures that at least one kernel 111 may involve. These data structures can be stored in memory 12 or other storage areas. At least one kernel 111 can store the starting address and size of these data structures. In addition, the data structures in Table 3 other than the heat threshold (T) can also be accessed by the PI circuit 114.

[0097] Table 3

[0098]

[0099] At least one kernel 111 can obtain the row offset (including the start and end offset) of a vertex from the vertex array. The difference between the end offset and the start offset is taken as the vertex's heat value, which represents the number of its neighboring vertices. When the heat value of a vertex is greater than or equal to a heat value threshold, the vertex is considered a high-heat vertex; otherwise, it is considered a low-heat vertex. For high-heat vertices, at least one kernel 111 can store the vertex's state in a coalesced states table, so that the PI circuit 114 can obtain the vertex's state from the coalesced states table in step S102. For low-heat vertices, at least one kernel 111 can store the vertex's state in a vertex states array, so that the PI circuit 114 can obtain the vertex's state from the vertex states array in step S102. Vertices with high heat value are more likely to be accessed by at least one kernel 111. Performing data merging and storage can maximize the saving of storage space and avoid increasing the complexity of data processing.

[0100] like Figure 11 As shown, at least one kernel 111 and PI circuit 114 can locate the vertex states stored in the coalesced states table in the following ways:

[0101] S1031. Based on the identifier of the graph processing task (stored in the task identifier (job ID)), find the first base address (base_addr) of the corresponding coalesced states array and the second base address of the state offset array in the job offset array.

[0102] That is, based on the identifier of the graph processing task, the corresponding pair of coalesced states array and state offset array is found in the job offset array. For example, for graph processing task 0, the corresponding first pair of coalesced states array 0 and state offset array 0 can be found in the job offset array.

[0103] S1032. Based on the identifier of the graph processing task, find the offset of the vertex state in the state offset array within the merged item of the coalesced states array.

[0104] This involves finding the column coordinates of a vertex's state in the merged item based on the identifier of the graph processing task in the state offset array. For example, graph processing task 0 can be used to find the column coordinates of a vertex's state in the merged item in the state offset array.

[0105] S1033. Based on the vertex identifier, find the offset (vertex_offset) of the corresponding merged item in the coalesced states array in the hash table.

[0106] This means finding the row coordinates of the corresponding merged item in the coalesced states array based on the vertex's identifier in the hash table. For example, finding the row coordinates of the corresponding merged item in the coalesced states array using the vertex identifier 1.

[0107] The intersection of the two offsets obtained through steps S1032 and S1033 is the storage location of the vertex state in the merged state array. That is, the storage address of the vertex state accessed by the graph processing task is base_addr + vertex_offset + offset.

[0108] The graph processing apparatus and method provided in this application improve data processing throughput by providing a common traversal path to at least one kernel, instructing these kernels to access vertices in the graph structure in the same order. This ensures regular access to vertices by at least one kernel, avoiding irregular access by at least one kernel, and further improving memory bandwidth utilization and cache capacity utilization. Compared with existing advanced software concurrent graph processing systems, this solution achieves a speedup of 11.3 to 23.9 times with only a 0.5% increase in area overhead. Compared with the three most advanced hardware accelerators—Hats, Min-now, and XeonPhi—this solution improves performance by 4.7 to 10.3 times, 5.5 to 13.2 times, and 3.8 to 8.4 times, respectively.

[0109] This application also provides a computer-readable storage medium storing instructions that, when executed on a graph processing apparatus, cause the graph processing apparatus to perform... Figure 3 , Figure 5 , Figure 7 , Figure 10 , Figure 11 The method in the middle.

[0110] This application also provides a computer program product containing instructions that, when executed on a graph processing device, cause the graph processing device to perform... Figure 3 , Figure 5 , Figure 7 , Figure 10 , Figure 11 The method in the middle.

[0111] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0112] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0113] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and modules described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0114] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or modules may be electrical, mechanical, or other forms.

[0115] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located on one device or distributed across multiple devices. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0116] In addition, the functional modules in the various embodiments of this application can be integrated into one device, or each module can exist physically separately, or two or more modules can be integrated into one device.

[0117] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device containing one or more servers, data centers, etc., that can be integrated with the medium. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0118] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An image processing apparatus, characterized in that, include: At least one kernel, a topology-aware traversal path regularization (TATR) circuit, and a prefetch index (PI) circuit; The TATR circuit is used to obtain a common traversal path based on the vertices in the graph structure that are accessed by the at least one kernel. The common traversal path is used to indicate the order in which the vertices are accessed by the at least one kernel. The PI circuit is used to send the vertex information to the at least one kernel according to the order indicated by the common traversal path.

2. The image processing apparatus according to claim 1, characterized in that, The TATR circuit is specifically used for: First, the first source vertex that has not been added to the common traversal path is added to the common traversal path. Then, the first neighbor vertex of the first source vertex that has not been added to the common traversal path is added to the common traversal path. The first source vertex and the first neighbor vertex are two vertices of an edge in the graph structure. Both the first source vertex and the first neighbor vertex belong to the vertices in the graph structure that are accessed by at least one kernel.

3. The image processing apparatus according to any one of claims 1-2, characterized in that, For each core, the PI circuit is specifically used for: Obtain the second source vertex that has not been sent according to the order of the common traversal path; Obtain the unsent second neighbor vertex of the second source vertex; Send the information of the second source vertex and the information of the second neighbor vertex to each kernel; Wherein, the second source vertex and the second neighbor vertex are two vertices of an edge in the graph structure, and both the second source vertex and the second neighbor vertex belong to the vertices in the graph structure that are accessed by each kernel.

4. The image processing apparatus according to any one of claims 1-3, characterized in that, The at least one kernel runs multiple graph processing tasks; The at least one kernel is also used to merge and store the state of the same vertex from different graph processing tasks.

5. The image processing apparatus according to claim 4, characterized in that, The at least one kernel is specifically used for: The states of the same vertex from different graph processing tasks are merged and stored according to the size of the cache line.

6. The processing apparatus according to any one of claims 4-5, characterized in that, The same vertex is a vertex whose number of neighboring vertices is greater than a threshold.

7. The image processing apparatus according to any one of claims 1-6, characterized in that, The graph processing device further includes a buffer; The TATR circuit is also used to divide the common traversal path into blocks according to the size of the cache line; The PI circuit is also used to store the vertex information into the buffer according to the block.

8. The image processing apparatus according to any one of claims 1-7, characterized in that, The image processing device is at least one of a system-on-a-chip, a general-purpose processor, a special-purpose processor, a special-purpose integrated circuit, a programmable logic device, a stand-alone system, a distributed system, or a cloud computing platform.

9. A graph processing method, characterized in that, include: Based on the vertices in the graph structure that are accessed by at least one kernel, a common traversal path is obtained, which is used to indicate the order in which the vertices are accessed by the at least one kernel. The information of the vertices is sent to the at least one kernel in the order indicated by the common traversal path.

10. The method according to claim 9, characterized in that, The process of obtaining a common traversal path based on vertices accessed by at least one kernel in the graph structure includes: First, the first source vertex that has not been added to the common traversal path is added to the common traversal path. Then, the first neighbor vertex of the first source vertex that has not been added to the common traversal path is added to the common traversal path. The first source vertex and the first neighbor vertex are two vertices of an edge in the graph structure. Both the first source vertex and the first neighbor vertex belong to the vertices in the graph structure that are accessed by at least one kernel.

11. The method according to any one of claims 9-10, characterized in that, For each kernel, sending the vertex information to the at least one kernel in the order indicated by the common traversal path includes: Obtain the second source vertex that has not been sent according to the order of the common traversal path; Obtain the unsent second neighbor vertex of the second source vertex; Send the information of the second source vertex and the information of the second neighbor vertex to each kernel; Wherein, the second source vertex and the second neighbor vertex are two vertices of an edge in the graph structure, and both the second source vertex and the second neighbor vertex belong to the vertices in the graph structure that are accessed by each kernel.

12. The method according to any one of claims 9-11, characterized in that, The at least one kernel runs multiple graph processing tasks; the method further includes: The states of the same vertex from different graph processing tasks are merged and stored.

13. The method according to claim 12, characterized in that, The step of merging and storing the states of the same vertex from different graph processing tasks includes: The states of the same vertex from different graph processing tasks are merged and stored according to the size of the cache line.

14. The method according to any one of claims 12-13, characterized in that, The same vertex is a vertex whose number of neighboring vertices is greater than a threshold.

15. The method according to any one of claims 9-14, characterized in that, Also includes: The common traversal path is divided into blocks according to the size of the cache line; The information of the vertex is stored in the cache according to the block.

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