A three-dimensional integrated circuit layout method with physical perception incremental partitioning

Abstract

The application discloses a three-dimensional (3D) integrated circuit layout method with physical perception incremental partition, comprising the following steps: (1) according to a given netlist, all units are placed on a layer of chips to make global layout to find ideal positions of the units; (2) based on the physical positions of the units, further grid-based minimum cut partition is adopted to distribute the units in the netlist to two chips; (3) incremental half perimeter wire length (HPWL) driven partition and 3D global layout based on electric field energy are adopted to alternately optimize the partition and layout results; (4) sigmoid-based 3D post-global layout is executed to further relieve local congestion; (5) a legalization method is adopted to ensure layout legality; and (6) finally, a detailed layout method is executed to ensure legality and further improve the quality of a solution. The application can quickly obtain a high-quality 3D layout result, effectively reduces wire length and can meet the needs of a super-large-scale three-dimensional integrated circuit layout stage.

Description

Technical Field

[0001] This invention relates to a three-dimensional integrated circuit layout method with physical sensing incremental partitioning, belonging to the field of integrated circuit physical design automation technology. Background Technology

[0002] In the chiplet era, three-dimensional (3D) integrated circuits (ICs) have attracted much attention due to their superior performance and lower power consumption compared to 2D ICs. Initially, 3D ICs used through-silicon vias (TSVs) to connect nets located on different chips, where the minimum spacing between the interconnects was greater than 10 μm. TSVs can consume available placement area for standard cells, thus limiting the ability of 3D ICs to maximize their advantages.

[0003] Unlike TSV-based 3D ICs, emerging monolithic 3D (M3D) ICs with submicron pitch monolithic through-layer vias (MIVs) and stacked 3D ICs with hybrid bonding terminals can achieve higher device densities. In stacked 3D ICs, different chips can be fabricated in parallel before bonding, compared to M3D ICs where multiple chips are fabricated sequentially. Furthermore, another major advantage of stacked 3D ICs is the ability to use different process technologies on different chips. Therefore, stacked 3D ICs employing hybrid bonding terminals became popular in the chiplet era for better yield, performance, and cost. By dividing a large single chip into two or more smaller chips and vertically stacking the split chips, chip-to-chip (D2D) stacked 3D ICs have shorter linelengths, reducing interconnect delays and circuit power consumption. However, with the vertical stacking configurations and different process technologies of stacked 3D ICs, layout issues become more challenging.

[0004] Placement is one of the most important and time-consuming optimization steps in physical design. It is closely related to subsequent routing operations and can significantly affect the efficiency and quality of 3D IC design. With the continuous development of integrated circuits, 3D ICs are exhibiting characteristics of ultra-large scale and heterogeneity, which poses a severe challenge to the improvement of placement technology. Summary of the Invention

[0005] The purpose of this invention is to provide a three-dimensional integrated circuit layout method with physically-aware incremental partitioning to solve the problem of poor 3D ICs layout results in the prior art.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A high-performance 3D layout method with physically-aware incremental partitioning includes the following steps:

[0008] Step S1: Based on the given netlist, use a compact 2D global layout to find the ideal location for all cells in the chip;

[0009] Step S2: Based on the location of the cells, a progressive density-driven partitioning model is further adopted to allocate the cells in the netlist to two chips;

[0010] Step S3: Incremental HPWL-driven partitioning and 3D global layout based on electric field energy are used to alternately optimize the partitioning and layout results.

[0011] Step S4: Perform sigmoid-based 3D post-global layout to further alleviate local congestion;

[0012] Step S5: Use a legalization method to ensure the legality of the layout;

[0013] Step S6: Perform a detailed layout method to ensure legality while further improving the quality of the solution.

[0014] In step S1, all units are placed on a single die and the constraint optimization problem is solved.

[0015]

[0016] Where B represents a set of n×n rectangular grids. For each grid b∈B, when the global layout ends, its density ρ b (v) should be equal to or lower than the target placement density ρ t Because at this stage all the units that would normally be placed on two chip layers are placed on the same chip, the implementation will use ρ t Set to 2.

[0017] In step S2, based on the cell location, a mesh-based minimum cut partitioning method is further employed to allocate the cells in the netlist to the two chips. The chips are divided into a set of meshes, and a progressive density-driven minimum cut partitioning algorithm is executed within each mesh. After each mesh is partitioned, the cells in that mesh are fixed to their corresponding layer. Each time a mesh is partitioned, the partitioning results of the already completed meshes are considered.

[0018] Step S3 employs incremental HPWL-driven partitioning and electric field energy-based 3D global placement to alternately optimize the partitioning and placement results. The incremental partitioning algorithm optimizes line length by moving cells between chips, while the 3D global placement algorithm optimizes line length by moving cells within the chip. The two algorithms are executed alternately to achieve 3D line length optimization.

[0019] Incremental HPWL-driven partitioning optimizes line length by moving cells between chips. Each time, cells that minimize line length are selected for inter-layer movement until the line length deteriorates. First, an undirected hypergraph H = (V, E, α, ω) is constructed based on the netlist. It is defined as a set of vertices V and a set of hyperedges E, with vertex weights of α and hyperedge weights of ω. Each vertex represents a cell, and each hyperedge is a subset of the vertex set V. Since the two chips need to satisfy the maximum layout utilization constraint, the area of ​​the cell when allocated to different chips is used as the node weight α. i In addition, each wire also has a corresponding weight ω. i Since the primary goal in this stage is to better optimize line length, the reduction in HPWL when moving a cell from the current chip to another chip is used as its weight ω. i .

[0020] The maximum gain and total gain are set to zero. For each cell, its initial state is set to free state, and the decrease in HPWL is calculated when the cell moves from the current chip to another chip. During this process, the newly generated terminal for connecting the two layers of nets is placed directly in the optimal region. When a free cell exists, the cell with the largest gain in the free state is selected, and this cell is moved from its current chip to another chip. Once a cell has moved in each round of the algorithm, its state becomes fixed. Afterward, the line length gains of other cells connected to this moved cell will change, and the gains of these cells need to be updated. If the total gain is large during the movement, this partitioning result is recorded. Once all cells are fixed, a new round of the algorithm begins as long as the total gain is greater than zero. Otherwise, the algorithm terminates.

[0021] The 3D global placement algorithm optimizes line length by moving cells within the chip. Unlike 2D global placement, cells connected by cut meshes are connected through terminals in the 3D global placement. To better minimize the total HPWL, 3D global placement is performed on both cells and terminals. Therefore, the WA line length model approximates the HPWL, and the horizontal part is shown below:

[0022]

[0023] Where γ is the smoothing parameter. Vertical part It can be obtained using a similar method. In equation (2) above, the terminal is also included in the calculation of the lengths of the two chip lines.

[0024] Step S4 performs a sigmoid-based 3D global layout to further alleviate local congestion. A quadratic sigmoid function is used to smoothly approximate the density function, as shown below:

[0025]

[0026] Where β is a parameter controlling the smoothness. The same optimization method is used to solve the nonlinear layout problem defined in equation (1). Through post-global layout, the local cell density distribution is diffused and a more uniform layout scheme is obtained. In this way, legalization can be completed with a small amount of displacement.

[0027] Step S5 performs legalization to ensure layout legality. Abacus is extended to legalize cells on the top and bottom chips, and the legalization of cells on the top and bottom chips is performed in parallel. In terminal legalization, since terminals do not need to be aligned to rows, only the spacing constraints between terminals need to be satisfied. Under certain conditions, a global optimal solution exists. To minimize the additional line length increase caused by terminals, we try to place terminals in the optimal region. Therefore, a bipartite graph matching method is used to legalize terminals, placing them in the optimal region where they will not increase line length. The bipartite graph matching method is an existing technique, but due to the unique characteristic of terminals having uniform size and shape, this invention is the first to use bipartite graph matching for terminal legalization. Detailed steps are as follows:

[0028] First, place all terminals in the optimal region. Divide the chip into n*n regions based on the number of terminals. Then, assign the terminals to their corresponding regions based on their positions. Since each terminal is the same size, divide each region into several grids of the same size as the terminals. Use a matching method to assign the terminals to the grids.

[0029] Then, the Hungarian algorithm is used to connect each terminal to a portion of the grid along the edge of the optimal region, ensuring that each terminal can be matched. After this, the bipartite graph best perfect matching—KM algorithm—is used to achieve matching with the minimum movement. To speed up the legalization process, legalization for each region is performed in parallel.

[0030] Step S6 executes a detailed layout method to ensure legality while further improving the quality of the solution. Line length is further optimized through global swapping and local reordering methods.

[0031] Beneficial effects: 1) This invention proposes a physically-aware density-driven initial partitioning method, including a compact 2D global layout based on electric field energy and progressive density-driven partitioning, to partition the netlist into two bare dies while considering cell locations. This provides the desired cell locations for subsequent partitioning.

[0032] 2) Incremental HPWL-driven partitioning and electric field-based 3D global layout are proposed to alternately optimize the partitioning and layout results, thereby further shortening the line length.

[0033] 3) A sigmoid-based post-3D global layout is proposed to further alleviate local congestion and further reduce the increase in line length caused by unit movement during the legalization process.

[0034] 4) Develop Abacus-based cell legalization and bipartite graph matching-based terminal legalization methods to achieve layout legalization.

[0035] This invention can effectively improve the layout quality of ultra-large scale heterogeneous 3D ICs and reduce wiring length, especially for large-scale designs, it can significantly improve layout quality. Attached Figure Description

[0036] Figure 1 This is a flowchart of a three-dimensional integrated circuit layout method with physically-aware incremental partitioning according to the present invention;

[0037] Figure 2 This is the incremental HPWL-driven partitioning algorithm of the present invention. Detailed Implementation

[0038] The technical solution of the invention will now be described in detail with reference to the accompanying drawings.

[0039] This invention provides a 3D integrated circuit layout method with physically-aware incremental partitioning. The method first performs a global layout of all cells on a single chip layer based on a given netlist to find the desired cell locations. Based on the cell locations, a mesh-based minimum cut partitioning is further employed to distribute the cells in the netlist across two chips. Incremental HPWL-driven partitioning and electric field-based 3D global layout are then alternately used to optimize the partitioning and layout results. Subsequently, a sigmoid-based 3D post-global layout is employed to further alleviate local congestion. Finally, cell and terminal legalization and detailed layout are performed to ensure layout legality and further optimize line lengths. Figure 1 As shown, the method includes the following steps:

[0040] 101. Based on the given netlist, place all cells on a single chip layer for global placement to find the desired cell location.

[0041] 102. Based on the cell location, a mesh-based minimum cut partitioning method is further adopted to allocate the cells in the netlist to two chips;

[0042] 103. Incremental HPWL-driven partitioning and 3D global layout based on electric field energy are used to alternately optimize the partitioning and layout results.

[0043] 104. Perform sigmoid-based 3D post-global layout to further alleviate local congestion;

[0044] 105. Employ legalization methods to ensure the legality of the layout;

[0045] 106. Implement a detailed layout methodology to ensure legality while further improving the quality of the solution.

[0046] In version 101, all elements are placed on a single die and the constrained optimization problem is solved.

[0047]

[0048] Where B represents a set of n×n rectangular grids. For each grid b∈B, when the global layout ends, its density ρ b (v) should be equal to or lower than the target placement density ρ t Because at this stage all the units that would normally be placed on two chip layers are placed on the same chip, the implementation will use ρ t Set to 2.

[0049] Based on cell location, step 102 further employs a mesh-based minimum cut partitioning algorithm to distribute cells from the netlist across two chips. The chips are divided into a set of meshes, and a progressive density-driven minimum cut partitioning algorithm is executed within each mesh. After each mesh is partitioned, the cells in that mesh are fixed to their corresponding layer. Each time a mesh is partitioned, the partitioning results of already completed meshes are considered.

[0050] The 103 algorithm employs incremental HPWL-driven partitioning and electric field energy-based 3D global placement to alternately optimize the partitioning and placement results. The incremental partitioning algorithm optimizes line length by moving cells between chips, while the 3D global placement algorithm optimizes line length by moving cells within the chip. The two algorithms are executed alternately to achieve 3D line length optimization.

[0051] Incremental HPWL-driven partitioning optimizes line length by moving cells between chips. Each time, cells that minimize line length are selected for interlayer movement until the line length becomes worse.

[0052] The 3D global placement algorithm optimizes line length by moving cells within the chip. Unlike 2D global placement, cells connected by cut meshes are connected through terminals in the 3D global placement. To better minimize the total HPWL, 3D global placement is performed on both cells and terminals. Therefore, the WA line length model approximates the HPWL, and the horizontal part is shown below:

[0053]

[0054] Where γ is the smoothing parameter. Vertical part It can be obtained using a similar method. In equation (2) above, the terminal is also included in the calculation of the lengths of the two chip lines.

[0055] The specific steps for partitioning incremental HPWL drivers are as follows: Figure 2 As shown in the first row, an undirected hypergraph H = (V, E, α, ω) is constructed based on the netlist. It is defined as a set of vertices V and a set of hyperedges E, with vertex weights of α and hyperedge weights of ω. Each vertex represents a cell, and each hyperedge is a subset of the vertex set V. Since the two chips need to satisfy the maximum layout utilization constraint, the area of ​​the cells allocated to different chips is used as the node weight α. i In addition, each wire also has a corresponding weight ω. i Since the primary goal in this stage is to better optimize line length, the reduction in HPWL when moving a cell from the current chip to another chip is used as its weight ω. i .

[0056] In line 3, G m and G tThese represent the maximum gain and total gain, respectively. Then, for each cell, its initial state is set to the free state (line 5). In line 6, the function `calculateInitialGain(H, c)` calculates the reduction in HPWL when the cell moves from the current chip to another chip. During this process, newly generated bonding terminals are placed directly in the optimal region. Lines 7-16 describe the cell movement process. When a free cell exists (line 7), the function `getMaxGain(H)` selects the cell with the largest gain in the free state, and the function `doMove(c)` in line 9 moves the cell from its current chip to another chip. Once a cell has moved in each round of the algorithm, its state becomes fixed (line 10). Afterward, the line length gains of other cells connected to this moved cell will change, and the function `updateGain(H, c)` updates the gains of these cells (lines 11-12). If the total gain is large during the movement, the function `savePartitioningResult()` records this partitioning result (lines 14-16). Once all cells are fixed, a new round of the algorithm begins as long as Gm > 0. Otherwise, the algorithm terminates (line 17).

[0057] 104. Perform sigmoid-based 3D post-global layout to further alleviate local congestion. A quadratic sigmoid function is used to smoothly approximate the density function, as shown below:

[0058]

[0059] Where β is a parameter controlling the smoothness. The same optimization method is used to solve the nonlinear layout problem defined in equation (1). Through post-global layout, the local cell density distribution is diffused and a more uniform layout scheme is obtained. In this way, legalization can be completed with a small amount of displacement.

[0060] 105. Perform legalization to ensure layout legality. Extend Abacus to legalize cells on the top and bottom chips, performing cell legalization on both chips in parallel. In terminal legalization, since terminals do not need to be aligned to rows, only the spacing constraints between terminals need to be satisfied. A globally optimal solution exists under certain conditions. To minimize the additional line length increase caused by terminals, we try to place terminals in the optimal region. Therefore, a matching-based method is used to legalize terminals, placing them in the optimal region where they will not cause additional line length increases.

[0061] 106. A detailed layout approach is implemented to ensure legality while further improving the quality of the solution. Line length is further optimized through global swapping and local reordering methods.

[0062] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A three-dimensional integrated circuit layout method with physically-aware incremental partitioning, characterized in that: Includes the following steps: Step S1: Based on the given netlist, place all cells on a single chip layer for global placement to find the ideal location for the cells. Step S2: Based on the cell location, a mesh-based minimum cut partitioning method is further used to allocate the cells in the netlist to the two chips; Step S3: Incremental HPWL-driven partitioning and 3D global layout based on electric field energy are used to alternately optimize the partitioning and layout results. Step S4: Perform sigmoid-based 3D post-global layout to further alleviate local congestion; Step S5: Use a legalization method to ensure the legality of the layout; Step S6: Perform a detailed layout method to ensure legality while further improving the quality of the solution; Among them, the incremental partitioning algorithm optimizes line length by moving units between chips, while the 3D global layout algorithm optimizes line length by moving units within the chip. Incremental HPWL-driven partitioning optimizes line length by moving cells between chips. Each time, cells that minimize line length are selected for inter-layer movement until the line length deteriorates. Specific steps include: First, construct an undirected hypergraph based on the netlist. It is defined as a set of vertices. and a set of super edges The vertex weight is The weight of the hyperedge is Each vertex represents a unit, and each hyperedge is a set of vertices. A subset; since both chips need to satisfy the maximum layout utilization constraint, the area of ​​the cells allocated to different chips is used as the node weight. In addition, each wire also has a corresponding weight. The reduction in HPWL when a cell is moved from the current chip to another chip is used as its weight. ; Set the maximum gain and total gain to zero; for each cell, set its initial state to free state, and then calculate the reduction in HPWL when the cell moves from the current chip to another chip; during this process, the newly generated terminal for connecting the two layers of wire mesh is placed directly in the optimal area; when a free cell exists, select the cell with the largest gain in the free state and move this cell from its current chip to another chip; once a cell has moved in each round of the algorithm, its state becomes fixed; afterwards, the gain of other cells connected to this moved cell will change, and the gains of these cells need to be updated; if the total gain is large during the movement, record this partitioning result; once all cells are fixed, start a new round of the algorithm as long as the total gain is greater than zero; otherwise, terminate the algorithm.

2. The three-dimensional integrated circuit layout method with physically-aware incremental partitioning according to claim 1, characterized in that: In step S1, all units are placed on a single die and the constraint optimization problem is solved. ； in Represents a group Rectangular grid; for each cell When the global layout ends, its density Equal to or lower than the target placement density .

3. The three-dimensional integrated circuit layout method with physically-aware incremental partitioning according to claim 1, characterized in that: The specific steps of step S2 include: The chip is divided into a group of bins, and a progressive density-driven minimum cut partitioning algorithm is executed in each bin. After each bin is partitioned, the cells in the bin are fixed to their corresponding layers. Each time a bin is partitioned, the partitioning results of the bins that have already been partitioned are considered.

4. The three-dimensional integrated circuit layout method with physically-aware incremental partitioning according to claim 1, characterized in that: The cells connected by the cut mesh are connected through terminals in the 3D global layout. At the same time, the 3D global layout is performed on cells and terminals in multiple layers. The horizontal part of the WA line length model is shown below: ； in It's a smoothing parameter, the vertical part. The same method is used to obtain it; in equation (2) above, the terminal is also included in the calculation of the two chip line lengths.

5. The three-dimensional integrated circuit layout method with physically-aware incremental partitioning according to claim 1, characterized in that: To further alleviate local congestion, a sigmoid-based 3D global layout is performed. A quadratic sigmoid function is used to smoothly approximate the density function, as shown below: ； in It is a parameter that controls the smoothness; the same optimization method is used to solve the nonlinear layout problem defined in equation (1); through post-global layout, the local unit density distribution is diffused and a more uniform layout scheme is obtained.

6. The three-dimensional integrated circuit layout method with physically-aware incremental partitioning according to claim 1, characterized in that: Step S5 includes the following steps: extending Abacus to legalize cells on the top and bottom chips, and performing cell legalization of the top and bottom chips in parallel; in the legalization of the terminal, since the terminal does not need to be aligned to the row, it only needs to satisfy the spacing constraint between terminals; under certain conditions, there exists a global optimal solution; to avoid the terminal causing additional line length increase, the terminal is placed in the optimal region, so a bipartite graph matching method is used to legalize the terminal, placing the terminal in the optimal region that will not increase the line length due to the terminal.

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