Data processing methods, apparatus, electronic devices and readable storage media

Abstract

This invention provides a data processing method, apparatus, electronic device, and readable storage medium. The method involves obtaining interpolation coefficients corresponding to primitives to be processed; dividing the interpolation coefficients of primitives corresponding to the same attribute component within the same attribute into the same data block, obtaining at least two data blocks to be stored; and storing the at least two data blocks into a designated memory. The data in any of the data blocks to be stored is stored contiguously in the designated memory. The designated memory includes multiple storage banks, and data with consecutive addresses in the designated memory is stored in different storage banks. This reduces the dispersion of data to be read in each storage bank, concentrating the data to be read in a smaller, contiguous number of storage banks, thereby reducing the probability of the data to be read falling into different rows of the same storage bank, thus avoiding address conflicts and improving read efficiency to some extent.

Description

Technical Field

[0001] This invention belongs to the field of graphics processing, and in particular relates to a data processing method, apparatus, electronic device, and readable storage medium. Background Technology

[0002] In modern graphics processing, graphics program data includes the positional dimensions and shapes of various primitives that constitute an image, typically representing data corresponding to three-dimensional space. The process of processing graphics program data to obtain the final image includes: vertex data is transformed and calculated by the vertex shader, then enters the primitive assembly module to become primitives, and then passes through the rasterization module to become fragment data. The fragment data is calculated by the fragment shader to obtain the color of the final pixel, thus obtaining the final image. A vertex is a basic element that stores a series of fundamental drawing attributes. It can be information obtained after processing the original image program data, such as points in two-dimensional or three-dimensional space, or multiple points on a surface. In the shader, the graphics elements connected to the vertex are called primitives, and the area within a primitive that should be colored is called a fragment. Besides positional information, a vertex may also contain vertex attributes such as color, normals, and texture coordinates. The fragment obtained by rasterizing a primitive containing that vertex inherits some of the vertex's attributes. The attributes of each fragment can be obtained by interpolating the vertex attributes; correspondingly, attribute interpolation requires interpolation coefficients. Since each attribute of different primitives has different interpolation coefficients, these coefficients need to be stored for use during attribute interpolation. For example, the interpolation coefficients can be stored in scratchpad memory.

[0003] In existing technologies, for each graphic element, the interpolation coefficients for each attribute of that element are first stored consecutively in memory. Then, the interpolation coefficients for different graphic elements are stored consecutively, and finally, they are stored consecutively according to their attribute numbers. These attribute numbers can be understood as identifiers for different attributes and can be user-defined. However, this storage method sometimes results in data to be read falling into different rows of the same memory bank during a single read operation. Because different word addresses within the same bank are accessed simultaneously, address conflicts occur, leading to low read efficiency. Summary of the Invention

[0004] This invention provides a data processing method, apparatus, electronic device, and readable storage medium to solve the problem of low read efficiency caused by address conflicts when reading data.

[0005] To solve the above-mentioned technical problems, the present invention is implemented as follows:

[0006] In a first aspect, the present invention provides a data processing method, the method comprising:

[0007] Obtain the interpolation coefficients corresponding to the primitives to be processed;

[0008] The interpolation coefficients of each primitive to be processed corresponding to the same attribute component in the same attribute are divided into the same data block to obtain at least two data blocks to be stored.

[0009] The at least two data blocks to be stored are stored in a designated memory; wherein, the data in any of the data blocks to be stored is stored contiguously in the designated memory; the designated memory includes multiple memory banks, and data with consecutive addresses in the designated memory are stored in different memory banks.

[0010] In a second aspect, the present invention provides a data processing apparatus, the apparatus comprising:

[0011] The acquisition module is used to acquire the interpolation coefficients corresponding to the primitives to be processed.

[0012] The partitioning module is used to divide the interpolation coefficients of each primitive to be processed that corresponds to the same attribute component in the same attribute into the same data block, so as to obtain at least two data blocks to be stored.

[0013] A storage module is used to store the at least two data blocks to be stored into a designated memory; wherein the data in any of the data blocks to be stored is stored contiguously in the designated memory; the designated memory includes multiple memory banks, and data with consecutive addresses in the designated memory are stored in different memory banks.

[0014] Thirdly, the present invention provides an electronic device comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the above-described data processing method when executing the program.

[0015] Fourthly, the present invention provides a readable storage medium that, when the instructions in the storage medium are executed by the processor of an electronic device, enables the electronic device to perform the above-described data processing method.

[0016] In this embodiment of the invention, the interpolation coefficients corresponding to the primitives to be processed are obtained; the interpolation coefficients of each primitive to be processed corresponding to the same attribute component in the same attribute are divided into the same data block to obtain at least two data blocks to be stored; the at least two data blocks to be stored are stored in a designated memory; wherein, the data in any of the data blocks to be stored is stored continuously in the designated memory; the designated memory includes multiple memory banks, and data with consecutive addresses in the designated memory are stored in different memory banks. Since the data required for each read is divided into the same data block, and the data in the same data block is stored continuously in the designated memory, it can be stored in different memory banks to a greater extent. In this way, the dispersion of the data to be read each time in the bank can be reduced, so that the data to be read each time is concentrated in a smaller number of consecutive banks as much as possible, thereby reducing the probability that the data to be read falls into different rows of the same bank, thus avoiding address conflicts to a certain extent and improving read efficiency. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of the steps of a data processing method provided in an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of storage in the prior art provided by an embodiment of the present invention;

[0020] Figure 3 This is an example diagram of a data processing method provided in an embodiment of the present invention;

[0021] Figure 4 This is a structural diagram of a data processing device provided in an embodiment of the present invention;

[0022] Figure 5 This is a structural diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] Figure 1 This is a flowchart of the steps of a data processing method provided in an embodiment of the present invention, as follows: Figure 1 As shown, the method may include:

[0025] Step 101: Obtain the interpolation coefficients corresponding to the primitives to be processed.

[0026] The primitives to be processed can be the primitives corresponding to fragment data that require subsequent attribute interpolation. They are obtained by vertices through the primitive assembly module. Primitives can be points, line segments, or polygons, and a primitive can contain multiple vertices. Different primitives to be processed can be obtained from different vertices. Specifically, the fragment shader can process a group of fragments at a time. This group of fragments can contain interpolation coefficients corresponding to multiple primitives. The primitives to be processed can be one or multiple. These interpolation coefficients are data generated by the rasterization module in the graphics processor for each attribute of each primitive.

[0027] Specifically, the interpolation coefficients can be directly read from the GPU (Graphics Processing Unit) to achieve the acquisition, or the interpolation coefficients can be generated one by one using the GPU. For example, this step can directly obtain all the interpolation coefficients needed for attribute interpolation using the rasterization module; that is, obtain the interpolation coefficients corresponding to all attributes of each primitive to be processed.

[0028] Step 102: Divide the interpolation coefficients of each primitive to be processed that corresponds to the same attribute component in the same attribute into the same data block to obtain at least two data blocks to be stored.

[0029] In this embodiment of the invention, the attributes of a primitive can be divided into multiple attribute components. Specifically, the number of attribute components contained in an attribute can be set according to actual needs, and this embodiment of the invention does not impose any restrictions on this. Specifically, all the above-mentioned interpolation coefficients can be divided according to attribute components, and all interpolation coefficients of all primitives with the same attribute component in the same attribute can be divided into the same data block. The attributes of a primitive can include some attributes of the vertices that make up the primitive. Correspondingly, since a primitive is usually composed of multiple vertices, a single primitive can contain attributes of multiple different vertices. Different attribute data refers to different types of descriptive data, such as vertex position, vertex color, vertex texture, etc. Correspondingly, the above-mentioned attribute components refer to the different components that constitute an attribute. For example, the color attribute can be composed of three attribute components (R, G, B), and the position component can be composed of three components (x, y, z). Further, the attribute data of any single primitive is generated by the rasterization module based on the attribute data of the vertices that constitute the primitive.

[0030] For example, assuming there are five primitives to be processed (represented by primitives 0-4), each primitive has three attributes (represented by attributes 0-2), and each attribute includes four attribute components (represented by x / y / z / w), in this step, all interpolation coefficients corresponding to attribute 0 and attribute component x of primitives 0-4 can be divided into the same data block. This data block contains the coefficients corresponding to attribute 0 and attribute component x of primitive 0, the coefficients corresponding to attribute 0 and attribute component x of primitive 1, ..., the coefficients corresponding to attribute 0 and attribute component x of primitive 4. Correspondingly, all interpolation coefficients corresponding to attribute 0 and attribute component y of primitives 0-4 can be divided into the same data block, ..., and so on, ultimately resulting in 12 data blocks to be stored.

[0031] Step 103: Store the at least two data blocks to be stored into a designated memory; wherein the data in any one of the data blocks to be stored is stored continuously in the designated memory.

[0032] This step involves storing interpolation coefficients into a designated memory using a rasterization module. Specifically, the rasterization module can write all interpolation coefficients for all attribute components of a single attribute of a primitive at a time, and through multiple writes, store the data from all data blocks to be stored contiguously in the designated memory. Taking the example in step 102, the interpolation coefficients for all components (x / y / z / w) of primitive 0 and attribute 0 in all data blocks to be stored can be written in parallel at once, ensuring that data belonging to the same data block is stored contiguously in the designated memory during writing. Alternatively, data from one data block to be stored can be written at a time; this embodiment of the invention does not limit this, as long as it ensures that the data within the same data block is stored contiguously in the designated memory.

[0033] Furthermore, the designated memory can be a note-based memory, which can contain multiple banks to support parallel access. The interpolation coefficients required for attribute interpolation operations are stored in different banks within the designated memory according to a specific arrangement order. Each attribute of each primitive has different interpolation coefficients, and each attribute can also include multiple attribute components. Therefore, the interpolation coefficients under different attribute components are also different, and the interpolation coefficients under an attribute component can also be represented by several categories. To represent a set of interpolation coefficients, it can be represented using multiple dimensions: attribute number, attribute component number, primitive number, and interpolation coefficient number.

[0034] To improve the efficiency of attribute interpolation operations, it is often necessary to process a group of fragments at once. These fragments typically come from different primitives and use different components of multiple attributes. Therefore, when interpolation coefficients need to be read, the interpolation coefficients of all primitives to be processed corresponding to one attribute component can be read at once. Furthermore, due to the characteristics of parallel computing, all interpolation coefficients of all primitives need to be read at once. In this embodiment of the invention, a contiguously stored data block contains all coefficients of all primitives for one attribute component. Thus, when the fragment shader performs attribute interpolation, it only needs to retrieve one data block at a time. However, in existing writing methods, when performing attribute interpolation, the data to be read at one time is scattered across multiple banks, which can sometimes lead to the data falling into different rows of the same bank, causing address conflicts and resulting in low read efficiency. For example, Figure 2 This is a storage diagram in the prior art, where Prim represents primitives, Attr represents attributes, A, B, and C represent coefficients, and x, y, z, and w represent components, such as... Figure 2 As shown, the total number of primitives is 4, with several attributes, and each row stores 32 data points. Assuming attribute (Attr) is 0, the address of the interpolation coefficient A corresponding to the attribute component x of primitive (Prim) 0 is 0, and the address increments by 1 for each additional interpolation coefficient. Therefore, when reading the interpolation coefficient corresponding to the attribute component x of attribute 0, the addresses to be read are 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, and 44, totaling 3*4 = 12 data points. In this case, using 4, 8, 16, or 32 banks will result in address conflicts. For example, addresses 0 and 32 will always fall on different rows within the same bank, preventing simultaneous readings and requiring additional clock cycles, leading to lower read efficiency. Note that different rows within the same bank correspond to different addresses.

[0035] The data processing method provided in this embodiment obtains the interpolation coefficients corresponding to the primitives to be processed; divides the interpolation coefficients of each primitive to be processed corresponding to the same attribute component in the same attribute into the same data block, obtaining at least two data blocks to be stored; and stores the at least two data blocks to be stored into a designated memory; wherein, the data in any of the data blocks to be stored is stored contiguously in the designated memory; the designated memory includes multiple memory banks, and data with consecutive addresses in the designated memory are stored in different memory banks. Since the data required for each read is divided into the same data block, and the data in the same data block is stored contiguously in the designated memory, it can be stored in different memory banks to a greater extent. In this way, the dispersion of the data to be read each time in the bank can be reduced, so that the data to be read each time is concentrated in a smaller number of consecutive banks as much as possible, thereby reducing the probability that the data to be read falls into different rows of the same bank, thus avoiding address conflicts to a certain extent and improving read efficiency.

[0036] Optionally, in this embodiment of the invention, the number of banks in the specified memory can be no less than the number of data items in any data block. This allows data to be stored in different banks to a greater extent, thereby avoiding the need to read data falling into different rows of the same bank and ensuring that address conflicts do not occur during subsequent reads. For example, taking the storage of 9 primitives to be processed, with each attribute component corresponding to 3 interpolation coefficients, a total of 3*9=27 data items need to be read at once. One data item can be in one bank, and in this case, a specified memory of 32 banks can be selected. Here, one data item can be an interpolation coefficient under one attribute component of a primitive. Corresponding to the characteristics of the arrangement method in this embodiment of the invention, subsequent data can always be read continuously. Therefore, as long as the number of reads does not exceed the number of banks (27<32), all reads will not cause bank conflicts.

[0037] Optionally, embodiments of the present invention may also perform the following steps:

[0038] Step S21: In response to a data read instruction, read the data block indicated by the data read instruction from at least two data blocks stored in a specified memory; wherein, the same data block includes interpolation coefficients of each primitive to be processed corresponding to the same attribute component in the same attribute.

[0039] In this embodiment of the invention, the data read instruction can be triggered when attribute interpolation is required. The data block indicated by the data read instruction can be the data block required for this attribute interpolation. The data block indicated by the data read instruction can be specified according to actual needs, and this embodiment of the invention does not impose any restrictions on this. It should be noted that the data block in this step can be a data block to be stored in a designated memory.

[0040] Step S22: Perform attribute interpolation operation based on the interpolation coefficients in the read data block.

[0041] Specifically, after obtaining all interpolation coefficients of all primitives of an attribute component of an attribute contained in a data block, the present invention can perform attribute interpolation operation through a specific attribute interpolation algorithm.

[0042] For example, attribute interpolation can be implemented using the Ap+Bq+C algorithm, where (p, q) is the position representation of the fragment in the primitive, and (A, B, C) are the interpolation coefficients under this position representation method. The interpolation coefficients can come from the primitive's own attributes, and the position representation comes from the fragment's position during rasterization. Therefore, the interpolation of a certain attribute remains unchanged for each fragment of the same primitive, but their positions are different. Conversely, for different attributes of the same fragment, the position representation remains unchanged. The fragment's position representation is usually stored in the fragment shader's register. This embodiment of the invention does not limit the method of obtaining (p, q). Specifically, after obtaining all the interpolation coefficients of an attribute component of an attribute contained in a data block, i.e., after obtaining (A, B, C) for all primitives of an attribute component of an attribute, the attribute interpolation operation can be performed using the aforementioned Ap+Bq+C algorithm.

[0043] In this embodiment of the invention, in response to a data read instruction, the data block indicated by the data read instruction is directly read from at least two data blocks stored in a designated memory. Each data block includes interpolation coefficients for each primitive to be processed corresponding to the same attribute component within the same attribute. Attribute interpolation is performed based on the interpolation coefficients in the read data block. Thus, when the fragment shader performs attribute interpolation, it only needs to directly read the data from the required data block. Since the data in the same required data block is stored contiguously in the designated memory, the probability of the required data falling into different rows of the same bank is reduced, thereby avoiding address conflicts during the read process to some extent, improving read efficiency and access performance.

[0044] Optionally, the above-mentioned at least two data blocks to be stored are stored consecutively in the designated memory according to a preset attribute component order.

[0045] In this context, attribute components are the different components corresponding to each attribute. Taking the color attribute as an example, it can include three components: R, G, and B. The preset attribute component order can be the reading order commonly used by the fragment shader when reading interpolation coefficients. Optionally, a first preset threshold can be set, and an attribute component order with a usage frequency greater than the first preset threshold can be selected as the preset attribute component order. The preset attribute component order can be the attribute component order used during attribute interpolation, and the first usage frequency can be the frequency with which the fragment shader uses the attribute component order during attribute interpolation.

[0046] For example, taking the attribute components R, G, and B mentioned above as an example, the preset attribute component order can be R, G, B, which allows the data block to be stored corresponding to R, the data block to be stored corresponding to G, and the data block to be stored corresponding to B to be stored consecutively in the specified memory in the order of R, G, B.

[0047] In this embodiment of the invention, at least two data blocks to be stored are consecutively stored in the designated memory according to a preset attribute component order. This ensures that the data arrangement in subsequently read data blocks conforms to the preset attribute component order, ensuring that the read data is more consistent with the attribute interpolation process, thereby improving the interpolation effect of attribute interpolation to a certain extent.

[0048] Optionally, the above operation of dividing the interpolation coefficients of each primitive to be processed corresponding to the same attribute component in the same attribute into the same data block may also include the following steps:

[0049] Step S41: Divide the interpolation coefficients of the same attribute component of the primitives to be processed into the same sub-data block.

[0050] In this invention, the same attribute component can correspond to multiple interpolation coefficients, and each interpolation coefficient can belong to a coefficient category. The specific coefficient category can be set according to actual needs, and this embodiment of the invention does not impose any restrictions on it. For example, the coefficient category can be one of the three categories (A, B, C) used in the above attribute interpolation algorithm. Optionally, this step can obtain the interpolation coefficients directly according to different coefficient categories while simultaneously obtaining them through the rasterization module; this embodiment of the invention does not impose any restrictions on this.

[0051] Specifically, a data block can contain all interpolation coefficients for all primitives of a given attribute component. When generating data blocks, the interpolation coefficients of primitives to be processed corresponding to the same attribute component within the same attribute can be directly divided into a single data block. The order of data within a data block can be set according to actual needs. Specifically, interpolation coefficients of the same coefficient category among the interpolation coefficients of primitives to be processed corresponding to the same attribute component within the same attribute can be divided into the same sub-data block, thus allowing interpolation coefficients of the same coefficient category to be stored contiguously in subsequently generated data blocks.

[0052] For example, the interpolation coefficients of the primitives to be processed corresponding to attribute component x in attribute 0 can be divided into sub-data block 1, sub-data block 2, and sub-data block 3.

[0053] Step S42: Arrange the sub-data blocks according to the coefficient category corresponding to each sub-data block in a preset coefficient category order to obtain the data blocks.

[0054] The preset coefficient category order can be pre-set according to actual needs. For example, the preset coefficient category order can be A, B, C, or B, C, A; this embodiment of the invention does not limit this. Optionally, a second preset threshold can be set, and a coefficient category order with a second usage frequency greater than the second preset threshold can be selected as the preset coefficient category order. The preset coefficient category order can be the coefficient category order used when performing attribute interpolation, and the second usage frequency can be the frequency of use of the coefficient category order used by the fragment shader when performing attribute interpolation.

[0055] Specifically, the coefficients of all primitives in the data block of the attribute component are divided into three sub-data blocks 1, 2, and 3. Taking the preset coefficient category order as B, C, and A as an example, the three sub-data blocks 1, 2, and 3 are arranged consecutively in the data block in the order of 2, 3, and 1.

[0056] Optionally, in each of the above sub-data blocks, the interpolation coefficients of all primitives corresponding to the coefficient category can also be arranged according to a preset primitive order. Specifically, taking primitive 0-4 as an example, if the preset primitive order is set to 0-4, then in this sub-data block, the interpolation coefficients of all primitives corresponding to the coefficient category are arranged according to primitive 0-4.

[0057] In this embodiment of the invention, interpolation coefficients of the same attribute component among the primitives to be processed are divided into the same sub-data block, and the sub-data blocks are arranged according to the coefficient category of each sub-data block in a preset coefficient category order to obtain a data block. By storing the data within the data block continuously according to the preset coefficient category order, it can be further ensured that the data arrangement in the subsequently read data blocks conforms to the preset coefficient category order, thereby improving the interpolation effect of attribute interpolation to a certain extent.

[0058] Optionally, embodiments of the present invention may further include the following steps:

[0059] Step S51: Detect the number of the primitives to be processed to obtain the target number.

[0060] The target number is the total number of primitives to be processed. Specifically, in this step, when obtaining the interpolation coefficients, the primitives that need to undergo attribute interpolation can be counted to obtain the final total number of primitives.

[0061] Step S52: If the number of storage units is an integer multiple of the target number, then the primitives to be processed are expanded so that the number of storage units is not an integer multiple of the target number.

[0062] The designated memory can be divided into multiple memory modules of equal size, i.e., storage banks, where data with consecutive addresses are stored in different banks. Specifically, in this embodiment, the total number of primitives requiring attribute interpolation can be obtained in advance. It is then determined whether the number of banks in the designated memory is an integer multiple of the total number of primitives. If so, it indicates that interpolation coefficients for different components of the same attribute of a primitive may be stored in different rows of the same bank, leading to write conflicts. For example, if the designated memory contains 16 banks and the total number of primitives to be stored is 4, the interpolation coefficients are stored according to the above arrangement. That is, the A, B, and C coefficients of the four primitives with attribute 0 and attribute component x are stored in one data block, and the A, B, and C coefficients are stored in three sub-data blocks. Each of the three sub-data blocks occupies 4 banks, so the data block actually occupies 3*4 banks. In this scenario, the interpolation coefficient A corresponding to attribute component x of attribute 0 of primitive 0 will be stored in bank0. Similarly, the interpolation coefficient B corresponding to attribute component y of attribute 0 of primitive 0 will also be stored in bank0. When writing all interpolation coefficients of primitive 0 and attribute 0 to a specified memory at once, the aforementioned attributes 0, attribute component x, coefficient A, and primitive 0, and attributes 0, attribute component y, coefficient B, and interpolation coefficients of primitive 0 will be simultaneously written to bank0, resulting in a write conflict. Therefore, to avoid this situation, the number of banks needs to be expanded so that it is not an integer multiple of the total number of primitives. This ensures that the last row stores only a portion of a sub-data block, preventing interpolation coefficients of the same attribute and primitive from being stored in different rows of the same bank.

[0063] It should be noted that since the number of memory banks included in the specified memory may vary in different scenarios, determining whether primitives need to be expanded based on whether the number of memory banks is an integer multiple of the target number can be applied to scenarios with different numbers of memory banks, ensuring that write conflicts can be avoided in various cases with different numbers of memory banks.

[0064] In this embodiment of the invention, the target number of primitives to be processed is obtained by detecting the number of primitives to be processed. If the number of storage units is an integer multiple of the target number, the number of primitives to be processed is expanded so that the number of storage units is not an integer multiple of the target number. In this way, when writing all the interpolation coefficients of a primitive's attribute, the interpolation coefficients of different components of that attribute will not be stored in the same storage unit, thereby avoiding write conflicts and improving write efficiency.

[0065] Optionally, the specified memory includes 2 nThere are multiple memory banks, where n is a positive integer, and data at consecutive addresses in the specified memory are stored in different memory banks. Embodiments of the present invention may further include the following steps:

[0066] Step S61: If the number of targets is detected to be even, the primitives to be processed are expanded so that the number of targets is not even.

[0067] In this embodiment, 2 can be selected. n The memory bank consists of 32 memory banks. Optionally, n can be 5, meaning the specified memory typically uses 32 memory banks. In cases where the number of memory banks is 2... n In cases where the total number of primitives is even, it indicates that interpolation coefficients for different components of that primitive's attribute may be stored in different rows of the same bank, leading to write conflicts. For example, if the specified memory has 32 banks and the total number of primitives to be stored is 4, the interpolation coefficients are stored according to the above arrangement: the A, B, and C coefficients of the four primitives with attribute 0 and attribute component x are stored in one data block, and the A, B, and C coefficients are each stored in three sub-data blocks. Each of the three sub-data blocks occupies 4 banks, so the data block actually occupies 3*4 banks. In this case, the interpolation coefficient A corresponding to attribute component x of primitive 0's attribute 0 will be stored in bank 0, and correspondingly, the interpolation coefficient C corresponding to attribute component z of primitive 0's attribute 0 will also be stored in bank 0. At this point, when all interpolation coefficients for primitive 0 and attribute 0 are written to the designated memory at once, the interpolation coefficients for attribute 0, attribute component x, coefficient A, primitive 0, and attribute 0, attribute component z, coefficient C, primitive 0 will be written to bank0 simultaneously, causing a write conflict. Therefore, to avoid this situation, the primitives need to be expanded so that the total number of primitives is not even, thus ensuring that only a portion of the data from a sub-data block is stored at the end of each row, preventing interpolation coefficients of the same attribute and primitive from being stored in different rows of the same bank. It should be noted that when the designated memory uses 2... n In the case of a single memory bank, the number of primitives that cause write conflicts is often a specific even number. In this case, expanding the number of primitives to an odd number can avoid write conflicts. Therefore, in this situation, by detecting whether the number of primitives to be processed is even, and if it is even, expanding the number to an odd number can avoid write conflicts. In this embodiment, to improve processing efficiency, when the total number of primitives to be processed is detected to be even, an expansion operation can be performed directly to make it odd.

[0068] Optionally, in another embodiment, when the number of primitives to be processed is detected to be even, it can be further checked whether the total number of primitives will cause a write conflict. If so, the primitives can be expanded, thus avoiding unnecessary expansion operations. For example, when the specified memory uses 32 memory banks and the total number of primitives to be processed is 6, when writing the interpolation coefficient of one attribute for one primitive at a time, the interpolation coefficients of the same attribute and the same primitive will not be stored in different rows of the same bank, thus avoiding write conflicts. In this case, it is not necessary to expand the primitives to be processed.

[0069] In this embodiment of the invention, when the target quantity is detected to be even, the primitives to be processed are expanded so that the target quantity is not even. Thus, when writing all the interpolation coefficients of a single attribute of a primitive, interpolation coefficients of different components of that attribute of the primitive are not stored in the same memory, thereby avoiding write conflicts and improving write efficiency.

[0070] Optionally, the above-described step of expanding the primitive to be processed may specifically include:

[0071] Step S71: Add a virtual element to the elements to be processed; the interpolation coefficients corresponding to the virtual element are default values.

[0072] When it is necessary to expand the primitives to be processed, a virtual primitive d can be added directly to the primitives to be processed while obtaining all interpolation coefficients. The interpolation coefficient data corresponding to the virtual primitive d can be the default value. Since the virtual primitive is a primitive that does not actually exist, the default value can be 0 in order to avoid affecting subsequent attribute interpolation operations.

[0073] In this embodiment of the invention, an expansion is achieved by adding a virtual element to the primitives to be processed, and a default value is set for the virtual element. Thus, when expansion of the primitives to be processed is needed, since the virtual element is a non-existent primitive, its default value is used for subsequent attribute interpolation, avoiding any impact on subsequent attribute interpolation operations.

[0074] Optionally, before storing the at least two data blocks to be stored into the designated memory, embodiments of the present invention may further include the following steps:

[0075] Step S81: Determine the address offset corresponding to each interpolation coefficient based on the attribute number, attribute component number, interpolation coefficient number, and primitive number corresponding to each interpolation coefficient in the data block to be stored; wherein, the address offset is positively correlated with the attribute number, attribute component number, interpolation coefficient number, and primitive number; the primitive numbers of the interpolation coefficients corresponding to each primitive to be processed in the same sub-data block are continuously distributed.

[0076] Step S82: Calculate the write address of each interpolation coefficient based on the address offset and the preset base address.

[0077] The attribute number indicates which attribute the interpolation coefficient belongs to. The number of attributes can be n+1, so the attribute number can be 0 to n. The attribute component number indicates which component of each attribute in the interpolation coefficient is represented, typically four components (x / y / z / w), and can also be 0 to n. The interpolation coefficient (three categories A, B, and C) number, also called the coefficient number, indicates which coefficient it belongs to, and can be 0 to 2. The primitive number indicates which primitive it belongs to, and can also be 0 to n.

[0078] The storage address of each interpolation coefficient can be calculated based on the address offset and the base address. The base address is the starting point of the specified memory, and the address offset is the amount of address offset relative to the base address. Specifically, the attribute number, attribute component number, and interpolation coefficient number of each interpolation coefficient in the same sub-data block are all the same and are arranged according to a preset primitive order. Correspondingly, the address offset of each interpolation coefficient in the same sub-data block is only related to the primitive number and is positively correlated due to the preset primitive order. Similarly, the attribute number and attribute component number of each interpolation coefficient in the same data block are all the same and are arranged according to a preset coefficient category order. Correspondingly, the address offset of each interpolation coefficient in each sub-data block in the same data block is only related to the coefficient number and primitive number and is positively correlated due to the preset coefficient category order. Similarly, the address offset is also positively correlated with the attribute number and attribute component number, which will not be elaborated further in this embodiment of the invention.

[0079] Specifically, in this embodiment, the formula for calculating the write and read addresses of a single interpolation coefficient can be as follows:

[0080] addr=base+((attrid*chancnt+chanid)*coeffcnt+coeffid)*primcnt+primid,

[0081] Where base represents the base address, atrid represents the attribute number, chancnt represents the number of attribute components, chanid represents the attribute component number, coeffcnt represents the number of coefficients (i.e., 3), coeffid represents the coefficient number, primcnt represents the number of primitives to be processed after adjustment, and primid represents the primitive number.

[0082] Specifically, primcnt0 can be used to represent the number of primitives to be processed before adjustment.

[0083] If the data type of primcnt0 is an integer, the adjusted number of primitives to be processed can be obtained by primcnt = |primcnt0 / 2| * 2 + 1. Specifically, by first rounding primcnt0 / 2 to the nearest integer and then multiplying by 2 and adding 1, the number of primitives to be processed is incremented by 1 when the number is even, and remains unchanged when the number is odd.

[0084] If primcnt0 is binary, you can directly change the least significant bit of primcnt0 to 1 while leaving the other bits unchanged to obtain primcnt.

[0085] Example, Figure 3 This is an example diagram of a data processing method provided in an embodiment of the present invention, wherein A: p0 / 1 / 2 / 3 / d sub-data blocks represent the 0th, 1st, 2nd, and 3rd primitives of coefficient A under attribute 0 and attribute component x, and an additional virtual primitive d.

[0086] by Figure 3 Taking the z-component of the C coefficient of attr0p0 as an example, with a base address of 0, the write and read addresses can be obtained as 55 according to the above formula. Specifically, converting the obtained address to binary, i.e., 00110111, gives the lower five bits (10111), which is the storage location of the interpolation coefficient in the 10111th memory bank, and the higher five bits (001) are the internal address of the interpolation coefficient in the 10111th memory bank. For... Figure 3 The scenario shown illustrates the following: For the data to be written: the attribute components of attribute 0 (attr0) corresponding to primitive 0 (p0): interpolation coefficients of x / y / z / w: A / B / C. The write addresses for these 12 data items can be 0, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, and 55, respectively, and their bank numbers can be 0, 5, 10, 15, 20, 25, 30, 3, 8, 13, 18, and 23, respectively, without causing bank conflicts. The bank number can be the lower 5 bits of the address. It should be noted that the number of primitives to be processed before expansion can be 1 to 8. Using different numbers of primitives to be processed can, to a certain extent, ensure that no bank conflicts occur when writing a set of data.

[0087] In this embodiment of the invention, the address offset corresponding to each interpolation coefficient is determined based on the attribute number, attribute component number, interpolation coefficient number, and primitive number corresponding to each interpolation coefficient in the data block to be stored. The address offset is positively correlated with the attribute number, attribute component number, interpolation coefficient number, and primitive number. The primitive numbers of the interpolation coefficients corresponding to each primitive to be processed in the same sub-data block are continuously distributed. The write address of each interpolation coefficient is calculated based on the address offset and a preset base address. Thus, writing the interpolation coefficients according to the storage address calculated from the attribute number, attribute component number, interpolation coefficient number, and primitive number ensures that all interpolation coefficients are stored in the designated memory in the order of attribute number, attribute component number, coefficient number, and primitive number, thereby ensuring the orderliness of the data arrangement to a certain extent.

[0088] Meanwhile, when the specified memory contains a power of 2 number of memory banks, the low and high bits of the address of a single interpolation coefficient are respectively the order of the memory bank where the interpolation coefficient is stored and the internal address of the memory bank, thereby reducing computational complexity and making it easy to implement.

[0089] The following describes an application scenario related to an embodiment of the present invention. A graphics application programming interface (API), such as OpenGL, defines the rendering pipeline and describes the process of converting graphics program data into the final image. Specifically, vertex data is transformed and calculated by the vertex shader, then enters the primitive assembly module to become basic graphics elements: primitives. After passing through the rasterization module, it becomes fragment data, i.e., pixels on the screen. The fragment data is calculated by the fragment shader to obtain the final pixel color. Modern graphics processors implement most of the functions of the rendering pipeline, which, exemplarily, may include programmable vertex and fragment shaders, as well as non-programmable rasterization functions.

[0090] Fragments obtained by rasterizing primitives containing a vertex inherit some of the vertex's attributes. The attributes of each fragment are obtained by interpolating the vertex attributes. Since the number of fragments is usually greater than the number of vertices, attribute interpolation in non-programmable rasterization is very costly. Therefore, in modern GPUs, attribute interpolation is often performed in the fragment shader. Thus, the data prepared for attribute interpolation by the rasterization module and transmitted to the fragment shader typically includes: a set of interpolation coefficients for each attribute of each primitive, and a position representation for each fragment. The position representation for each fragment is usually stored in the fragment shader's registers. To improve the efficiency of the fragment shader, it processes a group of fragments at a time. These fragments may come from different primitives and use different components of multiple different attributes. Therefore, the interpolation coefficients provided by the rasterization module for this group of fragments can include multiple dimensions such as primitive number, attribute number, attribute component number, and coefficient number. The rasterization module can prepare interpolation coefficients for this group of fragments first per attribute and then per primitive. Specifically, the initialization information for a set of interpolation coefficients can include: storage address, attribute number, total number of primitives in the set, primitive number, and interpolation coefficient data. The interpolation coefficient data can include three sets of coefficients (a, b, and c) corresponding to the four components of the attribute, totaling 12 floating-point data points. When the fragment shader performs interpolation calculations, it retrieves the coefficients of one attribute component at a time. Due to the parallel computing nature of the computation, all coefficients for all primitives must be retrieved at once.

[0091] In other words, a write access to the note storage writes all interpolation coefficients of all attribute components of a single attribute for one primitive at a time. A read access reads all interpolation coefficients of all primitives of a single attribute component for one primitive at a time. Therefore, a single write operation requires writing 12 data items simultaneously; a single read operation requires reading 3*n data items simultaneously, where n is the number of primitives contained in the segment (without loss of generality, let n be 1 to 8). Therefore, a specified memory can contain multiple banks to provide sufficient parallelism to support parallel access.

[0092] One approach uses a designated memory with an odd number of banks, which can, to some extent, prevent address conflicts during writes and reads. For example, assuming 31 banks are used... Figure 2In the case shown, the read addresses are still 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, but address 32 falls in bank1, and address 0 and address 32 no longer fall in the same bank. However, using an odd number of banks requires division to obtain the bank number and the address within the bank after calculating the address, which leads to greater implementation difficulty. The data processing method provided by this embodiment of the invention can use an even number of banks while avoiding conflicts. When the specified memory contains a power of 2 number of memory banks, the low and high bits of the address of the calculated single interpolation coefficient are the order of the memory bank where the interpolation coefficient is stored and the internal address of the memory bank, respectively, thereby reducing computational complexity and making it easier to implement.

[0093] Figure 4 This is a structural diagram of a data processing apparatus provided in an embodiment of the present invention. The apparatus 40 may include:

[0094] The acquisition module 401 is used to acquire the interpolation coefficients corresponding to the primitives to be processed;

[0095] The partitioning module 402 is used to partition the interpolation coefficients of each primitive to be processed that corresponds to the same attribute component in the same attribute into the same data block, so as to obtain at least two data blocks to be stored.

[0096] Storage module 403 is used to store the at least two data blocks to be stored into a designated memory; wherein, the data in any of the data blocks to be stored is stored continuously in the designated memory; the designated memory includes multiple memory banks, and data with consecutive addresses in the designated memory are stored in different memory banks.

[0097] Optionally, the device 40 further includes:

[0098] A reading module is configured to read, in response to a data reading instruction, a data block indicated by the data reading instruction from at least two data blocks stored in a specified memory; wherein the same data block includes interpolation coefficients of each primitive to be processed corresponding to the same attribute component in the same attribute.

[0099] The operation module is used to perform attribute interpolation operations based on the interpolation coefficients in the read data block.

[0100] Optionally, the at least two data blocks to be stored are stored consecutively in the designated memory according to a preset attribute component order.

[0101] Optionally, the partitioning module is specifically used for:

[0102] Interpolation coefficients of the same attribute component in the same attribute of the primitive to be processed are divided into the same sub-data block.

[0103] According to the coefficient category corresponding to each sub-data block, the sub-data blocks are arranged in a preset coefficient category order to obtain the data blocks.

[0104] Optionally, the device 40 further includes:

[0105] The detection module is used to detect the number of the primitives to be processed and obtain the target number.

[0106] The first expansion module is used to expand the primitives to be processed if the number of storage units is an integer multiple of the target number, so that the number of storage units is not an integer multiple of the target number.

[0107] Optionally, the designated memory includes 2 n The device 40 further includes: a storage bank, wherein n is a positive integer, and data at consecutive addresses in the specified memory are stored in different storage banks;

[0108] The second expansion module is used to expand the primitives to be processed when the number of targets is detected to be even, so that the number of targets is not even.

[0109] Optionally, the first expansion module or the second expansion module is specifically used to add a virtual graphic element to the graphic elements to be processed; the interpolation coefficient corresponding to the virtual graphic element is a default value.

[0110] Optionally, the device 40 further includes:

[0111] The first calculation module is used to determine the address offset corresponding to each interpolation coefficient based on the attribute number, attribute component number, interpolation coefficient number, and primitive number corresponding to each interpolation coefficient in the data block to be stored, before the storage module stores the at least two data blocks to be stored into the designated memory; wherein, the address offset is positively correlated with the attribute number, attribute component number, interpolation coefficient number, and primitive number; and the primitive numbers of the interpolation coefficients corresponding to each primitive to be processed in the same sub-data block are continuously distributed.

[0112] The second calculation module is used to calculate the write address of each interpolation coefficient based on the address offset and the preset base address.

[0113] In summary, the data processing apparatus provided in this embodiment of the invention obtains the interpolation coefficients corresponding to the primitives to be processed; divides the interpolation coefficients of each primitive to be processed corresponding to the same attribute component in the same attribute into the same data block to obtain at least two data blocks to be stored; and stores the at least two data blocks to be stored into a designated memory; wherein, the data in any of the data blocks to be stored is stored continuously in the designated memory; the designated memory includes multiple memory banks, and data with consecutive addresses in the designated memory are stored in different memory banks. Since the data required for each read is divided into the same data block, and the data in the same data block is stored continuously in the designated memory, it can be stored in different memory banks to a greater extent. In this way, the dispersion of the data to be read each time in the bank can be reduced, so that the data to be read each time is concentrated in a smaller number of consecutive banks as much as possible, thereby reducing the probability that the data to be read falls into different rows of the same bank, thus avoiding address conflicts to a certain extent and improving read efficiency.

[0114] The present invention also provides an electronic device, see [link to relevant documentation]. Figure 5 The system includes: a processor 501, a memory 502, and a computer program 5021 stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the various embodiments of the above-described data processing method.

[0115] The present invention also provides a readable storage medium, wherein when the instructions in the storage medium are executed by the processor of an electronic device, the electronic device is able to perform the steps of the embodiments of the above data processing methods.

[0116] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0117] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings herein. The required structure for constructing such systems is apparent from the above description. Furthermore, this invention is not directed to any particular programming language. It should be understood that the contents of the invention described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of the invention.

[0118] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0119] Similarly, it should be understood that, in order to simplify the invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, this disclosure should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into this detailed description, wherein each claim itself is a separate embodiment of the invention.

[0120] Those skilled in the art will understand that modules in the device of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0121] The various component embodiments of the present invention can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some or all of the components in the sorting device according to the present invention. The present invention can also be implemented as a device or apparatus program for performing part or all of the methods described herein. Such a program implementing the present invention can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

[0122] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0123] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0124] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0125] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A data processing method, characterized in that, The method includes: Obtain the interpolation coefficients corresponding to the primitives to be processed; The interpolation coefficients of each primitive to be processed corresponding to the same attribute component in the same attribute are divided into the same data block to obtain at least two data blocks to be stored. The at least two data blocks to be stored are stored in a designated memory; wherein, the data in any of the data blocks to be stored is stored contiguously in the designated memory; the designated memory includes multiple memory banks, and data with consecutive addresses in the designated memory are stored in different memory banks.

2. The method according to claim 1, characterized in that, The method further includes: In response to a data read instruction, a data block indicated by the data read instruction is read from at least two data blocks stored in a specified memory; wherein the same data block includes interpolation coefficients of each primitive to be processed corresponding to the same attribute component in the same attribute. Based on the interpolation coefficients in the read data block, attribute interpolation is performed.

3. The method according to claim 1 or 2, characterized in that, The at least two data blocks to be stored are stored consecutively in the designated memory according to the preset attribute component order.

4. The method according to claim 1 or 2, characterized in that, The step of dividing the interpolation coefficients of each primitive to be processed corresponding to the same attribute component in the same attribute into the same data block includes: Interpolation coefficients of the same attribute component in the same attribute of the primitive to be processed are divided into the same sub-data block. According to the coefficient category corresponding to each sub-data block, the sub-data blocks are arranged in a preset coefficient category order to obtain the data blocks.

5. The method according to claim 1, characterized in that, The method further includes: The number of the primitives to be processed is detected to obtain the target number; If the number of storage units is an integer multiple of the target number, then the primitives to be processed are expanded so that the number of storage units is not an integer multiple of the target number.

6. The method according to claim 5, characterized in that, The designated memory includes 2 n There are multiple memory banks, where n is a positive integer, and data at consecutive addresses in the specified memory are stored in different memory banks; The method further includes: If the number of targets is detected to be even, the primitives to be processed are expanded so that the number of targets is not even.

7. The method according to claim 5 or 6, characterized in that, The expansion of the primitives to be processed includes: A virtual element is added to the elements to be processed; the interpolation coefficients corresponding to the virtual element are default values.

8. The method according to claim 4, characterized in that, Before storing the at least two data blocks to be stored into the designated memory, the method further includes: Based on the attribute number, attribute component number, interpolation coefficient number, and primitive number corresponding to each interpolation coefficient in the data block to be stored, the address offset corresponding to the interpolation coefficient is determined; wherein, the address offset is positively correlated with the attribute number, attribute component number, interpolation coefficient number, and primitive number; the primitive numbers of the interpolation coefficients corresponding to each primitive to be processed in the same sub-data block are continuously distributed; The write address of each interpolation coefficient is calculated based on the address offset and the preset base address.

9. A data processing apparatus, characterized in that, The device includes: The acquisition module is used to acquire the interpolation coefficients corresponding to the primitives to be processed. The partitioning module is used to divide the interpolation coefficients of each primitive to be processed that corresponds to the same attribute component in the same attribute into the same data block, so as to obtain at least two data blocks to be stored. A storage module is used to store the at least two data blocks to be stored into a designated memory; wherein the data in any of the data blocks to be stored is stored contiguously in the designated memory; the designated memory includes multiple memory banks, and data with consecutive addresses in the designated memory are stored in different memory banks.

10. The apparatus according to claim 9, characterized in that, The device further includes: A reading module is configured to read a data block indicated by a data reading instruction from at least two data blocks stored in a specified memory in response to a data reading instruction; wherein the same data block includes interpolation coefficients of each primitive to be processed corresponding to the same attribute component in the same attribute; The operation module is used to perform attribute interpolation operations based on the interpolation coefficients in the read data block.

11. The apparatus according to claim 9 or 10, characterized in that, The at least two data blocks to be stored are stored consecutively in the designated memory according to the preset attribute component order.

12. The apparatus according to claim 9 or 10, characterized in that, The partitioning module is specifically used for: Interpolation coefficients of the same attribute component in the same attribute of the primitive to be processed are divided into the same sub-data block. According to the coefficient category corresponding to each sub-data block, the sub-data blocks are arranged in a preset coefficient category order to obtain the data blocks.

13. The apparatus according to claim 9, characterized in that, The device further includes: The detection module is used to detect the number of the primitives to be processed and obtain the target number. The first expansion module is used to expand the primitives to be processed if the number of storage units is an integer multiple of the target number, so that the number of storage units is not an integer multiple of the target number.

14. The apparatus according to claim 13, characterized in that, The designated memory includes 2 n There are multiple memory banks, where n is a positive integer, and data at consecutive addresses in the specified memory are stored in different memory banks; The device further includes: The second expansion module is used to expand the primitives to be processed when the number of targets is detected to be even, so that the number of targets is not even.

15. The apparatus according to claim 13 or 14, characterized in that, The first or second expansion module is specifically used to add a virtual graphic element to the graphic element to be processed; the interpolation coefficient corresponding to the virtual graphic element is a default value.

16. The apparatus according to claim 12, characterized in that, The device further includes: The first calculation module is configured to determine the address offset corresponding to each interpolation coefficient based on the attribute number, attribute component number, interpolation coefficient number, and primitive number corresponding to each interpolation coefficient in the data block to be stored, before the storage module stores the at least two data blocks to be stored into the designated memory; wherein, the address offset is positively correlated with the attribute number, attribute component number, interpolation coefficient number, and primitive number; and the primitive numbers of the interpolation coefficients corresponding to each primitive to be processed in the same sub-data block are continuously distributed; The second calculation module is used to calculate the write address of each interpolation coefficient based on the address offset and the preset base address.

17. An electronic device, characterized in that, include: A processor, a memory, and a computer program stored in the memory and executable on the processor, characterized in that the processor, when executing the program, implements the data processing method as described in any one of claims 1-8.

18. A readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the electronic device, the electronic device is able to perform the data processing method according to any one of claims 1-8.

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