A method of manufacturing a semiconductor device and a semiconductor device

Abstract

The application provides a semiconductor device manufacturing method and a semiconductor device. The method comprises the following steps: providing a semiconductor epitaxial structure with a p-type doped region; forming a mask layer and an isolation layer on the semiconductor epitaxial structure; performing mask etching on the isolation layer and the mask layer to form an opening and expose the p-type doped region; forming an ohmic metal layer on the residual isolation layer and the exposed p-type doped region; performing high-temperature annealing to form an ohmic metal contact layer on the part of the ohmic metal layer in contact with the p-type doped region; removing the other part of the ohmic metal layer on the residual isolation layer, and the residual isolation layer and the mask layer. The application adds the isolation layer between the ohmic metal layer and the mask layer, and forms the ohmic contact through one-step high-temperature annealing. The process can ensure that the ohmic contact formed through high-temperature annealing contains aluminum components, and at the same time, the metal piercing of the mask layer is inhibited, so that the low contact resistance and high reliability of the P-type ohmic contact are ensured.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a method for manufacturing a semiconductor device and the semiconductor device itself. Background Technology

[0002] Silicon carbide (SiC) possesses excellent properties such as a wide bandgap, high critical electric field, high thermal conductivity, and high electron saturation velocity, making it a prominent candidate for next-generation power semiconductor devices. Most mature processes currently used in silicon-based semiconductors, such as ion implantation, thermal oxidation, and self-aligned silicide technology, have been applied to SiC power devices and have achieved significant progress. However, many significant technical challenges remain. For example, achieving low contact resistance and high reliability ohmic contacts is one of the key technical problems limiting the performance of SiC electronic devices, allowing SiC materials to reach their optimal potential.

[0003] Silicon carbide ohmic contacts can be classified into P-type and N-type depending on the implantation method. Currently, there are two main methods for fabricating ohmic contacts: gold peeling and silicide self-alignment. Silicide self-alignment is widely used in silicon-based devices, and nickel-based self-alignment has also been reported in silicon carbide N-type ohmic contacts. Traditional self-alignment processes generally employ a two-step tempering process: first, low-temperature tempering to form silicides, then wet etching to remove unreacted metals, followed by high-temperature tempering to form the ohmic contact. Due to the influence of the metal work function and the SiC bandgap width, forming P-type ohmic contacts is more difficult than forming N-type ohmic contacts. Forming a good P-type ohmic contact generally requires the addition of aluminum components. However, during high-temperature tempering, the aluminum forming the silicide risks puncturing the silicon oxide. Therefore, the challenge in forming P-type ohmic contacts lies in how to incorporate aluminum components during high-temperature ohmic contact formation while ensuring that the aluminum does not puncture the silicon oxide. Summary of the Invention

[0004] This application provides a method for manufacturing a semiconductor device and the semiconductor device thereof, the method being able to ensure the formation of a P-type ohmic contact with low contact resistance and high reliability.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a method for manufacturing a semiconductor device, comprising: providing a semiconductor epitaxial structure with a p-type doped region; forming a mask layer on the semiconductor epitaxial structure and forming an isolation layer on the mask layer; performing photomask etching on the isolation layer and the mask layer to form a first opening in the isolation layer and the mask layer, exposing the p-type doped region in the semiconductor epitaxial structure; forming an ohmic metal layer on the remaining isolation layer and the exposed p-type doped region in the semiconductor epitaxial structure, wherein a portion of the ohmic metal layer is located above the p-type doped region in the semiconductor epitaxial structure, and other portions of the ohmic metal layer are located above the remaining isolation layer; performing a high-temperature tempering process to form an ohmic metal contact layer on the portion of the ohmic metal layer in contact with the p-type doped region; removing the other portions of the ohmic metal layer on the remaining isolation layer, and the remaining isolation layer and the mask layer.

[0006] The semiconductor epitaxial structure is a silicon carbide substrate, or includes a substrate and a silicon carbide epitaxial layer grown on the substrate.

[0007] The step of providing a semiconductor epitaxial structure with a p-type doped region includes: performing ion implantation on a silicon carbide substrate or a silicon carbide epitaxial layer to form the semiconductor epitaxial structure with the p-type doped region; wherein the silicon carbide substrate or the silicon carbide epitaxial layer includes N-type 4H-SiC or 6H-SiC.

[0008] The step of forming a mask layer on the semiconductor epitaxial structure includes: depositing silicon oxide on the semiconductor epitaxial structure to form the mask layer; wherein the silicon oxide deposition temperature is 100℃-500℃ and the thickness of the mask layer is 1000Å-10000Å.

[0009] The step of forming an isolation layer on the mask layer includes: setting an isolation layer on the mask layer using a magnetron sputtering process, wherein the isolation layer has a thickness of 1000A-5000A.

[0010] The step of forming an ohmic metal layer on the p-type doped region in the residual isolation layer and the exposed semiconductor epitaxial structure includes: sequentially depositing nickel, titanium, and aluminum on the p-type doped region in the residual isolation layer and the exposed semiconductor epitaxial structure to form the ohmic metal layer; or sequentially depositing nickel and aluminum on the p-type doped region in the residual isolation layer and the exposed semiconductor epitaxial structure to form the ohmic metal layer; or sequentially depositing titanium and aluminum on the p-type doped region in the residual isolation layer and the exposed semiconductor epitaxial structure to form the ohmic metal layer; wherein the atomic ratio of aluminum in the ohmic metal layer is 50% to 80%, and the thickness of the ohmic metal layer is 1000 Å to 3000 Å.

[0011] The step of performing high-temperature tempering treatment to form an ohmic metal contact layer in the portion of the ohmic metal layer in contact with the p-type doped region includes: performing a high-temperature tempering treatment at 900℃-1200℃ for 60 seconds to 300 seconds to form an ohmic metal contact layer in the portion of the ohmic metal layer in contact with the p-type doped region.

[0012] The method further includes, after the step of removing the remaining portion of the ohmic metal layer on the residual isolation layer, and the residual isolation layer and mask layer, forming an electrode on the ohmic metal contact layer; forming a passivation layer on the semiconductor epitaxial structure and the electrode; forming a second opening on the passivation layer corresponding to the electrode to expose a portion of the electrode, wherein the passivation layers on both sides of the second opening are at least partially located on the electrode.

[0013] The insulating layer includes at least one of titanium nitride, tungsten, tantalum carbide, tantalum nitride, tantalum silicide, tungsten carbide, tungsten nitride, tungsten silicide, zirconium carbide, zirconium nitride, zirconium silicide, niobium carbide, or niobium nitride.

[0014] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a semiconductor device, which is manufactured by the method described in any of the above-mentioned methods.

[0015] Unlike existing technologies, the semiconductor device manufacturing method provided in this application adds an isolation layer between the ohmic metal layer and the mask layer, then forms an ohmic contact through a one-step high-temperature tempering process, and finally removes unreacted metal and the isolation layer through wet etching. This process ensures that the high-temperature tempering process for forming the ohmic contact contains aluminum components, while suppressing metal penetration of the mask layer, thus ensuring the formation of a P-type ohmic contact with low contact resistance and high reliability. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0017] Figure 1 A schematic flowchart of the first embodiment of the method for manufacturing a semiconductor device provided in this application;

[0018] Figure 2 for Figure 1 A schematic diagram of the structure of one embodiment of step S11;

[0019] Figure 3 for Figure 1 A schematic diagram of the structure of one embodiment of step S12;

[0020] Figure 4 for Figure 1 A schematic diagram of the structure of one embodiment of step S13;

[0021] Figure 5 for Figure 1 A schematic diagram of the structure of one embodiment of step S14;

[0022] Figure 6 for Figure 1 A schematic diagram of the structure of one embodiment of step S16;

[0023] Figure 7 for Figure 1 A schematic diagram of the structure of one embodiment of step S16;

[0024] Figure 8 A schematic flowchart of a second embodiment of the method for manufacturing a semiconductor device provided in this application;

[0025] Figure 9 for Figure 8 A schematic diagram of the structure of one embodiment of step S17;

[0026] Figure 10 This is a schematic diagram of the structure of the semiconductor device provided in this application. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0028] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0029] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0030] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0031] Please see Figure 1 This is a flowchart illustrating the first embodiment of the semiconductor device fabrication method of this application, specifically including:

[0032] Step S11: Provide a semiconductor epitaxial structure with p-type doped regions.

[0033] In one embodiment, the semiconductor epitaxial structure is a silicon carbide substrate, or includes a substrate and a silicon carbide epitaxial layer grown on the substrate. The silicon carbide substrate or the silicon carbide epitaxial layer comprises N-type 4H-SiC or 6H-SiC.

[0034] During the fabrication process, ion implantation is performed on a silicon carbide substrate or a silicon carbide epitaxial layer to form the p-type doped semiconductor epitaxial structure. Specifically, if the semiconductor epitaxial structure is a silicon carbide substrate, ion implantation is performed on the semiconductor epitaxial structure to form the p-type doped semiconductor epitaxial structure. If the semiconductor epitaxial structure includes a substrate and a silicon carbide epitaxial layer grown on the substrate, ion implantation is performed on the silicon carbide epitaxial layer to form the p-type doped semiconductor epitaxial structure. In a specific embodiment, taking a silicon carbide epitaxial layer as an example, aluminum is ion implanted into the silicon carbide epitaxial layer at an ion implantation concentration of 10E18-10E21 cm⁻³ and a temperature of 1500℃-2000℃, which activates and forms the p-type doped region. It should be noted that a protective film (not shown in the figure) is present on the surface of the silicon carbide epitaxial layer when forming the p-type doped region. The protective film can be a 1-50 nm carbon film or a 1-2 μm photoresist after an ashing process. After forming the p-type doped region, the surface of the silicon carbide epitaxial layer with the protective film removed is subjected to high-temperature surface treatment to form a smooth passivated surface. Then, sacrificial oxidation is performed on the silicon carbide surface, and the sacrificial oxide layer is removed using a BOE solution (buffered oxide etchant). Please refer to [link / reference] for details. Figure 2 , Figure 2 In this semiconductor epitaxial structure, there is a substrate 21 and a silicon carbide epitaxial layer 22 grown on the substrate 21. The silicon carbide epitaxial layer 22 is ion implanted to form a p-type doped region 23.

[0035] Step S12: Form a mask layer on the semiconductor epitaxial structure and form an isolation layer on the mask layer.

[0036] For details, please see Figure 3 A mask layer 24 is formed on the semiconductor epitaxial structure, and an isolation layer 25 is formed on the mask layer 24.

[0037] In one embodiment, the mask layer 24 is silicon oxide, that is, silicon oxide is deposited on the semiconductor epitaxial structure to form the mask layer 24. The silicon oxide deposition temperature is 100℃-500℃, and the thickness of the mask layer 24 is 1000Å-10000Å. The silicon oxide deposition can be achieved using plasma-enhanced chemical vapor deposition (PECVD).

[0038] In one embodiment, an isolation layer 25 is formed on the mask layer using a magnetron sputtering process, wherein the isolation layer 25 has a thickness of 1000 Å-5000 Å.

[0039] In one embodiment, the insulating layer 25 is titanium nitride. Titanium nitride has high stability and melting point, and also acts as an insulating layer. Ohmic metals (especially aluminum) are at risk of penetrating silicon oxide during high-temperature tempering, and the higher the temperature, the higher the risk. Therefore, adding titanium nitride between the ohmic metal and silicon oxide prevents metal penetration.

[0040] In another embodiment, the insulating layer may also be at least one of tungsten, tantalum carbide, tantalum nitride, tantalum silicide, tungsten carbide, tungsten nitride, tungsten silicide, zirconium carbide, zirconium nitride, zirconium silicide, niobium carbide, or niobium nitride.

[0041] Step S13: Perform photomask etching on the isolation layer and mask layer to form openings in the isolation layer and mask layer, exposing the p-type doped region in the semiconductor epitaxial structure.

[0042] For specific details, please refer to... Figure 4 The isolation layer 25 and the mask layer 24 are etched using a photomask to form a first opening 26 in the isolation layer 25 and the mask layer 24. The etching is performed using ICP-RIE dry etching, and fluorine-based or chlorine-based gases are used for etching.

[0043] Step S14: An ohmic metal layer is formed on the residual isolation layer and the p-type doped region in the exposed semiconductor epitaxial structure.

[0044] Please combine Figure 5 An ohmic metal layer 27 is formed on the remaining isolation layer 25 and the exposed p-type doped region 23 in the semiconductor epitaxial structure. For example... Figure 5 As shown, a portion of the ohmic metal layer 27 is located above the p-type doped region 23 in the semiconductor epitaxial structure, while the other portion of the ohmic metal layer 27 is located above the remaining isolation layer 25.

[0045] In one embodiment, nickel, titanium, and aluminum are sequentially deposited on the residual isolation layer 25 and the exposed p-type doped region 23 in the semiconductor epitaxial structure to form the ohmic metal layer 27, that is, the ohmic metal layer 27 includes nickel, titanium, and aluminum.

[0046] In another embodiment, nickel and aluminum are sequentially deposited on the residual isolation layer 25 and the exposed p-type doped region 23 in the semiconductor epitaxial structure to form the ohmic metal layer 27; that is, the ohmic metal layer 27 includes nickel and aluminum.

[0047] In another embodiment, titanium and aluminum are sequentially deposited on the residual isolation layer 25 and the exposed p-type doped region 23 in the semiconductor epitaxial structure to form the ohmic metal layer 27; that is, the ohmic metal layer 27 includes titanium and aluminum.

[0048] In this process, aluminum accounts for 50% to 80% of the atomic ratio of the ohmic metal layer 27, and the thickness of the ohmic metal layer 27 is 1000 Å to 3000 Å.

[0049] Step S15: Perform a high-temperature tempering process to form an ohmic metal contact layer on the portion of the ohmic metal layer in contact with the p-type doped region.

[0050] Specifically, perform a high-temperature tempering treatment at 900℃-1200℃ for 60 seconds to 300 seconds to ensure it is compatible with the desired temperature.

[0051] The portion of the ohmic metal layer 27 that is in contact with the p-type doped region 23 (i.e. Figure 5 An ohmic metal contact layer is formed in the region shown in Figure 20.

[0052] Step S16: Remove the remaining portion of the ohmic metal layer on the residual isolation layer, as well as the residual isolation layer and mask layer.

[0053] 5. Please combine Figure 6 Wet etching is used to remove the ohmic metal layer 27 on the isolation layer 25. Please refer to...

[0054] Figure 7 The remaining isolation layer 25 and mask layer 24 are removed. In one embodiment, the isolation layer 25 is removed by wet etching, and the mask layer 24 is removed by BOE etching (buffered oxide etchant).

[0055] In this embodiment, an isolation layer 25 is added between the ohmic metal layer 27 and the mask layer 24. Then, an ohmic contact is formed through a one-step high-temperature tempering process. Finally, unreacted metal and the isolation layer are removed by wet etching. This process ensures that the high-temperature tempering process for forming the ohmic contact contains aluminum components while suppressing metal penetration of the mask layer 24, thus ensuring the formation of a low-contact-resistance, high-reliability P-type ohmic contact.

[0056] Please see Figure 8 , Figure 8 This is a schematic flowchart of the second embodiment of the semiconductor device manufacturing method of this application, and is consistent with the above. Figure 1 Compared to the first embodiment shown, this embodiment further includes the following after step S16:

[0057] Step S17: Form an electrode on the ohmic metal contact layer.

[0058] For specific details, please refer to... Figure 9An electrode 28 is formed on the ohmic metal contact layer to form the positive electrode of the device. The ohmic contact can improve the surge resistance of the device. The electrode 28 can be fabricated using a gold peeling process. In one embodiment, the electrode 28 is made of aluminum, and the aluminum electrode thickness is 4–5 micrometers. Of course, in other embodiments, the electrode 28 may also be made of copper or other metals or alloys.

[0059] Step S18: Form a passivation layer on the semiconductor epitaxial structure and the electrode.

[0060] See Figure 10 Silicon oxide or silicon nitride is deposited on the semiconductor epitaxial structure and electrodes to form a passivation layer 29. The passivation layer 29 is used to protect the device, reduce the surface electric field strength of the device, and increase the reliability of the device in high temperature and humid environment.

[0061] Step S19: A second opening is formed on the passivation layer corresponding to the electrode to expose part of the electrode, wherein the passivation layers on both sides of the second opening are at least partially located on the electrode.

[0062] Please refer to the specific details. Figure 10 A passivation layer 29 is deposited on the semiconductor epitaxial structure and the electrode 28. A second opening 30 is formed on the passivation layer 29 corresponding to the electrode 28, exposing part of the electrode 28 to facilitate subsequent packaging wire bonding. Specifically, the passivation layers 29 on both sides of the second opening 30 are at least partially located on the electrode 28.

[0063] In this embodiment, an isolation layer 25 is added between the ohmic metal layer 27 and the mask layer 24. An ohmic contact is then formed through a one-step high-temperature tempering process. Finally, unreacted metal and the isolation layer are removed by wet etching. This process ensures that the high-temperature tempering process for forming the ohmic contact contains aluminum components while suppressing metal penetration of the mask layer 24, thus ensuring the formation of a low-contact-resistance, high-reliability P-type ohmic contact.

[0064] This application also provides a semiconductor device, please refer to [link / reference needed]. Figure 10 The semiconductor device is fabricated through steps S11-S19 described above. This semiconductor device is a power semiconductor device and can be applied to systems such as home appliances, power electronic equipment, new energy vehicles, industrial control, power systems, and computer servers. It enables the efficient conversion, control, management, and use of electrical energy.

[0065] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: Provides a semiconductor epitaxial structure with a p-type doped region; A mask layer is formed on the semiconductor epitaxial structure, and an isolation layer is formed on the mask layer; Photomask etching is performed on the isolation layer and the mask layer to form a first opening in the isolation layer and the mask layer, exposing the p-type doped region in the semiconductor epitaxial structure; An ohmic metal layer is formed on the p-type doped region in the residual isolation layer and the exposed semiconductor epitaxial structure, wherein a portion of the ohmic metal layer is located above the p-type doped region in the semiconductor epitaxial structure, and the other portion of the ohmic metal layer is located above the residual isolation layer; wherein the ohmic metal layer contains aluminum, and the isolation layer is used to suppress aluminum from penetrating the mask layer. Perform a high-temperature tempering process to form an ohmic metal contact layer on a portion of the ohmic metal layer that is in contact with the p-type doped region. Remove the remaining portion of the ohmic metal layer on the remaining isolation layer, as well as the remaining isolation layer and mask layer.

2. The method according to claim 1, characterized in that, The semiconductor epitaxial structure is a silicon carbide substrate, or includes a substrate and a silicon carbide epitaxial layer grown on the substrate.

3. The method according to claim 2, characterized in that, The step of providing a semiconductor epitaxial structure with a p-type doped region includes: Ion implantation is performed on a silicon carbide substrate or a silicon carbide epitaxial layer to form a semiconductor epitaxial structure of the p-type doped region; The silicon carbide substrate or the silicon carbide epitaxial layer includes N-type 4H-SiC or 6H-SiC.

4. The method according to claim 1, characterized in that, The step of forming a mask layer on the semiconductor epitaxial structure includes: Silicon oxide is deposited on the semiconductor epitaxial structure to form the mask layer; wherein the silicon oxide deposition temperature is 100℃-500℃ and the thickness of the mask layer is 1000A-10000A.

5. The method according to claim 1, characterized in that, The step of forming an isolation layer on the mask layer includes: An isolation layer is formed on the mask layer using a magnetron sputtering process, and the thickness of the isolation layer is 1000A-5000A.

6. The method according to claim 1, characterized in that, The step of forming an ohmic metal layer on the residual isolation layer and the exposed p-type doped region in the semiconductor epitaxial structure includes: Nickel, titanium, and aluminum are sequentially deposited on the residual isolation layer and the exposed p-type doped region in the semiconductor epitaxial structure to form the ohmic metal layer; or Nickel and aluminum are sequentially deposited on the residual isolation layer and the exposed p-type doped region in the semiconductor epitaxial structure to form the ohmic metal layer; or Titanium and aluminum are sequentially deposited on the p-type doped region in the residual isolation layer and the exposed semiconductor epitaxial structure to form the ohmic metal layer. The atomic ratio of aluminum in the ohmic metal layer is 50% to 80%, and the thickness of the ohmic metal layer is 1000 Å to 3000 Å.

7. The method according to claim 1, characterized in that, The step of performing high-temperature tempering treatment to form an ohmic metal contact layer on the portion of the ohmic metal layer in contact with the p-type doped region includes: Perform a high-temperature tempering treatment at 900℃-1200℃ for 60 seconds to 300 seconds to form an ohmic metal contact layer on the portion of the ohmic metal layer that is in contact with the p-type doped region.

8. The method according to claim 1, characterized in that, After the step of removing the remaining portion of the ohmic metal layer on the residual isolation layer, and the remaining isolation layer and mask layer, the method further includes: An electrode is formed on the ohmic metal contact layer; A passivation layer is formed on the semiconductor epitaxial structure and the electrode; A second opening is formed on the passivation layer corresponding to the electrode, exposing a portion of the electrode, wherein the passivation layers on both sides of the second opening are at least partially located on the electrode.

9. The method according to claim 1, characterized in that, The insulating layer includes at least one of titanium nitride, tungsten, tantalum carbide, tantalum nitride, tantalum silicide, tungsten carbide, tungsten nitride, tungsten silicide, zirconium carbide, zirconium nitride, zirconium silicide, niobium carbide, or niobium nitride.

10. A semiconductor device, characterized in that, The semiconductor device is manufactured by the method described in any one of claims 1 to 9.

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