Semiconductor power module, motor controller and vehicle
By arranging conductive regions and power chips alternately on the substrate to form the bridge arm structure of a half-bridge circuit, the problems of large stray inductance and poor heat dissipation in semiconductor power modules are solved, achieving efficient current output and improved heat dissipation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BYD SEMICON CO LTD
- Filing Date
- 2021-11-12
- Publication Date
- 2026-06-02
AI Technical Summary
Existing semiconductor power modules suffer from problems such as large stray inductance, severe electromagnetic interference, and excessive chip space during the inverter process. In particular, the inductance increases when outputting high current, affecting heat dissipation and integration.
The design employs staggered conductive regions and power chips on a substrate to form the bridge arm structure of a half-bridge circuit. Parasitic inductance is reduced through mutual inductance, and heat dissipation is improved through an insulating substrate. The power chips are uniformly arranged within the conductive regions to optimize the structure.
It effectively reduces the parasitic inductance of the module, improves heat dissipation and integration, reduces switching losses, and enhances current output capability.
Smart Images
Figure CN116130446B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of vehicle technology, and in particular to a semiconductor power module, a motor controller, and a vehicle. Background Technology
[0002] Semiconductor power modules are widely used in industry. They are typically used in inverters to convert AC to DC or vice versa.
[0003] Semiconductor power modules have advantages such as high integration and small size. However, during the inverter process, the stray inductance of the circuit generates excessive voltage during the switching of the semiconductor chip, which causes electromagnetic interference due to damped oscillation and increases switching losses. At the same time, if a large current is to be output, multiple chips need to be connected in parallel, but this will make the chip occupy a larger space and the inductance will also increase. Summary of the Invention
[0004] The present invention aims to at least solve one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a semiconductor power module that can reduce the stray inductance of the entire module and improve the heat dissipation of the module.
[0005] The second objective of this invention is to provide a motor controller.
[0006] The third objective of this invention is to provide a vehicle.
[0007] To address the aforementioned problems, a first aspect of the present invention provides a semiconductor power module, comprising: a substrate having a first direction and a second direction orthogonal to each other; a first conductive region, a second conductive region, a third conductive region, and a fourth conductive region disposed at intervals on the substrate and arranged sequentially along the first direction of the substrate, wherein the first conductive region, the second conductive region, the third conductive region, and the fourth conductive region all extend along the second direction of the substrate, wherein the first conductive region and the third conductive region are used to receive DC signals, and the fourth conductive region is used to output AC signals; a first power chip and a second power chip, wherein the first power chip is connected to the first conductive region and the second conductive region respectively, and the second power chip is connected to the second conductive region, the third conductive region, and the fourth conductive region respectively.
[0008] According to the semiconductor power module of the present invention, based on the layout design of a first conductive region, a second conductive region, a third conductive region, and a fourth conductive region, by connecting a first power chip disposed in the second conductive region to the first conductive region, and connecting a second power chip disposed in the third conductive region to the second and fourth conductive regions, a first bridge arm and a second bridge arm of a half-bridge circuit can be formed after the circuit is connected. Mutual inductance is formed between the first bridge arm and the second bridge arm, thereby reducing the parasitic inductance of the entire module. Furthermore, based on the layout of the first conductive region, the second conductive region, the third conductive region, and the fourth conductive region, a plurality of first power chips and second power chips are evenly arranged in the four conductive regions, resulting in good heat dissipation performance, simple structure, and high integration.
[0009] In some embodiments, the first power chip and the second power chip are arranged in the first direction.
[0010] In some embodiments, there are multiple first power chips, which are arranged along the second direction and adjacent first power chips are staggered in the first direction; there are multiple second power chips, which are arranged along the second direction and adjacent second power chips are staggered in the first direction.
[0011] In some embodiments, the first power chip is disposed in the second conductive region, and the second power chip is disposed in the third conductive region.
[0012] In some embodiments, the first conductive region includes: a first main conductive portion extending along a second direction and used to receive the DC signal; a plurality of first conductive branches arranged along the second direction, the first conductive branches being connected to the first main conductive portion and extending along the first direction toward the second conductive region; wherein, there are multiple first power chips, at least one of the multiple first power chips is connected to the first main conductive portion of the first conductive region, and at least one of the multiple first power chips is connected to the first conductive branch of the first conductive region.
[0013] In some embodiments, the second conductive region includes: a second main conductive portion extending along a second direction; a plurality of second conductive branches arranged along the second direction, the second conductive branches being connected to the second main conductive portion and extending towards the first conductive region along the first direction; and a plurality of third conductive branches arranged along the second direction, the third conductive branches being connected to the second main conductive portion and extending towards the third conductive region along the first direction; wherein at least one of the plurality of first power chips is connected to the second main conductive portion of the second conductive region, at least one of the plurality of first power chips is connected to the second conductive branch of the second conductive region, there are multiple second power chips, at least one of the plurality of second power chips is connected to the second main conductive portion of the second conductive region, and at least one of the plurality of second power chips is connected to the third conductive branch of the second conductive region.
[0014] In some embodiments, the first conductive branch and the second conductive branch are arranged alternately along the second direction; the corresponding positions of each first conductive branch and the second main conductive branch are connected through the first power chip, and the corresponding positions of each second conductive branch and the first main conductive branch are connected through the first power chip.
[0015] In some embodiments, the third conductive region includes: a third main conductive portion extending along the second direction and used to receive the DC signal; a plurality of fourth conductive branches arranged along the second direction, the fourth conductive branches being connected to the third main conductive portion and extending along the first direction toward the second conductive region; and a plurality of fifth conductive branches arranged along the second direction, the fifth conductive branches being connected to the third main conductive portion and extending along the first direction toward the fourth conductive region; wherein at least one of the plurality of second power chips is connected to the fourth conductive branch of the third conductive region, and at least one of the plurality of second power chips is connected to the fifth conductive branch of the third conductive region.
[0016] In some embodiments, the third conductive branch and the fourth conductive branch are arranged alternately along the second direction; each fourth conductive branch and the corresponding position of the second main conductive part are connected through the second power chip, and each third conductive branch and the corresponding position of the fifth conductive branch are connected through the second power chip.
[0017] In some embodiments, the fourth conductive region includes: a fourth main conductive portion extending along the second direction and used to output the AC signal; a plurality of sixth conductive branches arranged along the second direction, the sixth conductive branches being connected to the fourth main conductive portion and extending toward the third conductive region; wherein at least one of the plurality of second power chips is connected to the fourth main conductive portion of the fourth conductive region, and at least one of the plurality of second power chips is connected to the sixth conductive branch of the fourth conductive region.
[0018] In some embodiments, the fifth conductive branch and the sixth conductive branch are arranged alternately along the second direction; each sixth conductive branch and the corresponding fourth conductive branch are connected through the second power chip, and each fifth conductive branch and the corresponding position of the fourth main conductive part are connected through the second power chip.
[0019] In some embodiments, at least one of the plurality of first power chips is disposed on the second conductive branch and connected to the first main conductive branch, and at least one of the plurality of first power chips is disposed on the second main conductive branch and connected to the first conductive branch.
[0020] In some embodiments, at least one of the plurality of second power chips is disposed on the fourth conductive branch and connected to the second main conductive branch and the sixth conductive branch respectively, and at least one of the plurality of second power chips is disposed on the fifth conductive branch and connected to the third conductive branch and the fourth main conductive branch respectively.
[0021] In some embodiments, the semiconductor power module further includes a fifth conductive region and a sixth conductive region, the fifth conductive region and the sixth conductive region being connected to both ends of the third conductive region, the fifth conductive region and the sixth conductive region being located on both sides of the first conductive region and the second conductive region respectively in the second direction and being spaced apart from the first conductive region and the second conductive region respectively; wherein, the third conductive region is connected to the DC signal through the fifth conductive region and the sixth conductive region.
[0022] In some embodiments, the first conductive region has a first DC connection point for connecting the DC signal on the side opposite to the second conductive region, the fifth conductive region has a second DC connection point for connecting the DC signal at the end away from the third conductive region, the sixth conductive region has a third DC connection point for connecting the DC signal at the end away from the third conductive region, and the fourth conductive region has an AC connection point on the side opposite to the third conductive region.
[0023] The first DC connection point, the second DC connection point, and the third DC connection point are located on one side of the substrate in the first direction and arranged along the second direction. The first DC connection point is located between the second DC connection point and the third DC connection point. The DC signals connected to the second DC connection point and the third DC connection point have the same polarity and the opposite polarity to the DC signals connected to the first DC connection point. The AC connection point is located on the other side of the substrate in the first direction.
[0024] In some embodiments, the semiconductor power module further includes: a seventh conductive region, the seventh conductive region being located on the side of the first conductive region away from the second conductive region and spaced apart from the first conductive region, the two ends of the seventh conductive region being connected to the fifth conductive region and the sixth conductive region respectively, and the third conductive region, the fifth conductive region, the sixth conductive region and the seventh conductive region together surrounding the first conductive region and the second conductive region.
[0025] In some embodiments, the semiconductor power module further includes a first small-signal conductive region disposed on the substrate; and a first small-signal input substrate disposed on the second conductive region. The first small-signal input substrate is connected to the first small-signal conductive region and the first power chip respectively, and is used to transmit a gate signal to the first power chip.
[0026] In some embodiments, the semiconductor power module further includes a second small-signal conductive region disposed on the substrate; and a second small-signal input substrate disposed on the third conductive region. The second small-signal input substrate is connected to the second small-signal conductive region and the second power chip respectively, for transmitting a gate signal to the second power chip.
[0027] In some embodiments, the semiconductor power module further includes: an insulating cover, the insulating cover being mounted on the substrate and covering the first conductive region, the second conductive region, the third conductive region, the fourth conductive region, the first power chip, and the second power chip.
[0028] A second aspect of the present invention provides a motor controller, the motor controller comprising: a heat dissipation base plate and a coolant channel, the heat dissipation base plate being mounted on the coolant channel; and a semiconductor power module according to the above embodiment, the semiconductor power module being disposed on the heat dissipation base plate.
[0029] According to the motor controller of the present invention, by employing the semiconductor power module provided in the above embodiments and placing it on a heat dissipation base plate, stray inductance in the circuit can be effectively reduced, and heat dissipation is good.
[0030] A third aspect of the present invention provides a vehicle, including: an electric motor and a motor controller as described in the above embodiments, wherein the motor controller is connected to the electric motor.
[0031] According to the present invention, by employing the motor controller provided in the above embodiments, the inductance can be reduced and the heat dissipation improved.
[0032] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0033] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:
[0034] Figure 1 This is a schematic diagram of a semiconductor power module according to an embodiment of the present invention;
[0035] Figure 2 This is a schematic diagram of the current flow direction of a semiconductor power module according to an embodiment of the present invention;
[0036] Figure 3 This is a schematic diagram of a semiconductor power module according to another embodiment of the present invention;
[0037] Figure 4 This is a top view of a semiconductor power module according to an embodiment of the present invention;
[0038] Figure 5 This is a schematic diagram of the plastic package of a semiconductor power module according to an embodiment of the present invention;
[0039] Figure 6 This is a perspective structural diagram of a semiconductor power module after molding, according to an embodiment of the present invention;
[0040] Figure 7 This is a side view of a semiconductor power module according to an embodiment of the present invention;
[0041] Figure 8 This is a schematic diagram of a semiconductor power module according to another embodiment of the present invention;
[0042] Figure 9 This is a schematic diagram of the structure of a motor controller according to an embodiment of the present invention;
[0043] Figure 10 This is a structural block diagram of a vehicle according to an embodiment of the present invention.
[0044] Figure label:
[0045] 100 vehicles;
[0046] Semiconductor power module 10; Motor controller 20;
[0047] Substrate 1; First conductive region 2; Second conductive region 3; Third conductive region 4; Fourth conductive region 5; First DC connection point 11; Second DC connection point 12; Third DC connection point 13; AC connection point 14; First power chip 6; Second power chip 7;
[0048] First main conductive section 21; First conductive branch 22; Second main conductive section 31; Second conductive branch 32; Third conductive branch 33; Third main conductive section 43; Fourth conductive branch 44; Fifth conductive branch 45; Fourth main conductive section 51; Sixth conductive branch 52; First small signal conductive area 8; Second small signal conductive area 9; First small signal input substrate 34; Second small signal input substrate 46; Fifth conductive area 101; Sixth conductive area 102; Seventh conductive area 103;
[0049] Coolant channel 15; heat dissipation base plate 16; motor 17. Detailed Implementation
[0050] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention are described in detail below.
[0051] To address the aforementioned problems, the first aspect of this invention proposes a semiconductor power module, which reduces the stray inductance of the entire module and improves its heat dissipation.
[0052] The following is for reference. Figures 1-8 A semiconductor power module according to an embodiment of the present invention is described.
[0053] like Figure 1 As shown, the semiconductor power module 10 includes a substrate 1 and a first conductive region 2, a second conductive region 3, a third conductive region 4 and a fourth conductive region 5 disposed on the substrate 1 and arranged sequentially along a first direction of the substrate 1, as well as a first power chip 6 and a second power chip 7.
[0054] In the embodiments, the substrate 1 can be an insulating substrate with high insulation strength, good thermal conductivity and stable chemical properties, such as insulating ceramics, such as Al2O3, AlN or Si3N4. Thus, by setting the insulating substrate 1, the electrical connection between the circuit and external devices such as heat sinks can be blocked, thus playing an insulating role. It can also provide a heat dissipation channel for the losses generated when the power chip is working, thereby improving the overall heat dissipation of the module.
[0055] The substrate 1 has a first direction and a second direction that are orthogonal to each other. That is, if the first direction is the length direction of the substrate 1, then the second direction is the width direction of the substrate 1; or, if the first direction is the width direction of the substrate 1, then the second direction is the length direction of the substrate 1. This can be set according to the actual situation, such as the shape of the substrate 1, and there is no restriction on it.
[0056] And, such as Figure 1 As shown, the first conductive region 2, the second conductive region 3, the third conductive region 4, and the fourth conductive region 5 are spaced apart to avoid short circuits caused by overlapping conductive regions. All four regions extend along a second direction of the substrate 1. Furthermore, the first conductive region 2 and the third conductive region 4 are used to receive DC signals, and the fourth conductive region 5 is used to output AC signals, thereby realizing the power conversion function of the semiconductor power module 10.
[0057] In this process, copper layers are attached to both sides of substrate 1 through a printing process. The copper layer on one side of substrate 1 is etched to form the four conductive areas mentioned above. Thus, a three-layer substrate can be formed between substrate 1 and the conductive areas, namely copper layer-ceramic layer-copper layer. Therefore, the back side of the substrate, which is away from the conductive areas, is a whole piece of bare copper, and the front side of the substrate, which is where the conductive areas are located, is the etched copper layer. The etched copper layer forms a conductive channel, which is then electrically connected to form the half-bridge circuit of semiconductor power module 10.
[0058] Specifically, refer to Figure 2 As shown, based on the first power chip 6 being connected to the first conductive region 2 and the second conductive region 3 respectively, and the second power chip 7 being connected to the second conductive region 3, the third conductive region 4, and the fourth conductive region 5 respectively, when multiple first power chips 6 and multiple first power chips 7 are provided, a portion of the first power chips 6 and a portion of the second power chips 7 can form the first bridge arm of a half-bridge circuit, such as the upper bridge arm of the half-bridge circuit, and another portion of the first power chips 6 and another portion of the second power chips 7 can form the second bridge arm of a half-bridge circuit, such as the lower bridge arm of the half-bridge circuit. Thus, when the semiconductor power module 10 is connected, mutual inductance is formed between the first bridge arm and the second bridge arm, which cancels out the inductance, thereby reducing the parasitic inductance of the entire module. Simultaneously, the arrangement of the first conductive region 2, the second conductive region 3, the third conductive region 4, and the fourth conductive region 5 along the first direction of the substrate 1 also facilitates the uniform distribution of the first power chips 6 and the second power chips 7 in the four conductive regions, avoiding a compact arrangement of the power chips. This helps to reduce inductance while increasing heat dissipation and improving current output capability.
[0059] In the embodiments, the power chip can use silicon or silicon carbide or other semiconductor materials as the substrate. For example, the power chip can use a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or it can use a device that combines an IGBT (Insulated Gate Bipolar Transistor) and an FRD (Fast Recovery Diode). There are no restrictions on this.
[0060] Provided that electrical connections are achieved between the power chip and different conductive areas, there are no restrictions on the arrangement of the power chip and the different conductive areas. For example, the power chip can be fixed to the corresponding conductive area by soldering or bonding, or it can be suspended in the corresponding conductive area. Furthermore, each power chip can use leads to achieve electrical connections between different conductive areas, for example... Figure 3 As shown, the first power chip 6 in the second conductive region 3 is connected to the first conductive region 2 via leads; or, each power chip can be electrically connected between different conductive regions by copper bonding, without limitation.
[0061] The number of the first power chip 6 and the second power chip 7 can be set according to actual needs and there is no limit to this. For example, Figure 1 The semiconductor power module 10 shown contains 6 first power chips 6 and 6 second power chips 7. Considering the need for high current output, the number of power chips can be increased, such as... Figure 3 As shown, the semiconductor power module 10 contains 7 first power chips 6 and 7 second power chips 7. It should be noted that the total number of first power chips 6 is the same as the total number of second power chips.
[0062] In the embodiments, the design shape of the first conductive region 2, the second conductive region 3, the third conductive region 4, and the fourth conductive region 5 can be a regular conductive region, such as a square conductive region, or an irregular conductive region, such as two conductive regions being staggered or matched, etc., and there is no limitation on this.
[0063] In this embodiment, in practical application, the semiconductor power module 10 needs to be packaged. For example, a plastic encapsulation method can be used, which is the process of injection molding the semi-finished semiconductor power module 10 into a plastic package. Specifically, the semiconductor power module 10 is packaged into a plastic package... Figure 4 All structures in the semiconductor power module 10 shown are mounted in a frame and encapsulated to form a molded module. The encapsulated semiconductor power module 10 is as follows: Figure 5, Figure 6 and Figure 7 As shown. Alternatively, a potting method can be used, which involves encapsulating the semi-finished semiconductor power module 10 with insulating materials such as silicone gel. Specifically, the process involves... Figure 4 All structures in the semiconductor power module 10 shown are mounted within a frame, and silicone gel is filled into the frame to form a potting module. It should be noted that the semiconductor power module 10 is a half-bridge power module, which can be used in a half-bridge circuit or a three-phase full-bridge circuit. Specifically, for the molding process, a single semiconductor power module 10 forms a molded body, i.e., one half-bridge circuit forms one molded body; for the potting process, either a single semiconductor power module 10 can form a potting body, i.e., one half-bridge circuit forms one potting body, or three semiconductor power modules 10 can form a potting body, i.e., a three-phase full-bridge circuit composed of three half-bridge circuits forms one potting body.
[0064] According to the semiconductor power module 10 of the present invention, based on the layout design of the first conductive region 2, the second conductive region 3, the third conductive region 4, and the fourth conductive region 5, by connecting the first power chip 6 disposed in the second conductive region 3 to the first conductive region 2, and the second power chip 7 disposed in the third conductive region 4 to the second conductive region 3 and the fourth conductive region 5, the first and second arms of the half-bridge circuit can be formed after the circuit is connected. Mutual inductance is formed between the first and second arms, thereby reducing the parasitic inductance of the entire module. Furthermore, based on the layout of the first conductive region 2, the second conductive region 3, the third conductive region 4, and the fourth conductive region 5, a plurality of first power chips 6 and second power chips 7 are evenly arranged in the four conductive regions, resulting in good heat dissipation performance, simple structure, and high integration. In addition, by using an insulating substrate 1, a heat dissipation channel can also be provided for the losses generated during the operation of the power chips, thereby improving the overall heat dissipation of the module.
[0065] In some embodiments, the first power chip 6 and the second power chip 7 are arranged in a first direction, for example... Figure 1 As shown, along the first direction, six first power chips 6 are disposed in the second conductive region 3 and electrically connected to the first conductive region 2, and six second power chips 7 are disposed in the third conductive region 4 and electrically connected to the second conductive region 3 and the fourth conductive region 5. Thus, the first power chips 6 and the second power chips 7 are arranged separately in the first direction, which allows the first power chips 6 and the second power chips 7 to be connected in series in the first direction to form a half-bridge circuit of the semiconductor power module 10, reducing the parasitic inductance of the entire module. At the same time, it can also avoid the problem of increased heat caused by the compact layout of the power chips.
[0066] In some embodiments, such as Figure 1As shown, there are multiple first power chips 6, which are arranged along a second direction with adjacent first power chips 6 staggered in the first direction; there are also multiple second power chips 7, which are arranged along a second direction with adjacent second power chips 7 staggered in the first direction. Therefore, by staggering the power chips arranged along the second direction, the inductance can be reduced while further improving the heat dissipation of the module.
[0067] In some embodiments, such as Figure 1 As shown, when the DC signal connected to the first conductive region 2 is a negative signal and the DC signal connected to the third conductive region 4 is a positive signal, the first power chip 6 is disposed in the second conductive region 3 and the second power chip 7 is disposed in the third conductive region 4. Thus, under the premise of realizing the power conversion function of the semiconductor power module 10, the first power chip 6 and the second power chip 7 are connected in series to form a half-bridge circuit of the semiconductor power module 10, thereby reducing the parasitic inductance of the entire module.
[0068] In some embodiments, such as Figure 8 As shown, the first conductive region 2 includes a first main conductive portion 21 and a plurality of first conductive branches 22 arranged along a second direction. The first main conductive portion 21 extends along the second direction and is used to receive DC signals. The first conductive branches 22 are connected to the first main conductive portion 21 and extend along a first direction toward the second conductive region 3. Multiple first power chips 6 are present, with at least one of the multiple first power chips 6 connected to the first main conductive portion 21 of the first conductive region 2, and at least one of the multiple first power chips 6 connected to the first conductive branch 22 of the first conductive region 2. This arrangement allows mutual inductance to be formed within the semiconductor power module 10 during operation, effectively reducing the parasitic inductance of the entire module. It also optimizes the internal structural layout of the semiconductor power module 10, improving the integration of the entire module. Furthermore, based on the arrangement of the first main conductive portion 21 and the first conductive branches 22, the multiple first power chips 6 can be evenly arranged, rather than connecting multiple first power chips 6 to the same conductive part of the conductive region, thereby avoiding the problem of increased heat due to a compact power chip layout and improving the heat dissipation of the module. In some embodiments, such as... Figure 8As shown, the second conductive region 3 includes a second main conductive portion 31, a plurality of second conductive branches 32 arranged along a second direction, and a plurality of third conductive branches 33 arranged along the second direction. The second main conductive portion 31 extends along the second direction; the second conductive branches 32 are connected to the second main conductive portion 31 and extend along a first direction toward the first conductive region 2; and the third conductive branches 33 are connected to the second main conductive portion 31 and extend along the first direction toward the third conductive region 4. At least one of the plurality of first power chips 6 is connected to the second main conductive portion 31 of the second conductive region 3, and at least one of the plurality of first power chips 6 is connected to the second conductive branch 32 of the second conductive region 3. There are multiple second power chips 7, with at least one of the multiple second power chips 7 connected to the second main conductive portion 31 of the second conductive region 3, and at least one of the multiple second power chips 7 connected to the third conductive branch 33 of the second conductive region 3. This configuration not only allows mutual inductance to be formed within the semiconductor power module 10 during operation, effectively reducing the parasitic inductance of the entire module, but also optimizes the internal structural layout of the semiconductor power module 10, which is beneficial to improving the integration of the entire module. In addition, based on the layout of the second main conductive part 31, the second conductive branch 32 and the third conductive branch 33, multiple first power chips 6 and multiple second power chips 7 can be evenly arranged, rather than arranged in the same conductive part where multiple power chips are connected to the conductive area. This avoids the problem of increased heat caused by the compact layout of power chips and improves the heat dissipation of the module.
[0069] In some embodiments, the first conductive branch 22 and the second conductive branch 32 are arranged alternately along a second direction; the corresponding positions of each first conductive branch 22 and the second main conductive part 31 are connected through a first power chip 6, and the corresponding positions of each second conductive branch 32 and the first main conductive part 31 are connected through a first power chip 6. Thus, by arranging the first conductive branch 22 and the second conductive branch 32 in an alternating manner, adjacent first power chips 6 can be staggered in the first direction, thereby improving the heat dissipation of the module.
[0070] Furthermore, based on the layout of the first conductive region 2 and the second conductive region 3, any number of first conductive branches 22 and second conductive branches 32 matching any number of first conductive branches 22 can be set. Thus, when the first power chip 6 is arranged in the first conductive region 2 and the second conductive region 3, it is applicable to both even-numbered and odd-numbered power chips. It is no longer limited to a symmetrical arrangement, and the placement method is diversified, with low cost and simple structure.
[0071] In some embodiments, such as Figure 8As shown, the third conductive region 4 includes a third main conductive part 43, a plurality of fourth conductive branches 44 arranged along the second direction, and a plurality of fifth conductive branches 45 arranged along the second direction.
[0072] The third main conductive portion 43 extends along the second direction and is used to receive DC signals; the fourth conductive branch 44 is connected to the third main conductive portion 43 and extends along the first direction toward the second conductive region 3; the fifth conductive branch 45 is connected to the third main conductive portion 43 and extends along the first direction toward the fourth conductive region 5. At least one of the plurality of second power chips 7 is connected to the fourth conductive branch 44 of the third conductive region 4, and at least one of the plurality of second power chips 7 is connected to the fifth conductive branch 45 of the third conductive region 4. This configuration not only forms mutual inductance within the semiconductor power module 10 during operation, effectively reducing the parasitic inductance of the entire module, but also optimizes the internal structural layout of the semiconductor power module 10, which is beneficial to improving the integration of the entire module. In addition, based on the layout of the fourth conductive branch 44 and the fifth conductive branch 45, the plurality of second power chips 7 can be evenly arranged, rather than arranged in a manner where multiple power chips are connected to the same conductive part of the conductive region, thereby avoiding the problem of increased heat caused by the compact layout of power chips and improving the heat dissipation of the module.
[0073] In some embodiments, the third conductive branch 33 and the fourth conductive branch 44 are arranged alternately along the second direction; each fourth conductive branch 44 is connected to the corresponding position of the second main conductive part 31 through the second power chip 7, and each third conductive branch 33 is connected to the corresponding position of the fifth conductive branch 45 through the second power chip 7. Thus, by arranging the third conductive branch 33 and the fourth conductive branch 44 in an alternating manner, adjacent second power chips 7 can be staggered in the first direction, thereby improving the heat dissipation of the module.
[0074] In some embodiments, such as Figure 8As shown, the fourth conductive region 5 includes a fourth main conductive portion 51 and a plurality of sixth conductive branches 52 arranged along a second direction. The fourth main conductive portion 51 extends along the second direction and is used to output AC signals; the sixth conductive branches 52 are connected and extend towards the third conductive region 4; at least one of the plurality of second power chips 7 is connected to the fourth main conductive portion 51 of the fourth conductive region 5, and at least one of the plurality of second power chips 7 is connected to the sixth conductive branch 52 of the fourth conductive region 5. This arrangement not only forms mutual inductance within the semiconductor power module 10 during operation, effectively reducing the parasitic inductance of the entire module, but also optimizes the internal structural layout of the semiconductor power module 10, improving the integration of the entire module. Furthermore, based on the arrangement of the sixth conductive branches 52, the plurality of second power chips 7 can be evenly arranged, rather than being arranged with multiple power chips connected to the same conductive part of the conductive region, thereby avoiding the problem of increased heat due to a compact power chip layout and improving the heat dissipation of the module.
[0075] In some embodiments, the fifth conductive branch 45 and the sixth conductive branch 52 are arranged alternately along the second direction; each sixth conductive branch 52 and the corresponding fourth conductive branch 44 are connected through the second power chip 7, and each fifth conductive branch 45 and the corresponding position of the fourth main conductive part 51 are connected through the second power chip 7. Thus, by arranging the fifth conductive branch 45 and the sixth conductive branch 52 in an alternating manner, adjacent second power chips 7 can be staggered in the first direction, thereby improving the heat dissipation of the module.
[0076] Furthermore, based on the layout of the second conductive region 3, the third conductive region 4, and the fourth conductive region 5, any number of fourth conductive branches 44, fifth conductive branches 45, and sixth conductive branches 52 can be set. Thus, when the second power chip 7 is arranged in the second conductive region 3, the third conductive region 4, and the fourth conductive region 5, it is applicable to both even-numbered and odd-numbered power chips. It is no longer limited to a symmetrical arrangement, and the placement method is diversified, with low cost and simple structure.
[0077] In some embodiments, such as Figure 8As shown, at least one of the plurality of first power chips 6 is disposed on the second conductive branch 32 and connected to the first main conductive branch 21, and at least one of the plurality of first power chips 6 is disposed on the second main conductive branch 31 and connected to the first conductive branch 22. This arrangement optimizes the internal structural layout of the semiconductor power module 10. When the number of first power chips 6 is increased, the number of second conductive branches 32 can be adjusted accordingly to accommodate the first power chips 6, improving the module's flexibility and increasing the overall integration. It also facilitates the formation of mutual inductance within the semiconductor power module 10 during operation, effectively reducing the parasitic inductance of the entire module.
[0078] In some embodiments, such as Figure 8 As shown, at least one of the plurality of second power chips 7 is disposed on the fourth conductive branch 44 and is connected to the second main conductive branch 31 and the sixth conductive branch 52 respectively; at least one of the plurality of second power chips 7 is disposed on the fifth conductive branch 45 and is connected to the third conductive branch 33 and the fourth main conductive branch 51. This arrangement optimizes the internal structural layout of the semiconductor power module 10. When the number of second power chips 7 is increased, the number of fifth conductive branches 45 can be adjusted accordingly to accommodate the second power chips 7, improving the module's flexibility and increasing the overall integration. It also facilitates the formation of mutual inductance within the semiconductor power module 10 during operation, thereby effectively reducing the parasitic inductance of the entire module.
[0079] In some embodiments, the first conductive region 2 and the third conductive region 4 each have a DC connection point for receiving DC signals, and the fourth conductive region has an AC connection point for outputting AC signals. In practical applications, the semiconductor power module 10 can be electrically connected to the DC connection point of the corresponding conductive region through a DC terminal, and electrically connected to the AC connection point of the fourth conductive region through an AC terminal. Thus, the semiconductor power module 10 can be connected to the outside through the DC and AC terminals to receive DC signals sent from the outside and output AC signals to the outside, thereby realizing the function of power conversion.
[0080] The location of each DC connection point within its corresponding conductive region can be determined based on actual conditions, such as the shape of each conductive region. For example, all DC connection points can be located on either side of substrate 1, or each DC connection point can be arbitrarily located, such as on different sides of substrate 1; there are no restrictions on this. Similarly, the location of the AC connection point within the fourth conductive region can be determined based on actual conditions; there are no restrictions on this.
[0081] In some embodiments, the semiconductor power module 10 further includes a fifth conductive region 101 and a sixth conductive region 102, which are respectively connected to the two ends of the third conductive region 4, for example... Figure 1 or Figure 8 As shown, the fifth conductive region 101 and the sixth conductive region 102 are respectively connected to both ends of the third conductive region 4 to form an integrated conductive region; the fifth conductive region 101 and the sixth conductive region 102 are located on both sides of the first conductive region 2 and the second conductive region 3 respectively in the second direction and are spaced apart from the first conductive region 2 and the second conductive region 3 respectively; wherein, the third conductive region 4 receives a DC signal through the fifth conductive region 101 and the sixth conductive region 102. Thus, by connecting the fifth conductive region 101 and the sixth conductive region 102 to the third conductive region 4 respectively, a DC signal can be received on the same side of the substrate 1 and led to the third conductive region 4 through the fifth conductive region 101 and the sixth conductive region 102. That is to say, a DC signal can be received on the same side of the semiconductor power module 10, thereby reducing the difficulty of subsequent processes.
[0082] In some embodiments, such as Figure 1 As shown, the first conductive region 2 has a first DC connection point 11 for receiving a DC signal on the side opposite to the second conductive region 3; the fifth conductive region 101 has a second DC connection point 12 for receiving a DC signal on the end away from the third conductive region 4; the sixth conductive region 102 has a third DC connection point 13 for receiving a DC signal on the end away from the third conductive region 4; and the fourth conductive region 5 has an AC connection point 14 on the side opposite to the third conductive region 4. This arrangement ensures that the first DC connection point 11, the second DC connection point 12, and the third DC connection point 13 are located on the same side of the substrate 1, thereby reducing the complexity of the subsequent packaging process.
[0083] Among them, such as Figure 1 As shown, the first DC connection point 11, the second DC connection point 12 and the third DC connection point 13 are located on one side of the first direction of the substrate 1 and arranged along the second direction. The first DC connection point 11 is located between the second DC connection point 12 and the third DC connection point 13, and the AC connection point 14 is located on the other side of the first direction of the substrate.
[0084] The DC signals connected to the second DC connection point 12 and the third DC connection point 13 have the same polarity but opposite polarity to the DC signal connected to the first DC connection point 11. That is, if the DC signal connected to the third DC connection point 13 and the second DC connection point 12 is positive, then the DC signal connected to the first DC connection point 11 is negative. For example... Figure 1As shown; or, if the DC signal connected to the third DC connection point 13 and the second DC connection point 12 is negative, then the DC signal connected to the first DC connection point 11 is positive.
[0085] Specifically, with Figure 1 For example, in practical applications, the first DC connection point 11 of the first conductive region 2 is connected to the negative terminal, the second DC connection point 12 of the fifth conductive region 101 is connected to the positive terminal, the third DC connection point 13 of the sixth conductive region 102 is connected to the positive terminal, and the AC connection point 14 of the fourth conductive region 5 is connected to the AC terminal. Specifically, refer to... Figure 2 As shown, the second DC connection point 12 and the third DC connection point 13 are high-potential DC terminals, and the first DC connection point 11 is a low-potential DC terminal. The first DC connection point 11, the second DC connection point 12, and the third DC connection point 13 are arranged on the same side of the substrate 1, and the AC connection point 14 is arranged opposite to the above three DC connection terminals. With this configuration, after the half-bridge circuit of the semiconductor power module 10 is connected, the high-potential DC terminal is connected to the AC connection point 14 to form the first bridge arm of the half-bridge circuit, and the AC connection point 14 is connected to the low-potential DC terminal to form the second bridge arm of the half-bridge circuit. Thus, mutual inductance is formed between the circuit formed by the first bridge arm and the circuit formed by the second bridge arm within the semiconductor power module 10, thereby reducing the parasitic inductance of the entire module.
[0086] Understandably, in practical applications, the DC and AC terminals used for connection to the DC and AC connection points are made of copper, which has good electrical and thermal conductivity, in order to achieve the connection between the semiconductor power module 10 and external devices.
[0087] In some embodiments, such as Figure 8 As shown, the semiconductor power module 10 also includes a seventh conductive region 103. The seventh conductive region 103 is located on the side of the first conductive region 2 facing away from the second conductive region 3 and is spaced apart from the first conductive region 2. The two ends of the seventh conductive region 103 are respectively connected to the fifth conductive region 101 and the sixth conductive region 102. Figure 8 As shown, the seventh conductive region 103, the fifth conductive region 101, the sixth conductive region 102 and the third conductive region 4 are connected to each other to form an integrated conductive region; the third conductive region 4, the fifth conductive region 101, the sixth conductive region 102 and the seventh conductive region 103 together surround the first conductive region 2 and the second conductive region 3.
[0088] In some embodiments, such as Figure 8 As shown, the semiconductor power module 10 also includes a first small signal conductive region 8 and a first small signal input substrate 34.
[0089] The first small signal conductive region 8 is disposed on the substrate 1; the first small signal input substrate 34 is disposed on the second conductive region 3. The first small signal input substrate 34 is connected to the first small signal conductive region 8 and the first power chip 6 respectively, and is used to transmit the gate signal to the first power chip 6. That is, the gate signal of the first power chip 6 is separately led out by the first small signal input substrate 34 at the second conductive region 3, so that the small signal in the circuit can be effectively output to facilitate the control of the small signal in the circuit.
[0090] Specifically, for example Figure 8 As shown, a substrate can be electrically connected between the first power chips 6 interleaved in the second conductive region 3, such as at the second main conductive part 31, to serve as the first small signal input substrate 34. The first small signal input substrate 34 is electrically connected to the first small signal conductive region 8. For example, the two can be connected by a lead wire, thereby electrically connecting the control terminal of the first power chip 6 to the first small signal input substrate 34. Thus, the gate signal is transmitted to the first power chip 6 through the first small signal conductive region 8 and the first small signal input substrate 34, thereby achieving the purpose of controlling the first power chip 6 and realizing the output of small signals in the circuit, which facilitates the subsequent control of small signals.
[0091] In some embodiments, such as Figure 8 As shown, the semiconductor power module 10 also includes a second small signal conductive region 9 and a second small signal input substrate 46.
[0092] The second small signal conductive region 9 is disposed on the substrate 1; the second small signal input substrate 46 is disposed on the third conductive region 4. The second small signal input substrate 46 is connected to the second small signal conductive region 9 and is used to transmit the gate signal to the second power chip 7. That is, the gate signal of the second power chip 7 is separately led out by the second small signal input substrate 46 at the third conductive region 4, so that the small signal in the circuit can be effectively output to facilitate the control of the small signal in the circuit.
[0093] Specifically, for example Figure 8 As shown, a substrate can be electrically connected between the second power chips 7, which are staggered in the third conductive region 4, such as at the third main conductive part 43, to serve as the second small signal input substrate 46. The second small signal input substrate 46 is electrically connected to the second small signal conductive region 9. For example, the two can be connected by a lead wire, thereby electrically connecting the control terminal of the second power chip 7 to the first small signal input substrate 34. Thus, the gate signal is transmitted to the second power chip 7 through the second small signal conductive region 9 and the second small signal input substrate 46, so as to achieve the purpose of controlling the second power chip 7, realizing the output of small signals in the circuit, and facilitating subsequent control of small signals.
[0094] Furthermore, in the embodiments, the first small signal input substrate 34 or the second small signal input substrate 46 includes at least a conductive layer and an insulating layer. The insulating layer is electrically connected to the corresponding main conductive portion, such as by soldering or bonding it to the corresponding main conductive portion, or by suspending it above the corresponding main conductive portion while being electrically connected to it; there are no limitations on this. When the first small signal input substrate 34 or the second small signal output substrate 46 is positioned, the insulating layer of the first small signal input substrate 34 or the second small signal input substrate 46 is electrically connected to the corresponding main conductive portion, and the conductive layer of the first small signal input substrate 34 or the second small signal input substrate 46 is electrically connected to the corresponding small signal conductive area.
[0095] In this embodiment, the positions of the first small-signal conductive region 8 and the second small-signal conductive region 9 on the substrate 1 can be set according to actual conditions, and there is no limitation thereto. For example, Figure 8 As shown, the first small signal conductive region 8 extending along the first direction of the substrate 1 and the second small signal conductive region 9 extending along the first direction of the substrate 1 are respectively located on both sides of the fourth conductive region 5 in the second direction. Alternatively, the first small signal conductive region 8 is located on one side of the second conductive region 3 to facilitate connection with the first small signal input substrate 34; the second small signal conductive region 9 is located on one side of the third conductive region 4 to facilitate connection with the second small signal input substrate 46.
[0096] In some embodiments, the semiconductor power module 10 further includes an insulating cover, which is mounted on the substrate 1 and covers the first conductive region 2, the second conductive region 3, the third conductive region 4, the fourth conductive region 56, the first power chip, and the second power chip 7, so as to serve as insulation and protection for the device.
[0097] In summary, the semiconductor power module 10 according to the present invention has the advantages of high integration, good heat dissipation performance and simple structure.
[0098] A second aspect of the present invention provides a motor controller, such as... Figure 9 As shown, the motor controller 20 includes a heat dissipation base plate 16, a coolant channel 15, and a semiconductor power module 10 provided in the above embodiment.
[0099] The heat dissipation base plate 16 is mounted on the coolant channel 15; at least one semiconductor power module 10 is disposed on the heat dissipation base plate 16.
[0100] For example, such as Figure 9 As shown, three semiconductor power modules 10 connected in parallel are arranged in a straight line, and a heat dissipation base plate 18 is welded to their bottom. The coolant channel 15 has a groove, like a water channel. The heat dissipation base plate 16 is installed on the groove of the coolant channel 15 to dissipate heat from the semiconductor power modules 10. The design process is simple, easy to implement and convenient to operate.
[0101] In the embodiments, the semiconductor power module 10 provided by the above embodiments has a uniform structure and good heat dissipation effect. The motor controller 20 can be applied to various coolant channel applications, such as series coolant channels or parallel coolant channels, which improves the application flexibility of the motor controller 20. Moreover, the stray inductance in the circuit is small when applied.
[0102] According to the present invention, the motor controller 20, by employing the semiconductor power module 10 provided in the above embodiment and disposed on the heat dissipation base plate 16, can effectively reduce stray inductance in the circuit and has good heat dissipation.
[0103] A third aspect of the present invention provides a vehicle, such as Figure 10 As shown, the vehicle 100 includes a motor 17 and a motor controller 20 provided in the above embodiment, wherein the semiconductor power module 10 of the motor controller 20 is connected to the motor 17.
[0104] According to the vehicle 100 of the present invention, by employing the motor controller 20 provided in the above embodiments, inductance can be reduced and heat dissipation can be improved.
[0105] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.
[0106] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
Claims
1. A semiconductor power module, characterized in that, include: A substrate having a first direction and a second direction orthogonal to each other; A first conductive region, a second conductive region, a third conductive region, and a fourth conductive region are spaced apart on the substrate and arranged sequentially along a first direction of the substrate. The first conductive region, the second conductive region, the third conductive region, and the fourth conductive region all extend along a second direction of the substrate. The first conductive region and the third conductive region are used to receive DC signals, and the fourth conductive region is used to output AC signals. A first power chip and a second power chip, wherein the first power chip is connected to the first conductive region and the second conductive region respectively, and the second power chip is connected to the second conductive region, the third conductive region and the fourth conductive region respectively; There are multiple first power chips, and the multiple first power chips are arranged along the second direction with adjacent first power chips staggered in the first direction; There are multiple second power chips, which are arranged along the second direction and adjacent second power chips are staggered in the first direction; The first conductive region includes: A first main conductive portion extends along the second direction and is used to connect to the DC signal; A plurality of first conductive branches are arranged along the second direction, the first conductive branches are connected to the first main conductive portion and extend along the first direction toward the second conductive region; Wherein, at least one of the plurality of the first power chips is connected to the first main conductive portion of the first conductive region, and at least one of the plurality of the first power chips is connected to the first conductive branch of the first conductive region; The second conductive region includes: The second main conductive portion extends along the second direction; A plurality of second conductive branches are arranged along the second direction, the second conductive branches are connected to the second main conductive part and extend along the first direction toward the first conductive area; A plurality of third conductive branches are arranged along the second direction, the third conductive branches being connected to the second main conductive portion and extending along the first direction toward the third conductive region; In this configuration, at least one of the plurality of first power chips is connected to the second main conductive portion of the second conductive region, at least one of the plurality of first power chips is connected to the second conductive branch of the second conductive region, at least one of the plurality of second power chips is connected to the second main conductive portion of the second conductive region, and at least one of the plurality of second power chips is connected to the third conductive branch of the second conductive region.
2. The semiconductor power module according to claim 1, characterized in that, Also includes: The fifth conductive region and the sixth conductive region are respectively connected to both ends of the third conductive region. The fifth conductive region and the sixth conductive region are respectively located on both sides of the first conductive region and both sides of the second conductive region in the second direction and are respectively spaced apart from the first conductive region and the second conductive region. The third conductive region is connected to the DC signal through the fifth and sixth conductive regions.
3. The semiconductor power module according to claim 2, characterized in that, Also includes: The seventh conductive region is located on the side of the first conductive region opposite to the second conductive region and is spaced apart from the first conductive region. The two ends of the seventh conductive region are respectively connected to the fifth conductive region and the sixth conductive region. The third conductive region, the fifth conductive region, the sixth conductive region and the seventh conductive region together surround the first conductive region and the second conductive region.
4. The semiconductor power module according to claim 1, characterized in that, The first power chip and the second power chip are arranged in the first direction.
5. The semiconductor power module according to claim 1, characterized in that, The first power chip is disposed in the second conductive region, and the second power chip is disposed in the third conductive region.
6. The semiconductor power module according to claim 1, characterized in that, The first conductive branch and the second conductive branch are arranged alternately along the second direction; The corresponding positions of each of the first conductive branches and the second main conductive parts are connected through the first power chip, and the corresponding positions of each of the second conductive branches and the first main conductive parts are connected through the first power chip.
7. The semiconductor power module according to claim 1, characterized in that, The third conductive region includes: A third main conductive part extends along the second direction and is used to connect the DC signal; A plurality of fourth conductive branches are arranged along the second direction, the fourth conductive branches being connected to the third main conductive portion and extending along the first direction toward the second conductive region; A plurality of fifth conductive branches are arranged along the second direction, the fifth conductive branches being connected to the third main conductive portion and extending along the first direction toward the fourth conductive region; At least one of the plurality of second power chips is connected to the fourth conductive branch of the third conductive region, and at least one of the plurality of second power chips is connected to the fifth conductive branch of the third conductive region.
8. The semiconductor power module according to claim 7, characterized in that, The third conductive branch and the fourth conductive branch are arranged alternately along the second direction; Each of the fourth conductive branches and the corresponding position of the second main conductive branch are connected through the second power chip, and each of the third conductive branches and the corresponding position of the fifth conductive branch are connected through the second power chip.
9. The semiconductor power module according to claim 7, characterized in that, The fourth conductive region includes: A fourth main conductive part extends along the second direction and is used to output the alternating current signal; A plurality of sixth conductive branches are arranged along the second direction, the sixth conductive branches being connected to the fourth main conductive portion and extending toward the third conductive region; At least one of the plurality of second power chips is connected to the fourth main conductive portion of the fourth conductive region, and at least one of the plurality of second power chips is connected to the sixth conductive branch of the fourth conductive region.
10. The semiconductor power module according to claim 9, characterized in that, The fifth conductive branch and the sixth conductive branch are arranged alternately along the second direction; Each of the sixth conductive branches and the corresponding fourth conductive branch are connected through the second power chip, and each of the fifth conductive branches and the corresponding position of the fourth main conductive part are connected through the second power chip.
11. The semiconductor power module according to claim 1, characterized in that, At least one of the plurality of first power chips is disposed on the second conductive branch and connected to the first main conductive branch, and at least one of the plurality of first power chips is disposed on the second main conductive branch and connected to the first conductive branch.
12. The semiconductor power module according to claim 9, characterized in that, At least one of the plurality of second power chips is disposed on the fourth conductive branch and is respectively connected to the second main conductive branch and the sixth conductive branch; at least one of the plurality of second power chips is disposed on the fifth conductive branch and is respectively connected to the third conductive branch and the fourth main conductive branch.
13. The semiconductor power module according to claim 2, characterized in that, The first conductive region has a first DC connection point for connecting the DC signal on the side opposite to the second conductive region; the fifth conductive region has a second DC connection point for connecting the DC signal on the end away from the third conductive region; the sixth conductive region has a third DC connection point for connecting the DC signal on the end away from the third conductive region; and the fourth conductive region has an AC connection point on the side opposite to the third conductive region. The first DC connection point, the second DC connection point, and the third DC connection point are located on one side of the substrate in the first direction and arranged along the second direction. The first DC connection point is located between the second DC connection point and the third DC connection point. The DC signals connected to the second DC connection point and the third DC connection point have the same polarity and the opposite polarity to the DC signals connected to the first DC connection point. The AC connection point is located on the other side of the substrate in the first direction.
14. The semiconductor power module according to claim 1, characterized in that, Also includes: A first small signal conductive region is disposed on the substrate; A first small signal input substrate is disposed in the second conductive region. The first small signal input substrate is connected to the first small signal conductive region and the first power chip respectively, and is used to transmit a gate signal to the first power chip.
15. The semiconductor power module according to claim 1, characterized in that, Also includes: The second small signal conductive region is disposed on the substrate; The second small signal input substrate is disposed in the third conductive region and is connected to the second small signal conductive region and the second power chip respectively, for transmitting gate signals to the second power chip.
16. The semiconductor power module according to claim 1, characterized in that, Also includes: An insulating cover is mounted on the substrate and covers the first conductive region, the second conductive region, the third conductive region, the fourth conductive region, the first power chip, and the second power chip.
17. A motor controller, characterized in that, include: A heat dissipation base plate and a coolant channel, wherein the heat dissipation base plate is installed in the coolant channel; The semiconductor power module according to any one of claims 1-16 is disposed on the heat dissipation base plate.
18. A vehicle, characterized in that, include: Electric motor; The motor controller according to claim 17 is connected to the motor.