A switched capacitor converter

Abstract

This application belongs to the field of switching power supply technology, specifically relating to a switched capacitor converter. An auxiliary circuit is added between the two branches to transfer the charge of one branch to the other branch during the dead time when all main power transistors are off, thereby achieving zero-voltage turn-on of all main power transistors and reducing switching losses.

Description

Technical Field

[0001] This application belongs to the field of switching power supply technology, specifically relating to a switched capacitor converter. Background Technology

[0002] Traditional inductive DC-DC converters, such as buck, boost, and buck-boost converters, are widely used in 5G base stations, server power supplies, and mobile phone motherboards to convert between different voltages. However, due to significant switching and inductance losses, inductive DC-DC converters typically have low conversion efficiency. Applications such as high-energy-consuming 5G communication and high-power fast charging for mobile phones demand much higher conversion efficiency from inductive DC-DC converters. Traditional inductive DC-DC converters can no longer meet these efficiency requirements.

[0003] Compared to inductors, capacitors have a higher energy density. Therefore, switched-capacitor converters, which use capacitors for energy transfer, have a much higher conversion efficiency than inductive DC-DC converters and are widely used in various high-efficiency applications. Dickson-type switched-capacitor converters are widely adopted due to their low equivalent impedance.

[0004] like Figure 1 The diagram shows an existing Dickson-type 4:1 switched-capacitor converter, comprising eight power transistors (Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8), three capacitors (C1, C2, and C3), an input capacitor CIN, an output capacitor COUT, and an output load IOUT. In terms of control, power transistors Q1, Q3, Q5, and Q7 are driven by the same control signal, as are power transistors Q2, Q4, Q6, and Q8. Both control signals are 50% duty cycle square wave signals with complementary waveforms. This Dickson-type 4:1 switched-capacitor converter can make the output voltage VOUT 1 / 4 of the input voltage VIN, i.e., VIN = 4 * VOUT. The voltage differences between the three capacitors are VC1 = VOUT, VC2 = 2 * VOUT, and VC3 = 3 * VOUT.

[0005] While existing Dickson-type 4:1 switched-capacitor converters have no turn-off or inductance losses, they still require overcoming the parasitic capacitances Cds and Cgd when the power transistors are turned on, resulting in some turn-on losses. For high-voltage, low-current applications, the higher the voltage difference between Cds and Cgd, the greater their proportion in the turn-on losses, limiting further improvements in the conversion efficiency of the 4:1 Dickson switched-capacitor converter. Summary of the Invention

[0006] This application addresses the aforementioned problems by proposing a switched-capacitor converter. By adding auxiliary circuitry, zero-voltage turn-on of all main power transistors can be achieved, reducing switching losses. Furthermore, this switched-capacitor converter can be an N:1 Dickson switched-capacitor converter, where N is an integer greater than or equal to 3.

[0007] On one hand, this application provides a switched capacitor converter, including a first branch, a second branch, an auxiliary circuit, N common power transistors and N-1 capacitors, wherein N is an integer greater than or equal to 3; the first branch includes a first power transistor and a second power transistor, the second branch includes a third power transistor and a fourth power transistor, the first end of the second power transistor and the first end of the third power transistor are connected to the output terminal of the switched capacitor converter, the second end of the second power transistor and the first end of the first power transistor are connected through a first node, the second end of the third power transistor and the first end of the fourth power transistor are connected through a second node, and the second end of the first power transistor and the second end of the fourth power transistor are grounded.

[0008] The input terminal of the switched capacitor converter is connected to the output terminal of the switched capacitor converter through N common power transistors connected in sequence. Each of the N-1 capacitors corresponds to its two adjacent common power transistors, and each capacitor is connected between its two adjacent common power transistors. In any two adjacent capacitors connected to the N common power transistors, one capacitor is connected to the first node and the other capacitor is connected to the second node.

[0009] The two ends of the auxiliary circuit are connected to the first node and the second node respectively. The first power transistor, the second power transistor, the third power transistor, the fourth power transistor and N common power transistors are the main power transistors. The auxiliary circuit is used to transfer the charge of one of the first and second nodes to the other node during the dead time when all the main power transistors are turned off, so that the voltage difference between the two ends of each main power transistor becomes zero, and each main power transistor is turned on with zero voltage.

[0010] In some embodiments, when N=4, the N shared power transistors include a fifth power transistor, a sixth power transistor, a seventh power transistor, and an eighth power transistor, and the N-1 capacitors include a first capacitor, a second capacitor, and a third capacitor; the first terminal of the eighth power transistor is the input terminal of the switched capacitor converter and is connected to the external input voltage; the second terminal of the eighth power transistor is connected to the first terminal of the third capacitor and the first terminal of the seventh power transistor; the second terminal of the seventh power transistor is connected to the first terminal of the second capacitor and the first terminal of the sixth power transistor; the second terminal of the sixth power transistor is connected to the first terminal of the first capacitor and the first terminal of the fifth power transistor; the second terminal of the fifth power transistor is connected to the first terminal of the second power transistor and the first terminal of the third power transistor, and the second terminal of the fifth power transistor is also connected to the output terminal of the switched capacitor converter; the second terminals of the first capacitor and the second terminal of the third capacitor are connected to the first node, and the second terminal of the second capacitor is connected to the second node.

[0011] In some embodiments, when N is an integer greater than or equal to 5, the N common power transistors include a first common power transistor, a second common power transistor, ..., the (N-3)th common power transistor, the (N-2)th common power transistor, the (N-1)th common power transistor and the Nth common power transistor connected in sequence, and the N-1 capacitors include a first capacitor, a second capacitor, a third capacitor, ..., the (N-1)th capacitor.

[0012] The input terminal of the switched capacitor converter is connected to the output terminal of the switched capacitor converter in sequence through the Nth common power transistor, the (N-1)th common power transistor, the (N-2)th common power transistor, the (N-3)th common power transistor, ..., the second common power transistor and the first common power transistor.

[0013] The first terminal of the first capacitor is connected between the first common power transistor and the second common power transistor, and the second terminal of the first capacitor is connected to the first node, so that M out of N-1 capacitors are connected to the first node, and NM-1 out of N-1 capacitors are connected to the second node. When N is even, M = N / 2, and when N is odd, M = (N-1) / 2.

[0014] In some embodiments, when N is even, the (N-1)th capacitor is the 2M-1th capacitor, the first terminal of the 2M-1th capacitor is connected between the (N-1)th common power transistor and the Nth common power transistor, and the second terminals of the first capacitor, the third capacitor, ..., and the 2M-1th capacitor are connected to the first node; when N is odd, the (N-1)th capacitor is the 2(NM-1)th capacitor, the first terminal of the 2(NM-1)th capacitor is connected between the (N-1)th common power transistor and the Nth common power transistor, and the second terminals of the second capacitor, ..., and the 2(NM-1)th capacitor are connected to the second node.

[0015] In some embodiments, the auxiliary circuit includes a ninth power transistor, a tenth power transistor, an eleventh power transistor, a twelfth power transistor, and an inductor; the first terminal of the ninth power transistor is connected to the first node of the first branch, the second terminal of the ninth power transistor is connected to the first terminal of the tenth power transistor and the first terminal of the inductor, and the second terminal of the tenth power transistor is grounded; the second terminal of the inductor is connected to the first terminal of the eleventh power transistor and the first terminal of the twelfth power transistor, the second terminal of the eleventh power transistor is grounded, and the second terminal of the twelfth power transistor is connected to the second node of the second branch.

[0016] In some embodiments, the operating timing of the switched capacitor converter includes four stages, as described below.

[0017] Phase 1: The second, fourth, sixth, eighth, tenth, and twelfth power transistors are turned on, while the other power transistors are turned off; the input voltage supplies power to the load through the third capacitor, and the first and second capacitors are connected in series to supply power to the load. The first capacitor is in a charging state, the second capacitor is in a discharging state, and the third capacitor is in a charging state. The inductor current is 0.

[0018] Second stage: The ninth and twelfth power transistors are turned on, while the other power transistors are turned off; the inductor current first rises and then falls until it drops to 0.

[0019] Phase 3: The first, third, fifth, seventh, ninth, and eleventh power transistors are turned on, while the other power transistors are turned off; the first capacitor supplies power to the load and is in a discharging state; the second and third capacitors are connected in series to supply power to the load, the second capacitor is in a charging state, the third capacitor is in a discharging state, and the inductor current is 0.

[0020] Fourth stage: The ninth and twelfth power transistors are turned on, while the other power transistors are turned off; the inductor current first rises and then falls until it drops to 0, at which point it returns to the first stage.

[0021] In some embodiments, the auxiliary circuit includes a ninth power transistor, a tenth power transistor, an eleventh power transistor, a twelfth power transistor, and an inductor; the first terminal of the ninth power transistor is connected to the first node of the first branch, the second terminal of the ninth power transistor is connected to the first terminal of the tenth power transistor and the first terminal of the inductor, and the second terminal of the tenth power transistor is grounded; the second terminal of the inductor is connected to the first terminal of the eleventh power transistor and the first terminal of the twelfth power transistor, the second terminal of the eleventh power transistor is grounded, and the second terminal of the twelfth power transistor is connected to the second node of the second branch.

[0022] In some embodiments, the auxiliary circuit includes a ninth power transistor, a tenth power transistor, a first diode, a second diode, and an inductor; the first end of the ninth power transistor is connected to the first node of the first branch, the second end of the ninth power transistor is connected to the first end of the first diode and the first end of the inductor, and the second end of the first diode is grounded; the second end of the inductor is connected to the first end of the second diode and the first end of the tenth power transistor, the second end of the second diode is grounded, and the second end of the tenth power transistor is connected to the second node of the second branch.

[0023] In some embodiments, the auxiliary circuit includes a ninth power transistor, a tenth power transistor, and an inductor; wherein, a first terminal of the ninth power transistor is connected to a first node of a first branch, a second terminal of the ninth power transistor is connected to a first terminal of the inductor, a second terminal of the inductor is connected to a first terminal of the tenth power transistor, and a second terminal of the tenth power transistor is connected to a second node of a second branch.

[0024] In some embodiments, the ninth, tenth, eleventh, and twelfth power transistors are all N-type power transistors; or, the ninth and twelfth power transistors are P-type power transistors, and the tenth and eleventh power transistors are N-type power transistors.

[0025] In some embodiments, the ninth and twelfth power transistors are N-type or P-type power transistors.

[0026] The above scheme is a feasible control timing sequence. Based on the above circuit structure, there are of course many other control timing sequences.

[0027] An auxiliary circuit is added between the two branches of a traditional converter. During the dead time when all main power transistors are off, this circuit transfers charge from one branch to the other, achieving zero-voltage turn-on for all main power transistors and reducing switching losses. The on-resistance of the power transistors in the added auxiliary circuit is much larger than that of the main power transistors, while the inductance of the inductor in the auxiliary circuit is very small, resulting in low package size and cost. Therefore, this application can significantly reduce the switching losses of a switched-capacitor converter and improve conversion efficiency by adding a low-cost auxiliary circuit, offering excellent performance benefits and commercial prospects. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the circuit structure of a traditional Dickson-type 4:1 switched capacitor converter.

[0029] Figure 2 This is a schematic diagram of the circuit structure of a Dickson-type 4:1 switched capacitor converter according to an embodiment of this application.

[0030] Figure 3 This is a schematic diagram of the operating timing of the 4:1 switched capacitor converter according to an embodiment of this application.

[0031] Figure 4 This is an equivalent circuit diagram of the 4:1 switched capacitor converter in this application operating in Stage 0.

[0032] Figure 5 This is an equivalent circuit diagram of the 4:1 switched capacitor converter operating in Stage 1 according to an embodiment of this application.

[0033] Figure 6 This is an equivalent circuit diagram of the 4:1 switched capacitor converter operating in Stage 2 of this application embodiment.

[0034] Figure 7 This is an equivalent circuit diagram of the 4:1 switched capacitor converter operating in Stage 3 according to an embodiment of this application.

[0035] Figure 8 This is a schematic diagram of the circuit structure of an N:1 switched capacitor converter according to an embodiment of this application.

[0036] Figure 9 The diagram shows various auxiliary circuit structures according to embodiments of this application. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the embodiments and accompanying drawings. The illustrative embodiments and descriptions of this application are only for explaining this application and are not intended to limit this application.

[0038] like Figure 2 As shown, the 4:1 Zero Voltage Switch (ZVS) switched capacitor converter proposed in this application includes a main power circuit and an auxiliary circuit. The main power circuit includes eight main power transistors (Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8), three capacitors (C1, C2, and C3), an input capacitor CIN, an output capacitor COUT, and an output load IOUT. The auxiliary circuit includes four auxiliary power transistors (QX1A, QX2A, QX1B, and QX2B) and an inductor L.

[0039] The main power circuit includes two branches, namely the first branch and the second branch. The first branch includes a first power transistor Q1 and a second power transistor Q2 that are connected to each other. The second branch includes a third power transistor Q3 and a fourth power transistor Q4 that are connected to each other.

[0040] The first terminal of the eighth power transistor Q8 is the input terminal of the Dickson switched-capacitor converter, which is connected to the external input voltage. The second terminal of the eighth power transistor Q8 is connected to the first terminal of the third capacitor C3 and the first terminal of the seventh power transistor Q7. The second terminal of the seventh power transistor Q7 is connected to the first terminal of the second capacitor C2 and the first terminal of the sixth power transistor Q6. The second terminal of the sixth power transistor Q6 is connected to the first terminal of the first capacitor C1 and the first terminal of the fifth power transistor Q5. The second terminal of the fifth power transistor Q5 is connected to the first terminal of the second power transistor Q2 and the first terminal of the third power transistor Q3. The connection point of the second terminal of the fifth power transistor Q5, the first terminal of the second power transistor Q2, and the first terminal of the third power transistor Q3 is the output terminal of the Dickson switched-capacitor converter.

[0041] The second terminal of the second power transistor Q2 is connected to the second terminal of the first capacitor C1, the second terminal of the third capacitor C3, and the first terminal of the first power transistor Q1, respectively. The second terminal of the first power transistor Q1 is grounded.

[0042] The second terminal of the third power transistor Q3 is connected to the second terminal of the second capacitor C2 and the first terminal of the fourth power transistor Q4, respectively. The second terminal of the fourth power transistor Q4 is grounded.

[0043] The connection point of the second terminal of the second power transistor Q2, the second terminal of the first capacitor C1, the second terminal of the third capacitor C3, and the first terminal of the first power transistor Q1 is the first node CFLA of the first branch, and the connection point of the second terminal of the third power transistor Q3, the second terminal of the second capacitor C2, and the first terminal of the fourth power transistor Q4 is the second node CFLB of the second branch.

[0044] The first terminal of the ninth power transistor QX1A is connected to the first node CFLA of the first branch. The second terminal of the ninth power transistor QX1A is connected to the first terminal of the tenth power transistor QX2A and the first terminal of the inductor L, respectively. The second terminal of the tenth power transistor is grounded. The second terminal of the inductor L is connected to the first terminal of the eleventh power transistor QX2B and the first terminal of the twelfth power transistor QX1B, respectively. The second terminal of the eleventh power transistor QX2B is grounded. The second terminal of the twelfth power transistor QX1B is connected to the second node CFLB of the second branch.

[0045] Under steady-state operation, VIN = 4 * VOUT, VC1 = VOUT, VC2 = 2 * VOUT, and VC3 = 3 * VOUT. Here, VIN represents the input voltage, VOUT represents the output voltage, VC1 represents the voltage difference across the first capacitor C1, VC2 represents the voltage difference across the second capacitor C2, and VC3 represents the voltage difference across the third capacitor C3.

[0046] Figure 3This is the timing diagram of a 4:1 switched capacitor converter during one switching cycle. There are four operating states sequentially within one cycle: stage0, stage1, stage2, and stage3. Signal PHA is the original clock signal with a 50% duty cycle; signal PHB is the inverted signal of signal PHA; signal PHA_DLY is the clock signal obtained by delaying signal PHA; and signal PHB_DLY is the clock signal obtained by delaying signal PHB. Signals Q1, Q3, Q5, and Q7 represent the switching states of the first power transistor Q1, the third power transistor Q3, the fifth power transistor Q5, and the seventh power transistor Q7, respectively. Signals Q2, Q4, Q6, and Q8 represent the switching states of the second power transistor Q2, the fourth power transistor Q4, the sixth power transistor Q6, and the eighth power transistor Q8, respectively. Signals QX1A, QX2A, QX1B, and QX2B represent the switching states of the ninth power transistor QX1A, the tenth power transistor QX2A, the twelfth power transistor QX1B, and the eleventh power transistor QX2B, respectively. Signals CFLA and CFLB represent the voltage waveforms of the first node CFLA of the first branch and the second node CFLB of the second branch, respectively. Signals LXA and LXB represent the voltage waveforms of nodes LXA and LXB, respectively. Signal iL represents the current waveform flowing through inductor L.

[0047] Stage 0 (t0-t1): For example Figure 4 As shown, the second power transistor Q2, the fourth power transistor Q4, the sixth power transistor Q6, and the eighth power transistor Q8 are turned on, while the first power transistor Q1, the third power transistor Q3, the fifth power transistor Q5, and the seventh power transistor Q7 are turned off (i.e., disconnected or not conducting). The input voltage supplies power to the load through the third capacitor C3, and the first capacitor C1 and the second capacitor C2 are connected in series to supply power to the load. The first capacitor C1 is in a charging state, the second capacitor C2 is in a discharging state, and the third capacitor C3 is in a charging state. In the auxiliary circuit section, the twelfth power transistor QX1B and the tenth power transistor QX2A are turned on, while the ninth power transistor QX1A and the eleventh power transistor QX2B are turned off. During this stage, the voltage at the first node CFLA of the first branch is equal to the output voltage VOUT, the voltage at the second node CFLB of the second branch is zero, the voltages at nodes LXA and LXB are zero, and the current flowing through the inductor L is zero.

[0048] Stage 1 (t1-t2): such as Figure 5As shown, at time t1, the first power transistor Q1, the third power transistor Q3, the fifth power transistor Q5, and the seventh power transistor Q7 remain off, while the second power transistor Q2, the fourth power transistor Q4, the sixth power transistor Q6, and the eighth power transistor Q8 are off. At this time, all eight main power transistors are in the off state. The first capacitor C1, the second capacitor C2, and the third capacitor C3 stop charging or discharging, maintaining the current voltage difference. The load current is provided by the discharge of the output capacitor COUT. The tenth power transistor QX2A and the eleventh power transistor QX2B are off, while the ninth power transistor QX1A and the twelfth power transistor QX1B are on.

[0049] Before time t1, the voltage of the first node CFLA in the first branch is VOUT, and the voltage of the second node CFLB in the second branch is zero. Starting from time t1, inductor L is connected between the first node CFLA in the first branch and the second node CFLB in the second branch. At this time, the parasitic capacitance of the first node CFLA in the first branch, the parasitic capacitance of the second node CFLB in the second branch, and inductor L begin to resonate. The voltage of the first node CFLA in the first branch resonates and decreases, while the voltage of the second node CFLB in the second branch resonates and increases, and the current in inductor L gradually increases. When the voltage of the first node CFLA in the first branch and the voltage of the second node CFLB in the second branch are the same, the current flowing through inductor L reaches its positive peak. Afterward, the voltage of the first node CFLA in the first branch continues to decrease, the voltage of the second node CFLB in the second branch continues to increase, and the current in inductor L begins to decrease. By time t2, the voltage of the first node CFLA in the first branch resonates to zero, the voltage of the second node CFLB in the second branch resonates to the output voltage VOUT, and the current in inductor L decreases to zero. Stage 2 begins.

[0050] As can be seen, during stage 1, the charge at the first node CFLA of the first branch can be transferred to the second node CFLB of the second branch by utilizing the resonance between the inductor and the parasitic capacitance. This provides the zero-voltage turn-on (i.e., conduction) conditions for the first power transistor Q1, the third power transistor Q3, the fifth power transistor Q5, and the seventh power transistor Q7 to be turned on in the next stage.

[0051] Stage 2 (t2-t3): such as Figure 6As shown, at time t2, the first power transistor Q1, the third power transistor Q3, the fifth power transistor Q5, and the seventh power transistor Q7 are turned on with zero voltage, while the second power transistor Q2, the fourth power transistor Q4, the sixth power transistor Q6, and the eighth power transistor Q8 remain off. The ninth power transistor QX1A and the eleventh power transistor QX2B are turned on, while the tenth power transistor QX2A and the twelfth power transistor QX1B are turned off. The first capacitor C1 discharges to supply power to the load, and the second capacitor C2 and the third capacitor C3 are connected in series to supply power to the load. The first capacitor C1 is in a discharging state, the second capacitor C2 is in a charging state, and the third capacitor C3 is in a discharging state. The voltage at the first node CFLA of the first branch is zero, the voltage at the second node CFLB of the second branch is equal to the output voltage VOUT, the voltages at nodes LXA and LXB are zero, and the current flowing through the inductor L is zero.

[0052] Stage 3 (t3-t0): For example Figure 7 As shown, at time t3, the first power transistor Q1, the third power transistor Q3, the fifth power transistor Q5, and the seventh power transistor Q7 are off, while the second power transistor Q2, the fourth power transistor Q4, the sixth power transistor Q6, and the eighth power transistor Q8 remain off. At this time, all eight main power transistors are in the off state. The first capacitor C1, the second capacitor C2, and the third capacitor C3 stop charging or discharging, maintaining the current voltage. The load current is provided by the discharge of the output capacitor COUT. The tenth power transistor QX2A and the eleventh power transistor QX2B are off, while the ninth power transistor QX1A and the twelfth power transistor QX1B are on.

[0053] Before time t3, the voltage of the first node CFLA in the first branch is zero, and the voltage of the second node CFLB in the second branch is the output voltage VOUT. Starting at time t3, inductor L is connected between the first node CFLA in the first branch and the second node CFLB in the second branch. At this time, the parasitic capacitance of the first node CFLA in the first branch, the parasitic capacitance of the second node CFLB in the second branch, and inductor L begin to resonate. The voltage of the first node CFLA in the first branch resonates and rises, while the voltage of the second node CFLB in the second branch resonates and falls, and the current in inductor L gradually increases negatively. When the voltage of the first node CFLA in the first branch is the same as the voltage of the second node CFLB in the second branch, the current flowing through inductor L reaches a negative peak. Afterward, the voltage of the first node CFLA in the first branch continues to rise, the voltage of the second node CFLB in the second branch continues to fall, and the current in inductor L begins to decrease negatively. By time t0, the voltage of the first node CFLA in the first branch resonates to the output voltage VOUT, the voltage of the second node CFLB in the second branch resonates to zero, and the current in inductor L drops to zero. Stage 0 begins.

[0054] As can be seen, during stage 3, the charge at the second node CFLB of the second branch can be transferred to the first node CFLA of the first branch by utilizing the resonance between the inductor and the parasitic capacitance. This provides the zero-voltage turn-on condition for the second power transistor Q2, the fourth power transistor Q4, the sixth power transistor Q6, and the eighth power transistor Q8 to be turned on in the next stage.

[0055] According to the switched capacitor converter of this application embodiment, the switching of the ninth power transistor QX1A, the tenth power transistor QX2A, the twelfth power transistor QX1B, and the eleventh power transistor QX2B is controlled by the above-described control timing. In stage 1, the charge on the first node CFLA of the first branch is transferred to the second node CFLB of the second branch through inductor L. In stage 3, the charge on the second node CFLB of the second branch is transferred to the first node CFLA of the first branch through inductor L. This ensures that the voltage difference between the first power transistor Q1, the second power transistor Q2, the third power transistor Q3, the fourth power transistor Q4, the fifth power transistor Q5, the sixth power transistor Q6, the seventh power transistor Q7, and the eighth power transistor Q8 is zero before each conduction, which greatly reduces switching losses and improves the conversion efficiency of the switched capacitor converter.

[0056] exist Figure 2 Based on the 4:1 switched capacitor converter shown, an N:1 switched capacitor converter can be realized by adding a main power transistor and a capacitor, such as... Figure 8 As shown. This N:1 switched capacitor converter can employ and Figure 2 The same auxiliary circuit and similar control method are used to achieve zero-voltage turn-on of all main power transistors, where N is an integer greater than or equal to 3.

[0057] The Dickson switched-capacitor converter is an N:1 switched-capacitor converter, where N is an integer greater than or equal to 5. This N:1 switched-capacitor converter may include auxiliary circuitry, a first branch, a second branch, N shared power transistors, and N-1 capacitors. The first branch includes a first power transistor Q1 and a second power transistor Q2, and the second branch includes a third power transistor Q3 and a fourth power transistor Q4. The first power transistor Q1, the second power transistor Q2, the third power transistor Q3, the fourth power transistor Q4, and the N shared power transistors are all main power transistors.

[0058] The first terminal of the second power transistor Q2 and the first terminal of the third power transistor Q3 are both connected to the output terminal of the N:1 switched capacitor converter. The second terminal of the second power transistor Q2 is connected to the first terminal of the first power transistor Q1. There is a first node CFLA of the first branch between the first power transistor Q1 and the second power transistor Q2. The second terminal of the third power transistor Q3 is connected to the first terminal of the fourth power transistor Q4. There is a second node CFLB of the second branch between the third power transistor Q3 and the fourth power transistor Q4. The second terminals of the first power transistor Q1 and the fourth power transistor Q4 are both grounded.

[0059] The two ends of the auxiliary circuit are connected to the first node CFLA and the second node CFLB, respectively. Figure 8 The connection structure of the auxiliary circuit of the N:1 switched capacitor converter and Figure 2 The connection structure of the auxiliary circuit of the 4:1 switched capacitor converter is the same.

[0060] The input terminal of the N:1 switched capacitor converter is connected to an external input voltage VIN, where VIN = N * VOUT. The input terminal of the N:1 switched capacitor converter is connected to the output terminal of the N:1 switched capacitor converter sequentially through N shared power transistors. The N shared power transistors are connected sequentially, and each of the N-1 capacitors corresponds to two adjacent shared power transistors. For example, each capacitor corresponds to a shared power transistor pair, and each shared power transistor pair includes two interconnected adjacent shared power transistors. Two adjacent shared power transistor pairs include three sequentially connected shared power transistors, where the middle shared power transistor is the shared power transistor of the two adjacent shared power transistor pairs. The first terminal of each capacitor is connected between its corresponding two adjacent shared power transistors, such that different capacitors are connected between different pairs of adjacent shared power transistors. In any two adjacent capacitors connected to shared power transistors, the second terminal of one capacitor is connected to the first node CFLA, and the second terminal of the other capacitor is connected to the second node CFLB.

[0061] Optionally, when the first terminal of a capacitor is connected between the common power transistor connected to the output terminal of the N:1 switched capacitor converter and its adjacent common power transistor, and the second terminal of the capacitor is connected to the first node CFLA, there are M capacitors connected to the first node CFLA and NM-1 capacitors connected to the second node CFLB. When N is even, M = N / 2, and when N is odd, M = (N-1) / 2.

[0062] For example, such as Figure 8As shown, the N shared power transistors include a first shared power transistor, a second shared power transistor, ..., the (N-3)th shared power transistor Q(N+1), the (N-2)th shared power transistor Q(N+2), the (N-1)th shared power transistor Q(N+3), and the Nth shared power transistor Q(N+4), connected in sequence. The first shared power transistor is the fifth power transistor Q5, and the second shared power transistor is the sixth power transistor Q6. The N-1 capacitors include a first capacitor C1, a second capacitor C2, a third capacitor C3, ..., the (N-1)th capacitor C(N-1).

[0063] The input terminals of the N:1 switched capacitor converter are connected to the output terminals of the N:1 switched capacitor converter in sequence through the Nth common power transistor Q(N+4), the N-1th common power transistor Q(N+3), the N-2nd common power transistor Q(N+2), the N-3rd common power transistor Q(N+1), ..., the second common power transistor and the first common power transistor.

[0064] According to the order of capacitors C1, C2, C3, ..., and the (N-1)th capacitor C(N-1), the first terminal of capacitor C1 is connected between the first and second shared power transistors; the first terminal of capacitor C2 is connected between the second and third shared power transistors; the third capacitor C3 is connected between the third and fourth shared power transistors; ..., the first terminal of the (N-1)th capacitor C(N-1) is connected between the (N-1)th shared power transistor Q(N+3) and the Nth shared power transistor Q(N+4). When N is even, the (N-1)th capacitor C(N-1) is... Figure 8 In the given configuration, the 2M-1th capacitor C(2M-1), where M = N / 2, has its first terminal connected between the (N-1)th shared power transistor Q(N+3) and the Nth shared power transistor Q(N+4). When N is odd, the (N-1)th capacitor C(N-1) is... Figure 8 The second (NM-1) capacitor C2(NM-1) is connected between the N-1 common power transistor Q(N+3) and the Nth common power transistor Q(N+4). Therefore, the second terminals of the first capacitor C1, the third capacitor C3, ..., the 2M-3 capacitor C(2M-3), and the 2M-1 capacitor C(2M-1) are connected to the first node CFLA. The second terminals of the second capacitor C2, ..., the 2(NM-1)-2 capacitor C(2(NM-1)-2), and the 2(NM-1) capacitor C2(NM-1) are connected to the second node CFLB.

[0065] The voltage differences between the first capacitor C1, the second capacitor C2, the third capacitor C3, ..., and the (N-1)th capacitor C(N-1) are, in order: VOUT, 2VOUT, 3VOUT, ..., (N-4)VOUT, (N-3)VOUT, (N-2)VOUT and (N-1)VOUT.

[0066] In this embodiment, all power transistors on the first and second branches, as well as the common power transistor, are main power transistors, and all main power transistors have parasitic capacitance.

[0067] In this article, the power transistor and the common power transistor can be either N-type or P-type switching transistors.

[0068] Figure 2 The auxiliary circuit shown includes four NMOS transistors and an inductor. It enables the transfer of charge from one branch to another during the dead time when all main power transistors are off, achieving zero-voltage turn-on for all main power transistors and reducing switching losses. Besides... Figure 2 Besides the auxiliary circuit in the diagram, various other types of circuits can also achieve this function. Figure 2 The function of auxiliary circuits, such as Figure 9 As shown, there are several different auxiliary circuits.

[0069] Optionally, such as Figure 9 As shown, the auxiliary circuit may include a ninth power transistor, a tenth power transistor, an eleventh power transistor, a twelfth power transistor, and an inductor. The first terminal of the ninth power transistor is connected to the first node CFLA of the first branch, and the second terminal of the ninth power transistor is connected to the first terminal of both the tenth power transistor and the inductor. The second terminal of the tenth power transistor is grounded. The second terminal of the inductor is connected to the first terminals of both the eleventh and twelfth power transistors. The second terminal of the eleventh power transistor is grounded, and the second terminal of the twelfth power transistor is connected to the second node CFLB of the second branch. The ninth, tenth, eleventh, and twelfth power transistors can all be N-type power transistors, such as... Figure 9 As shown in auxiliary circuit A, alternatively, the ninth and twelfth power transistors can both be P-type power transistors, and the tenth and eleventh power transistors can both be N-type power transistors, as shown in the diagram. Figure 9 The auxiliary circuit D is shown in the figure.

[0070] Optionally, such as Figure 9As shown, the auxiliary circuit may include a ninth power transistor, a twelfth power transistor, a first diode, a second diode, and an inductor. The first terminal of the ninth power transistor is connected to the first node CFLA of the first branch. The second terminal of the ninth power transistor is connected to the first terminal of both the first diode and the inductor. The second terminal of the first diode is grounded, with the first terminal being the negative terminal and the second terminal being the positive terminal. The second terminal of the inductor is connected to the first terminal of both the second diode and the twelfth power transistor. The second terminal of the second diode is grounded. The second terminal of the twelfth power transistor is connected to the second node CFLB of the second branch, with the first terminal of the second diode being the negative terminal and the second terminal being the positive terminal. Both the ninth and twelfth power transistors can be N-type power transistors, such as... Figure 9 As shown in auxiliary circuit B, or, the ninth and twelfth power transistors can both be P-type power transistors, such as... Figure 9 The auxiliary circuit E is shown in the figure.

[0071] Optionally, the auxiliary circuit may include a ninth power transistor, a twelfth power transistor, and an inductor; wherein, the first terminal of the ninth power transistor is connected to the first node CFLA of the first branch, the second terminal of the ninth power transistor is connected to the first terminal of the inductor, the second terminal of the inductor is connected to the first terminal of the twelfth power transistor, and the second terminal of the twelfth power transistor is connected to the second node CFLB of the second branch. The ninth and twelfth power transistors may both be N-type, such as... Figure 9 As shown in the auxiliary circuit C, or, the ninth and twelfth power transistors can both be P-type, such as... Figure 9 The auxiliary circuit F is shown in the figure.

[0072] This demonstrates that the specific implementation circuits are diverse. Therefore, after understanding the content of this application, those skilled in the art can easily conceive of various modifications, variations, or equivalents of the above examples, but they should still be subject to the limitations set forth in the claims and any equivalents.

Claims

1. A switched-capacitor converter, characterized by, The switched capacitor converter includes a first branch, a second branch, an auxiliary circuit, N common power transistors and N-1 capacitors, where N is an integer greater than or equal to 3; The first branch includes a first power transistor and a second power transistor, the second branch includes a third power transistor and a fourth power transistor, the first end of the second power transistor and the first end of the third power transistor are connected to the output terminal of the switched capacitor converter, the second end of the second power transistor and the first end of the first power transistor are connected through a first node, the second end of the third power transistor and the first end of the fourth power transistor are connected through a second node, and the second end of the first power transistor and the second end of the fourth power transistor are grounded. The input terminal of the switched capacitor converter is connected to the output terminal of the switched capacitor converter through the N common power transistors connected in sequence. Each of the N-1 capacitors corresponds to its two adjacent common power transistors, and each capacitor is connected between its two adjacent common power transistors. In any two adjacent capacitors connected to the N common power transistors, one capacitor is connected to the first node and the other capacitor is connected to the second node. The two ends of the auxiliary circuit are respectively connected to the first node and the second node. The first power transistor, the second power transistor, the third power transistor, the fourth power transistor and the N common power transistors are the main power transistors. The auxiliary circuit is used to transfer the charge of one of the first node and the second node to the other node during the dead time when all the main power transistors are turned off, so that the voltage difference between the two ends of each main power transistor becomes zero, and each main power transistor is turned on with zero voltage. When N=4, the N shared power transistors include the fifth power transistor, the sixth power transistor, the seventh power transistor, and the eighth power transistor, and the N-1 capacitors include the first capacitor, the second capacitor, and the third capacitor; The first terminal of the eighth power transistor is the input terminal of the switched capacitor converter and is connected to an external input voltage. The second terminal of the eighth power transistor is connected to the first terminal of the third capacitor and the first terminal of the seventh power transistor. The second terminal of the seventh power transistor is connected to the first terminal of the second capacitor and the first terminal of the sixth power transistor. The second terminal of the sixth power transistor is connected to the first terminal of the first capacitor and the first terminal of the fifth power transistor. The second terminal of the fifth power transistor is connected to the first terminal of the second power transistor and the first terminal of the third power transistor. The second terminal of the fifth power transistor is also connected to the output terminal of the switched capacitor converter. The second terminal of the first capacitor and the second terminal of the third capacitor are connected to the first node, and the second terminal of the second capacitor is connected to the second node; The auxiliary circuit includes a ninth power transistor, a tenth power transistor, an eleventh power transistor, a twelfth power transistor, and an inductor; The first end of the ninth power transistor is connected to the first node of the first branch, the second end of the ninth power transistor is connected to the first end of the tenth power transistor and the first end of the inductor, and the second end of the tenth power transistor is grounded. The second end of the inductor is connected to the first end of the eleventh power transistor and the first end of the twelfth power transistor, respectively. The second end of the eleventh power transistor is grounded, and the second end of the twelfth power transistor is connected to the second node of the second branch.

2. The switched-capacitor converter of claim 1, wherein, When N is an integer greater than or equal to 5, the N common power transistors include a first common power transistor, a second common power transistor, ..., the (N-3)th common power transistor, the (N-2)th common power transistor, the (N-1)th common power transistor and the Nth common power transistor connected in sequence, and the N-1 capacitors include a first capacitor, a second capacitor, a third capacitor, ..., the (N-1)th capacitor; The input terminal of the switched capacitor converter is connected to the output terminal of the switched capacitor converter in sequence through the Nth common power transistor, the (N-1)th common power transistor, the (N-2)th common power transistor, the (N-3)th common power transistor, ..., the second common power transistor and the first common power transistor; The first terminal of the first capacitor is connected between the first common power transistor and the second common power transistor, and the second terminal of the first capacitor is connected to the first node, such that M of the N-1 capacitors are connected to the first node, and NM-1 of the N-1 capacitors are connected to the second node, wherein when N is even, M=N / 2, and when N is odd, M=(N-1) / 2.

3. The switched capacitor converter of claim 2, wherein, When N is an even number, the (N-1)th capacitor is the (2M-1)th capacitor. The first terminal of the (N-1)th capacitor is connected between the (N-1)th common power transistor and the Nth common power transistor. The second terminals of the first capacitor, the third capacitor, ..., and the (2M-1)th capacitor are connected to the first node. When N is an odd number, the (N-1)th capacitor is the second (NM-1)th capacitor. The first end of the second (NM-1)th capacitor is connected between the (N-1)th common power transistor and the Nth common power transistor. The second end of the second capacitor, ..., and the second (NM-1)th capacitor is connected to the second node.

4. The switched-capacitor converter of claim 1, wherein, The ninth power transistor, the tenth power transistor, the eleventh power transistor, and the twelfth power transistor are all N-type power transistors; Alternatively, the ninth and twelfth power transistors may be P-type power transistors, and the tenth and eleventh power transistors may be N-type power transistors.

5. The switched-capacitor converter of claim 1, wherein, The operating timing of the switched capacitor converter includes four stages: First stage: The second, fourth, sixth, eighth, tenth, and twelfth power transistors are turned on, and the other power transistors are turned off; the input voltage supplies power to the load through the third capacitor, and the first and second capacitors are connected in series to supply power to the load. The first capacitor is in a charging state, the second capacitor is in a discharging state, the third capacitor is in a charging state, and the inductor current is 0. Second stage: The ninth and twelfth power transistors are turned on, and the other power transistors are turned off; The inductor current first rises and then falls until it drops to 0. Third stage: The first power transistor, the third power transistor, the fifth power transistor, the seventh power transistor, the ninth power transistor, and the eleventh power transistor are turned on, and the other power transistors are turned off; The first capacitor supplies power to the load and is in a discharging state. The second and third capacitors are connected in series to supply power to the load. The second capacitor is in a charging state, the third capacitor is in a discharging state, and the inductor current is 0. Fourth stage: The ninth and twelfth power transistors are turned on, while the other power transistors are turned off; The inductor current first rises and then falls until it drops to 0, at which point it returns to the first stage.

6. The switched capacitor converter of any of claims 1-3, wherein, The auxiliary circuit includes a ninth power transistor, a twelfth power transistor, a first diode, a second diode, and an inductor; The first end of the ninth power transistor is connected to the first node of the first branch, the second end of the ninth power transistor is connected to the first end of the first diode and the first end of the inductor, and the second end of the first diode is grounded. The second end of the inductor is connected to the first end of the second diode and the first end of the twelfth power transistor, respectively. The second end of the second diode is grounded, and the second end of the twelfth power transistor is connected to the second node of the second branch.

7. The switched capacitor converter of any of claims 1-3, wherein, The auxiliary circuit includes a ninth power transistor, a twelfth power transistor, and an inductor; wherein, the first end of the ninth power transistor is connected to the first node of the first branch, the second end of the ninth power transistor is connected to the first end of the inductor, the second end of the inductor is connected to the first end of the twelfth power transistor, and the second end of the twelfth power transistor is connected to the second node of the second branch.

8. The switched capacitor converter of claim 1, wherein, The ninth power transistor, the tenth power transistor, the eleventh power transistor, and the twelfth power transistor are all N-type power transistors; Alternatively, the ninth and twelfth power transistors may be P-type power transistors, and the tenth and eleventh power transistors may be N-type power transistors.

9. The switched capacitor converter of claim 6, wherein, The ninth power transistor and the twelfth power transistor are either N-type or P-type power transistors.

10. The switched capacitor converter according to claim 7, characterized in that, The ninth power transistor and the twelfth power transistor are either N-type or P-type power transistors.

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