Gallium nitride power device and packaging method thereof

Abstract

The invention discloses a gallium nitride power device and a packaging method thereof. The packaging method comprises the steps of wafer pretreatment and chip packaging, wherein a copper-titanium-nickel-molybdenum metal layer is grown through electroplating / sputtering in pretreatment, a welding column is formed through etching, an air channel is reserved, and a single chip is obtained through scribing; the heat stress is relieved through the copper-titanium-nickel-molybdenum buffer layer, cavities are eliminated through the welding columns and the bottom partition design, the bonding cost is reduced through the copper connecting structure, meanwhile, the parasitic inductance can be reduced, and the heat dissipation efficiency is improved by combining the diamond cooling fins; finally, current uniformity improvement, reliability enhancement and cost optimization of gallium nitride device packaging are realized, and technical support is provided for large-scale industrial application.

Description

Technical Field

[0001] This invention relates to the field of gallium nitride power device packaging technology, and in particular to a gallium nitride power device and its packaging method. Background Technology

[0002] Gallium nitride (GaN) power devices, due to their excellent electrical characteristics such as high electron mobility, high saturation drift velocity, and high breakdown electric field strength, have advantages such as low on-resistance, high operating frequency, and high switching speed. They can provide high power and high efficiency in a small size, and therefore have a wide range of applications in power conversion, wireless communication, radar, and solar inverters.

[0003] For gallium nitride (GaN) power device packaging technology, most manufacturers currently use metal bonding connections. When GaN power devices operate in high-frequency, high-voltage, and high-power applications, the multi-aluminum wire bonding process can lead to uneven current distribution, causing localized overheating and affecting lifespan. Simultaneously, multiple aluminum wire connections introduce significant parasitic inductance and mutual inductance effects. Especially under high-frequency operating conditions, this parasitic inductance can cause spikes in the power transistor during rapid switching. These spikes can couple to the gate capacitance of the GaN silicon MOSFET through the power transistor's parasitic capacitance, resulting in false turn-on due to high gate voltage and punch-through. In severe cases, this can damage the device and cause it to fail.

[0004] In summary, developing a gallium nitride power device packaging process that can overcome the aforementioned technical deficiencies and balance cost and performance has become an urgent technical problem to be solved in this field. Summary of the Invention

[0005] This invention alleviates thermal stress through a copper-titanium-nickel-molybdenum buffer layer (matching the 3.7ppm / K thermal stress coefficient of gallium nitride), eliminates the welding void effect by using a solder post design, reduces bonding costs and parasitic inductance by using a copper connection structure, and improves heat dissipation efficiency by combining a diamond heat sink (thermal conductivity 2000W / m・K). Moreover, the low-cost solution reduces the cost by more than 50% compared to ceramic substrate packaging.

[0006] This invention provides a gallium nitride power device packaging method, comprising: A first metal layer is grown on the PAD surface of the gallium nitride power device wafer; The metal layer at the pad location of gallium nitride power devices is etched into independent bonding pillars; Separate gallium nitride power device wafers into individual gallium nitride power chips; To package a single gallium nitride power chip.

[0007] In one embodiment of the present invention, the first metal layer is a copper-titanium-nickel-molybdenum metal layer with a thickness of 1 micrometer to 1 millimeter.

[0008] In one embodiment of the present invention, the process of packaging a single gallium nitride power chip includes: The bottom of the gallium nitride power chip with solder pillars is soldered to the base island of the package frame using conductive solder. A welding frame is placed at the solder joints of the packaging frame and the gallium nitride power chip, and the welding frame, the chip's bonding pads, and the packaging frame's solder joints are welded together. The package frame with the gallium nitride power chip mounted and connected is placed in the mold for injection molding; The encapsulated frame is then cut and electroplated. Multiple packaging frames and multiple welding frames form a frame array for mass packaging of gallium nitride power chips.

[0009] In one embodiment of the present invention, a diamond sheet or other insulating and thermally conductive sheet is placed on the base island of the packaging frame.

[0010] In one embodiment of the present invention, the welding frame is chamfered.

[0011] The present invention also provides a gallium nitride power device, comprising: Gallium nitride power chips are mounted on the substrate island of the packaging frame; A packaging frame configured to encapsulate the gallium nitride power chip; A welding frame configured to connect the gallium nitride power chip and the packaging frame; The frame array, consisting of multiple packaging frames and multiple welding frames, is used for mass packaging of silicon carbide power chips.

[0012] In one embodiment of the present invention, a heat sink is further included. The heat sink is a diamond sheet or other insulating and thermally conductive sheet, and the heat sink is disposed on the base island of the packaging frame.

[0013] In one embodiment of the present invention, a molding layer is also included, which is configured to mold the gallium nitride power chip and the packaging frame.

[0014] In one embodiment of the present invention, the gallium nitride power chip includes: A wafer configured as the gallium nitride power chip substrate; A first metal layer is disposed on the front side of the wafer, on which a plurality of uniformly spaced solder pillars are etched.

[0015] In one embodiment of the present invention, the welding frame is made of copper that has undergone surface anti-oxidation treatment.

[0016] The present invention has the following beneficial effects: (1) By forming a frame array with multiple welding frames and packaging frames, multiple chips can be packaged at once, which greatly reduces the time cost of packaging.

[0017] (2) By replacing the traditional multiple aluminum wire bonding with "independent copper-titanium-nickel-molybdenum bonding pillars" + "copper welding frame" etched on the wafer surface, the current bias problem caused by the impedance difference and uneven layout of aluminum wires is eliminated, avoiding local current concentration and heat generation, and reducing device performance degradation caused by overheating. The copper connection structure (bonding pillars + welding frame) has a shorter conduction path and lower impedance, and the parasitic inductance is reduced by more than 40% compared with the traditional aluminum wire bonding. It effectively suppresses high voltage spikes and glitches during the fast switching of gallium nitride devices, and reduces switching losses and the risk of gate mis-opening and punch-through failure.

[0018] (3) The wafer metal layer is etched with solder pillars to reserve "gas channels". During soldering, the gas in the solder can be discharged in time, completely eliminating the void problem of traditional large-area source and drain electrode soldering, and avoiding local heating and high-temperature gas expansion failure caused by voids. The copper-titanium-nickel-molybdenum metal layer on the wafer surface serves as a "thermal buffer layer". Its thermal stress coefficient is closer to that of gallium nitride (3.7ppm / K). It can alleviate the thermal expansion difference between copper / aluminum and gallium nitride, reduce metal fatigue and solder layer cracking under thermal cycling, and extend the device life by more than 30%.

[0019] (4) Embedded diamond heat sink (thermal conductivity 2000W / m・K, much higher than aluminum nitride 150~180W / m・K), combined with "double-sided heat dissipation" design, heat dissipation efficiency is 2~3 times higher than traditional plastic packaging, which can support gallium nitride devices with higher power density and avoid performance degradation caused by high temperature. Attached Figure Description

[0020] Figure 1 A schematic diagram of a gallium nitride power chip structure in one embodiment of the present invention is shown; Figure 2 A flowchart of a gallium nitride power device packaging method according to an embodiment of the present invention is shown; Figures 3A to 3B A flowchart of a gallium nitride power wafer preprocessing process in one embodiment of the present invention is shown; Figures 4A to 4D A single-chip packaging process flow diagram is shown in one embodiment of the present invention; Figure 5 A single-chip package structure diagram according to an embodiment of the present invention is shown; Figure 6 A schematic diagram of the welding stage structure is shown in one embodiment of the present invention; Figure 7 A schematic diagram of the die-bonding stage of a half-bridge circuit in one embodiment of the present invention is shown; Figure 8 A schematic diagram of the half-bridge circuit welding stage in one embodiment of the present invention is shown; Figure 9 A schematic diagram of a gallium nitride chip structure according to an embodiment of the present invention is shown; Figure 10 A schematic diagram of the die-bonding stage of a half-bridge circuit in one embodiment of the present invention is shown; Figure 11 A schematic diagram of the half-bridge circuit welding stage in one embodiment of the present invention is shown; Figure 12 A schematic diagram of the half-bridge circuit welding stage in one embodiment of the present invention is shown; Figure 13 A schematic diagram of the half-bridge circuit welding stage in one embodiment of the present invention is shown; Figures 14A to 14C The following is an embodiment of the gallium nitride power device module packaging process of the present invention; Figure 15 A schematic diagram of a gallium nitride power device module structure in one embodiment of the present invention is shown; Figures 16A to 16C The substrate fabrication process is shown in one embodiment of the present invention; Figure 17 A half-bridge circuit diagram is shown in one embodiment of the present invention; Figure 18 A schematic diagram of the pinout of a gallium nitride half-bridge circuit in one embodiment of the present invention is shown; and Figure 19 An assembly diagram of a gallium nitride chip in a half-bridge circuit according to one embodiment of the present invention. Detailed Implementation

[0021] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or with other alternatives and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific quantities, materials, and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details.

[0022] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0023] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0024] Furthermore, the numbering of the steps in the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps may be executed in different orders.

[0025] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0026] Figure 1 A schematic diagram of a gallium nitride power chip structure according to an embodiment of the present invention is shown.

[0027] like Figure 1 As shown, in this embodiment, the source, gate, and drain of the gallium nitride chip are all located on the same surface.

[0028] Figure 2 A flowchart of a gallium nitride power device packaging method according to an embodiment of the present invention is shown.

[0029] like Figure 2 As shown, in one embodiment of the present invention, the gallium nitride power device packaging method includes: S100, gallium nitride power wafer preprocessing, steps include: S110, layering process, such as Figure 3A As shown, a first metal layer 100 is grown on the surface of a gallium nitride power device wafer using mature processes such as electroplating and sputtering.

[0030] The metal layer is made of copper-titanium-nickel-molybdenum alloy, with a thickness controlled between 1 and 1000 micrometers. It needs to cover the wafer surface to ensure the conductivity of subsequent electrode leads. The copper-titanium-nickel-molybdenum alloy acts as a "buffer layer," reducing the difference in thermal stress between it and gallium nitride (thermal stress coefficient 3.7ppm / K) (copper thermal stress 17.8ppm / K, aluminum 23ppm / K), thus preventing metal fatigue failure at high temperatures. It also provides a base metal layer for subsequent bonding post fabrication, replacing traditional aluminum pads and improving current conduction efficiency.

[0031] S120, Etching of solder pillars, such as Figure 3B As shown, the copper-titanium-nickel-molybdenum metal layer on the wafer surface is etched into multiple independent bonding pillars 110 through photolithography and etching processes (the number of bonding pillars matches the chip electrode lead-out requirements, such as independent bonding pillars for the source and gate).

[0032] The weld pillars must be regularly shaped (e.g., cylindrical or square) and evenly spaced to avoid short circuits between different electrode pillars. The etching depth must penetrate the metal layer, exposing the electrode area on the wafer surface. This step replaces traditional multi-aluminum wire bonding, achieving uniform current distribution through "independent weld pillars + subsequent welding framework," thus solving the problem of "uneven current and localized heating" in aluminum wire bonding. Furthermore, gaps are reserved between the weld pillars to provide gas venting channels during subsequent welding, reducing the risk of solder voids from the source.

[0033] S130, dicing and cutting, separates a wafer into individual chips through thinning, dicing and cutting processes.

[0034] The purposes of the above process steps include: The electrodes on the chip pads are brought out to facilitate subsequent soldering; To ensure uniform flow and allow for gas flow through the outlet, welding columns are constructed to prevent "void" phenomena during welding. This effectively increases the heat dissipation area on the chip surface; A copper-titanium-nickel-molybdenum metal buffer layer was added to reduce the thermal stress of the chip at high temperatures; S200, packaging of gallium nitride power chips.

[0035] Figures 4A to 4D A flowchart of a single-chip packaging process according to an embodiment of the present invention is shown.

[0036] A dedicated soldering frame is designed based on the package frame. Taking the TO247 package as an example, the packaging steps are as follows: S211, crystal bonding, such as Figure 4A As shown, it includes: Prepare a dedicated TO package frame 310 (the base island is made of copper with a thermal conductivity of 401W / mK to improve heat dissipation). Apply / place conductive solder (such as silver paste or tin foil) on the surface of the frame base island. Silver paste has better conductivity than tin foil, while tin foil is cheaper. Choose according to power requirements. The bottom of the pre-treated gallium nitride chip 320 is attached to the base island solder of the packaging frame 310. The solder is then cured by heating (such as reflow soldering, with the temperature adjusted according to the melting point of the solder, approximately 220°C for tin foil and approximately 200°C for silver paste), thus completing the fixation of the gallium nitride chip 320.

[0037] S212, Welding, such as Figure 4B As shown, a welding frame 330 is placed at the solder joints of the packaging frame 310 and the gallium nitride chip 320. The welding frame 330, the pressure solder joints of the gallium nitride chip 320 and the solder joints of the packaging frame 310 are connected using a jig and related alignment equipment.

[0038] Since the device operates in a high-voltage, high-frequency environment, the welding frame 330 requires chamfering during fabrication to prevent electric field concentration in this area, which could generate high voltage and affect chip reliability. Replacing traditional aluminum wire bonding, the "rigid welding frame" reduces parasitic inductance (aluminum wires have strong mutual inductance, resulting in high parasitic inductance and a tendency to generate high-voltage spikes) while improving connection efficiency (aluminum wires require single-strand bonding, while the welding frame 330 can connect multiple solder joints at once).

[0039] In another embodiment of the present invention, in the silicon carbide chip fabrication process, a 1-micrometer to 1-millimeter copper-titanium-nickel-molybdenum metal layer is directly grown on the pad window area of ​​the silicon carbide power device wafer surface using a layer-addition process (mature processes such as electroplating and sputtering), without etching of the bonding pillars. In this case, since the bottom layer of the chip is a large area of ​​bonding pads, the gallium nitride chip... Figure 9 As shown, to avoid weld voids, the wire bonding frame 330 requires openings. Its structural diagram is shown below. Figure 6 As shown.

[0040] S213, Injection molding, such as Figure 4C As shown, the frame with the chip already mounted and connected is placed in the mold for injection molding to form the molding compound 340.

[0041] S214, Beam cutting and electroplating, such as Figure 4D As shown, it includes: The excess ribs connecting the pins on the package frame are cut off through a punching process, making each pin independent (such as the three pins of TO247). The polarity of each pin is as follows: Figure 4D As shown; A layer of anti-oxidation metal (such as tin or gold) with a thickness of about 1 to 3 micrometers is electroplated on the surface of the pin to improve the solderability of the pin (it is less prone to oxidation when soldered to external circuits later). Because the molding compound itself has very poor thermal conductivity, the heat on the surface of the gallium nitride chip encapsulated in the molding compound can only be transferred to the base island for heat dissipation. As shown in Table 2, diamond has a much higher heat dissipation coefficient than other materials used in gallium nitride packaging.

[0042] Figure 5 A schematic diagram of a single-chip structure in one embodiment of the present invention is shown.

[0043] like Figure 5 As shown, in order to further improve heat dissipation and increase reliability, a heat sink 350 with a diamond sheet or other insulating thermal conductive sheet can be placed in the base island of the packaging frame 310 during the die bonding process. The heat on the surface of the gallium nitride chip is transferred to the bottom base island through the heat conductive sheet via the connecting copper sheet of the chip source, thereby achieving double-sided heat dissipation.

[0044] In one embodiment of the present invention, a gallium nitride power device includes: The gallium nitride chip 320 is mounted on the base island of the package frame; A packaging frame 310 is configured to encapsulate the gallium nitride power chip; A welding frame 330 is configured to connect the gallium nitride power chip and the packaging frame, wherein the welding frame is made of copper with a surface anti-oxidation treatment (such as tin plating or gold plating). In this embodiment, the gallium nitride power device further includes: A heat sink, which is a diamond sheet or other insulating and thermally conductive sheet, is disposed on the base island of the packaging frame.

[0045] A molding layer is configured to mold the gallium nitride power chip and the package frame.

[0046] The gallium nitride chips include: A wafer configured as the gallium nitride power chip substrate; A first metal layer 100 is disposed on the front side of the wafer, and a plurality of uniformly spaced solder pillars 110 are etched thereon. In one embodiment of the present invention, a method for molding a half-bridge circuit is also provided.

[0047] Half-bridge circuit connection method as follows Figure 17 As shown, in this embodiment, a frame array is formed by multiple welding frames and packaging frames, which can package multiple chips at once, greatly reducing the packaging time cost. The packaging frame and welding frame are designed according to the interconnection relationship of power devices in the half-bridge circuit.

[0048] like Figure 7 As shown, the packaging frame 310 contains two independent base islands arranged side-by-side, indicating that this is a dual-chip packaging frame capable of packaging two chips simultaneously. The bottom lead area contains multiple parallel-arranged external leads. These external leads are secured by connecting ribs, with a positioning hole (circular mark) at the center of the bottom of the connecting rib for equipment positioning during the packaging process, ensuring precise alignment of the frame during manufacturing, bonding, and molding. In subsequent processes, the connecting ribs are removed, and the packaging structure is as follows... Figure 12 As shown.

[0049] Figure 19 An assembly diagram of a gallium nitride chip in a half-bridge circuit according to one embodiment of the present invention.

[0050] like Figure 19 As shown, the flat area at the top of the welding frame 330 is the welding area 331, a metal platform (usually copper alloy) used to connect the chip electrodes to the external leads of the package frame via solder pads 332. Below the welding area 331 are five parallel cantilever structures, which are the solder pads 332, connecting to the external leads of the package frame 310. Finally, connecting ribs 333 are used to fix the solder pads 332 and are removed after injection molding. There is a height difference between the connecting ribs 333 and the welding area 331 to facilitate subsequent removal.

[0051] Figure 18 A schematic diagram of the pinout of a gallium nitride half-bridge circuit in one embodiment of the present invention is shown.

[0052] The final gallium nitride half-bridge circuit pinout is as follows: Figure 18 As shown.

[0053] Its overall process is the same as that of single-chip molding. A schematic diagram of the die bonding stage is shown below. Figure 7 As shown in the diagram, the structural schematic diagram of the welding stage is as follows: Figure 8 As shown. The finished product image is as follows. Figure 12 As shown.

[0054] When the bottom layer of the chip has a large area of ​​pads, the same opening process is performed on the bonding frame 330. The structural diagram of the die bonding stage at this time is as follows. Figure 10 As shown in the diagram, the structural schematic diagram of the welding stage is as follows: Figure 11 As shown. The finished product image is as follows. Figure 13 As shown.

[0055] Figures 14A to 14C The present invention illustrates the packaging process of a gallium nitride power device module in one embodiment of the present invention.

[0056] In one embodiment of the present invention, a gallium nitride power device module packaging method is also provided, comprising: like Figure 14A As shown, a ceramic substrate 500 for designing half-bridge or full-bridge circuits is constructed using a ceramic material (aluminum nitride or aluminum oxide) with good heat dissipation.

[0057] like Figure 14B As shown, a gallium nitride chip 320 with solder pillars is soldered onto a ceramic substrate 500 using solder.

[0058] like Figure 14B As shown, the bottom of the gallium nitride chip 320 and the heat sink 510 are soldered together with the ceramic substrate 500 to achieve double-sided heat dissipation.

[0059] After injecting thermal adhesive, it is encapsulated.

[0060] Figure 15 A schematic diagram of a gallium nitride power device module structure is shown in one embodiment of the present invention.

[0061] In one embodiment of the present invention, such as Figure 15 As shown, for better heat dissipation, a diamond heat sink 511 can also be added to achieve double-sided heat dissipation.

[0062] Figures 16A to 16C The substrate fabrication process is shown in one embodiment of the present invention.

[0063] Currently, half-bridge or full-bridge gallium nitride (GaN) power modules generally use aluminum nitride ceramic materials, which have good heat dissipation, but are relatively expensive. To reduce costs, this embodiment uses a combination of ordinary PCB and diamond heat sinks to achieve heat dissipation without compromising reliability.

[0064] In this embodiment, the substrate fabrication process includes: like Figure 16A As shown, the ordinary PCB is first slotted / cut out below the position where the gallium nitride power chip is placed; like Figure 16B As shown, place the diamond heat sink in the groove; like Figure 16C As shown, electroplating and etching processes are performed to create a metal layer with the required connection relationship between the top and bottom layers of the PCB.

[0065] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A method for packaging gallium nitride power devices, characterized in that, include: A first metal layer is grown on the PAD surface of the gallium nitride power device wafer; The metal layer at the pad location of gallium nitride power devices is etched into independent bonding pillars; Separate gallium nitride power device wafers into individual gallium nitride power chips; To package a single gallium nitride power chip.

2. The method according to claim 1, characterized in that, The first metal layer is a copper-titanium-nickel-molybdenum metal layer with a thickness of 1 micrometer to 1 millimeter.

3. The method according to claim 1, characterized in that, The process of packaging a single gallium nitride power chip includes: The bottom of the gallium nitride power chip with solder pillars is soldered to the base island of the package frame using conductive solder. A welding frame is placed at the solder joints of the packaging frame and the gallium nitride power chip, and the welding frame, the chip's bonding pads, and the packaging frame's solder joints are welded together. The package frame with the gallium nitride power chip mounted and connected is placed in the mold for injection molding; The encapsulated frame is then cut and electroplated. Multiple packaging frames and multiple welding frames form a frame array for mass packaging of gallium nitride power chips.

4. The method according to claim 3, characterized in that, The base island of the encapsulation frame is covered with a diamond sheet or other insulating and thermally conductive sheet.

5. The method according to claim 3, characterized in that, The welding frame is chamfered.

6. A gallium nitride power device, characterized in that, include: Gallium nitride power chips are mounted on the substrate island of the packaging frame; A packaging frame configured to encapsulate the gallium nitride power chip; A welding frame configured to connect the gallium nitride power chip and the packaging frame; The frame array, consisting of multiple packaging frames and multiple welding frames, is used for mass packaging of gallium nitride power chips.

7. The gallium nitride power device according to claim 6, characterized in that, It also includes a heat sink, which is a diamond sheet or other insulating and thermally conductive sheet, and the heat sink is disposed on the base island of the packaging frame.

8. The gallium nitride power device according to claim 6, characterized in that, It also includes a molding layer configured to mold the gallium nitride power chip and the package frame.

9. The gallium nitride power device according to claim 6, characterized in that, The gallium nitride power chip includes: A wafer configured as the gallium nitride power chip substrate; A first metal layer is disposed on the front side of the wafer, on which a plurality of uniformly spaced solder pillars are etched.

10. The gallium nitride power device according to claim 6, characterized in that, The welded frame is made of copper with a surface anti-oxidation treatment.

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