Vector processor functional verification method and system

Abstract

This invention discloses a method and system for verifying the functionality of a vector processor. The method unifies matrix, vector, and scalar data formats into a matrix type using a reference model. Multi-input interface data is stored in corresponding data queues in the form of address plus data. The required computational data is extracted according to the current instruction, and unused data is stored back to the original queue. Expected output data at the clock cycle level is generated and compared with the actual output data of the vector processor to determine functional correctness. The system includes an instruction generator module, a controller module, a data generation module, a reference model module, a data collection module, and a data comparator module. This invention can improve the accuracy of vector processor fault location, simplify verification logic, and improve overall verification efficiency.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and more specifically, to a method and system for verifying the functionality of a vector processor. Background Technology

[0002] A vector processor is a type of hardware specifically designed for single-instruction multiple-data (SMD) computation. Its core logic involves executing the same operation on a continuous set of data simultaneously using a single instruction, enabling efficient processing of large-scale, structured numerical computation tasks. With the rapid development of fields such as artificial intelligence and deep learning, signal and image processing, scientific computing and simulation, and multimedia and audio-visual applications, the application scope of vector processors is constantly expanding. Their performance and functional correctness directly affect the operational performance of related systems. Therefore, functional verification of vector processors has become a crucial step in the chip design process.

[0003] Current functional verification of vector processors primarily employs end-to-end data comparison, determining design correctness solely by comparing the consistency between input and final output data. This verification method is a black-box approach, unable to track instruction execution and internal data flow. When calculation errors occur, it can only confirm a problem with the final result, failing to pinpoint the specific clock cycle, executed instruction, or data interface where the fault occurred. Furthermore, vector processors support three different data formats: matrices, vectors, and scalars, and typically have multiple data input interfaces. Existing technologies require separate processing for different data formats, and the lack of a unified scheduling mechanism for multi-interface data further increases the complexity of the verification logic, resulting in long fault location times, low verification efficiency, and difficulty meeting the rapid iterative development needs of vector processors.

[0004] Therefore, there is an urgent need for a vector processor functional verification method and system to solve the technical problems of long fault location time and low verification efficiency in existing vector processor verification. Summary of the Invention

[0005] Based on existing technology, the objective of this invention is to provide a method and system for verifying the functionality of a vector processor, which can improve the accuracy of fault location, simplify the design logic of the reference model, realize the precise scheduling and efficient reuse of multi-input interface data, and improve the overall verification efficiency of the vector processor.

[0006] A first aspect of the present invention provides a method for verifying the functionality of a vector processor, comprising: Provides instructions that meet the design requirements of vector processors; Input data is fed into the vector processor through multiple data input interfaces; Provide the configuration parameters required for vector processor verification; The input data is converted into a matrix type and stored in the corresponding data queues, wherein the data queues include data addresses and corresponding input data; The required input data is extracted from the data queue as computation data according to the instruction; Based on the instructions, calculated data, and configuration parameters, the processing is performed to calculate the desired output data. The actual output data from the vector processor design module was acquired; and The expected output data is compared with the actual output data to determine whether the vector processor design module functions correctly.

[0007] Furthermore, the data format of the input data includes at least one of matrix, vector, and scalar.

[0008] Further, the step of retrieving the required input data from the data queue according to the instruction includes: The system sequentially retrieves input data from each data queue using a polling method. It then determines whether the retrieved input data is required to execute the current instruction based on the current instruction. Input data that is not required to execute the current instruction is stored in a temporary queue.

[0009] Furthermore, after the calculation is completed, the input data in the temporary queue is stored back into the corresponding data queue.

[0010] Further, the step of converting the input data format into a matrix type includes: Process the input data in row vector format into a matrix with 1 row; Process the input data in column vector format into a matrix with one column; and Process the scalar format input data into a matrix with 1 row and 1 column.

[0011] A second aspect of the present invention provides a vector processor function verification system for performing the method described in the first aspect of the present invention, the system comprising: The instruction generator module is used to provide instructions that meet the design requirements of the vector processor; The controller module is used to provide configuration parameters that meet the design requirements. The data generation module is used to provide input data to the vector processor's design module and reference model module. The reference model module is used to calculate the desired output data based on the instructions provided by the instruction generator module, the configuration parameters provided by the controller module, and the input data provided by the data generation module, wherein the input data is uniformly processed into a matrix type in the reference model module. A data collection module is used to collect the actual output data from the design module of the vector processor; and The data comparator module is used to determine the correctness of the design module function of the vector processor by comparing the expected output data with the actual output data.

[0012] Furthermore, the instruction generator module includes: An instruction generation unit is used to generate instructions that meet the design requirements of the vector processor. An instruction sending unit is configured to send the instructions generated by the instruction generation unit to the design module of the vector processor; and An instruction acquisition unit is configured to acquire the instructions currently being executed by the vector processor.

[0013] Furthermore, there are multiple data generation modules, each providing input data with different data bit widths and / or different address bit widths.

[0014] The present invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, characterized in that the processor executes the computer program to implement the steps of the method described in the first aspect of the present invention.

[0015] The present invention also provides a computer-readable storage medium having a computer program stored thereon, characterized in that the computer program, when executed by a processor, implements the steps of the method described in the first aspect of the present invention.

[0016] The present invention has at least the following beneficial effects: This invention outputs expected output data at the clock cycle level through a reference model. Combined with an instruction acquisition and data queue management mechanism, when a calculation error occurs, it can directly locate the specific clock cycle, executed instruction, and data interface where the fault occurred, thus reducing the difficulty of fault location.

[0017] This invention unifies the processing of three different data formats—matrices, vectors, and scalars—into a single matrix type, eliminating the need to design separate processing logic for each data format. This unified data processing approach reduces the amount of code and logical complexity in the reference model, lowers the probability of errors in the verification system itself, and improves the maintainability and scalability of the reference model.

[0018] This invention enables precise scheduling and efficient reuse of data from multiple input interfaces. It stores input data from multiple interfaces into corresponding data queues, precisely extracts the required computational data based on the needs of the current execution instruction, and restores unused data to its original queue. This mechanism effectively solves the problem of chaotic multi-interface data scheduling, ensures the accuracy of data retrieval, and achieves data reuse and retention, avoiding resource waste caused by duplicate data input.

[0019] In summary, this invention reduces the time cost of manual debugging through precise fault location capabilities, lowers the development and maintenance difficulty of the verification system through simplified reference model logic, and ensures smooth operation of the verification process through an efficient multi-interface data scheduling mechanism. Overall, it improves the verification efficiency of vector processors and shortens the R&D cycle. It is applicable to the functional verification of vector processors in fields such as artificial intelligence and deep learning, signal and image processing, scientific computing and simulation, and multimedia and audio-visual applications. Attached Figure Description

[0020] To further illustrate the advantages and other features of the various embodiments of the present invention, a more specific description of the embodiments of the present invention will be presented with reference to the accompanying drawings. It is understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by the same or similar reference numerals for clarity.

[0021] Figure 1 A flowchart of a vector processor function verification method in one embodiment of the present invention is shown.

[0022] Figure 2 The data format of the vector processor in one embodiment of the present invention is shown.

[0023] Figure 3 A flowchart involving multiple data processing is shown in one embodiment of the present invention.

[0024] Figure 4 A module architecture diagram of a vector processor functional verification system according to one embodiment of the present invention is shown.

[0025] Figure 5 An internal architecture diagram of the instruction generator module in one embodiment of the present invention is shown.

[0026] List of reference numerals in the attached figures: 100-Verification system; 101-Instruction generator module; 101-1-Instruction generation unit; 101-2-Instruction sending unit; 101-3-Instruction acquisition unit; 102-Controller module; 103-Data generation module; 104-Reference model module; 105-Data collection module; 106-Data comparator module. Detailed Implementation

[0027] It should be noted that the components in the various figures may be shown exaggeratedly for illustrative purposes and are not necessarily to scale. In each figure, the same reference numerals are used for components that are identical or have the same function.

[0028] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0029] In this invention, unless otherwise specified, the quantifiers “a” and “one” do not exclude scenarios involving multiple elements.

[0030] It should also be noted that, in the embodiments of the present invention, only a portion of the components or parts may be shown for clarity and simplicity. However, those skilled in the art will understand that, under the teachings of the present invention, necessary components or parts can be added as needed for specific scenarios. Furthermore, unless otherwise stated, features in different embodiments of the present invention can be combined with each other. For example, a feature in the second embodiment can replace a corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment will also fall within the scope of disclosure or description of this application.

[0031] It should also be noted that within the scope of this invention, the terms "same", "equal", and "equal to" do not mean that the two values ​​are absolutely equal, but allow for a certain reasonable error. In other words, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".

[0032] In this invention, the modules of the system according to the invention can be implemented using software, hardware, firmware, or a combination thereof. When a module is implemented using software, its function can be implemented through computer program flow. For example, the module can be implemented using code segments (such as code segments in languages ​​like C and C++) stored in a storage device (such as a hard disk, memory, etc.), wherein the corresponding function of the module can be implemented when the code segment is executed by a processor. When a module is implemented using hardware, its function can be implemented by setting a corresponding hardware structure. For example, the module's function can be implemented by hardware programming a programmable device such as a field-programmable gate array (FPGA), or by designing an application-specific integrated circuit (ASIC) that includes multiple transistors, resistors, capacitors, and other electronic devices. When a module is implemented using firmware, the module's function can be written into a read-only memory such as an EPROM or EEPROM in the form of program code, and the corresponding function of the module can be implemented when the program code is executed by a processor. In addition, some functions of the module may need to be implemented by separate hardware or by working in cooperation with the hardware. For example, the detection function is implemented by a corresponding sensor (such as a proximity sensor, accelerometer, gyroscope, etc.), the signal transmission function is implemented by a corresponding communication device (such as a Bluetooth device, infrared communication device, baseband communication device, Wi-Fi communication device, etc.), the output function is implemented by a corresponding output device (such as a display, speaker, etc.), and so on.

[0033] Furthermore, the numbering of the steps in the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps may be executed in different orders.

[0034] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0035] In one embodiment of the present invention, a vector processor function verification method is provided, comprising the following steps: Step S100: Verification Instruction Generation: Based on the design requirements of the vector processor to be verified, generate verification instructions that adapt to the instruction set architecture, operation rules, and timing constraints of the vector processor. The design requirements include: the operation types, instruction formats, data bit width, and address bit width supported by the vector processor.

[0036] Step S200: Multi-interface data input and verification configuration parameter generation: Matrix, vector, and scalar data are input in parallel to the vector processor's design module through multiple data input interfaces. This input data is adaptable to different data bit widths and address bit widths, meeting the verification scenarios of multi-dimensional data operations by the vector processor. Simultaneously, a configurable controller module generates the configuration parameters required for vector processor functional verification. These parameters match the vector processor's hardware configuration, operation mode, and interface timing, providing a standardized control basis for the verification process.

[0037] Step S300: Unified Data Format Conversion and Data Queue Storage: Input data from each data input interface, including matrix, vector, and scalar formats, is uniformly processed into matrix type data. After format conversion, the input data corresponding to each data input interface is stored in the form of "data address + data content" into a data queue corresponding to each data input interface. Data from different interfaces is cached independently to avoid data confusion.

[0038] Step S400: Sequential Data Extraction: Based on the current execution instruction obtained by the instruction collector, the input data in each data queue is sequentially extracted. Input data from each data queue is retrieved in turn, and the retrieved data is determined to be the computational data required for executing the current instruction, based on the computational requirements of the current instruction and address matching rules. Data that meets the instruction requirements is directly used as computational data for subsequent computational processes; redundant input data that does not belong to the current instruction is temporarily stored in a temporary queue to maintain data integrity.

[0039] Step S500: Redundant Data Back-Storage and Expected Output Data Calculation: After the current instruction's computation flow is completed, the redundant input data temporarily stored in the temporary queue is back-stored to the corresponding target data queue according to its original data input interface. This achieves the reuse and retention of unused data, ensuring that subsequent instructions can continue to call this part of the data. Subsequently, based on the current instruction, the extracted computational data, and the configuration parameters, the equivalent computational logic of the vector processor is executed through the reference model to calculate the expected output data at the clock cycle level.

[0040] Step S600: Actual output data acquisition: Through multiple output data collection modules, the actual output data generated by the vector processor's design module after executing the current instruction is collected synchronously, and the calculation output results of the design module are completely captured.

[0041] Step S700, Data Comparison and Functional Verification: The expected output data generated by the reference model is compared bit by bit and clock cycle by clock cycle with the actual output data collected by the output data collection module. Based on the comparison results, it is determined whether the function of the vector processor design module meets the design requirements. If the two sets of data are completely consistent, the vector processor design module is deemed to be functionally correct; if there are data differences, the fault location can be quickly located based on the clock cycle-level comparison results, thus completing the functional verification of the vector processor.

[0042] In one embodiment of the present invention, in step S100, instruction sets that meet the verification requirements are generated in batches, and the instructions are sent to the vector processor design module. At the same time, the instructions actually received by the vector processor design module are collected in real time to ensure the accuracy and traceability of instruction transmission and provide instruction basis for subsequent synchronous operation of the reference model.

[0043] In one embodiment of the present invention, such as Figure 2 As shown, input data in row vector format is converted into a matrix with 1 row, input data in column vector format is converted into a matrix with 1 column, and input data in scalar format is converted into a matrix with 1 row and 1 column. All data formats are ultimately processed uniformly as an m-row n-column matrix structure.

[0044] In one embodiment of the present invention, the complete execution logic of steps S400 and S500 is as follows: Figure 3 As shown, this is used to achieve precise scheduling and unified management of data from multiple input interfaces. The specific execution process is as follows: After the process begins, the input data storage operation is performed first. All data input from the k data input interfaces of the vector processor is stored into k data queues corresponding to each interface. The data in each data queue is stored in the form of "data address + data content". Data from different interfaces is cached independently to avoid confusion between data from different sources.

[0045] After data storage is complete, a sequential polling method is used to retrieve single sets of data from the first data queue to the kth data queue. After each set of data is retrieved, it is immediately determined whether the data set is the computational data required for executing the current instruction, based on the computational requirements of the current instruction and the address matching rules. If the determination result is negative, the retrieved data set is temporarily stored in a temporary queue, and the sequential polling step is returned to continue retrieving data from the next data queue for determination, until a round of polling of all k data queues is completed. If the determination result is positive, the data set is used as computational data and input into the computation unit of the reference model. Combined with the current instruction and configuration parameters, the corresponding expected output data is calculated. This polling, determination, and calculation process is repeated until all computational data required by the current instruction has been retrieved and all related calculations have been completed.

[0046] After all data for the current instruction has been calculated, a temporary queue data write-back operation is performed. All unused data temporarily stored in the temporary queue is written back to the corresponding original data queue according to its original data input interface, ensuring that the data can be called back when subsequent instructions are executed.

[0047] Figure 4 A module architecture diagram of a vector processor functional verification system is shown in one embodiment of the present invention.

[0048] like Figure 4 As shown, in one embodiment of the present invention, a vector processor functional verification system 100 (hereinafter referred to as the "verification system") is provided, including an instruction generator module 101, a controller module 102, a data generation module 103, a reference model module 104, a data collection module 105, and a data comparator module 106. Each module establishes a connection relationship through hardware circuits or standardized software interfaces to collaboratively complete the functional verification process of the vector processor design module.

[0049] Figure 5 An internal architecture diagram of the instruction generator module is shown in one embodiment of the present invention.

[0050] like Figure 5 As shown, in one embodiment of the present invention, the instruction generator module 101 is used to provide instructions that meet the design requirements of the vector processor. The design requirements include the instruction set architecture supported by the vector processor, instruction format, opcode definition, operation type, and timing constraints. The instruction generator module 101 includes an instruction generation unit 101-1, an instruction sending unit 101-2, and an instruction acquisition unit 101-3. The output of the instruction generation unit 101-1 is connected to the input of the instruction sending unit 101-2, the output of the instruction sending unit 101-2 is connected to the instruction input of the vector processor design module, the input of the instruction acquisition unit 101-3 is connected to the instruction input of the vector processor design module, and the output of the instruction acquisition unit 101-3 is connected to the instruction input of the reference model module 104.

[0051] In one embodiment of the present invention, the instruction generation unit 101-1 is used to generate an instruction set that meets the design requirements of the vector processor. The instruction sending unit 101-2 is used to send the instructions generated by the instruction generation unit 101-1 to the design module of the vector processor according to a preset timing sequence. The instruction acquisition unit 101-3 is used to acquire the instructions currently being executed by the design module of the vector processor in real time, and synchronously transmit the acquired instructions to the reference model module 104, so that the reference model module 104 can maintain synchronization of instruction execution with the design module of the vector processor.

[0052] In one embodiment of the present invention, the controller module 102 is used to provide configuration parameters that meet the design requirements of the vector processor. The controller module 102 is a configurable controller module, and its output is connected to the control input of the reference model module 104. The configuration parameters include the vector processor's hardware configuration parameters, operation mode parameters, and interface timing parameters, which can be flexibly adjusted according to different verification requirements, providing a standardized control basis for the verification process.

[0053] In one embodiment of the present invention, a data generation module 103 is used to provide input data to the vector processor design module and the reference model module 104. Multiple data generation modules 103 are provided, and their outputs are respectively connected to multiple data inputs of the vector processor design module and the reference model module 104. The multiple data generation modules 103 provide input data with different data bit widths and different address bit widths. The input data formats include matrices, vectors, and scalars, which can cover the verification requirements of all data operation scenarios of the vector processor.

[0054] In one embodiment of the present invention, the reference model module 104 is used to calculate the desired output data based on the instructions provided by the instruction generator module 101, the configuration parameters provided by the controller module 102, and the input data provided by the data generation module 103. The reference model module 104 integrates a data format conversion unit, a data queue management unit, and a calculation unit.

[0055] In one embodiment of the present invention, the data format conversion unit is used to uniformly process input data in matrix, vector, and scalar formats into a matrix type. Specifically, input data in row vector format is processed into a matrix with 1 row, input data in column vector format is processed into a matrix with 1 column, and input data in scalar format is processed into a matrix with 1 row and 1 column. All data are processed in subsequent operations using a unified matrix structure.

[0056] In one embodiment of the present invention, a data queue management unit is used to manage the input data of multiple data input interfaces. The data queue management unit stores the input data from each data input interface in the form of "data address + data content" into a data queue corresponding to each data input interface. Upon receiving the currently executed instruction, the data queue management unit extracts the computational data required to execute the current instruction from the corresponding data queue according to the instruction's computational requirements and address matching rules. For input data not required by the current instruction, the data queue management unit temporarily stores it in a temporary queue. After all computations of the current instruction are completed, the data in the temporary queue is stored back to the corresponding original data queue, achieving reuse and retention of unused data. The computation unit is used to execute computational logic equivalent to the vector processor's design module based on the current instruction, the extracted computational data, and configuration parameters, generating the desired output data at the clock cycle level.

[0057] In one embodiment of the present invention, a data collection module 105 is used to collect the actual output data output by the vector processor design module. Multiple data collection modules 105 are used, with their input terminals connected to multiple data output terminals of the vector processor design module, and their output terminals connected to the first input terminal of the data comparator module 106. The multiple data collection modules 105 synchronously collect multiple output data from the vector processor design module, ensuring the temporal integrity and accuracy of the collected data.

[0058] In one embodiment of the present invention, the data comparator module 106 is used to determine the correctness of the vector processor design module's function by comparing the expected output data and the actual output data. The second input terminal of the data comparator module 106 is connected to the output terminal of the reference model module 104. The data comparator module 106 receives the expected output data at the clock cycle level output by the reference model module 104 and the actual output data collected by the data collection module 105, and performs a bit-by-bit, clock-cycle-by-clock comparison of the two sets of data. If the two sets of data are completely consistent, it is determined that the vector processor design module functions correctly under the current instruction; if there are data differences, the specific clock cycle, execution instruction, or data interface where the fault occurred can be quickly located based on the clock cycle-level comparison result, thereby achieving accurate fault location.

[0059] In one embodiment of the present invention, the overall workflow of the verification system 100 is as follows: First, the instruction generator module 101 generates instructions that meet the design requirements and sends them to the vector processor design module. Simultaneously, it collects the instructions currently being executed by the vector processor design module and synchronizes them to the reference model module 104. Second, multiple data generation modules 103 generate input data of different formats and bit widths, which are input in parallel to the vector processor design module and the reference model module 104. The controller module 102 generates appropriate configuration parameters and transmits them to the reference model module 104. Then, the reference model module 104 performs format unification conversion and queue management on the input data, executes calculations according to the synchronized instructions and configuration parameters, and generates the expected output data at the clock cycle level. Simultaneously, the vector processor design module executes the same instructions and calculations to generate the actual output data. Finally, the data collection module 105 collects the actual output data and transmits it to the data comparator module 106. The data comparator module 106 compares the expected output data with the actual output data to determine the functional correctness of the vector processor design module.

[0060] In one embodiment of the present invention, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor is connected to the memory via a bus. The processor is capable of reading and executing the computer program stored in the memory. When the processor executes the computer program, it implements the steps of the vector processor functional verification method described in the foregoing embodiments of the present invention. The computer device can be a standalone server, workstation, personal computer, or embedded computing device, capable of providing computational support for the functional verification of the vector processor, and completing all verification processes such as instruction generation, data processing, reference model calculation, and data comparison.

[0061] In one embodiment of the present invention, a computer-readable storage medium is provided on which a computer program is stored. The computer-readable storage medium may be a hard disk, optical disk, flash memory, read-only memory, or random access memory, or any other medium capable of storing a computer program. When the computer program is executed by a processor, it implements the steps of the vector processor function verification method described in the foregoing embodiments of the present invention. Through this computer-readable storage medium, the vector processor function verification method of the present invention can be stored and disseminated, facilitating deployment and use on different computing devices.

[0062] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A method for verifying the functionality of a vector processor, characterized in that, include: Provides instructions that meet the design requirements of vector processors; Input data is fed into the vector processor through multiple data input interfaces; Provide the configuration parameters required for vector processor verification; The input data is converted into a matrix type and stored in the corresponding data queues, wherein the data queues include data addresses and corresponding input data; The required input data is extracted from the data queue as computation data according to the instruction; Based on the instructions, calculated data, and configuration parameters, the processing is performed to calculate the desired output data. Acquire the actual output data from the vector processor design module; as well as The expected output data is compared with the actual output data to determine whether the vector processor design module functions correctly.

2. The method according to claim 1, characterized in that, The input data format includes at least one of matrix, vector, and scalar.

3. The method according to claim 1, characterized in that, The step of retrieving the required input data from the data queue according to the instruction includes: The system sequentially retrieves input data from each data queue using a polling method. It then determines whether the retrieved input data is required to execute the current instruction based on the current instruction. Input data that is not required to execute the current instruction is stored in a temporary queue.

4. The method according to claim 3, characterized in that, After the calculation is completed, the input data in the temporary queue is stored back into the corresponding data queue.

5. The method according to claim 1, characterized in that, The steps of converting the input data format to a matrix type include: Process the input data in row vector format into a matrix with 1 row; Process the input data in column vector format into a matrix with one column; and Process the scalar format input data into a matrix with 1 row and 1 column.

6. A vector processor function verification system, characterized in that, The system for performing the method according to any one of claims 1 to 5 comprises: The instruction generator module is used to provide instructions that meet the design requirements of the vector processor; The controller module is used to provide configuration parameters that meet the design requirements. The data generation module is used to provide input data to the vector processor's design module and reference model module. The reference model module is used to calculate the desired output data based on the instructions provided by the instruction generator module, the configuration parameters provided by the controller module, and the input data provided by the data generation module, wherein the input data is uniformly processed into a matrix type in the reference model module. A data collection module is used to collect the actual output data from the design module of the vector processor; and The data comparator module is used to determine the correctness of the design module function of the vector processor by comparing the expected output data with the actual output data.

7. The system according to claim 6, characterized in that, The instruction generator module includes: An instruction generation unit is used to generate instructions that meet the verification requirements of the vector processor. An instruction sending unit is configured to send the instructions generated by the instruction generation unit to the design module of the vector processor; and An instruction acquisition unit is configured to acquire the instructions currently being executed by the vector processor.

8. The system according to claim 6, characterized in that, The number of data generation modules is multiple, each providing input data with different data bit widths and / or different address bit widths.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 5.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.

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