Dual power supply redundant error correction transient dose rate radiation hardened flip-flop of an fdsoi process

Abstract

The application discloses a dual power supply redundancy error correction instantaneous dose rate radiation hardened flip-flop of an FDSOI process, adopts a circuit and layout combined design reinforcement method, designs a dual power supply redundancy error correction circuit structure for the problem that instantaneous dose rate radiation causes power voltage disturbance, can filter pulse signals caused by instantaneous dose rate radiation, and designs the redundancy power supply as the shortest length and the maximum width wiring in the layout reinforcement design, so that the disturbance of the redundancy power supply voltage can be reduced. The application suppresses logic errors caused by power voltage disturbance through the dual power supply redundancy error correction structure, improves the instantaneous dose rate radiation resistance of the flip-flop unit, and simultaneously uses the redundancy power supply non-globally, so that the reinforcement cost is small.

Description

TECHNICAL FIELD

[0001] The present application relates to a kind of double power supply redundancy error correction instantaneous dose rate radiation hardening flip-flop of FDSOI process, especially, it relates to a kind of circuit of double power supply redundancy structure. BACKGROUND

[0002] Instantaneous dose rate radiation effect is the overall radiation that electronic device receives, refers to a large number of rays etc. in extremely short time incident in semiconductor, generates electron hole pair, forms photocurrent, triggers a series of logic errors of device or circuit.Power supply voltage disturbance is the typical form of instantaneous dose rate radiation.For the basic combination logic unit and timing unit of digital circuit, instantaneous dose rate radiation can produce different influences.In combination logic unit, the disturbance can trigger transient pulse to appear in data signal, and in timing unit, bit flip can be triggered.When dose rate is relatively high, latch-up phenomenon caused by parasitic structure can also appear, and even lead to circuit burnout.Instantaneous dose rate radiation makes the reliability of integrated circuit in radiation environment be seriously influenced, threatens the normal operation of electronic system.

[0003] Flip-flop is the basic unit of integrated circuit, and its anti-radiation performance is very critical and important.With the continuous progress of technology, the performance of integrated circuit is also improved.In order to cope with the problem that feature size decreases and makes leakage current too large, FDSOI (Fully Depleted Silicon-on-Insulator) structure is widely used.FDSOI process realizes the complete medium isolation of device by increasing buried oxide layer, and its mechanism of instantaneous dose rate radiation effect is different from that of bulk silicon process.The traditional hardening design method, such as dual interlocked structure (Dual Interlocked Storage Cell, DICE) and triple modular redundancy structure, will sacrifice larger layout area and power consumption, so as to offset the advantages of high integration and low power consumption of FDSOI process, and is not suitable for anti-instantaneous dose rate radiation hardening design of FDSOI process integrated circuit.Based on the characteristics of FDSOI process, a kind of double power supply redundancy error correction instantaneous dose rate radiation hardening flip-flop of FDSOI process is designed. SUMMARY

[0004] The technical problem solved by the present application is to overcome the shortcomings of the prior art, provide a kind of double power supply redundancy error correction instantaneous dose rate radiation hardening flip-flop of FDSOI process, improve the anti-instantaneous dose rate radiation hardening ability of flip-flop, and be easy to realize through circuit and layout design hardening.

[0005] The technical solution of the present application is:

[0006] A dual power supply redundancy error correction instantaneous dose rate radiation hardened flip-flop of FDSOI process, comprising: a data input structure, a clock input structure, a redundant clock input structure, a first clock control structure, a second clock control structure, a data master latch structure, a data slave latch structure and a data output structure;

[0007] The data input structure sends external input data into the first clock control structure, the first clock control structure transmits the input data into the data master latch structure when the clock is low; the data master latch structure transmits data to the second clock control structure when the clock is low; the data master latch structure latches data when the clock is high;

[0008] The second clock control structure transmits data input therein into the data slave latch structure when the clock is high, the data slave latch structure transmits data to the data output structure for data output when the clock is high; the data slave latch structure latches data when the clock is low.

[0009] Further, the data input structure comprises a first stacked inverter circuit 101 and a second stacked inverter circuit 102;

[0010] The first stacked inverter circuit 101 comprises PMOS tubes 301, 302, NMOS tubes 303, 304;

[0011] Wherein the gates of the PMOS tubes 301, 302 and the NMOS tubes 303, 304 are connected together as the input end In of the first stacked inverter circuit 101, the source of the PMOS tube 301 is connected to the power supply VDD, the drain is connected to the source of the PMOS tube 302, the drain of the PMOS tube 302 is connected to the drain of the NMOS tube 303 and serves as the output end Out of the first stacked inverter circuit 101, the source of the NMOS tube 303 is connected to the drain of the NMOS tube 304, the source of the NMOS tube 304 is connected to the power supply ground VSS; the input end In of the first stacked inverter circuit 101 is connected to the input signal Input of the flip-flop circuit, and the output end Out is connected to the input end In of the second stacked inverter circuit 102;

[0012] The second stacked inverter circuit 102 comprises PMOS tubes 305, 306, NMOS tubes 307, 308;

[0013] The gates of the PMOS transistors 305, 306 and the NMOS transistors 307, 308 are connected together as the input In of the second stacked inverter circuit 102, the source of the PMOS transistor 305 is connected to the power supply VDD, the drain of the PMOS transistor 305 is connected to the source of the PMOS transistor 306, the drain of the PMOS transistor 306 is connected to the drain of the NMOS transistor 307 and serves as the output Out of the second stacked inverter circuit 102, the source of the NMOS transistor 307 is connected to the drain of the NMOS transistor 308, and the source of the NMOS transistor 308 is connected to the power supply ground VSS; the input In of the second stacked inverter circuit 102 is connected to the output Out of the first stacked inverter circuit 101, and the output Out of the second stacked inverter circuit 102 is connected to the input In of the first clock control structure 103.

[0014] Further, the fourth stacked inverter circuit 110 constitutes the clock input structure, and the fourth stacked inverter circuit 110 further includes PMOS transistors 325, 326 and NMOS transistors 327, 328.

[0015] The gates of the PMOS transistors 325, 326 and the NMOS transistors 327, 328 are connected together as the input In of the fourth stacked inverter circuit 110, the source of the PMOS transistor 325 is connected to the power supply VDD, the drain of the PMOS transistor 325 is connected to the source of the PMOS transistor 326, the drain of the PMOS transistor 326 is connected to the drain of the NMOS transistor 327 and serves as the output CLKN of the fourth stacked inverter circuit 110, the source of the NMOS transistor 327 is connected to the drain of the NMOS transistor 328, and the source of the NMOS transistor 328 is connected to the power supply ground VSS; the input In of the fourth stacked inverter circuit 110 is connected to the clock signal CLK, and the output CLKN of the fourth stacked inverter circuit 110 is connected to the input CLKN of the first clock control structure and the second clock control structure, the clock input CP of the data master latch structure and the data slave latch structure.

[0016] The fifth stacked inverter circuit 111 constitutes a redundant clock input structure powered by a redundant power supply, and the fifth stacked inverter circuit 111 further includes PMOS transistors 329, 330 and NMOS transistors 331, 332.

[0017] The gates of the PMOS transistors 329 and 330 and the NMOS transistors 331 and 332 are connected together as an input end In of the fifth stacked inverter circuit 111, the source of the PMOS transistor 329 is connected to the redundant power supply VDDC signal, the drain of the PMOS transistor 329 is connected to the source of the PMOS transistor 330, the drain of the PMOS transistor 330 is connected to the drain of the NMOS transistor 331 and serves as an output end CLKN1 of the fifth stacked inverter circuit 111, the source of the NMOS transistor 331 is connected to the drain of the NMOS transistor 332, the source of the NMOS transistor 332 is connected to the power supply ground VSS; the input end In of the fifth stacked inverter circuit 111 is connected to the clock signal CLK, and the output end CLKN1 of the fifth stacked inverter circuit 111 is connected to the data slave latch structure.

[0018] Further, the first clock control structure is formed by using the first stacked clock control structure 103; the first stacked clock control structure 103 comprises PMOS transistors 401, 402 and 403 and NMOS transistors 404, 405 and 406.

[0019] The gates of the PMOS transistors 401 and 402 and the NMOS transistors 405 and 406 in the first stacked clock control structure 103 are connected together as an input end In of the first stacked clock control structure 103, the gate of the PMOS transistor 403 in the first stacked clock control structure 103 serves as an input end CLK of the first stacked clock control structure 103 and is connected to the clock signal CLK, the gate of the NMOS transistor 404 in the first stacked clock control structure 103 serves as an input end CLKN of the first stacked clock control structure 103 and is connected to the output end CLKN of the fourth stacked inverter circuit 110; the source of the PMOS transistor 401 is connected to the power supply VDD, the drain of the PMOS transistor 401 is connected to the source of the PMOS transistor 402, the drain of the PMOS transistor 402 is connected to the source of the PMOS transistor 403, the drain of the PMOS transistor 403 is connected to the drain of the NMOS transistor 404 and serves as an output end Out of the first stacked clock control structure 103, the source of the NMOS transistor 404 is connected to the drain of the NMOS transistor 405, the source of the NMOS transistor 405 is connected to the drain of the NMOS transistor 406, and the source of the NMOS transistor 406 is connected to the power supply ground VSS; the input end In of the first stacked clock control structure 103 is connected to the output end Out of the second stacked inverter circuit 102, and the output end Out of the first stacked clock control structure 103 is connected to the input end In of the data master latch structure.

[0020] The second clock control structure is formed by using the second stacked clock control structure 105; the second stacked clock control structure 105 comprises PMOS transistors 413, 414 and 415 and NMOS transistors 416, 417 and 418.

[0021] The gates of the PMOS transistors 413 and 414 and the NMOS transistors 417 and 418 in the second stacked clock control structure 105 are connected together as an input terminal In of the second stacked clock control structure 105, the gate of the PMOS transistor 415 in the second stacked clock control structure 105 is connected to the output terminal CLKN of the fourth stacked inverter circuit 110 as an input terminal CLKN of the second stacked clock control structure 105, and the gate of the NMOS transistor 416 in the second stacked clock control structure 105 is connected to the clock signal CLK as an input terminal CLK of the second stacked clock control structure 105; the source of the PMOS transistor 413 is connected to the power supply VDD, the drain of the PMOS transistor 413 is connected to the source of the PMOS transistor 414, the drain of the PMOS transistor 414 is connected to the source of the PMOS transistor 415, the drain of the PMOS transistor 415 is connected to the drain of the NMOS transistor 416, and serves as an output terminal Out of the second stacked clock control structure 105, the source of the NMOS transistor 416 is connected to the drain of the NMOS transistor 417, the source of the NMOS transistor 417 is connected to the drain of the NMOS transistor 418, the source of the NMOS transistor 418 is connected to the power supply ground VSS; the output terminal Out of the data main latch structure is connected to the input terminal In of the second stacked clock control structure 105, and the output terminal Out of the second stacked clock control structure 105 is connected to the input terminal In of the data slave latch structure.

[0022] Further, the data main latch structure is formed by the first stacked latch structure 104;

[0023] The first stacked latch structure 104 comprises a first sub-stacked inverter circuit 201 and a first sub-stacked clock control structure 202;

[0024] The output terminal Out of the first sub-stacked inverter circuit 201 is connected to the input terminal In of the first sub-stacked clock control structure 202, and serves as the output terminal Out of the first stacked latch structure 104; the output terminal Out of the first sub-stacked clock control structure 202 is connected to the input terminal In of the first sub-stacked inverter circuit 201, and serves as the input terminal In of the first stacked latch structure 104;

[0025] The input terminal CLKN of the first sub-stacked clock control structure 202 serves as the input terminal CP of the first stacked latch structure 104, and is connected to the output terminal CLKN of the fourth stacked inverter circuit 110; the input terminal CLK of the first sub-stacked clock control structure 202 serves as the input terminal CPN of the first stacked latch structure 104, and is connected to the clock signal CLK; the input terminal In of the first stacked latch structure 104 is connected to the output terminal Out of the first stacked clock control structure 103, and the output terminal Out of the first stacked latch structure 104 is connected to the input terminal In of the second stacked clock control structure 105.

[0026] Further,

[0027] The first sub-stack inverter circuit 201 comprises PMOS tubes 309, 310, NMOS tubes 311, 312;

[0028] The gates of the PMOS tubes 309, 310 and the NMOS tubes 311, 312 are connected together as the input end of the first sub-stack inverter circuit 201, the source of the PMOS tube 309 is connected to the power supply VDD, the drain is connected to the source of the PMOS tube 310, the drain of the PMOS tube 310 is connected to the drain of the NMOS tube 311 and serves as the output end Out of the first sub-stack inverter circuit 201, the source of the NMOS tube 311 is connected to the drain of the NMOS tube 312, and the source of the NMOS tube 312 is connected to the power supply ground VSS; the input end of the first sub-stack inverter circuit 201 is connected to the output end Out of the first stack clock control structure 103 and the output end Out of the first sub-stack clock control structure 202, and the output end of the first sub-stack inverter circuit 201 is connected to the input end In of the first sub-stack clock control structure 202 and the input end In of the second stack clock control structure 105;

[0029] The first sub-stack clock control structure 202 comprises PMOS tubes 407, 408, 409, and NMOS tubes 410, 411, 412.

[0030] The gates of the PMOS tubes 407, 408 and the NMOS tubes 411, 412 are connected together as the input end In of the first sub-stack clock control structure 202, the gate of the PMOS tube 409 in the first sub-stack clock control structure 202 serves as the input end CLKN of the first sub-stack clock control structure 202, and is connected to the output end CLKN of the fourth stack inverter circuit 110; the gate of the NMOS tube 410 in the first sub-stack clock control structure 202 serves as the input end CLK of the first sub-stack clock control structure 202, and is connected to the clock signal CLK; the source of the PMOS tube 407 is connected to the power supply VDD, the drain is connected to the source of the PMOS tube 408, the drain of the PMOS tube 408 is connected to the source of the PMOS tube 409, the drain of the PMOS tube 409 is connected to the drain of the NMOS tube 410, and serves as the output end Out of the first sub-stack clock control structure 202; the source of the NMOS tube 410 is connected to the drain of the NMOS tube 411, the source of the NMOS tube 411 is connected to the drain of the NMOS tube 412, and the source of the NMOS tube 412 is connected to the power supply ground VSS.

[0031] The input end In of the first sub-stack clock control structure 202 is connected to the output end Out of the first sub-stack inverter circuit 201 and the input end In of the second stack clock control structure 105, and the output end of the first sub-stack clock control structure 202 is connected to the output end Out of the first stack clock control structure 103 and the input end In of the first sub-stack inverter circuit 201.

[0032] Further, the data from latch structure with redundant power supply and redundant clock is composed of the second stacked latch structure 106, the third stacked latch structure 107 and the stacked C cell structure 108;

[0033] The input end In of the second stacked latch structure 106 is connected with the input end In of the third stacked latch structure 107, and the output end Out of the second stacked latch structure 106 is connected with the first input end In1 of the stacked C cell structure 108, and the output end Out of the third stacked latch structure 107 is connected with the second input end In2 of the stacked C cell structure 108;

[0034] The second stacked latch structure 106 comprises a second sub-stacked inverter circuit 203 and a second sub-stacked clock control structure 204;

[0035] The output end Out of the second sub-stacked inverter circuit 203 is connected with the input end In of the second sub-stacked clock control structure 204 and serves as the output end Out of the second stacked latch structure 106; the output end Out of the second sub-stacked clock control structure 204 is connected with the input end In of the second sub-stacked inverter circuit 203 and serves as the input end In of the second stacked latch structure 106; the input end CLK of the second sub-stacked clock control structure 204 serves as the input end CP of the second stacked latch structure 106 and is connected with the clock signal CLK; the input end CLKN1 of the second sub-stacked clock control structure 204 serves as the input end CPN of the second stacked latch structure 106 and is connected with the output end CLKN1 of the fifth stacked inverter circuit 111; the input end In of the second stacked latch structure 106 is connected with the output end Out of the second stacked clock control structure 105 and the input end In of the third stacked latch structure 107, and the output end Out of the second stacked latch structure 106 is connected with the first input end In1 of the stacked C cell structure 108;

[0036] The third stacked latch structure 107 comprises a third sub-stacked inverter circuit 205 and a third sub-stacked clock control structure 206;

[0037] The output end Out of the third sub-stack inverter circuit 205 is connected to the input end In of the third sub-stack clock control structure 206 and serves as the output end Out of the third stack latch structure 107; the output end Out of the third sub-stack clock control structure 206 is connected to the input end In of the third sub-stack inverter circuit 205 and serves as the input end In of the third stack latch structure 107; the input end CLK of the third sub-stack clock control structure 206 serves as the input end CP of the third stack latch structure 107 and is connected to the clock signal CLK; the input end CLKN of the third sub-stack clock control structure 206 serves as the input end CPN of the third stack latch structure 107 and is connected to the output end CLKN of the fourth stack inverter circuit 110; the input end In of the third stack latch structure 107 is connected to the output end Out of the second stack clock control structure 105 and the input end In of the second stack latch structure 106, and the output end Out of the third stack latch structure 107 is connected to the second input end In2 of the stack C cell structure 108.

[0038] Further, the stack C cell structure 108 comprises PMOS tubes 501, 502, 503 and NMOS tubes 504, 505, 506.

[0039] The gates of the PMOS tubes 501, 502 and the NMOS tubes 505, 506 in the stack C cell structure 108 are connected together as the first input end In1 of the stack C cell structure 108, and the gates of the PMOS tube 503 and the NMOS tube 504 are connected together as the second input end In2 of the stack C cell structure 108; the source of the PMOS tube 501 is connected to the redundant power supply VDDC signal, the drain of the PMOS tube 501 is connected to the source of the PMOS tube 502, the drain of the PMOS tube 502 is connected to the source of the PMOS tube 503, the drain of the PMOS tube 503 is connected to the drain of the NMOS tube 504 and serves as the output end Out of the stack C cell structure 108, the source of the NMOS tube 504 is connected to the drain of the NMOS tube 505, the source of the NMOS tube 505 is connected to the drain of the NMOS tube 506, and the source of the NMOS tube 506 is connected to the power supply ground VSS.

[0040] The first input end In1 of the stack C cell structure 108 is connected to the output end Out of the second stack latch structure 106, the second input end In2 of the stack C cell structure 108 is connected to the output end Out of the third stack latch structure 107, and the output end Out of the stack C cell structure 108 is connected to the input end In of the data output structure, which is the third stack inverter circuit 109.

[0041] Further,

[0042] The second sub-stack inverter circuit 203 comprises PMOS tubes 313, 314, NMOS tubes 315, 316;

[0043] The gates of the PMOS tubes 313, 314 and the NMOS tubes 315, 316 are connected together as the input end of the second sub-stack inverter circuit 203, the source of the PMOS tube 313 is connected to the redundant power supply VDDC signal, the drain is connected to the source of the PMOS tube 314, the drain of the PMOS tube 314 is connected to the drain of the NMOS tube 315 and serves as the output end Out of the second sub-stack inverter circuit 203, the source of the NMOS tube 315 is connected to the drain of the NMOS tube 316, the source of the NMOS tube 316 is connected to the power supply ground VSS; the input end of the second sub-stack inverter circuit 203 is connected to the output end Out of the second stack clock control structure 105, the input end In of the third stack latch structure 107 and the output end Out of the second sub-stack clock control structure 204, and the output end of the second sub-stack inverter circuit 203 is connected to the input end In of the second sub-stack clock control structure 204 and the first input end In1 of the stack C cell structure 108;

[0044] The second sub-stack clock control structure 204 comprises PMOS tubes 419, 420, 421, NMOS tubes 422, 423, 424;

[0045] The gates of the PMOS transistors 419 and 420 and the NMOS transistors 423 and 424 are connected together as an input terminal In of the second sub-stack clock control structure 204, the gate of the PMOS transistor 421 in the second sub-stack clock control structure 204 is an input terminal CLK of the second sub-stack clock control structure 204, and the clock signal CLK is connected to the input terminal CLK, the gate of the NMOS transistor 422 in the second sub-stack clock control structure 204 is an input terminal CLKN1 of the second sub-stack clock control structure 204, and the output terminal CLKN1 of the fifth stack inverter circuit 111 is connected to the input terminal CLKN1; the source of the PMOS transistor 419 is connected to the redundant power supply VDDC signal, the drain of the PMOS transistor 419 is connected to the source of the PMOS transistor 420, the drain of the PMOS transistor 420 is connected to the source of the PMOS transistor 421, the drain of the PMOS transistor 421 is connected to the drain of the NMOS transistor 422, and the drain of the PMOS transistor 421 is an output terminal Out of the second sub-stack clock control structure 204, the source of the NMOS transistor 422 is connected to the drain of the NMOS transistor 423, the source of the NMOS transistor 423 is connected to the drain of the NMOS transistor 424, the source of the NMOS transistor 424 is connected to the power supply ground VSS; the input terminal In of the second sub-stack clock control structure 204 is connected to the output terminal Out of the second sub-stack inverter circuit 203 and the first input terminal In1 of the stack C cell structure 108, and the output terminal of the second sub-stack clock control structure 204 is connected to the output terminal Out of the second stack clock control structure 105, the input terminal In of the third stack latch structure 107, and the input terminal In of the second sub-stack inverter circuit 203;

[0046] The third sub-stack inverter circuit 205 includes PMOS transistors 317 and 318 and NMOS transistors 319 and 320.

[0047] The gates of the PMOS transistors 317 and 318 and the NMOS transistors 319 and 320 are connected together as an input terminal of the third sub-stack inverter circuit 205, the source of the PMOS transistor 317 is connected to the power supply VDD, the drain of the PMOS transistor 317 is connected to the source of the PMOS transistor 318, the drain of the PMOS transistor 318 is connected to the drain of the NMOS transistor 319 and is an output terminal Out of the third sub-stack inverter circuit 205, the source of the NMOS transistor 319 is connected to the drain of the NMOS transistor 320, and the source of the NMOS transistor 320 is connected to the power supply ground VSS; the input terminal of the third sub-stack inverter circuit 205 is connected to the output terminal Out of the second stack clock control structure 105, the input terminal In of the second stack latch structure 106, and the output terminal Out of the third sub-stack clock control structure 206, and the output terminal of the third sub-stack inverter circuit 205 is connected to the input terminal In of the third sub-stack clock control structure 206 and the input terminal In2 of the stack C cell structure 108.

[0048] The third sub-stack clock control structure 206 includes PMOS transistors 425, 426, and 427 and NMOS transistors 428, 429, and 430.

[0049] The gates of the PMOS transistors 425, 426 and the NMOS transistors 429, 430 are connected together as an input terminal In of the third sub-stacked clock control structure 206, the gate of the PMOS transistor 427 in the third sub-stacked clock control structure 206 is an input terminal CLK of the third sub-stacked clock control structure 206, and is connected to the clock signal CLK, the gate of the NMOS transistor 428 in the third sub-stacked clock control structure 206 is an input terminal CLKN of the third sub-stacked clock control structure 206, and is connected to the output terminal CLKN of the fourth stacked inverter circuit 110; the source of the PMOS transistor 425 is connected to the power supply VDD, the drain of the PMOS transistor 425 is connected to the source of the PMOS transistor 426, the drain of the PMOS transistor 426 is connected to the source of the PMOS transistor 427, the drain of the PMOS transistor 427 is connected to the drain of the NMOS transistor 428, and is an output terminal Out of the third sub-stacked clock control structure 206, the source of the NMOS transistor 428 is connected to the drain of the NMOS transistor 429, the source of the NMOS transistor 429 is connected to the drain of the NMOS transistor 430, the source of the NMOS transistor 430 is connected to the power supply ground VSS; the input terminal In of the third sub-stacked clock control structure 206 is connected to the output terminal Out of the third sub-stacked inverter circuit 205 and the input terminal In2 of the stacked C cell structure 108, and the output terminal of the third sub-stacked clock control structure 206 is connected to the output terminal Out of the second stacked clock control structure 105, the input terminal In of the second stacked latch structure 106, and the input terminal In of the third sub-stacked inverter circuit 205.

[0050] Further, the third stacked inverter circuit 109 constitutes the data output structure, and the third stacked inverter circuit 109 further includes PMOS transistors 321, 322 and NMOS transistors 323, 324.

[0051] The gates of the PMOS transistors 321, 322 and the NMOS transistors 323, 324 are connected together as an input terminal In of the third stacked inverter circuit 109, the source of the PMOS transistor 321 is connected to the redundant power supply VDDC signal, the drain of the PMOS transistor 321 is connected to the source of the PMOS transistor 322, the drain of the PMOS transistor 322 is connected to the drain of the NMOS transistor 323, and is an output terminal Out of the third stacked inverter circuit 109, the source of the NMOS transistor 323 is connected to the drain of the NMOS transistor 324, and the source of the NMOS transistor 324 is connected to the power supply ground VSS; the input terminal In of the third stacked inverter circuit 109 is connected to the output terminal Out of the stacked C cell structure 108, and the output terminal Out of the third stacked inverter circuit 109 is connected to the output terminal Output of the flip-flop circuit.

[0052] Further, the stacked latch structure 106, 107, the stacked C cell structure 108, and the fifth stacked inverter circuit 111 constitute a dual power supply redundancy error correction structure, which can filter pulse signals caused by power voltage disturbance, and realize the anti-transient dose rate radiation hardening of the FDSOI process flip-flop.

[0053] Further, the stacked inverter circuit 101, 102, 109, 110, 111, the stacked clock control structure 103, 105, the stacked latch structure 104, 106, 107, and the stacked C cell structure 108 are all designed based on the stacked structure, realizing the anti-transient dose rate radiation hardening of the FDSOI process flip-flop.

[0054] Further, in the layout design, the redundant power supply is designed as a shortest length and maximum width trace, realizing the anti-transient dose rate radiation hardening of the FDSOI process flip-flop.

[0055] The beneficial effects of the present application are:

[0056] (1) The dual power supply redundancy error correction transient dose rate radiation hardened flip-flop of the FDSOI process provided by the present application is based on dual power supply redundancy, stacked structure and power supply layout hardening, realizing the anti-transient dose rate radiation hardening.

[0057] (2) The present application adopts a design and layout combined hardening method, and the redundant power supply is not used globally, and the hardening cost is small.

[0058] (3) In the layout design, the redundant power supply is designed as a shortest length and maximum width trace, realizing the anti-transient dose rate radiation hardening of the FDSOI process flip-flop.

[0059] (4) The stacked inverter circuit, the stacked clock control structure, the stacked latch structure, and the stacked C cell structure of the present application are all designed based on the stacked structure, realizing the anti-transient dose rate radiation hardening of the FDSOI process flip-flop. BRIEF DESCRIPTION OF DRAWINGS

[0060] Figure 1 It is a circuit structure schematic diagram of the present application;

[0061] Figure 2 It is a structure diagram of the stacked latch circuit in the circuit structure of the present application;

[0062] Figure 3 It is a structure diagram of the stacked inverter circuit in the circuit structure of the present application;

[0063] Figure 4 It is a structure diagram of the stacked clock control circuit in the circuit structure of the present application;

[0064] Figure 5A structure diagram of a stacked C unit circuit of the present application;

[0065] Figure 6 A schematic diagram of a layout hardening design of the present application; DETAILED DESCRIPTION

[0066] All features disclosed in this specification, and / or all steps of any methods or processes disclosed in this specification, may be combined in any combination, except combinations where at least some of the features and / or steps are mutually exclusive.

[0067] Any of the features disclosed in this specification, unless explicitly stated otherwise, may be replaced by alternative features serving the same, or a similar, purpose.

[0068] A double power supply redundant error correction transient dose rate radiation hardened flip-flop of an FDSOI process of the present application is further described below in conjunction with the accompanying drawings and embodiments.

[0069] Figure 1 A double power supply redundant error correction transient dose rate radiation hardened flip-flop of an FDSOI process of the present application is further described below in conjunction with the accompanying drawings and embodiments.

[0070] The data input structure sends external input data into the first clock control structure, the first clock control structure transmits the input data into the data master latch structure when the clock is low; the data master latch structure transmits data into the second clock control structure when the clock is low; the data master latch structure latches data when the clock is high.

[0071] The second clock control structure transmits data input therein into the data slave latch structure when the clock is high, the data slave latch structure transmits data into the data output structure for data output when the clock is high; the data slave latch structure latches data when the clock is low.

[0072] A double power supply redundant error correction transient dose rate radiation hardened flip-flop of an FDSOI process, characterized in that comprising: a data input structure, a clock input structure, a redundant clock input structure, a first clock control structure, a second clock control structure, a data master latch structure, a data slave latch structure and a data output structure;

[0073] The data input structure sends external input data into the first clock control structure, the first clock control structure transmits the input data into the data master latch structure when the clock is low; the data master latch structure transmits data into the second clock control structure when the clock is low; the data master latch structure latches data when the clock is high.

[0074] The second clock control structure transmits the data input therein to the data latch structure when the clock is high, and the data latch structure transmits the data to the data output structure for data output when the clock is high; and the data latch structure latches the data when the clock is low.

[0075] The data input structure comprises a first stacked inverter circuit 101 and a second stacked inverter circuit 102.

[0076] The first stacked inverter circuit 101 comprises PMOS tubes 301, 302 and NMOS tubes 303, 304.

[0077] The gates of the PMOS tubes 301, 302 and the NMOS tubes 303, 304 are connected together as the input end In of the first stacked inverter circuit 101, the source of the PMOS tube 301 is connected to the power supply VDD, the drain of the PMOS tube 301 is connected to the source of the PMOS tube 302, the drain of the PMOS tube 302 is connected to the drain of the NMOS tube 303 and serves as the output end Out of the first stacked inverter circuit 101, the source of the NMOS tube 303 is connected to the drain of the NMOS tube 304, the source of the NMOS tube 304 is connected to the power supply ground VSS; the input end In of the first stacked inverter circuit 101 is connected to the input signal Input of the flip-flop circuit, and the output end Out is connected to the input end In of the second stacked inverter circuit 102.

[0078] The second stacked inverter circuit 102 comprises PMOS tubes 305, 306 and NMOS tubes 307, 308.

[0079] The gates of the PMOS tubes 305, 306 and the NMOS tubes 307, 308 are connected together as the input end In of the second stacked inverter circuit 102, the source of the PMOS tube 305 is connected to the power supply VDD, the drain of the PMOS tube 305 is connected to the source of the PMOS tube 306, the drain of the PMOS tube 306 is connected to the drain of the NMOS tube 307 and serves as the output end Out of the second stacked inverter circuit 102, the source of the NMOS tube 307 is connected to the drain of the NMOS tube 308, and the source of the NMOS tube 308 is connected to the power supply ground VSS; the input end In of the second stacked inverter circuit 102 is connected to the output end Out of the first stacked inverter circuit 101, and the output end Out of the second stacked inverter circuit 102 is connected to the input end In of the first stacked clock control structure 103.

[0080] The fourth stacked inverter circuit 110 constitutes the clock input structure, and the fourth stacked inverter circuit 110 comprises PMOS tubes 325, 326 and NMOS tubes 327, 328.

[0081] The gates of the PMOS transistors 325, 326 and the NMOS transistors 327, 328 are connected together as the input end In of the fourth stacked inverter circuit 110, the source of the PMOS transistor 325 is connected to the power supply VDD, the drain of the PMOS transistor 325 is connected to the source of the PMOS transistor 326, the drain of the PMOS transistor 326 is connected to the drain of the NMOS transistor 327 and serves as the output end CLKN of the fourth stacked inverter circuit 110, the source of the NMOS transistor 327 is connected to the drain of the NMOS transistor 328, and the source of the NMOS transistor 328 is connected to the power supply ground VSS; the input end In of the fourth stacked inverter circuit 110 is connected to the clock signal CLK, and the output end CLKN of the fourth stacked inverter circuit 110 is connected to the input end CLKN of the first clock control structure and the second clock control structure, the clock input end CP of the data master latch structure, and the data slave latch structure.

[0082] The fifth stacked inverter circuit 111 constitutes a redundant clock input structure supplied by a redundant power supply, and the fifth stacked inverter circuit 111 further includes PMOS transistors 329, 330 and NMOS transistors 331, 332.

[0083] The gates of the PMOS transistors 329, 330 and the NMOS transistors 331, 332 are connected together as the input end In of the fifth stacked inverter circuit 111, the source of the PMOS transistor 329 is connected to the redundant power supply VDDC signal, the drain of the PMOS transistor 329 is connected to the source of the PMOS transistor 330, the drain of the PMOS transistor 330 is connected to the drain of the NMOS transistor 331 and serves as the output end CLKN1 of the fifth stacked inverter circuit 111, the source of the NMOS transistor 331 is connected to the drain of the NMOS transistor 332, and the source of the NMOS transistor 332 is connected to the power supply ground VSS; the input end In of the fifth stacked inverter circuit 111 is connected to the clock signal CLK, and the output end CLKN1 of the fifth stacked inverter circuit 111 is connected to the data slave latch structure.

[0084] The first clock control structure is constituted by the first stacked clock control structure 103; the first stacked clock control structure 103 includes PMOS transistors 401, 402, 403 and NMOS transistors 404, 405, 406.

[0085] The gates of the PMOS transistors 401 and 402 and the NMOS transistors 405 and 406 in the first stacked clock control structure 103 are connected together as an input terminal In of the first stacked clock control structure 103, the gate of the PMOS transistor 403 in the first stacked clock control structure 103 is an input terminal CLK of the first stacked clock control structure 103 and is connected to a clock signal CLK, the gate of the NMOS transistor 404 in the first stacked clock control structure 103 is an input terminal CLKN of the first stacked clock control structure 103 and is connected to an output terminal CLKN of the fourth stacked inverter circuit 110; the source of the PMOS transistor 401 is connected to a power supply VDD, the drain of the PMOS transistor 401 is connected to the source of the PMOS transistor 402, the drain of the PMOS transistor 402 is connected to the source of the PMOS transistor 403, the drain of the PMOS transistor 403 is connected to the drain of the NMOS transistor 404 and is an output terminal Out of the first stacked clock control structure 103, the source of the NMOS transistor 404 is connected to the drain of the NMOS transistor 405, the source of the NMOS transistor 405 is connected to the drain of the NMOS transistor 406, the source of the NMOS transistor 406 is connected to a power supply ground VSS; the input terminal In of the first stacked clock control structure 103 is connected to the output terminal Out of the second stacked inverter circuit 102, and the output terminal Out of the first stacked clock control structure 103 is connected to an input terminal In of the data main latch structure;

[0086] The second clock control structure is formed by the second stacked clock control structure 105; the second stacked clock control structure 105 comprises PMOS transistors 413, 414 and 415 and NMOS transistors 416, 417 and 418.

[0087] The gates of the PMOS transistors 413 and 414 and the NMOS transistors 417 and 418 in the second stacked clock control structure 105 are connected together as an input terminal In of the second stacked clock control structure 105, the gate of the PMOS transistor 415 in the second stacked clock control structure 105 is connected to the output terminal CLKN of the fourth stacked inverter circuit 110 as an input terminal CLKN of the second stacked clock control structure 105, and the gate of the NMOS transistor 416 in the second stacked clock control structure 105 is connected to the clock signal CLK as an input terminal CLK of the second stacked clock control structure 105; the source of the PMOS transistor 413 is connected to the power supply VDD, the drain of the PMOS transistor 413 is connected to the source of the PMOS transistor 414, the drain of the PMOS transistor 414 is connected to the source of the PMOS transistor 415, the drain of the PMOS transistor 415 is connected to the drain of the NMOS transistor 416 and serves as an output terminal Out of the second stacked clock control structure 105, the source of the NMOS transistor 416 is connected to the drain of the NMOS transistor 417, the source of the NMOS transistor 417 is connected to the drain of the NMOS transistor 418, the source of the NMOS transistor 418 is connected to the power supply ground VSS; the input terminal In of the second stacked clock control structure 105 is connected to the output terminal Out of the data main latch structure, and the output terminal Out of the second stacked clock control structure 105 is connected to the input terminal In of the data slave latch structure.

[0088] The data main latch structure is formed by the first stacked latch structure 104.

[0089] The first stacked latch structure 104 comprises a first sub-stacked inverter circuit 201 and a first sub-stacked clock control structure 202.

[0090] The output terminal Out of the first sub-stacked inverter circuit 201 is connected to the input terminal In of the first sub-stacked clock control structure 202 and serves as the output terminal Out of the first stacked latch structure 104; the output terminal Out of the first sub-stacked clock control structure 202 is connected to the input terminal In of the first sub-stacked inverter circuit 201 and serves as the input terminal In of the first stacked latch structure 104.

[0091] The input terminal CLKN of the first sub-stacked clock control structure 202 serves as the input terminal CP of the first stacked latch structure 104 and is connected to the output terminal CLKN of the fourth stacked inverter circuit 110; the input terminal CLK of the first sub-stacked clock control structure 202 serves as the input terminal CPN of the first stacked latch structure 104 and is connected to the clock signal CLK; the input terminal In of the first stacked latch structure 104 is connected to the output terminal Out of the first stacked clock control structure 103, and the output terminal Out of the first stacked latch structure 104 is connected to the input terminal In of the second stacked clock control structure 105.

[0092] The first sub-stack inverter circuit 201 comprises PMOS tubes 309, 310, NMOS tubes 311, 312;

[0093] The gates of the PMOS tubes 309, 310 and the NMOS tubes 311, 312 are connected together as the input end of the first sub-stack inverter circuit 201, the source of the PMOS tube 309 is connected to the power supply VDD, the drain is connected to the source of the PMOS tube 310, the drain of the PMOS tube 310 is connected to the drain of the NMOS tube 311 and serves as the output end Out of the first sub-stack inverter circuit 201, the source of the NMOS tube 311 is connected to the drain of the NMOS tube 312, and the source of the NMOS tube 312 is connected to the power supply ground VSS; the input end of the first sub-stack inverter circuit 201 is connected to the output end Out of the first stack clock control structure 103 and the output end Out of the first sub-stack clock control structure 202, and the output end of the first sub-stack inverter circuit 201 is connected to the input end In of the first sub-stack clock control structure 202 and the input end In of the second stack clock control structure 105.

[0094] The first sub-stack clock control structure 202 comprises PMOS tubes 407, 408, 409, and NMOS tubes 410, 411, 412.

[0095] The gates of the PMOS tubes 407, 408 and the NMOS tubes 411, 412 are connected together as the input end In of the first sub-stack clock control structure 202, the gate of the PMOS tube 409 in the first sub-stack clock control structure 202 serves as the input end CLKN of the first sub-stack clock control structure 202, and is connected to the output end CLKN of the fourth stack inverter circuit 110; the gate of the NMOS tube 410 in the first sub-stack clock control structure 202 serves as the input end CLK of the first sub-stack clock control structure 202, and is connected to the clock signal CLK; the source of the PMOS tube 407 is connected to the power supply VDD, the drain is connected to the source of the PMOS tube 408, the drain of the PMOS tube 408 is connected to the source of the PMOS tube 409, the drain of the PMOS tube 409 is connected to the drain of the NMOS tube 410, and serves as the output end Out of the first sub-stack clock control structure 202; the source of the NMOS tube 410 is connected to the drain of the NMOS tube 411, the source of the NMOS tube 411 is connected to the drain of the NMOS tube 412, and the source of the NMOS tube 412 is connected to the power supply ground VSS.

[0096] The input end In of the first sub-stack clock control structure 202 is connected to the output end Out of the first sub-stack inverter circuit 201 and the input end In of the second stack clock control structure 105, and the output end of the first sub-stack clock control structure 202 is connected to the output end Out of the first stack clock control structure 103 and the input end In of the first sub-stack inverter circuit 201.

[0097] The data from latch structure with redundant power supply and redundant clock is composed of the second stacked latch structure 106, the third stacked latch structure 107 and the stacked C cell structure 108;

[0098] The input end In of the second stacked latch structure 106 is connected with the input end In of the third stacked latch structure 107, and the output end Out of the second stacked latch structure 106 is connected with the first input end In1 of the stacked C cell structure 108, and the output end Out of the third stacked latch structure 107 is connected with the second input end In2 of the stacked C cell structure 108;

[0099] The second stacked latch structure 106 comprises a second sub-stacked inverter circuit 203 and a second sub-stacked clock control structure 204;

[0100] The output end Out of the second sub-stacked inverter circuit 203 is connected with the input end In of the second sub-stacked clock control structure 204 and serves as the output end Out of the second stacked latch structure 106; the output end Out of the second sub-stacked clock control structure 204 is connected with the input end In of the second sub-stacked inverter circuit 203 and serves as the input end In of the second stacked latch structure 106; the input end CLK of the second sub-stacked clock control structure 204 serves as the input end CP of the second stacked latch structure 106 and is connected with the clock signal CLK; the input end CLKN1 of the second sub-stacked clock control structure 204 serves as the input end CPN of the second stacked latch structure 106 and is connected with the output end CLKN1 of the fifth stacked inverter circuit 111; the input end In of the second stacked latch structure 106 is connected with the output end Out of the second stacked clock control structure 105 and the input end In of the third stacked latch structure 107, and the output end Out of the second stacked latch structure 106 is connected with the first input end In1 of the stacked C cell structure 108;

[0101] The third stacked latch structure 107 comprises a third sub-stacked inverter circuit 205 and a third sub-stacked clock control structure 206;

[0102] The output end Out of the third sub-stack inverter circuit 205 is connected to the input end In of the third sub-stack clock control structure 206 and serves as the output end Out of the third stack latch structure 107; the output end Out of the third sub-stack clock control structure 206 is connected to the input end In of the third sub-stack inverter circuit 205 and serves as the input end In of the third stack latch structure 107; the input end CLK of the third sub-stack clock control structure 206 serves as the input end CP of the third stack latch structure 107 and is connected to the clock signal CLK; the input end CLKN of the third sub-stack clock control structure 206 serves as the input end CPN of the third stack latch structure 107 and is connected to the output end CLKN of the fourth stack inverter circuit 110; the input end In of the third stack latch structure 107 is connected to the output end Out of the second stack clock control structure 105 and the input end In of the second stack latch structure 106, and the output end Out of the third stack latch structure 107 is connected to the second input end In2 of the stack C cell structure 108.

[0103] The stack C cell structure 108 comprises PMOS tubes 501, 502, 503, NMOS tubes 504, 505, 506.

[0104] The gates of the PMOS tubes 501, 502 and the NMOS tubes 505, 506 in the stack C cell structure 108 are connected together as the first input end In1 of the stack C cell structure 108, and the gates of the PMOS tube 503 and the NMOS tube 504 in the stack C cell structure 108 are connected together as the second input end In2 of the stack C cell structure 108; the source of the PMOS tube 501 is connected to the redundant power supply VDDC signal, the drain of the PMOS tube 501 is connected to the source of the PMOS tube 502, the drain of the PMOS tube 502 is connected to the source of the PMOS tube 503, the drain of the PMOS tube 503 is connected to the drain of the NMOS tube 504 and serves as the output end Out of the stack C cell structure 108, the source of the NMOS tube 504 is connected to the drain of the NMOS tube 505, the source of the NMOS tube 505 is connected to the drain of the NMOS tube 506, and the source of the NMOS tube 506 is connected to the power supply ground VSS.

[0105] The first input end In1 of the stack C cell structure 108 is connected to the output end Out of the second stack latch structure 106, the second input end In2 of the stack C cell structure 108 is connected to the output end Out of the third stack latch structure 107, and the output end Out of the stack C cell structure 108 is connected to the input end In of the data output structure, which is the third stack inverter circuit 109.

[0106] The second sub-stack inverter circuit 203 comprises PMOS tubes 313, 314 and NMOS tubes 315, 316.

[0107] The gates of the PMOS transistor 313, 314 and the NMOS transistor 315, 316 are connected together as the input end of the second sub-stack inverter circuit 203, the source of the PMOS transistor 313 is connected to the redundant power supply VDDC signal, the drain is connected to the source of the PMOS transistor 314, the drain of the PMOS transistor 314 is connected to the drain of the NMOS transistor 315 and serves as the output end Out of the second sub-stack inverter circuit 203, the source of the NMOS transistor 315 is connected to the drain of the NMOS transistor 316, the source of the NMOS transistor 316 is connected to the power supply ground VSS; the input end of the second sub-stack inverter circuit 203 is connected to the output end Out of the second stack clock control structure 105, the input end In of the third stack latch structure 107 and the output end Out of the second sub-stack clock control structure 204, and the output end of the second sub-stack inverter circuit 203 is connected to the input end In of the second sub-stack clock control structure 204 and the first input end In1 of the stack C cell structure 108;

[0108] The second sub-stack clock control structure 204 includes PMOS transistors 419, 420, 421, and NMOS transistors 422, 423, 424.

[0109] The gates of the PMOS transistor 419, 420 and the NMOS transistor 423, 424 are connected together as the input end In of the second sub-stack clock control structure 204, the gate of the PMOS transistor 421 in the second sub-stack clock control structure 204 is the input end CLK of the second sub-stack clock control structure 204, connected to the clock signal CLK, the gate of the NMOS transistor 422 in the second sub-stack clock control structure 204 is the input end CLKN1 of the second sub-stack clock control structure 204, connected to the output end CLKN1 of the fifth stack inverter circuit 111; the source of the PMOS transistor 419 is connected to the redundant power supply VDDC signal, the drain is connected to the source of the PMOS transistor 420, the drain of the PMOS transistor 420 is connected to the source of the PMOS transistor 421, the drain of the PMOS transistor 421 is connected to the drain of the NMOS transistor 422, and serves as the output end Out of the second sub-stack clock control structure 204, the source of the NMOS transistor 422 is connected to the drain of the NMOS transistor 423, the source of the NMOS transistor 423 is connected to the drain of the NMOS transistor 424, and the source of the NMOS transistor 424 is connected to the power supply ground VSS; the input end In of the second sub-stack clock control structure 204 is connected to the output end Out of the second sub-stack inverter circuit 203 and the first input end In1 of the stack C cell structure 108, and the output end of the second sub-stack clock control structure 204 is connected to the output end Out of the second stack clock control structure 105, the input end In of the third stack latch structure 107 and the input end In of the second sub-stack inverter circuit 203;

[0110] The third sub-stack inverter circuit 205 comprises PMOS tubes 317, 318, NMOS tubes 319, 320;

[0111] The gates of the PMOS tubes 317, 318 and the NMOS tubes 319, 320 are connected together as the input end of the third sub-stack inverter circuit 205, the source of the PMOS tube 317 is connected to the power supply VDD, the drain is connected to the source of the PMOS tube 318, the drain of the PMOS tube 318 is connected to the drain of the NMOS tube 319 and serves as the output end Out of the third sub-stack inverter circuit 205, the source of the NMOS tube 319 is connected to the drain of the NMOS tube 320, and the source of the NMOS tube 320 is connected to the power supply ground VSS; the input end of the third sub-stack inverter circuit 205 is connected to the output end Out of the second stack clock control structure 105, the input end In of the second stack latch structure 106, and the output end Out of the third sub-stack clock control structure 206; the output end of the third sub-stack inverter circuit 205 is connected to the input end In of the third sub-stack clock control structure 206 and the input end In2 of the stack C cell structure 108.

[0112] The third sub-stack clock control structure 206 comprises PMOS tubes 425, 426, 427, NMOS tubes 428, 429, 430.

[0113] The gates of the PMOS tubes 425, 426 and the NMOS tubes 429, 430 are connected together as the input end In of the third sub-stack clock control structure 206, the gate of the PMOS tube 427 in the third sub-stack clock control structure 206 serves as the input end CLK of the third sub-stack clock control structure 206 and is connected to the clock signal CLK, the gate of the NMOS tube 428 in the third sub-stack clock control structure 206 serves as the input end CLKN of the third sub-stack clock control structure 206 and is connected to the output end CLKN of the fourth stack inverter circuit 110; the source of the PMOS tube 425 is connected to the power supply VDD, the drain is connected to the source of the PMOS tube 426, the drain of the PMOS tube 426 is connected to the source of the PMOS tube 427, the drain of the PMOS tube 427 is connected to the drain of the NMOS tube 428 and serves as the output end Out of the third sub-stack clock control structure 206, the source of the NMOS tube 428 is connected to the drain of the NMOS tube 429, the source of the NMOS tube 429 is connected to the drain of the NMOS tube 430, and the source of the NMOS tube 430 is connected to the power supply ground VSS; the input end In of the third sub-stack clock control structure 206 is connected to the output end Out of the third sub-stack inverter circuit 205 and the input end In2 of the stack C cell structure 108, and the output end of the third sub-stack clock control structure 206 is connected to the output end Out of the second stack clock control structure 105, the input end In of the second stack latch structure 106, and the input end In of the third sub-stack inverter circuit 205.

[0114] A third stacked inverter circuit 109 is configured to form the data output structure, and the third stacked inverter circuit 109 further comprises PMOS transistors 321, 322 and NMOS transistors 323, 324;

[0115] The gates of the PMOS transistors 321, 322 and the NMOS transistors 323, 324 are connected together as an input end In of the third stacked inverter circuit 109, the source of the PMOS transistor 321 is connected to a redundant power supply VDDC signal, the drain of the PMOS transistor 321 is connected to the source of the PMOS transistor 322, the drain of the PMOS transistor 322 is connected to the drain of the NMOS transistor 323 and serves as an output end Out of the third stacked inverter circuit 109, the source of the NMOS transistor 323 is connected to the drain of the NMOS transistor 324, and the source of the NMOS transistor 324 is connected to a power supply ground VSS; the input end In of the third stacked inverter circuit 109 is connected to the output end Out of the stacked C cell structure 108, and the output end Out of the third stacked inverter circuit 109 is connected to the output end Output of the flip-flop circuit.

[0116] Embodiment:

[0117] Figure 2The figure shows the structure of the stacked latch circuit in the dual power supply redundancy error correction instantaneous dose rate radiation hardened flip-flop provided by the application. The structure is used to realize the interlocking of data signals and the anti-instantaneous dose rate radiation hardening. Taking the first stacked latch structure 104 as an example, when the input end In of the first stacked latch structure 104 inputs the digital signal 1, the output end of the first stacked latch structure 104 is the digital signal 0 through the inversion of the first sub-stacked inverter circuit 201, and is input into the first sub-stacked clock control structure 202. When the input end CP of the first sub-stacked clock control structure 202 is the digital signal 0, the output end of the first sub-stacked clock control structure 202 is the digital signal 1, and the digital signal 1 will continue to be input into the first sub-stacked inverter circuit 201, so as to ensure that the output end Out of the first stacked latch structure 104 is stably maintained in the opposite logic state of the input end In of the first stacked latch structure 104, and the interlocking of data is realized. For the first stacked latch structure 104, the function of outputting the data signal of the first stacked clock control structure 103 when the clock signal CLK is the digital signal 0, and latching and inversely inputting the data signal into the second stacked clock control structure 105 when the clock signal CLK is the digital signal 1 is realized, which constitutes the main latch structure of the flip-flop. For the third stacked latch structure 107, the function of latching and inversely inputting the data signal output by the second stacked clock control structure 105 when the clock signal CLK is the digital signal 1 into the stacked C unit structure 108 when the clock signal is the digital signal 0 is realized, which constitutes the slave latch structure of the flip-flop. For the second stacked latch structure 106, it is supplied by the redundant power supply VDDC, and the input signal In is the same signal as the input signal In of the third stacked latch structure 107. The input signal CPN end is provided by the output end CLKN1 of the fifth stacked inverter circuit 111 using the redundant power supply, which constitutes the redundant slave latch structure of the flip-flop independent of the third stacked latch structure 107.When the clock signal CLK is a digital signal 0, the PMOS transistor 421 and the NMOS transistor 422 of the second sub-stack clock control structure 204 are turned on, and if the power supply VDD is disturbed, since the second stack latch structure 106 is powered by the redundant power supply VDDC, the second stack latch structure 106 will not be affected by the VDD disturbance, maintaining normal data latching and transmission functions, and ensuring that the output signal Out of the second stack latch structure 106 is correct and stable; when the clock signal CLK is a digital signal 1, the PMOS transistor 421 and the NMOS transistor 422 of the second sub-stack clock control structure 204 are turned off, and if the power supply VDD is disturbed, since the second sub-stack inverter circuit 203 is powered by the redundant power supply VDDC, the second stack latch structure 106 can still avoid the influence caused by the power supply VDD disturbance, ensuring that the output signal Out of the second stack latch structure 106 is correct and stable, and achieving the second stack latch structure 106 anti-transient dose rate radiation hardening; due to the design of the stacked transistor, the total capacitance of the circuit node is improved, the critical charge threshold is improved, the voltage of the output node is not easily affected by the photoelectric current, and the anti-transient dose rate radiation hardening effect is further achieved.

[0118] Figure 3The structure diagram of the stacked inverter circuit in the dual power supply redundancy error correction transient dose rate radiation hardened flip-flop provided by the FDSOI process is shown, which is the circuit implementation form of the stacked inverter circuit 101, 102, 109, 110, 111 and the sub-stacked inverter circuit 201, 203, 205. The basic inverter circuit is implemented, and the main purpose is to invert the input signal. The first stacked inverter circuit 101 inverts the input signal Input of the flip-flop circuit and inputs it into the second stacked inverter circuit 102; the second stacked inverter circuit 102 inverts the input signal and inputs it into the first stacked clock control structure 103; the third stacked inverter circuit 109 is powered by the redundant power supply VDDC, which ensures that the input signal can be inverted and output as the output of the flip-flop circuit when the power supply VDD is disturbed; the fourth stacked inverter circuit 110 inverts the clock signal CLK, outputs the inverted clock signal CLKN, and provides timing control for each part of the flip-flop structure; the fifth stacked inverter circuit 111 is powered by the redundant power supply VDDC, inverts the clock signal CLK, outputs the redundant inverted clock signal CLKN1, and provides timing control for the redundant slave latch structure composed of the second stacked latch structure 106; the first sub-stacked inverter circuit 201 inverts the input signal and inputs it into the first sub-stacked clock control structure 202, the second stacked clock control structure 105, and can realize data interlocking with the first sub-stacked clock control structure 202; the second sub-stacked inverter circuit 203 inverts the input signal and inputs it into the input end In1 of the second sub-stacked clock control structure 204 and the stacked C cell structure 108, can realize data interlocking with the second sub-stacked clock control structure 204, and at the same time, the second sub-stacked inverter circuit 203 is powered by the redundant power supply VDDC, which can realize anti-transient dose rate radiation hardening; the third sub-stacked inverter circuit 205 inverts the input signal and inputs it into the third sub-stacked clock control structure 206 and the input end In2 of the stacked C cell structure 108, and can realize data interlocking with the third sub-stacked clock control structure 206; due to the design of the stacked transistor, the total capacitance of the circuit node is improved, the critical charge threshold is improved, the voltage of the output node is not easily affected by the photoelectric current, and the effect of anti-transient dose rate radiation hardening is achieved.

[0119] Figure 4The structure of the clock control circuit in the dual power supply redundancy error correction transient dose rate radiation hardened flip-flop provided by the FDSOI process is shown in the figure, which is the circuit implementation form of the stacked clock control structure 103, 105 and the sub-stacked clock control structure 202, 204, 206. The level state of the clock signal CLK is used to control the data signal input and invert the input signal, and the effect of anti-transient dose rate radiation hardening is realized. Taking the first stacked clock control structure 103 as an example, when the clock signal CLK is a digital signal 0, the PMOS tube 403 and the NMOS tube 404 are turned on, and the first stacked clock control structure 103 realizes the function of inverting the input signal In; when the clock signal CLK is a digital signal 1, the PMOS tube 403 and the NMOS tube 404 are turned off, and the pull-up and pull-down networks of the output end Out of the first stacked clock control structure 103 are not connected, so the output end Out will remain the original logic value unchanged and enter the high resistance state. For the stacked clock control structure 103, 202 and the first sub-stacked inverter circuit 201, when the clock signal CLK is a digital signal 0, the input data of the first stacked clock control structure 103 will be transmitted to the output end of the first sub-stacked inverter circuit 201, and when the clock signal CLK is a digital signal 1, the current data will be latched through the first sub-stacked clock control structure 202 and the first sub-stacked inverter circuit 201; for the stacked clock control structure 105, 206 and the third sub-stacked inverter circuit 205, when the clock signal CLK is a digital signal 1, the input data of the second stacked clock control structure 105 will be transmitted to the output end of the third sub-stacked inverter circuit 205, and when the clock signal CLK is a digital signal 0, the current data will be latched through the stacked clock control structure 205 and the stacked inverter circuit 206; for the second sub-stacked clock control structure 204 and the second sub-stacked inverter circuit 203, they are powered by the redundant power supply VDDC and are time-controlled by the redundant inverted clock signal CLKN1 of the output end of the fifth stacked inverter circuit 111, when the clock signal CLK is a digital signal 0, the second sub-stacked clock control structure 204 and the second sub-stacked inverter circuit 203 will realize data interlocking and ensure that the transmission of data is not affected by the power supply VDD disturbance, realizing anti-transient dose rate radiation hardening; due to the design of the stacked transistor, the total capacitance of the circuit node is improved, the critical charge threshold is improved, the voltage of the output node is not easily affected by the photoelectric current, and the effect of anti-transient dose rate radiation hardening is further played.

[0120] Figure 5The structure of the stacked C cell circuit in the dual power supply redundancy error correction instantaneous dose rate radiation hardened flip-flop provided by the application is shown in the structural diagram of the FDSOI process, which is a circuit implementation form of the stacked C cell structure 108. The pulse signal caused by the power VDD disturbance is filtered by using this structure, and the instantaneous dose rate radiation hardening is realized. The stacked C cell structure 108 is powered by the redundant power VDDC, the input end In1 of the stacked C cell structure 108 is connected to the output end Out of the second stacked latch structure 106, the input end In2 of the stacked C cell structure 108 is connected to the output end Out of the third stacked latch structure 107, and the output end Out of the stacked C cell structure 108 is connected to the input end In of the third stacked inverter circuit 109. When the input signals In1 and In2 are the same, the stacked C cell structure 108 outputs a logic value opposite to In1 and In2, for example, In1 and In2 are both digital signals 1, the PMOS tube 501, the PMOS tube 502 and the PMOS tube 503 of the stacked C cell structure 108 are closed, that is, the pull-up network is disconnected, and the NMOS tube 504, the NMOS tube 505 and the NMOS tube 506 are opened, that is, the pull-down network is turned on, and the output node of the stacked C cell structure 108 is pulled down to a digital signal 0, realizing the function of inverting the input signals In1 and In2; when the input signals In1 and In2 are different, for example, In1 is a digital signal 1 and In2 is a digital signal 0, the PMOS tube 501, the PMOS tube 502 and the NMOS tube 504 of the stacked C cell structure 108 are closed, and the PMOS tube 503, the NMOS tube 505 and the NMOS tube 506 are opened, the pull-up network and the pull-down network of the output node Out of the stacked C cell structure 108 are not connected, and the output node Out remains the original output data unchanged in the high resistance state. When the instantaneous dose rate radiation causes the power VDD disturbance and causes the output end Out of the third stacked latch structure 107, that is, the input signal In2 of the stacked C cell structure 108 to flip, since the output end Out of the second stacked latch structure 106, that is, the input signal In1 of the stacked C cell structure 108 is not flipped by avoiding the influence of the power VDD disturbance by the redundant power VDDC, at this time, the logic values of the two input signals In1 and In2 are different, the output node of the stacked C cell structure 108 enters the high resistance state to keep the correct logic value unchanged, so that the power VDD disturbance caused by the instantaneous dose rate radiation is filtered, and the pulse signal caused by the power VDD disturbance is filtered; meanwhile, the PMOS tube 501, the PMOS tube 502, the NMOS tube 505 and the NMOS tube 506 of the stacked C cell structure 108 connected to the input signal In1 are designed as a stacked structure, due to the design of the stacked transistor, the total capacitance of the circuit node is improved, the critical charge threshold is improved, the voltage of the output node is not easily affected by the photoelectric current, the data signal powered by the redundant power VDDC is maintained stable during transmission, and the function of the instantaneous dose rate radiation hardening is further played.

[0121] Figure 6 The figure shows a layout reinforcement design of a dual power supply redundancy error correction transient dose rate radiation hardened flip-flop provided by the FDSOI process of the present application. Reducing the voltage drop of the redundant power supply VDDC signal on the metal line during transmission helps to reduce the power supply voltage disturbance and improve the ability to resist transient dose rate radiation. In the layout design, the redundant power supply needs to be designed as the shortest length and the maximum width trace. Figure 6 Taking the third stacked inverter circuit 109 and the fifth stacked inverter circuit 111 as examples, since the source of the PMOS tube 321 of the third stacked inverter circuit 109 and the PMOS tube 329 of the fifth stacked inverter circuit 111 both need to be connected to the redundant power supply VDDC signal, the length L of the metal line of the VDDC signal needs to be the shortest, such as Figure 6 The figure shows, at the same time, the width W of the metal line of the VDDC signal is the widest value that meets the process design rules to achieve the layout reinforcement against transient dose rate radiation.

[0122] The contents not described in detail in the specification of the present application are the known technology of the person skilled in the art. Although the embodiments of the present application are described in combination with the drawings, various modifications or changes can be made by the person skilled in the art within the scope of the appended claims.

Claims

1. A dual-power redundant error-correcting instantaneous dose rate radiation-hardened trigger for FDSOI process, characterized by include: A data input structure, a clock input structure, a redundant clock input structure, a first clock control structure, a second clock control structure, a data master latch structure, a data slave latch structure, and a data output structure; The data input structure sends external input data to the first clock control structure, and the first clock control structure transmits the input data to the data master latch structure when the clock is at a low level; The data master latch structure transmits data to the second clock control structure when the clock is at a low level; the data master latch structure latches the data when the clock is at a high level; The second clock control structure transmits the input data to the data slave latch structure when the clock is at a high level, and the data slave latch structure transmits the data to the data output structure for data output when the clock is at a high level; When the clock is low, the data is latched from the latch structure; The data input structure includes a first stacked inverter circuit (101) and a second stacked inverter circuit (102); The first stacked inverter circuit (101) includes PMOS transistors 301 and 302, and NMOS transistors 303 and 304; The gates of the PMOS transistors 301 and 302 and the NMOS transistors 303 and 304 are connected together as the input terminal In of the first stacked inverter circuit (101); the source of the PMOS transistor 301 is connected to the power supply VDD, and the drain is connected to the source of the PMOS transistor 302; the drain of the PMOS transistor 302 is connected to the drain of the NMOS transistor 303 and serves as the output terminal Out of the first stacked inverter circuit (101); the source of the NMOS transistor 303 is connected to the drain of the NMOS transistor 304; and the source of the NMOS transistor 304 is connected to the power ground VSS; the input terminal In of the first stacked inverter circuit (101) is connected to the input signal Input of the trigger circuit, and the output terminal Out is connected to the input terminal In of the second stacked inverter circuit (102); The second stacked inverter circuit (102) includes PMOS transistors 305 and 306 and NMOS transistors 307 and 308; The gates of the PMOS transistors 305 and 306 and the NMOS transistors 307 and 308 are connected together as the input terminal In of the second stacked inverter circuit (102); the source of the PMOS transistor 305 is connected to the power supply VDD, and the drain is connected to the source of the PMOS transistor 306; the drain of the PMOS transistor 306 is connected to the drain of the NMOS transistor 307 and serves as the output terminal Out of the second stacked inverter circuit (102); the source of the NMOS transistor 307 is connected to the drain of the NMOS transistor 308; and the source of the NMOS transistor 308 is connected to the power ground VSS; the input terminal In of the second stacked inverter circuit (102) is connected to the output terminal Out of the first stacked inverter circuit (101); and the output terminal Out of the second stacked inverter circuit (102) is connected to the input terminal In of the first stacked clock control structure (103).

2. The dual-power redundant error-correcting instantaneous dose rate radiation-hardened trigger for FDSOI process according to claim 1, characterized in that: The fourth stacked inverter circuit (110) constitutes the clock input structure, and the fourth stacked inverter circuit (110) further comprises PMOS transistors 325, 326, and NMOS transistors 327, 328; The gates of the PMOS transistors 325, 326 and the NMOS transistors 327, 328 are connected together as the input terminal In of the fourth stacked inverter circuit (110); the source of the PMOS transistor 325 is connected to the power supply VDD, the drain is connected to the source of the PMOS transistor 326, the drain of the PMOS transistor 326 is connected to the drain of the NMOS transistor 327 and serves as the output terminal CLKN of the fourth stacked inverter circuit (110); the source of the NMOS transistor 327 is connected to the drain of the NMOS transistor 328, and the source of the NMOS transistor 328 is connected to the power ground VSS; the input terminal In of the fourth stacked inverter circuit (110) is connected to the clock signal CLK, and the output terminal CLKN of the fourth stacked inverter circuit (110) is simultaneously connected to the input terminals CLKN of the first clock control structure, the second clock control structure, the clock input terminal CP of the data master latch structure, and the data slave latch structure; The fifth stacked inverter circuit (111) forms a redundant clock input structure powered by a redundant power supply, and the fifth stacked inverter circuit (111) further includes PMOS transistors 329, 330, and NMOS transistors 331, 332; The gates of the PMOS transistors 329, 330 and the NMOS transistors 331, 332 are connected together as the input terminal In of the fifth stacked inverter circuit (111); the source of the PMOS transistor 329 is connected to the redundant power supply VDDC signal, and the drain is connected to the source of the PMOS transistor 330; the drain of the PMOS transistor 330 is connected to the drain of the NMOS transistor 331 and serves as the output terminal CLKN1 of the fifth stacked inverter circuit (111); the source of the NMOS transistor 331 is connected to the drain of the NMOS transistor 332; and the source of the NMOS transistor 332 is connected to the power ground VSS; the input terminal In of the fifth stacked inverter circuit (111) is connected to the clock signal CLK, and the output terminal CLKN1 of the fifth stacked inverter circuit (111) is connected to the data slave latch structure.

3. The dual-power redundant error-correcting instantaneous dose rate radiation-hardened trigger for FDSOI process according to claim 2, characterized in that: The first clock control structure is formed by using a first stacked clock control structure (103); the first stacked clock control structure (103) includes PMOS transistors 401, 402, 403, and NMOS transistors 404, 405, and 406; The gates of the PMOS transistors 401 and 402 and the NMOS transistors 405 and 406 in the first stacked clock control structure (103) are connected together as the input terminal In of the first stacked clock control structure (103); the gate of the PMOS transistor 403 in the first stacked clock control structure (103) serves as the input terminal CLK of the first stacked clock control structure (103) and is connected to the clock signal CLK; the gate of the NMOS transistor 404 in the first stacked clock control structure (103) serves as the input terminal CLKN of the first stacked clock control structure (103) and is connected to the output terminal CLKN of the fourth stacked inverter circuit (110); the source of the PMOS transistor 401 is connected to the power supply VDD, and the drain is connected to the The source of the PMOS tube 402 and the drain of the PMOS tube 402 are connected to the source of the PMOS tube 403, the drain of the PMOS tube 403 is connected to the drain of the NMOS tube 404, and serve as the output terminal Out of the first stacked clock control structure (103), the source of the NMOS tube 404 is connected to the drain of the NMOS tube 405, the source of the NMOS tube 405 is connected to the drain of the NMOS tube 406, and the source of the NMOS tube 406 is connected to the power ground VSS; the input terminal In of the first stacked clock control structure (103) is connected to the output terminal Out of the second stacked inverter circuit (102), and the output terminal Out of the first stacked clock control structure (103) is connected to the input terminal In of the data master latch structure; The second stacked clock control structure (105) is used to form the second clock control structure; the second stacked clock control structure (105) includes PMOS transistors 413, 414, 415, and NMOS transistors 416, 417, and 418; The gates of the PMOS transistors 413, 414 and the NMOS transistors 417, 418 in the second stacked clock control structure (105) are connected together as the input terminal In of the second stacked clock control structure (105); the gate of the PMOS transistor 415 in the second stacked clock control structure (105) serves as the input terminal CLKN of the second stacked clock control structure (105) and is connected to the output terminal CLKN of the fourth stacked inverter circuit (110); the gate of the NMOS transistor 416 in the second stacked clock control structure (105) serves as the input terminal CLK of the second stacked clock control structure (105) and is connected to the clock signal CLK; the source of the PMOS transistor 413 is connected to the power supply VDD, The drain is connected to the source of the PMOS tube 414, the drain of the PMOS tube 414 is connected to the source of the PMOS tube 415, the drain of the PMOS tube 415 is connected to the drain of the NMOS tube 416, and serves as the output terminal Out of the second stacked clock control structure (105), the source of the NMOS tube 416 is connected to the drain of the NMOS tube 417, the source of the NMOS tube 417 is connected to the drain of the NMOS tube 418, and the source of the NMOS tube 418 is connected to the power ground VSS; the input terminal In of the second stacked clock control structure (105) is connected to the output terminal Out of the data master latch structure, and the output terminal Out of the second stacked clock control structure (105) is connected to the input terminal In of the data slave latch structure.

4. The dual-power redundant error-correcting instantaneous dose rate radiation-hardened trigger for FDSOI process according to claim 3, characterized in that: A data master latch structure formed by utilizing a first stacked latch structure (104); The first stacked latch structure (104) includes a first sub-stack inverter circuit (201) and a first sub-stack clock control structure (202); The output terminal Out of the first sub-stack inverter circuit (201) is connected to the input terminal In of the first sub-stack clock control structure (202), and serves as the output terminal Out of the first stack latch structure (104); the output terminal Out of the first sub-stack clock control structure (202) is connected to the input terminal In of the first sub-stack inverter circuit (201), and serves as the input terminal In of the first stack latch structure (104); The input terminal CLKN of the first sub-stack clock control structure (202) serves as the input terminal CP of the first stack latch structure (104) and is connected to the output terminal CLKN of the fourth stack inverter circuit (110); The input terminal CLK of the first sub-stack clock control structure (202) serves as the input terminal CPN of the first stack latch structure (104) and is connected to the clock signal CLK; the input terminal In of the first stack latch structure (104) is connected to the output terminal Out of the first stack clock control structure (103), and the output terminal Out of the first stack latch structure (104) is connected to the input terminal In of the second stack clock control structure (105).

5. The dual-power redundant error-correcting instantaneous dose rate radiation-hardened trigger for FDSOI process according to claim 4, characterized in that: The first sub-stack inverter circuit (201) includes PMOS transistors 309 and 310, and NMOS transistors 311 and 312; The gates of the PMOS transistors 309, 310 and the NMOS transistors 311, 312 are connected together as the input end of the first sub-stacked inverter circuit (201); the source of the PMOS transistor 309 is connected to the power supply VDD, and the drain is connected to the source of the PMOS transistor 310; the drain of the PMOS transistor 310 is connected to the drain of the NMOS transistor 311 and serves as the output end Out of the first sub-stacked inverter circuit (201); the source of the NMOS transistor 311 is connected to the drain of the NMOS transistor 312; and the source of the NMOS transistor 312 is connected to the power ground VSS; the input end of the first sub-stacked inverter circuit (201) is connected to the output end Out of the first stacked clock control structure (103) and the output end Out of the first sub-stacked clock control structure (202); and the output end of the first sub-stacked inverter circuit (201) is connected to the input end In of the first sub-stacked clock control structure (202) and the input end In of the second stacked clock control structure (105); The first sub-stack clock control structure (202) includes PMOS transistors 407, 408, 409, and NMOS transistors 410, 411, 412; The gates of the PMOS transistors 407 and 408 and the NMOS transistors 411 and 412 are connected together as the input terminal In of the first sub-stacked clock control structure (202); the gate of the PMOS transistor 409 in the first sub-stacked clock control structure (202) serves as the input terminal CLKN of the first sub-stacked clock control structure (202) and is connected to the output terminal CLKN of the fourth stacked inverter circuit (110); the gate of the NMOS transistor 410 in the first sub-stacked clock control structure (202) serves as the input terminal CLKN of the first sub-stacked clock control structure (202). The terminal CLK is connected to the clock signal CLK; the source of the PMOS tube 407 is connected to the power supply VDD, the drain is connected to the source of the PMOS tube 408, the drain of the PMOS tube 408 is connected to the source of the PMOS tube 409, the drain of the PMOS tube 409 is connected to the drain of the NMOS tube 410, and serves as the output terminal Out of the first sub-stack clock control structure (202); the source of the NMOS tube 410 is connected to the drain of the NMOS tube 411, the source of the NMOS tube 411 is connected to the drain of the NMOS tube 412, and the source of the NMOS tube 412 is connected to the power ground VSS; The input terminal In of the first sub-stacked clock control structure (202) is connected to the output terminal Out of the first sub-stacked inverter circuit (201) and the input terminal In of the second stacked clock control structure (105), and the output terminal of the first sub-stacked clock control structure (202) is connected to the output terminal Out of the first stacked clock control structure (103) and the input terminal In of the first sub-stacked inverter circuit (201).

6. The dual-power redundant error-correcting instantaneous dose rate radiation-hardened trigger for FDSOI process according to claim 4, characterized in that: A data slave latch structure with redundant power supply and redundant clock is formed by using a second stacked latch structure (106), a third stacked latch structure (107), and a stacked C unit structure (108); The input terminal In of the second stacked latch structure (106) is connected to the input terminal In of the third stacked latch structure (107), the output terminal Out of the second stacked latch structure (106) is connected to the first input terminal In1 of the stacked C unit structure (108), and the output terminal Out of the third stacked latch structure (107) is connected to the second input terminal In2 of the stacked C unit structure (108); The second stacked latch structure (106) includes a second sub-stack inverter circuit (203) and a second sub-stack clock control structure (204); The output terminal Out of the second sub-stack inverter circuit (203) is connected to the input terminal In of the second sub-stack clock control structure (204) and serves as the output terminal Out of the second stack latch structure (106); the output terminal Out of the second sub-stack clock control structure (204) is connected to the input terminal In of the second sub-stack inverter circuit (203) and serves as the input terminal In of the second stack latch structure (106); the input terminal CLK of the second sub-stack clock control structure (204) serves as the input terminal CP of the second stack latch structure (106) and is connected to Clock signal CLK; the input terminal CLKN1 of the second sub-stack clock control structure (204) serves as the input terminal CPN of the second stack latch structure (106) and is connected to the output terminal CLKN1 of the fifth stack inverter circuit (111); the input terminal In of the second stack latch structure (106) is connected to the output terminal Out of the second stack clock control structure (105) and the input terminal In of the third stack latch structure (107); the output terminal Out of the second stack latch structure (106) is connected to the first input terminal In1 of the stack C unit structure (108); The third stacked latch structure (107) includes a third sub-stack inverter circuit (205) and a third sub-stack clock control structure (206); The output terminal Out of the third sub-stack inverter circuit (205) is connected to the input terminal In of the third sub-stack clock control structure (206) and serves as the output terminal Out of the third stack latch structure (107); the output terminal Out of the third sub-stack clock control structure (206) is connected to the input terminal In of the third sub-stack inverter circuit (205) and serves as the input terminal In of the third stack latch structure (107); the input terminal CLK of the third sub-stack clock control structure (206) serves as the input terminal CP of the third stack latch structure (107) and is connected to the clock signal CLK; The input terminal CLKN of the third sub-stack clock control structure (206) serves as the input terminal CPN of the third stack latch structure (107) and is connected to the output terminal CLKN of the fourth stack inverter circuit (110); the input terminal In of the third stack latch structure (107) is connected to the output terminal Out of the second stack clock control structure (105) and the input terminal In of the second stack latch structure (106); the output terminal Out of the third stack latch structure (107) is connected to the second input terminal In2 of the stack C unit structure (108).

7. The dual-power redundant error-correcting instantaneous dose rate radiation-hardened trigger for FDSOI process according to claim 6, characterized in that: The stacked C unit structure (108) includes PMOS transistors 501, 502, 503, and NMOS transistors 504, 505, 506; The gate electrodes of the PMOS transistors 501 and 502 and the NMOS transistors 505 and 506 in the stacked C unit structure (108) are connected together as a first input terminal In1 of the stacked C unit structure (108); the gate electrodes of the PMOS transistor 503 and the NMOS transistor 504 in the stacked C unit structure (108) are connected together as a second input terminal In2 of the stacked C unit structure (108); the source electrode of the PMOS transistor 501 is connected to a redundant power supply VDDC signal, the drain electrode is connected to the source electrode of the PMOS transistor 502, the drain electrode of the PMOS transistor 502 is connected to the source electrode of the PMOS transistor 503, the drain electrode of the PMOS transistor 503 is connected to the drain electrode of the NMOS transistor 504, and serves as an output terminal Out of the stacked C unit structure (108); the source electrode of the NMOS transistor 504 is connected to the drain electrode of the NMOS transistor 505, the source electrode of the NMOS transistor 505 is connected to the drain electrode of the NMOS transistor 506, and the source electrode of the NMOS transistor 506 is connected to the power ground VSS; The first input terminal In1 of the stacked C unit structure (108) is connected to the output terminal Out of the second stacked latch structure (106), the second input terminal In2 of the stacked C unit structure (108) is connected to the output terminal Out of the third stacked latch structure (107), and the output terminal Out of the stacked C unit structure (108) is connected to the input terminal In of the data output structure, and the data output structure is the third stacked inverter circuit (109).

8. The dual-power redundant error-correcting instantaneous dose rate radiation-hardened trigger for FDSOI process according to claim 6, characterized in that: The second sub-stack inverter circuit (203) includes PMOS transistors 313 and 314, and NMOS transistors 315 and 316; The gates of the PMOS transistors 313, 314 and the NMOS transistors 315, 316 are connected together as the input end of the second sub-stack inverter circuit (203), the source of the PMOS transistor 313 is connected to the redundant power supply VDDC signal, and the drain is connected to the source of the PMOS transistor 314, the drain of the PMOS transistor 314 is connected to the drain of the NMOS transistor 315 and serves as the output end Out of the second sub-stack inverter circuit (203), the source of the NMOS transistor 315 is connected to the drain of the NMOS transistor 316, and the drain of the NMOS transistor 316 is connected to the drain of the NMOS transistor 316. The source of the MOS transistor 316 is connected to the power ground VSS; the input end of the second sub-stack inverter circuit (203) is connected to the output end Out of the second stack clock control structure (105), the input end In of the third stack latch structure (107) and the output end Out of the second sub-stack clock control structure (204); the output end of the second sub-stack inverter circuit (203) is connected to the input end In of the second sub-stack clock control structure (204) and the first input end In1 of the stack C unit structure (108); The second sub-stack clock control structure (204) includes PMOS transistors 419, 420, 421, and NMOS transistors 422, 423, and 424; The gates of the PMOS tubes 419, 420 and the NMOS tubes 423, 424 are connected together as the input terminal In of the second sub-stack clock control structure (204); the gate of the PMOS tube 421 in the second sub-stack clock control structure (204) serves as the input terminal CLK of the second sub-stack clock control structure (204) and receives the clock signal CLK; the gate of the NMOS tube 422 in the second sub-stack clock control structure (204) serves as the input terminal CLKN1 of the second sub-stack clock control structure (204) and receives the output terminal CLKN1 of the fifth stack inverter circuit (111); the source of the PMOS tube 419 is connected to the redundant power supply VDDC signal, and the drain is connected to the source of the PMOS tube 420; the drain of the PMOS tube 420 is connected to the source of the PMOS tube 421; and the PMOS The drain of the S transistor 421 is connected to the drain of the NMOS transistor 422 and serves as the output terminal Out of the second sub-stack clock control structure (204); the source of the NMOS transistor 422 is connected to the drain of the NMOS transistor 423; the source of the NMOS transistor 423 is connected to the drain of the NMOS transistor 424; and the source of the NMOS transistor 424 is connected to the power ground VSS; the input terminal In of the second sub-stack clock control structure (204) is connected to the output terminal Out of the second sub-stack inverter circuit (203) and the first input terminal In1 of the stacked C unit structure (108); the output terminal of the second sub-stack clock control structure (204) is connected to the output terminal Out of the second stacked clock control structure (105), the input terminal In of the third stacked latch structure (107), and the input terminal In of the second sub-stack inverter circuit (203); The third sub-stack inverter circuit (205) includes PMOS transistors 317 and 318, and NMOS transistors 319 and 320; The gates of the PMOS transistors 317 and 318 and the NMOS transistors 319 and 320 are connected together as the input end of the third sub-stacked inverter circuit (205); the source of the PMOS transistor 317 is connected to the power supply VDD, and the drain is connected to the source of the PMOS transistor 318; the drain of the PMOS transistor 318 is connected to the drain of the NMOS transistor 319 and serves as the output end Out of the third sub-stacked inverter circuit (205); the source of the NMOS transistor 319 is connected to the drain of the NMOS transistor 320, and the drain of the NMOS transistor 320 is connected to the drain of the NMOS transistor 320. The source of the OS transistor 320 is connected to the power ground VSS; the input end of the third sub-stack inverter circuit (205) is connected to the output end Out of the second stack clock control structure (105), the input end In of the second stack latch structure (106) and the output end Out of the third sub-stack clock control structure (206); the output end of the third sub-stack inverter circuit (205) is connected to the input end In of the third sub-stack clock control structure (206) and the input end In2 of the stack C unit structure (108); The third sub-stack clock control structure (206) includes PMOS transistors 425, 426, 427, and NMOS transistors 428, 429, and 430; The gates of the PMOS tubes 425, 426 and the NMOS tubes 429, 430 are connected together as the input terminal In of the third sub-stack clock control structure (206); the gate of the PMOS tube 427 in the third sub-stack clock control structure (206) serves as the input terminal CLK of the third sub-stack clock control structure (206) and receives the clock signal CLK; the gate of the NMOS tube 428 in the third sub-stack clock control structure (206) serves as the input terminal CLKN of the third sub-stack clock control structure (206) and receives the output terminal CLKN of the fourth stack inverter circuit (110); the source of the PMOS tube 425 is connected to the power supply VDD, the drain is connected to the source of the PMOS tube 426, the drain of the PMOS tube 426 is connected to the source of the PMOS tube 427, and the PMOS tube 4 The drain of transistor 27 is connected to the drain of NMOS transistor 428 and serves as the output terminal Out of the third sub-stack clock control structure (206), the source of NMOS transistor 428 is connected to the drain of NMOS transistor 429, the source of NMOS transistor 429 is connected to the drain of NMOS transistor 430, and the source of NMOS transistor 430 is connected to the power ground VSS; the input terminal In of the third sub-stack clock control structure (206) is connected to the output terminal Out of the third sub-stack inverter circuit (205) and the input terminal In2 of the stacked C unit structure (108), and the output terminal of the third sub-stack clock control structure (206) is connected to the output terminal Out of the second stacked clock control structure (105), the input terminal In of the second stacked latch structure (106) and the input terminal In of the third sub-stack inverter circuit (205).

9. The dual-power redundant error-correcting instantaneous dose rate radiation-hardened trigger for FDSOI process according to claim 8, characterized in that: The third stacked inverter circuit (109) constitutes the data output structure, and the third stacked inverter circuit (109) further comprises PMOS transistors 321, 322, and NMOS transistors 323, 324; The gates of the PMOS transistors 321, 322 and the NMOS transistors 323, 324 are connected together as the input terminal In of the third stacked inverter circuit (109); the source of the PMOS transistor 321 is connected to the redundant power supply VDDC signal, and the drain is connected to the source of the PMOS transistor 322; the drain of the PMOS transistor 322 is connected to the drain of the NMOS transistor 323 and serves as the output terminal Out of the third stacked inverter circuit (109); the source of the NMOS transistor 323 is connected to the drain of the NMOS transistor 324; and the source of the NMOS transistor 324 is connected to the power ground VSS; the input terminal In of the third stacked inverter circuit (109) is connected to the output terminal Out of the stacked C unit structure (108); and the output terminal Out of the third stacked inverter circuit (109) is connected to the output terminal Output of the trigger circuit.

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