A code word splicing device for multiple variable length coding

Abstract

The application provides a code word splicing device for various variable word length coding, comprising a pre-splicing module, a barrel shift module, a bit splicing module and a register selection module; the pre-splicing module comprises a bit expander, an adder and a barrel shift register, the expander is used for zero filling in low bits, the adder is used for outputting the actual bit width of the spliced indefinite length code word, and the barrel shift register is used for right shift; the barrel shift module is used for circular shift; the bit splicing module is responsible for bit splicing and buffering data which has not been spliced by turns through a ping-pong structure; and the register selection module is used for register selection. The application can efficiently splice various indefinite length code words generated by various variable word length coding algorithms without blocking, and enables the data stream to be output in byte units.

Description

TECHNICAL FIELD

[0001] The present application relates to a code word splicing device for a plurality of variable length codes. BACKGROUND

[0002] An important feature of the information age is the digitization of information, which has brought about "information explosion". Digital computers are faced with the problems of throughput, storage and transmission of information converted from analog quantities to digital quantities, which are carried by various media such as numerical values, characters, languages, music, graphics, animations, still images, and television video images. It is very important to realize high-bit-rate data compression for images and other data, because directly storing and transmitting huge data not only costs a lot, but also sometimes the equipment cannot bear such a large load, and the communication bandwidth and storage capacity are limited. The possibility of data compression lies in the redundancy of data itself. After digitization, a large amount of binary data is formed for an image. However, due to the redundancy of the image, it is not necessary to represent an image with so many binary digits. How to "delete" the unnecessary binary digits from the hardware level and only store the necessary binary digits becomes a crucial step in image compression in terms of storage.

[0003] The purpose of digital image compression is to remove the redundancy and unnecessary information of the image, reduce the data amount and storage space of the image without reducing the visual quality of the image, and improve the transmission rate of the image. By encoding the image source, the encoded data stream is smaller than the original data stream, achieving the purpose of compression. Symbols with high occurrence probability are given short codes, and symbols with low occurrence probability are given long codes. If code words of different lengths are represented with the same bit width, a large number of invalid bits will be caused when the data stream is output. In order to "delete" these invalid bits in the data stream, various combination splicing schemes can be used before storing the variable length codes, to further compress the data. Storing the spliced encoded data can effectively reduce the data storage space and the throughput rate of data compression.

[0004] In addition, a small part of the variable length codes need to be inserted with special code words when stored, for example, "0xFF" needs to be supplemented with "0x00" after it when storing the JEPG (Joint Photographic Experts Group, image file format) compressed encoded data, and the like. The variable length codes of this type need a high-flexibility combination splicing device to generate the indefinite length code words, which can realize high throughput rate while minimizing the hardware complexity.

[0005] The existing indefinite length code word splicing output scheme is shown as follows:

[0006] (1) Based on two shift registers splicing scheme. The indefinite length code word is loaded in 16 bits (Binary digit, bit) register, every other clock cycle, 8 bits register is right to move 1 bit, gradually 16 bits shift register in the encoding value of the 8 bits shift register is stored. When the 8 bits shift register is filled, the byte data is outputted and cleared to continue the operation; When 16 bits shift register is empty (no encoding value), through the finite state machine control it continues to load indefinite length code word data. The disadvantage of this kind of indefinite length code word splicing scheme is that the shift register waiting for update time is too long, not suitable for splicing length longer indefinite length code word. The schematic diagram of this scheme is shown in Figure 1 .

[0007] (2) Based on a bidirectional shift register and a normal register splicing scheme. 8 bits register is output register, 24 bits shift register is used to load indefinite length code word, when the shift register is loaded data, according to the number of bits in the output register already exists to carry on data shift (left or right). Shift register and output register data alignment, the byte data in the shift register is transmitted to the output register in parallel. Through the finite state machine to control a complete byte data alignment, transmission and output. The shift register can also be replaced by barrel shift register to achieve the same logic. The disadvantage of this kind of indefinite length code word splicing scheme is that the single register splicing data leads to low efficiency, at the same time, the loading of indefinite length code word may appear congestion phenomenon. The schematic diagram of this scheme is shown in Figure 2 .

[0008] (3) Based on the prediction technology splicing scheme. Through the advance of the prediction rule can achieve the purpose of parallel execution byte output and code word update. The disadvantage of this kind of indefinite length code word splicing scheme is that the single prediction rule may lead to code word splicing error, therefore, this scheme is not suitable for splicing lossless compression indefinite length code word. The schematic diagram of this scheme is shown in Figure 3 .

[0009] (4) Based on a barrel shift register and two normal register splicing scheme. A normal register A stores the high 32 bits (in byte unit) of indefinite length code word, the remaining bits are stored in another normal register B. When the register A is filled with data, it is outputted and cleared, the data in register B is moved to register A, and the data is spliced in register A until the splicing is completed. The disadvantage of this kind of indefinite length code word splicing scheme is that the splicing work is only in a single register, the data throughput is low, not suitable for splicing the indefinite length code word generated by the fast throughput of the variable length encoding in the front stage. SUMMARY

[0010] The application aims to provide a code word splicing device for multiple variable-length codes, which comprises a pre-splicing module, a barrel shift module, a bit splicing module and a register selection module.

[0011] The pre-splicing module comprises a bit expander, an adder and a barrel shift register, the expander is used for zero padding, the adder is used for outputting the actual bit width of the spliced indefinite-length code word, and the barrel shift register is used for right shifting.

[0012] The barrel shift module is used for cyclic shifting.

[0013] The bit splicing module is responsible for bit splicing and buffering data that has not been subjected to bit splicing through a ping-pong structure.

[0014] The register selection module is used for register selection.

[0015] The pre-splicing module expands the indefinite-length code word 1 by 1 bit, and then performs barrel shifting to the right according to the actual length of the indefinite-length code word 1, expands the indefinite-length code word 2, and then performs barrel shifting to the right according to the sum of the lengths of the two indefinite-length code words, performs OR operation on the two barrel shifted code word data, and then performs barrel shifting on the code word data again, so that the code word data can be subjected to formal combination and splicing.

[0016] The barrel shift module uses a selector and a shifter to perform cyclic shifting.

[0017] The selector selects the data before shifting or the data after shifting according to the input selection signal, and the shifter shifts the input data to the right according to the specific shift parameter.

[0018] The bit splicing module uses two registers to form a ping-pong structure, one register is responsible for bit splicing, and the other register is responsible for buffering data that has not been subjected to bit splicing operation, the functions of the two registers are not fixed, and they are responsible for bit splicing and buffering data that has not been subjected to bit splicing in turn.

[0019] The two registers in the bit splicing module are respectively denoted as a first register and a second register, the bit splicing module performs or operation on the barrel-shifted data and the first register temporarily responsible for bit splicing in the ping-pong structure to achieve the purpose of bit splicing, when the actual length of the data to be spliced exceeds the number of remaining bit positions in the first register temporarily responsible for bit splicing, the redundant code words are buffered into the second register in the ping-pong structure, after the first register temporarily responsible for bit splicing is completely filled, the data spliced is output, when the next code word to be spliced is input into the bit splicing module, the data to be spliced is subjected to or operation with the second register, after the first register temporarily responsible for bit splicing outputs the data spliced, the first register starts to buffer the data which has not been subjected to bit splicing operation.

[0020] The functions of the first register and the second register are alternated and work cyclically.

[0021] The register selection module uses a data selector and a buffer register to select the register.

[0022] The data selector is controlled by a register selection signal, after any one of the first register and the second register is completely filled with data, the register selection signal selects the register completely filled with data to output, and the output is output to the buffer register.

[0023] The buffer register outputs the data stored in the buffer register through a read enable signal.

[0024] Beneficial effects: the present application is aimed at the indefinite length code word data stream generated by the variable length coding (VLC) algorithm commonly used in data compression, uses the ping-pong structure, and improves the throughput rate of the indefinite length code stream byte output link in the compression engineering. The present application combines the existing efficient pre-splicing mode and the code word splicing system specially designed for the data after pre-splicing in the present application, can efficiently splice various indefinite length code words generated by various variable length coding algorithms and will not be blocked, and enables the data stream to be output in byte units. BRIEF DESCRIPTION OF DRAWINGS

[0025] The above and / or other aspects of the present application will become apparent and more readily appreciated from the following description, taken in conjunction with the accompanying drawings, in which:

[0026] Figure 1 is a schematic diagram of a splicing scheme based on two shift registers.

[0027] Figure 2 is a schematic diagram of a splicing scheme based on a bidirectional shift register and a normal register.

[0028] Figure 3 is a schematic diagram of a splicing scheme based on a prediction technique.

[0029] Figure 4 is a code word splicing flowchart of the present application.

[0030] Figure 5 is a schematic diagram of a pre-splicing module.

[0031] Figure 6 is a schematic diagram of a barrel shift module.

[0032] Figure 7 is a schematic diagram of a bit splicing module and a register selection module. DETAILED DESCRIPTION

[0033] The present application provides a code word splicing device for multiple variable-length codes. The present application first performs pre-splicing processing on two indefinite-length code words. Unlike four methods of the prior art, the present application has the following differences: (1) two byte-based registers are used to form a ping-pong structure, the high bits and the low bits of data are processed respectively, the high bits / low bits of data are subjected to an OR operation with the existing registers, the indefinite-length code words are ensured to be spliced into the existing content of the registers in priority, and after any register is filled, the spliced code word is output to the buffer, the functions of the two registers are alternated, and the splicing work is not limited to a single register. (2) For multiple indefinite-length code words, pre-splicing processing can be performed in parallel, and the indefinite-length code words are assembled into a single indefinite-length code word, barrel shift rules are designed according to the characteristics of the code word, and the multiple indefinite-length code words do not need to be spliced one by one, thereby simplifying the program and being friendly to hardware.

[0034] The present application performs splicing processing on indefinite-length code words generated by VLC (Variable Length Coding, VLC). The code word splicing flowchart sequentially includes a pre-splicing module, a barrel shift module, a bit splicing module, and a register selection module. If indefinite-length code word 1 occupies a bit width of W1, an actual length occupies a bit width of L1, indefinite-length code word 2 occupies a bit width of W2, and an actual length occupies a bit width of L2, the flowchart is as shown in Figure 4 .

[0035] The pre-splicing module in the application mainly comprises a bit expander (low bit zero filling), an adder and a barrel shifter (right shift), and the indefinite length code word 1 is extended by 1 bit and barrel shifted right according to its own code word length, the indefinite length code word 2 is extended by 1 bit and barrel shifted right according to the sum of the lengths of the two indefinite length code words, the two barrel shifted code word data are operated by OR, and then the barrel shifted code word data is subjected to formal combination and splicing processing. If the indefinite length code word 1 occupies a bit width of W1, the actual length occupies a bit width of L1, the indefinite length code word 2 occupies a bit width of W2, and the actual length occupies a bit width of L2, wherein W>W1>W2, L1>L2, W=8k, and k is a positive integer, the pre-splicing module is as shown in Figure 5 .

[0036] The barrel shifter module in the application utilizes a selector and a shifter to perform cyclic shift. If the bit width of the data to be shifted is equal to 2 N bits, the barrel shifter module is as shown in Figure 6 .

[0037] The bit splicing module in the application adopts a ping-pong structure to perform OR operation on the data and the existing register, so as to ensure that the indefinite length code word is preferentially spliced into the register with existing content, and the redundant code word is stored in another register. The functions of the two registers are alternated and work in cycles. The register selection module is controlled by a state machine, and any register is selected and stored in the output buffer after being filled. If the bit width of the data to be spliced is equal to 2W bits (Binary digit, bit), wherein W=8k, and k is a positive integer, the bit splicing module and the register selection module are as shown in Figure 7 .

[0038] The code word splicing device in the application is designed by using barrel shift and a ping-pong structure, so as to ensure that the indefinite length code word is preferentially spliced into the register with existing content, and the spliced code word is output to the buffer after any register is filled. The functions of the two registers are alternated. Multiple registers output data in turns, so as to improve the splicing throughput of the splicing scheme for indefinite length code words generated by different variable word length encoding, which is the fundamental source of the high efficiency and flexibility of the application scheme.

[0039] Embodiment

[0040] In the embodiment, the application is used for splicing code words after JPEG (Joint Photographic Experts Group, image file format) compression and encoding.

[0041] In the JPEG compression process, symbols with high occurrence probability are given short codes, and symbols with low occurrence probability are given long codes. Using this scientific entropy coding method, the source coding efficiency can be improved. In the entropy coding part, the direct current component is differentially coded, the alternating current component is run-length encoded (RLE) after Z scanning, and then Huffman coding is performed. Finally, two kinds of variable-length code words are generated. One is a variable-length code word 1 generated according to a Huffman code table, and the other is a variable-length code word 2 generated according to a number value actual value required bit number table. The coding of the variable-length code word 1 is represented by Huffman_code (16 bits), the coding length of the variable-length code word 1 is represented by Huffman_size (5 bits), the coding of the variable-length code word 2 is represented by Amp_code (11 bits), and the coding length of the variable-length code word 2 is represented by Amp_size (4 bits).

[0042] The splicing process is as follows: first, Huffman_code and Amp_code are pre-spliced, 16-bit Huffman_code is zero-padded to 32 bits, and then barrel shifting is performed by Huffman_size length bits, 11-bit Amp_code is zero-padded to 32 bits, and then barrel shifting is performed by (Huffman_size+Amp_size) length bits, the data is pre-spliced into a variable-length code word through or operation and fixed bit number barrel shifting, the variable-length code word coding value is represented by Total_code (32 bits), the coding length is represented by Total_size (5 bits), and it is stored in the memory unit.

[0043] Then, the low bits of Total_code are zero-padded to 64 bits, and barrel shifting is performed. The high 32 bits and the low 32 bits of the shifted data enter the two memories of the ping-pong structure, respectively. The ping-pong structure performs or operation on the data and the existing register, preferentially splices the high / low 32 bits of the variable-length code Total_code into the existing register, and stores the low / high 32 bits of Total_code in another register. When either register is full, the spliced code word is output to the buffer, and the two registers alternate. The data stream in byte units is saved to the memory unit in sequence. Thus, the last step of data compression is completed.

[0044] The JPEG image compression unit of the application is deployed on the development board of ZCU104, the working frequency of the compression processing is 145MHz, the parameter of the data to be compressed is 688*688, the number of cycles required to compress the whole image is about 193150, and therefore the compression speed is about 1066MB / s.

[0045] Experiments show that the scheme can effectively splice indefinite length code words generated by various variable length encodings, and has the characteristics of high throughput due to the round output of multiple registers.

[0046] The application provides a code word splicing device for various variable length encodings, and there are many methods and approaches to realize the technical scheme, and the above description is only the preferred embodiment of the application, and it should be pointed out that, for ordinary skilled in the art, some improvements and refinements can be made without departing from the principle of the application, and these improvements and refinements should also be regarded as the protection scope of the application. The components not explicitly described in the embodiment can be realized by the existing technology.

Claims

1. A codeword splicing device for various variable-length encodings, characterized in that, Includes a pre-assembly module, a barrel shifting module, a bit assembly module, and a register selection module; The pre-splicing module includes a bit expander, an adder, and a barrel shift register. The expander is used to pad the low-order bits with zeros, the adder is used to output the actual bit width of the spliced ​​variable-length codeword, and the barrel shift register is used to shift to the right. The barrel-shaped shifting module is used for cyclic shifting; The bit splicing module uses a ping-pong structure to take turns being responsible for bit splicing and caching data that has not yet been bit spliced; The register selection module is used to select registers; The bit splicing module uses two registers to form a ping-pong structure. One register is responsible for bit splicing, and the other register is responsible for caching data that has not yet been bit spliced. The functions of the two registers are not fixed. They take turns being responsible for bit splicing and caching data that has not yet been bit spliced. The two registers in the bit-joining module are designated as the first register and the second register, respectively. The bit-joining module uses a ping-pong structure to perform an OR operation between the barrel-shifted data and the first register temporarily responsible for bit-joining in the ping-pong structure to achieve the bit-joining purpose. When the actual length of the data to be joined exceeds the number of remaining bits in the first register temporarily responsible for bit-joining, the excess codeword is buffered in the second register in the ping-pong structure. After the first register temporarily responsible for bit-joining is completely filled, the joined data is output. When the next codeword to be joined is input into the bit-joining module, the data to be joined is ORed with the second register. After the first register temporarily responsible for bit-joining outputs the joined data, it begins to buffer the data that has not yet been joined.

2. The codeword splicing device for multiple variable-length encodings according to claim 1, characterized in that, The pre-splicing module expands the variable-length codeword by 1 bit, then performs a barrel shift to the right according to the actual length of the variable-length codeword 1. After expanding the variable-length codeword by 2 bits, it performs a barrel shift to the right according to the sum of the lengths of the two variable-length codewords. The codeword data after the two barrel shifts are ORed, and the codeword data after the barrel shift is performed again can then be used for formal combination and splicing processing.

3. The codeword splicing device for multiple variable-length encodings according to claim 2, characterized in that, The barrel-shaped shifting module uses a selector and a shifter to perform cyclic shifting.

4. The codeword splicing device for multiple variable-length encodings according to claim 3, characterized in that, The selector selects to output either the data before or after the shift based on the input selection signal, and the shifter shifts the input data to the right according to specific shift parameters.

5. A codeword splicing device for multiple variable-length encodings according to claim 4, characterized in that, The functions of the first register and the second register alternate continuously, working in a cyclical manner.

6. A codeword splicing device for multiple variable-length encodings according to claim 5, characterized in that, The register selection module uses a data selector and a buffer register to select registers.

7. A codeword splicing device for multiple variable-length encodings according to claim 6, characterized in that, The data selector is controlled by a register selection signal. When either the first register or the second register is fully filled with data, the register selection signal will select the register that is fully filled with data for output and output it to the buffer register.

8. A codeword splicing device for multiple variable-length encodings according to claim 7, characterized in that, The buffer register outputs the data stored in it through a read enable signal.

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