A carrier cancellation system based on digitally controlled passive vector modulator and its implementation method

Abstract

The present invention discloses a carrier cancellation system based on a digitally controlled passive vector modulator, comprising a transmitter, a power splitter network, a delay line, a transceiver isolator, an antenna, a carrier cancellation module, and a receiver. The transmitter is connected to the power splitter network, which is respectively connected to the delay line, the carrier cancellation module, and the transceiver isolator; the transceiver isolator is respectively connected to the antenna and the carrier cancellation module; and the carrier cancellation module is connected to the receiver. This system not only meets the precision of phase and amplitude control but also reduces the introduction of additional phase and amplitude noise, thereby increasing the communication range of the self-interference system.

Description

Technical Field

[0001] The present invention relates to a carrier cancellation system based on a digitally controlled passive vector modulator, and also relates to an implementation method of the carrier cancellation system, belonging to the technical field of carrier communication. Background Art

[0002] Radio Frequency Identification (RFID) is a technology that uses radio frequency to carry out contactless two-way data communication. It uses radio frequency to read and write recording media (electronic tags or radio frequency cards) to achieve the purpose of target identification and data exchange.

[0003] Carrier leakage in RFID readers refers to the signal that enters the receiver from the transmitter due to various non-ideal factors in certain full-duplex wireless communication systems. This carrier leakage signal can affect the demodulation of the signal reflected from the tag or target. This signal is primarily caused by three factors: first, the limited isolation of the transceiver isolator. Circulators and directional couplers are commonly used to separate the transmit and receive signals, with typical isolation levels of 25-30 dB. Second, antenna echo reflections. Because the antenna port and the transceiver port cannot be perfectly matched, an echo signal is generated at the port. Antenna return loss is typically only around 15-20 dB. Third, the reflected signal caused by the antenna's near-field environment. The amplitude and phase of this signal vary with the environment, which is the main cause of the uncertainty in the amplitude and phase of carrier leakage. Carrier signal leakage into the receiver is a significant factor affecting receiver performance. Excessive carrier leakage can saturate active components in the receive chain, causing the receiver to malfunction. Even if the carrier leakage amplitude is not sufficient to cause circuit saturation, its phase and amplitude noise can raise the receiver's noise floor and reduce receiver sensitivity. From a system perspective, as the carrier leakage signal increases, the receiver's sensitivity decreases (i.e., the sensitivity value increases). Therefore, it not only determines the maximum output power of the transmitter but also determines the receiver's ability to process the minimum signal, thereby limiting the system's maximum transmission distance.

[0004] In the Chinese patent application with application number 202111418672.0, a radio frequency cancellation circuit and an anti-interference receiver are disclosed. The radio frequency cancellation circuit proposes to use a vector modulator, a microprocessor, an ADC, a DAC and other supporting circuits to implement an adaptive carrier cancellation scheme. However, the control signal of the vector modulator in this technical solution is generated by the DAC. Since the baseband signal inevitably contains noise, the cancellation signal is synthesized by the mixer, and the DAC-related noise inevitably enters the receiving channel, thereby reducing the receiving sensitivity of the receiving link. In addition, the modulator itself is implemented by two multipliers, and the multiplier includes an active circuit. The active circuit will introduce additional noise, which is unrelated to the noise in the transmitted signal. Therefore, it will remain after cancellation and enter the subsequent modules of the receiver. After entering the subsequent modules of the receiver, this noise will raise the noise floor of the receiver, further aggravating the deterioration of the receiver sensitivity. Summary of the Invention

[0005] The primary technical problem to be solved by the present invention is to provide a carrier cancellation system based on a digitally controlled passive vector modulator.

[0006] Another technical problem to be solved by the present invention is to provide a method for implementing the above-mentioned carrier cancellation system.

[0007] In order to achieve the above technical objectives, the present invention adopts the following technical solutions:

[0008] According to a first aspect of an embodiment of the present invention, there is provided a carrier cancellation system based on a digitally controlled passive vector modulator, comprising a transmitter, a power division network, a delay line, a transceiver isolator, an antenna, a carrier cancellation module, and a receiver;

[0009] Among them, the transmitter is connected to the power division network, the power division network is respectively connected to the delay line, the carrier cancellation module and the transceiver isolator, the transceiver isolator is respectively connected to the antenna and the carrier cancellation module, and the carrier cancellation module is connected to the receiver.

[0010] Preferably, the carrier cancellation module includes a digitally controlled passive vector modulator, a cancellation directional coupler, a sampling directional coupler, an orthogonal demodulator, a dual-channel analog-to-digital converter, and a field programmable logic array;

[0011] Among them, the input end of the mixer in the digital controlled passive vector modulator is connected to the two output ends of the field programmable logic array, and the output end of the power combiner in the digital controlled passive vector modulator is connected to the other input end of the cancellation directional coupler; one input end of the cancellation directional coupler is connected to the other output end of the transceiver isolator, and the output end of the cancellation directional coupler is connected to the input end of the sampling directional coupler; one output end of the sampling directional coupler is respectively connected to the other input ends of the 0° phase and 90° phase of the orthogonal demodulator, and the other output end of the sampling directional coupler is connected to the input end of the receiver; the 0° phase and 90° phase of the orthogonal demodulator are respectively connected to the input ends of the dual-channel analog-to-digital converter; the I-channel and Q-channel output ends of the dual-channel analog-to-digital converter are respectively connected to the two input ends of the field programmable logic array.

[0012] Preferably, the digitally controlled passive vector modulator includes a mixer, a Q-channel inverter, an I-channel inverter, a Q-channel digital attenuator, an I-channel digital attenuator, and a power combiner; wherein the function and implementation of the Q-channel inverter are the same as those of the I-channel inverter, and the function and implementation of the Q-channel digital attenuator are the same as those of the I-channel digital attenuator;

[0013] The 0° phase output end of the mixer is connected to the I-channel inverter, and the 90° phase output end of the mixer is connected to the Q-channel inverter; the I-channel inverter is connected to the I-channel digital attenuator; the Q-channel inverter is connected to the Q-channel digital attenuator; and both the I-channel digital attenuator and the Q-channel digital attenuator are connected to the power combiner.

[0014] Wherein, the I-way inverter includes a single-pole double-throw switch at the input end, a first interconnection line, a second interconnection line, and a single-pole double-throw switch at the output end;

[0015] The first port of the single-pole double-throw switch at the input end is connected to the 0° phase output end of the mixer; the second port of the single-pole double-throw switch at the input end is connected to one end of the first interconnection line; the third port of the single-pole double-throw switch at the input end is connected to one end of the second interconnection line; the other end of the first interconnection line is connected to the second port of the single-pole double-throw switch at the output end; the other end of the second interconnection line is connected to the third port of the single-pole double-throw switch at the output end; and the first port of the single-pole double-throw switch at the output end is connected to the I-channel digital attenuator.

[0016] According to a second aspect of an embodiment of the present invention, a method for implementing a carrier cancellation system based on a digitally controlled passive vector modulator is provided, comprising the following steps:

[0017] S1: Build a test platform for digitally controlled passive vector modulators;

[0018] S2: Control word I for I channel CW and Q-way control word Q CW The complex gain list is tested to obtain the one-dimensional gain list of I path and Q path;

[0019] S3: Generate the cancellation complex baseband signal at time n;

[0020] S4: Obtain the error complex baseband signal at time n;

[0021] S5: Predict the complex gain of the vector modulator model in the next clock cycle based on the minimum mean square error principle;

[0022] S6: Using the one-dimensional gain list of I and Q channels obtained in step S2, calculate the control word I of channel I at time n CW and Q-way control word Q CW and the complex gains of their respective adjacent control words;

[0023] S7: Obtain the optimal control word offset by searching and determining the shortest Euclidean distance;

[0024] S8: Update internal complex gain;

[0025] S9: Update the control word of the vector modulator and repeat steps S3 to S9 until the operation stops.

[0026] Preferably, the method for building a test platform for a digitally controlled passive vector modulator is:

[0027] The output end of the power divider is respectively connected to one input end of the digital controlled passive vector modulator, the sine input end of the orthogonal demodulator, and the cosine input end of the orthogonal demodulator; the output end of the digital controlled passive vector modulator is respectively connected to the sine input end of the orthogonal demodulator and the cosine input end of the orthogonal demodulator; the cosine output end of the orthogonal demodulator is connected to the input end of ADC1; the sine output end of the orthogonal demodulator is connected to the input end of ADC2; the output end of ADC1 and the output end of ADC2 are both connected to a field programmable logic array (FPGA); one output end of the field programmable logic array is connected to the other input end of the digital controlled passive vector modulator; and the data output end of the field programmable logic array is connected to a host computer.

[0028] Preferably, step S2 further includes:

[0029] S21: Set the control word Q of Q channel CW =0, set the control word I of channel I CW =-255;

[0030] S22: Determine control word I CW Is the value less than or equal to 255?

[0031] If yes, then go to step S23; if no, then get the one-dimensional gain list of path I, where the elements are

[0032] S23: Get the current complex gain A through testing I +jA Q , record the complex gain and proceed to step S24;

[0033] Among them, A I is the real part of the complex gain; A Q is the imaginary part of the complex gain; j is the sign of the imaginary number, which mathematically means the square root of -1;

[0034] S24: Setting I CW =I CW +1, repeat step S21.

[0035] Preferably, the digital controlled passive vector modulator is used in the control word (I CW (n) = s, Q CW (n) = m) to generate a cancellation complex baseband signal in, is the real part of the vector modulator gain, are the imaginary part of the vector modulator gain, S ref The complex baseband signal of the reference signal is a complex constant.

[0036] Preferably, the calculation formula for predicting the complex gain of the vector modulator model in the next clock cycle is:

[0037]

[0038]

[0039] Among them, A(n)=A I (n)+j*A Q (n) is the internal complex gain; A I (n) is its real part, A Q (n) is its imaginary part; the parameter μ is used to control the loop bandwidth of the minimum mean square error algorithm based on Euclidean distance judgment; is the predicted complex gain of the vector modulator model for the next cycle; For its actual part, Its imaginary part.

[0040] Preferably, the control word I of the I-way at time n is calculated CW and Q-way control word Q CW and the complex gains of their respective adjacent control words are:

[0041] Assume that the gain control word of channel I is CW (n) = s, Q-path gain control word Q CW(n) = m, I-path control word offset l∈{-1,0,1}, Q-path control word offset k∈{-1,0,1};

[0042] The complex gain of channel I is obtained by looking up the one-dimensional gain list of channel I where l∈{-1,0,1};

[0043] The complex gain of the Q path is obtained by looking up the one-dimensional gain list of the Q path where k∈{-1,0,1};

[0044] The complex gains of the I and Q paths are added together to obtain the complex gain of the vector modulator model under the action of the 9 sets of control words. The calculation formula is:

[0045]

[0046] Preferably, the method for obtaining the offset of the optimal control word by searching and judging the shortest Euclidean distance is:

[0047] Calculate the predicted complex gain using the coordinate transformation calculator And the above 9 complex gains The Euclidean distance between them, where l,k∈{-1,0,1};

[0048] The offset (L, K) of the control word with the shortest Euclidean distance is obtained by searching. The calculation formula is:

[0049]

[0050] Wherein, L is the offset of the I-path control word, and K is the offset of the Q-path control word.

[0051] Preferably, the calculation formula for updating the internal complex gain is as follows:

[0052]

[0053] When (L, K) = (0, 0) it means that the complex gain is predicted after searching and The Euclidean distance is the shortest, that is, the control word of the next cycle will remain unchanged. At this time, the internal complex gain A(n+1) of the next cycle is set to

[0054] When (L,K)≠(0,0) indicates that the complex gain is predicted after searching and The Euclidean distance is the shortest, that is, the control word of the next cycle will change. At this time, the internal complex gain A(n+1) of the next cycle is set to

[0055] Preferably, the calculation formula for updating the control word of the vector controller is as follows:

[0056] I cw (n+1)=I cw (n)+L

[0057] Q cw (n+1)=Q cw (n)+K.

[0058] Compared with the prior art, the core idea of ​​the carrier cancellation system based on a digitally controlled passive vector modulator provided by the present invention is that no active circuits are used in the cancellation signal synthesis process. Specifically, the present invention improves the output noise suppression bandwidth by adding a delay feeder to the cancellation signal generation link to improve the correlation between the leakage signal and the cancellation signal at the cancellation point. The present invention uses two one-dimensional lookup tables to implement a two-dimensional lookup table to model the passive vector modulator, reducing the demand for storage resources for the FPGA algorithm. In response to the problem of inconsistent discrete complex gain deviations of the passive vector modulator, the present invention proposes an LMS algorithm based on Euclidean distance judgment to achieve dynamic tracking and suppression of carrier leakage. By using the present invention, not only can the accuracy of phase and amplitude control be met, but the introduction of additional phase noise and amplitude noise can also be reduced, thereby increasing the communication distance of the self-interference system. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 Schematic diagram of a circuit of a carrier cancellation system based on a digitally controlled passive vector modulator according to an embodiment of the present invention;

[0060] Figure 2 Schematic diagram of a digitally controlled passive vector modulator according to an embodiment of the present invention;

[0061] FIG3( a ) is a schematic diagram of a test platform in an embodiment of the present invention;

[0062] FIG3( b ) is a test workflow of a complex gain list according to an embodiment of the present invention. Figure 1 ;

[0063] FIG3(c) is a test workflow of a complex gain list according to an embodiment of the present invention. Figure 2 ;

[0064] Figure 4 This is a flow chart of a carrier cancellation method based on Euclidean distance search and decision in an embodiment of the present invention. DETAILED DESCRIPTION

[0065] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0066] <First embodiment>

[0067] like Figure 1 As shown, the first embodiment of the present invention discloses a carrier cancellation system based on a digitally controlled passive vector modulator, comprising at least a transmitter 1, a power division network 2, a delay line 3, a transceiver isolator 4, an antenna 5, a carrier cancellation module 6, and a receiver 7. The transmitter 1 is connected to the power division network 2, which is respectively connected to the delay line 3, the carrier cancellation module 6, and the transceiver isolator 4. The transceiver isolator 4 is respectively connected to the antenna 5 and the carrier cancellation module 6, and the carrier cancellation module 6 is connected to the receiver 7. Their specific components and operating principles are described below:

[0068] In the first embodiment of the present invention, the transmitter 1 includes a power amplifier 101 and a signal source 102 , wherein the output of the signal source 102 is connected to the input of the power amplifier 101 , and the output of the power amplifier 101 is connected to the input of the first power divider 201 .

[0069] Transmitter 1 is used to generate a high-power single-tone signal, which is used to:

[0070] 1) Cancellation signal generation;

[0071] 2) Local oscillator required for error signal demodulation;

[0072] 3) Radiate to the tag or target through the antenna.

[0073] In the first embodiment of the present invention, the power splitter network 2 includes a first power splitter 201 and a second power splitter 202. The input of the first power splitter 201 is connected to the output of the power amplifier 101, one output of the first power splitter 201 is connected to the input of the second power splitter 202, and the other output of the first power splitter 201 is connected to one end of the delay line 3; one output of the second power splitter 202 is connected to one input of the transceiver isolator 4, and the other output of the second power splitter 202 is connected to one input of the 0° phase and 90° phase of the quadrature demodulator 604, respectively.

[0074] Among them, the power division network 2 distributes and outputs the single-tone signal output by the transmitter 1 according to a reasonable proportion, and outputs a part of the signal distributed according to a reasonable proportion to the digital controlled passive vector modulator 601 through the delay line 3 through the first power divider 201, and outputs the other part of the signal distributed according to a reasonable proportion to the transceiver isolator 4 through the second power divider 202.

[0075] In the first embodiment of the present invention, the delay line 3 is formed by a coaxial cable of a certain length, wherein one end of the delay line 3 is connected to the other output end of the first power divider 201 , and the other end of the delay line 3 is connected to the digitally controlled passive vector modulator 601 .

[0076] The function of delay line 3 is to improve the correlation between the cancellation signal and the leakage signal at the cancellation point by reducing delay deviation. In other words, the correlation between the two signals is proportional to the error signal noise suppression bandwidth and also proportional to the processing bandwidth of the receiver.

[0077] In the first embodiment of the present invention, one input end of the transceiver isolator 4 is connected to one output end of the second power divider 202, one output end of the transceiver isolator 4 is connected to the antenna 5, and the other output end of the transceiver isolator 4 is connected to one input end of the cancellation directional coupler 602.

[0078] The transceiver isolator 4 is used to separate the transmit signal from the receive signal. Generally, the isolation of the transceiver isolator is 25-30 dB. The antenna 5 is used to radiate the transmit signal and receive the signal reflected by the tag (or target object).

[0079] In the first embodiment of the present invention, the carrier cancellation module 6 includes a digital control passive vector modulator (DPVM) 601, a cancellation directional coupler 602, a sampling directional coupler 603, an orthogonal demodulator 604, a dual analog-to-digital converter (ADC) 605, and a field programmable logic array (FPGA) 606. The input end of the mixer 607 in the digitally controlled passive vector modulator 601 is connected to two output ends of the field programmable logic array FPGA 606, and the output end of the power combiner 612 in the digitally controlled passive vector modulator 601 is connected to the other input end of the cancellation directional coupler 602; one input end of the cancellation directional coupler 602 is connected to the other output end of the transceiver isolator 4, and the output end of the cancellation directional coupler 602 is connected to the input end of the sampling directional coupler 603; one output end of the sampling directional coupler 603 is respectively connected to the other input ends of the 0° phase and 90° phase of the orthogonal demodulator 604, and the other output end of the sampling directional coupler 603 is connected to the input end of the receiver 7; the 0° phase and 90° phase of the orthogonal demodulator 604 are respectively connected to the two input ends of the dual-channel analog-to-digital converter ADC 605; the I and Q output ends of the dual-channel analog-to-digital converter ADC 605 are respectively connected to the two input ends of the field programmable logic array FPGA 606.

[0080] like Figure 2 As shown, the digitally controlled passive vector modulator 601 includes a mixer 607, a Q-channel inverter 608, an I-channel inverter 609, a Q-channel digital attenuator 610, an I-channel digital attenuator 611, and a power combiner 612. The function and implementation of the Q-channel inverter are the same as those of the I-channel inverter, and the function and implementation of the Q-channel digital attenuator are the same as those of the I-channel digital attenuator.

[0081] Among them, the 0° phase output end of the mixer 607 is connected to the I-channel inverter 609, and the 90° phase output end of the mixer 607 is connected to the Q-channel inverter 608; the I-channel inverter 609 is connected to the I-channel digital attenuator 611; the Q-channel inverter 608 is connected to the Q-channel digital attenuator 610; and both the I-channel digital attenuator 611 and the Q-channel digital attenuator 610 are connected to the power combiner 612.

[0082] The I-channel inverter 609 includes an input single-pole double-throw switch 613, a first interconnection line 0, a second interconnection line 1, and an output single-pole double-throw switch 614. The first port 1 of the input single-pole double-throw switch 613 is connected to the 0° phase output of the mixer 607; the second port 2 of the input single-pole double-throw switch 613 is connected to one end of the first interconnection line 0; the third port 3 of the input single-pole double-throw switch 613 is connected to one end of the second interconnection line 1; the other end of the first interconnection line 0 is connected to the second port 2 of the output single-pole double-throw switch 614; the other end of the second interconnection line 1 is connected to the third port 3 of the output single-pole double-throw switch 614; and the first port 1 of the output single-pole double-throw switch 614 is connected to the I-channel digital attenuator 611.

[0083] The role of the digital controlled passive vector modulator 601 is to CW [8:0] and Q CW [8:0] to change the amplitude and phase of the input signal.

[0084] The cancellation directional coupler 602 performs vector summation on the cancellation signal and the leakage signal and outputs an error signal.

[0085] The sampling directional coupler 603 is used to take a small portion of the error signal output by the cancellation directional coupler 602 to obtain the amplitude and phase information of the residual leakage signal in the error signal.

[0086] The quadrature demodulator 604 is used to convert the error signal output by the cancellation directional coupler 602 into a baseband signal, namely, an in-phase signal I and a quadrature signal Q.

[0087] The dual-channel analog-to-digital converter 605 is used to convert analog I and Q signals into digital signals and output them to the FGPA.

[0088] Among them, the function of the FPGA signal processing module 606 is to implement the minimum mean square error algorithm ELMS based on the Euclidean distance judgment, and solve the I / Q signal of the error signal. CW [8:0] and Q CW [8:0].

[0089] <Second embodiment>

[0090] A second embodiment of the present invention discloses a method for implementing a carrier cancellation system based on a digitally controlled passive vector modulator, comprising the following steps:

[0091] S1: Build a hardware platform for automatic complex gain testing of the Digital Control Passive Vector Modulator (DPVM).

[0092] As shown in Figure 3(a), the output end of the power divider is connected to one input end of the digital controlled passive vector modulator, the sine input end of the orthogonal demodulator, and the cosine input end of the orthogonal demodulator respectively; the output end of the digital controlled passive vector modulator is connected to the sine input end of the orthogonal demodulator and the cosine input end of the orthogonal demodulator respectively; the cosine output end of the orthogonal demodulator is connected to the input end of ADC1; the sine output end of the orthogonal demodulator is connected to the input end of ADC2; the output ends of ADC1 and ADC2 are both connected to a field programmable logic array (FPGA); the output end of the field programmable logic array is connected to another input end of the digital controlled passive vector modulator; and the data output end of the field programmable logic array is connected to a host computer.

[0093] S2: Control word I for I channel CW and Q-way control word Q CW The complex gain list is tested to obtain the one-dimensional gain list of I path and Q path.

[0094] As shown in Figure 3(b) and Figure 3(c), the specific testing method includes:

[0095] S21: Set the control word Q of Q channel CW =0, set the control word I of channel I CW =-255.

[0096] The Q-path attenuation value is maximized to reduce the influence of the Q-path signal on the I-path test.

[0097] S22: Determine control word I CW Is the value less than or equal to 255?

[0098] If yes, then go to step S23; if no, then get the one-dimensional gain list of path I, where the elements are

[0099] S23: Get the current complex gain A through testing I +jA Q , record the complex gain and go to step S24.

[0100] Among them, AI is the real part of the complex gain; A Q is the imaginary part of the complex gain; j is the sign of the imaginary number, which mathematically means the square root of -1.

[0101] S24: Setting I CW =I CW +1, repeat step S21.

[0102] The method for obtaining the one-dimensional gain list of the Q path is the same as the method for obtaining the one-dimensional gain list of the I path, and the present invention will not elaborate on this.

[0103] S3: Generate the cancellation complex baseband signal at time n.

[0104] Digitally controlled passive vector modulator in the control word (I CW (n) = s, Q CW (n) = m) to generate a cancellation complex baseband signal

[0105] in, is the real part of the vector modulator gain, are the imaginary part of the vector modulator gain, S ref The complex baseband signal of the reference signal is a complex constant.

[0106] S4: Obtain the error complex baseband signal at time n.

[0107] The error complex baseband signal at time n is the difference between the leakage complex baseband signal at time n and the cancellation complex baseband signal at time n.

[0108] S5: Predict the complex gain of the vector modulator model in the next clock cycle based on the minimum mean square error principle.

[0109] The formula for predicting the complex gain of the vector modulator model in the next clock cycle is:

[0110]

[0111]

[0112] Among them, A(n)=A I (n)+j*A Q (n) is the internal complex gain; A I (n) is its real part, A Q (n) is its imaginary part; the parameter μ is used to control the loop bandwidth of the ELMS algorithm; is the predicted complex gain of the vector modulator model for the next cycle; For its actual part, Its imaginary part.

[0113] The ELMS algorithm is a Least Mean Square Based on Euclidean Distance (ELMS) algorithm, which is used to cancel carrier leakage signals.

[0114] S6: Using the one-dimensional gain list of I and Q channels obtained in step S2, calculate the control word I of channel I at time n CW and Q-way control word Q CW and the complex gains of their respective adjacent control words.

[0115] Assume that the gain control word of channel I is CW (n) = s, Q-path gain control word Q CW (n)=m, I-path control word offset l∈{-1,0,1}, Q-path control word offset k∈{-1,0,1}.

[0116] The complex gain of channel I is obtained by looking up the one-dimensional gain list of channel I where l∈{-1,0,1}.

[0117] The complex gain of the Q path is obtained by looking up the one-dimensional gain list of the Q path where k∈{-1,0,1}.

[0118] The complex gains of the I and Q paths are added together to obtain the complex gain of the vector modulator model under the action of the 9 sets of control words. The calculation formula is:

[0119]

[0120] S7: Obtain the offset of the optimal control word by searching and determining the shortest Euclidean distance.

[0121] Calculate the predicted complex gain using the Coordinate Rotation Digital Computer (CORDIC) And the above 9 complex gains The Euclidean distance between them, where l,k∈{-1,0,1}.

[0122] The offset (L, K) of the control word with the shortest Euclidean distance is obtained by searching. The calculation formula is:

[0123]

[0124] Wherein, L is the offset of the I-path control word, and K is the offset of the Q-path control word.

[0125] S8: Update internal complex gain.

[0126] The calculation formula for updating the internal complex gain is as follows:

[0127]

[0128] When (L, K) = (0, 0) it means that the complex gain is predicted after searching and The Euclidean distance is the shortest, that is, the control word of the next cycle will remain unchanged. At this time, the internal complex gain A(n+1) of the next cycle is set to

[0129] When (L,K)≠(0,0) indicates that the complex gain is predicted after searching and The Euclidean distance is the shortest, that is, the control word of the next cycle will change. At this time, the internal complex gain A(n+1) of the next cycle is set to

[0130] S9: Update the control word of the vector modulator, and repeat steps S3 to S9 until the operation stops. The calculation formula for updating the control word of the vector controller is as follows:

[0131] I cw (n+1)=I cw (n)+L

[0132] Q cw (n+1)=Q cw (n)+K

[0133] Because the mixer, digitally controlled phase shifter, digitally controlled attenuator, and power combiner that make up the digitally controlled passive vector modulator (DPVM) inherently exhibit certain amplitude and phase errors, the relationship between the complex gain corresponding to the DPVM and the control word cannot be described using a simple mathematical formula. The ideal model is a two-dimensional lookup table that iterates through all possible control words and obtains the corresponding complex gain through testing. This invention constructs the DPVM model by approximating a two-dimensional table using two one-dimensional lists. This solves the existing problem of modeling two 9-bit control words, which requires a significant amount of testing time and consumes a large amount of FPGA memory resources.

[0134] Compared with the prior art, the core idea of ​​the carrier cancellation system based on a digitally controlled passive vector modulator provided by the present invention is that no active circuits are used in the cancellation signal synthesis process. Specifically, the present invention improves the output noise suppression bandwidth by adding a delay feeder to the cancellation signal generation link to improve the correlation between the leakage signal and the cancellation signal at the cancellation point. The present invention uses two one-dimensional lookup tables to implement a two-dimensional lookup table to model the passive vector modulator, reducing the demand for storage resources for the FPGA algorithm. In response to the problem of inconsistent discrete complex gain deviations of the passive vector modulator, the present invention proposes an LMS algorithm based on Euclidean distance judgment to achieve dynamic tracking and suppression of carrier leakage. By using the present invention, not only can the accuracy of phase and amplitude control be met, but the introduction of additional phase noise and amplitude noise can also be reduced, thereby increasing the communication distance of the self-interference system.

[0135] The above describes in detail the carrier cancellation system and implementation method based on a digitally controlled passive vector modulator provided by the present invention. For those skilled in the art, any obvious modifications made to this invention without departing from its essence will constitute an infringement of the present invention's patent rights and will result in the corresponding legal liability.

Claims

1. A method for implementing carrier cancellation based on a digitally controlled passive vector modulator, characterized in that The steps include: S1: Build a test platform for digitally controlled passive vector modulators; S2: Control word I for I channel CW and Q-way control word Q CW The complex gain list is tested to obtain the one-dimensional gain list of I path and Q path; S3: Generate the cancellation complex baseband signal at time n; S4: Obtain the error complex baseband signal at time n; S5: Predict the complex gain of the vector modulator model in the next clock cycle based on the minimum mean square error principle; S6: Using the one-dimensional gain list of I and Q channels obtained in step S2, calculate the control word I of channel I at time n CW and Q-way control word Q CW and the complex gains of their respective adjacent control words; S7: Obtain the optimal control word offset by searching and determining the shortest Euclidean distance; S8: Update internal complex gain; S9: Update the control word of the vector modulator and repeat steps S3 to S9 until the operation stops.

2. The implementation method according to claim 1, characterized in that The method of building a test platform for CNC passive vector modulator is as follows: The output end of the power divider is respectively connected to one input end of the digital controlled passive vector modulator, the sine input end of the orthogonal demodulator, and the cosine input end of the orthogonal demodulator; the output end of the digital controlled passive vector modulator is respectively connected to the sine input end of the orthogonal demodulator and the cosine input end of the orthogonal demodulator; the cosine output end of the orthogonal demodulator is connected to the input end of ADC1; the sine output end of the orthogonal demodulator is connected to the input end of ADC2; the output end of ADC1 and the output end of ADC2 are both connected to a field programmable logic array (FPGA); one output end of the field programmable logic array is connected to the other input end of the digital controlled passive vector modulator; and the data output end of the field programmable logic array is connected to a host computer.

3. The implementation method according to claim 1, characterized in that Step S2 further includes: S21: Set the control word Q of Q channel CW =0, set the control word I of channel I CW =-255; S22: Determine control word I CW Is the value less than or equal to 255? If yes, then go to step S23; if no, then get the one-dimensional gain list of path I, where the elements are I is the I road; S23: Get the current complex gain A through testing I +jA Q , record the complex gain and proceed to step S24; Among them, A I is the real part of the complex gain; A Q is the imaginary part of the complex gain; j is the sign of the imaginary number, which mathematically means the square root of -1; S24: Setting I CW =I CW +1, repeat step S21.

4. The implementation method according to claim 1, wherein: Digitally controlled passive vector modulator in the control word (I CW (n) = s, Q CW (n) = m) to generate a cancellation complex baseband signal in, is the real part of the vector modulator gain, are the imaginary part of the vector modulator gain, S ref The complex baseband signal of the reference signal is a complex constant.

5. The implementation method according to claim 3, wherein: The formula for predicting the complex gain of the vector modulator model in the next clock cycle is: Among them, A(n)=A I (n)+j*A Q (n) is the internal complex gain; A I (n) is its real part, A Q (n) is its imaginary part; the parameter μ is used to control the loop bandwidth of the minimum mean square error algorithm based on Euclidean distance judgment; is the predicted complex gain of the vector modulator model for the next cycle; For its actual part, is its imaginary part; e I (n) is the error signal of channel I at the nth sampling time; e Q (n) is the error signal of the Q path at the nth sampling.

6. The implementation method according to claim 1, wherein: Calculate the control word I of channel I at time n CW and Q-way control word Q CW and the complex gains of their respective adjacent control words are: Assume that the gain control word of channel I is CW (n) = s, Q-path gain control word Q CW (n) = m, I-path control word offset l∈{-1,0,1}, Q-path control word offset k∈{-1,0,1}; The complex gain of channel I is obtained by looking up the one-dimensional gain list of channel I where l∈{-1,0,1}; The complex gain of the Q path is obtained by looking up the one-dimensional gain list of the Q path where k∈{-1,0,1}; The complex gains of the I and Q paths are added together to obtain the complex gain of the vector modulator model under the action of 9 sets of control words. The calculation formula is:

7. The implementation method according to claim 6, characterized in that The method for obtaining the offset of the optimal control word by searching and judging the shortest Euclidean distance is: Calculate the predicted complex gain using the coordinate transformation calculator And the above 9 sets of complex gains The Euclidean distance between them, where l,k∈{-1,0,1}; The offset (L, K) of the control word with the shortest Euclidean distance is obtained by searching. The calculation formula is: Wherein, L is the offset of the I-path control word, and K is the offset of the Q-path control word.

8. A carrier cancellation system based on a digitally controlled passive vector modulator, used to implement the method according to any one of claims 1 to 7, characterized in that Includes transmitter, power splitter network, delay line, transceiver isolator, antenna, carrier cancellation module and receiver; The transmitter is connected to the power division network, the power division network is respectively connected to the delay line, the carrier cancellation module and the transceiver isolator, the transceiver isolator is respectively connected to the antenna and the carrier cancellation module, and the carrier cancellation module is connected to the receiver; The carrier cancellation module includes a digitally controlled passive vector modulator, a cancellation directional coupler, a sampling directional coupler, an orthogonal demodulator, a dual-channel analog-to-digital converter and a field programmable logic array; Among them, the input end of the mixer in the digital controlled passive vector modulator is connected to the two output ends of the field programmable logic array, and the output end of the power combiner in the digital controlled passive vector modulator is connected to the other input end of the cancellation directional coupler; one input end of the cancellation directional coupler is connected to the other output end of the transceiver isolator, and the output end of the cancellation directional coupler is connected to the input end of the sampling directional coupler; one output end of the sampling directional coupler is respectively connected to the other input ends of the 0° phase and 90° phase of the orthogonal demodulator, and the other output end of the sampling directional coupler is connected to the input end of the receiver; the 0° phase and 90° phase of the orthogonal demodulator are respectively connected to the input ends of the dual-channel analog-to-digital converter; the I-channel and Q-channel output ends of the dual-channel analog-to-digital converter are respectively connected to the two input ends of the field programmable logic array.

9. The carrier cancellation system according to claim 8, wherein: The digitally controlled passive vector modulator includes a mixer, a Q-channel inverter, an I-channel inverter, a Q-channel digital attenuator, an I-channel digital attenuator, and a power combiner; wherein the function and implementation method of the Q-channel inverter are the same as those of the I-channel inverter, and the function and implementation method of the Q-channel digital attenuator are the same as those of the I-channel digital attenuator; The 0° phase output terminal of the mixer is connected to the I-way inverter, and the 90° phase output terminal of the mixer is connected to the Q-way inverter; the I-way inverter is connected to the I-way digital attenuator; the Q-way inverter is connected to the Q-way digital attenuator; the I-way digital attenuator and the Q-way digital attenuator are both connected to the power combiner; Wherein, the I-way inverter includes a single-pole double-throw switch at the input end, a first interconnection line, a second interconnection line, and a single-pole double-throw switch at the output end; The first port of the single-pole double-throw switch at the input end is connected to the 0° phase output end of the mixer; the second port of the single-pole double-throw switch at the input end is connected to one end of the first interconnection line; the third port of the single-pole double-throw switch at the input end is connected to one end of the second interconnection line; the other end of the first interconnection line is connected to the second port of the single-pole double-throw switch at the output end; the other end of the second interconnection line is connected to the third port of the single-pole double-throw switch at the output end; and the first port of the single-pole double-throw switch at the output end is connected to the I-channel digital attenuator.

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