A signal timing synchronization method, apparatus, device and medium

Abstract

This application discloses a signal timing synchronization method, apparatus, device, and medium. The method includes: determining a feedforward sampling point by performing a feedforward timing synchronization operation on a received signal, and then selecting a specified signal from the received signal as a feedback signal based on the feedforward sampling point. Next, based on the initial feedback sampling point determined by the feedforward sampling point, the initial timing error of the loop filter is obtained through the initial feedback sampling point and the initial value of the oscillator of the loop filter. The loop filter then performs a feedback synchronization timing operation on the feedback signal based on the initial timing error to obtain a feedback sampling point. Finally, the timing synchronization signal of the received signal is determined based on the feedforward sampling point and the feedback sampling point. The above process does not limit the sampling time of the signal, and by setting an initial timing error for the loop filter, the convergence time of its operation is significantly reduced, thereby improving the accuracy of the timing synchronization signal.

Description

Technical Field

[0001] This application relates to the field of satellite wireless communication technology, specifically to a signal timing synchronization method, apparatus, device, and medium. Background Technology

[0002] In the field of satellite wireless communication, there is a large time delay during signal transmission at the transmitting and receiving ends, as well as time delay spread caused by relative motion. To ensure signal synchronization, it is necessary to obtain the position of the optimal sampling point from the received complete signal segment to recover the constellation diagram information, thereby providing correct input for subsequent decoding work.

[0003] In related technologies, timing synchronization techniques are often used to obtain the optimal sampling point in the received signal, i.e., the timing synchronization signal of the received signal. From an implementation perspective, there are mainly two types of algorithms: feedforward and feedback. Feedforward timing synchronization algorithms require a relatively long data length and the signal-to-noise ratio cannot be too low, making them unsuitable for scenarios with large time spans. While feedback timing synchronization algorithms can adapt to scenarios with large time spans and support lower signal-to-noise ratios, their longer convergence time can easily affect the accuracy of the timing synchronization signal acquisition. Summary of the Invention

[0004] This application provides a signal timing synchronization method, apparatus, device, and medium to solve the problems in related technologies where feedforward algorithms cannot be applied to scenarios with large time spans, and where feedback algorithms have low timing synchronization signal accuracy.

[0005] In a first aspect, embodiments of this application provide a signal timing synchronization method, the method comprising:

[0006] The feedforward timing error of the received signal is determined based on the feedforward timing synchronization algorithm, and the feedforward sampling point of the received signal is determined based on the feedforward timing error; wherein, the received signal is obtained by the signal receiving device based on the communication signal sampled within a time period of a preset oversampling multiple pair;

[0007] Based on the feedforward sampling points, a specified signal is selected from the received signal as a feedback signal;

[0008] The loop filter sets an initial feedback sampling point based on the feedforward sampling point, so that the loop filter determines an initial timing error based on the initial feedback sampling point and a preset oscillator initial value, and performs a feedback timing synchronization operation on the feedback signal based on the initial timing error to determine the feedback sampling point of the feedback signal; wherein, the preset oscillator initial value is determined based on the feedforward timing error;

[0009] The timing synchronization signal of the received signal is determined based on the feedforward sampling point and the feedback sampling point.

[0010] In some embodiments, determining the feedforward timing error of the received signal based on the feedforward timing synchronization algorithm includes:

[0011] Synchronization header data is extracted from the received signal, and the carrier data of the synchronization header data is determined based on the square of the modulus of the synchronization header data.

[0012] The feedforward timing error is determined based on the preset oversampling factor and the carrier data.

[0013] In some embodiments, determining the feedforward sampling point of the received signal based on the feedforward timing error includes:

[0014] The normalized timing error is determined based on the preset oversampling factor and the feedforward timing error;

[0015] The synchronization header data is linearly interpolated based on the normalized timing error to obtain the feedforward sampling points.

[0016] In some embodiments, selecting a specified signal from the received signal as a feedback signal based on the feedforward sampling points includes:

[0017] The candidate signal is determined based on the two feedforward sampling points with the latest sampling time; wherein, the candidate signal is the received signal whose sampling time is between the two feedforward sampling points;

[0018] The received signal preceding the candidate signal is taken as the target signal; and the target signal, along with the received signal whose sampling time is following the target signal, is taken as the feedback signal.

[0019] In some embodiments, the initial feedback sampling points include the two feedforward sampling points with the latest sampling time and an interpolation point with a sampling time between the two feedforward sampling points; wherein the interpolation point is obtained by performing linear interpolation on each of the feedforward sampling points.

[0020] In some embodiments, determining the timing synchronization signal of the received signal based on the feedforward sampling point and the feedback sampling point includes:

[0021] The target sampling point whose sampling time is between the first signal and the second signal is used as the synchronization timing signal of the first signal; wherein, the target sampling point includes the feedforward sampling point and the feedback sampling point; the first signal and the second signal are received signals with adjacent sampling times, and the sampling time of the first signal is before that of the second signal.

[0022] Secondly, embodiments of this application provide a signal timing synchronization device, the device comprising:

[0023] The feedforward sampling module is configured to perform a feedforward timing error determination based on a feedforward timing synchronization algorithm, and determine the feedforward sampling point of the received signal based on the feedforward timing error; wherein the received signal is obtained by the signal receiving device based on communication signals sampled within a time period of a preset oversampling factor pair;

[0024] The feedback signal module is configured to select a specified signal from the received signal as a feedback signal based on the feedforward sampling point.

[0025] The feedback sampling module is configured to set an initial feedback sampling point for the loop filter based on the feedforward sampling point, so that the loop filter determines an initial timing error based on the initial feedback sampling point and a preset oscillator initial value, and performs a feedback timing synchronization operation on the feedback signal based on the initial timing error to determine the feedback sampling point of the feedback signal; wherein, the preset oscillator initial value is determined based on the feedforward timing error;

[0026] The timing synchronization module is configured to execute a timing synchronization signal for determining the received signal based on the feedforward sampling point and the feedback sampling point.

[0027] In some embodiments, when performing the feedforward timing error determination of the received signal based on the feedforward timing synchronization algorithm, the feedforward sampling module is configured to:

[0028] Synchronization header data is extracted from the received signal, and the carrier data of the synchronization header data is determined based on the square of the modulus of the synchronization header data.

[0029] The feedforward timing error is determined based on the preset oversampling factor and the carrier data.

[0030] In some embodiments, when performing the step of determining the feedforward sampling point of the received signal based on the feedforward timing error, the feedforward sampling module is configured to:

[0031] The normalized timing error is determined based on the preset oversampling factor and the feedforward timing error;

[0032] The synchronization header data is linearly interpolated based on the normalized timing error to obtain the feedforward sampling points.

[0033] In some embodiments, the step of selecting a specified signal as a feedback signal from the received signal based on the feedforward sampling point is performed, wherein the feedback signal module is configured to:

[0034] The candidate signal is determined based on the two feedforward sampling points with the latest sampling time; wherein, the candidate signal is the received signal whose sampling time is between the two feedforward sampling points;

[0035] The received signal preceding the candidate signal is taken as the target signal; and the target signal, along with the received signal whose sampling time is following the target signal, is taken as the feedback signal.

[0036] In some embodiments, the initial feedback sampling points include the two feedforward sampling points with the latest sampling time and an interpolation point with a sampling time between the two feedforward sampling points; wherein the interpolation point is obtained by performing linear interpolation on each of the feedforward sampling points.

[0037] In some embodiments, the timing synchronization module is configured to determine a timing synchronization signal for the received signal based on the feedforward sampling point and the feedback sampling point.

[0038] The target sampling point whose sampling time is between the first signal and the second signal is used as the synchronization timing signal of the first signal; wherein, the target sampling point includes the feedforward sampling point and the feedback sampling point; the first signal and the second signal are received signals with adjacent sampling times, and the sampling time of the first signal is before that of the second signal.

[0039] Thirdly, embodiments of this application provide an electronic device, including:

[0040] Memory, used to store program instructions;

[0041] A processor is configured to invoke program instructions stored in the memory and execute the steps of the method described in any one of the first aspects according to the obtained program instructions.

[0042] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a computer, cause the computer to perform the method described in any one of the first aspects.

[0043] Fifthly, embodiments of this application provide a computer program product comprising: computer program code, which, when executed on a computer, causes the computer to perform the steps included in the method described in any of the first aspects.

[0044] In this embodiment, a feedforward sampling point is determined by performing feedforward timing synchronization calculations on the received signal. Based on this feedforward sampling point, a specified signal is selected from the received signal as a feedback signal, and an initial feedback sampling point is determined according to this feedforward sampling point. An initial timing error is set for the loop filter based on this initial feedback sampling point and the initial value of the loop filter's oscillator. The loop filter then performs feedback synchronization timing calculations on the feedback signal based on the initial timing error to obtain the feedback sampling point. Finally, a timing synchronization signal for the received signal is determined based on the feedforward sampling point and the feedback sampling point.

[0045] The above process combines feedforward and feedback timing synchronization algorithms to determine the timing synchronization signal for the received signal. This solves the time constraint problem of the feedforward timing synchronization algorithm, and by setting an initial timing error for the loop filter, it significantly reduces the convergence time and improves the computational accuracy, thereby solving the problem of low accuracy in the feedback timing synchronization algorithm.

[0046] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing this disclosure. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0047] Figure 1 This is an overall flowchart of a signal timing synchronization method provided in an embodiment of this application;

[0048] Figure 2 A schematic diagram of feedforward sampling points provided in the embodiments of this application;

[0049] Figure 3 This is a schematic diagram of the target signal provided in an embodiment of this application;

[0050] Figure 4 This is a schematic diagram of the burst signal structure provided in an embodiment of this application;

[0051] Figure 5 The oscillator provided in the embodiments of this application is the loop output diagram when the initial value is calculated in this application;

[0052] Figure 6 This is a loop output diagram corresponding to the oscillator value being 0, provided in an embodiment of this application.

[0053] Figure 7 The oscillator provided in this application embodiment is the constellation diagram used in calculating the initial values ​​in this application;

[0054] Figure 8 This is a constellation diagram corresponding to the oscillator value being 0 in the embodiments of this application;

[0055] Figure 9 The oscillator provided in the embodiments of this application is the loop output diagram when the initial value is calculated in this application;

[0056] Figure 10 This is a loop output diagram corresponding to the oscillator being set to 1 in the embodiments of this application;

[0057] Figure 11 The oscillator provided in the embodiments of this application is the constellation diagram used in calculating the initial values ​​of this application;

[0058] Figure 12 The constellation diagram corresponding to the oscillator being 1 provided in the embodiments of this application;

[0059] Figure 13 A structural diagram of a signal timing and synchronization device 1300 provided in an embodiment of this application;

[0060] Figure 14 A schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than that shown here.

[0062] The terms "first" and "second" in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the term "comprising" and any variations thereof are intended to cover non-exclusive protection. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses. The term "multiple" in this application can mean at least two, for example, two, three, or more, and is not limited by the embodiments of this application.

[0063] As mentioned earlier, most related technologies obtain the optimal sampling point in the received signal through timing synchronization techniques. Existing timing synchronization algorithms mainly fall into two categories: feedforward and feedback. Specifically, the feedforward timing synchronization algorithm performs overall calculations on the received signal and then performs Fourier analysis to obtain its timing error. This algorithm is relatively intuitive and, provided the oversampling factor is designed reasonably, does not require Fourier transform, and has advantages such as low resource consumption and insensitivity to frequency offset. However, this algorithm requires a long data length and has high signal-to-noise ratio requirements, making it unsuitable for applications with large time spans. The feedback timing synchronization algorithm typically uses the Gardner algorithm to directly extract the timing error from the estimated value of the received signal and then tracks the optimal sampling point position in real time through a phase-locked loop. It overcomes the shortcomings of the feedforward algorithm, has lower requirements for data signal-to-noise ratio, and is suitable for applications with large time spans. However, this algorithm has a long convergence time, which affects the accuracy of the optimal sampling point.

[0064] To address the aforementioned problems, the inventive concept of this application is as follows: A feedforward sampling point is determined by performing feedforward timing synchronization calculations on the received signal. Based on this feedforward sampling point, a specified signal is selected from the received signal as a feedback signal, and an initial feedback sampling point is determined according to this feedforward sampling point. An initial timing error is set for the loop filter based on this initial feedback sampling point and the initial value of the loop filter's oscillator. The loop filter then performs feedback synchronization timing calculations on the feedback signal based on the initial timing error to obtain the feedback sampling point. Finally, the timing synchronization signal for the received signal is determined based on the feedforward sampling point and the feedback sampling point.

[0065] The above process combines feedforward and feedback timing synchronization algorithms to determine the timing synchronization signal for the received signal. This solves the time constraint problem of the feedforward timing synchronization algorithm, and by setting an initial timing error for the loop filter, it significantly reduces the convergence time and improves the computational accuracy, thereby solving the problem of low accuracy in the feedback timing synchronization algorithm.

[0066] For a better understanding of the technical solution of this application, please refer to the following: Figure 1 , Figure 1 A flowchart of a signal timing synchronization method provided in this application embodiment specifically includes the following steps:

[0067] Step 101: Determine the feedforward timing error of the received signal based on the feedforward timing synchronization algorithm, and determine the feedforward sampling point of the received signal according to the feedforward timing error; wherein, the received signal is obtained by the signal receiving device based on the communication signal sampled within a time period of a preset oversampling multiple pair;

[0068] A complete signal is typically composed of pilot segments and data segments, and the modulation types of the pilot and data segments can be the same or different. Local pilots often use the simplest PSK modulation method. In the embodiments of this application, the communication signal within a certain time period is pre-sampled by a preset oversampling factor, and the signal obtained each time is the received signal. The sampling points (i.e., the received signals) are sorted in ascending order according to the reception timing of each received signal, resulting in the expression {r0, r2, ..., r...}. N-1 The multiple received signals are shown in the diagram.

[0069] Next, synchronization header data is extracted from the received signal, and the carrier data of the synchronization header data is determined based on the square of the modulus of the synchronization header data. Then, the feedforward timing error is determined based on the elements, the oversampling factor, and the carrier data.

[0070] The synchronization header data is a signal of a preset length selected from the received signals. This preset length is determined based on the communication protocol used to transmit each received signal. For example, a set of received signals with a length of 1016, i.e., received signals {1, 2, 3, 4...1015, 1016}. Assuming the protocol specifies that the synchronization header data length is 16, then the first 16 signals from 1 to 1016 are extracted as the synchronization header data. Each synchronization header data can be represented as {r0, r1, ..., r...}. K}; where r0~r K This is the synchronization header data, where K is the length of the synchronization header data as indicated in the protocol.

[0071] Furthermore, the carrier data of the synchronization header data is determined based on the square of the modulus of the synchronization header data, and the feedforward timing error is determined based on the carrier data. The square of the modulus of each synchronization header data in r1x above can be expressed as rp_x={rp0,rp1,…,rp K}, rp i =|r i | 2 The generated carrier data can be represented as i = 0, 1, ..., K. j is the imaginary unit. In practice, the feedforward timing error of the synchronization header data can be determined based on the carrier data using the following formula (1):

[0072]

[0073] Where ∈ represents the feedforward timing error, and the angle(x) function represents the phase of the complex number x within the parentheses. Next, the normalized timing error τ of the synchronization header data is determined using the following formula (2) based on the preset oversampling factor M and the feedforward timing error ∈:

[0074]

[0075] Furthermore, by performing linear interpolation on the synchronization header data based on the normalized timing error τ, the feedforward sampling points in r1x can be obtained. Sorting each feedforward sampling point in ascending order according to its corresponding receiving timing sequence, it can be represented as {y0, y1, ..., y...} K-1}

[0076] The above process considers that the length and signal-to-noise ratio of the synchronization header data largely meet the requirements of the feedforward timing synchronization algorithm. Therefore, after selecting the synchronization header data through the above process, the feedforward timing synchronization algorithm is used to determine the feedforward sampling point. This feedforward sampling point is the timing synchronization signal of the received signal corresponding to the synchronization header data. Let's continue with the above received signal {1, 2, 3, 4…1015, 1016}. Assuming the communication protocol specifies that the length of the synchronization header data is 16, then the first 16 signals are extracted from the received signal {1, 2, 3, 4…1015, 1016}, i.e., {1, 2, 3… 16}, as the synchronization header data. Sampling is performed every two points, and linear interpolation is applied to the synchronization header data to obtain the corresponding feedforward sampling points {3.5, 5.5, 7.5, 9.5, 11.5, 13.5, 15.5}.

[0077] Step 102: Based on the feedforward sampling points, select a specified signal from the received signals as the feedback signal;

[0078] In this embodiment, candidate signals are determined based on the two feedforward sampling points with the latest sampling times; wherein, the candidate signals are received signals whose sampling times are between the two feedforward sampling points. Further, the received signal whose sampling time is before and adjacent to the candidate signal is designated as the target signal. Finally, the target signal and the received signal whose sampling time is after the target signal are used as feedback signals.

[0079] The following is in the above Figure 2 Based on the example, the steps in step 102 above for determining the feedback signal will be explained. See [link to relevant documentation] for details. Figure 3 .like Figure 3 As shown, during implementation, the two sampling points with the latest sampling time are selected from the above feedforward sampling points {3.5, 5.5, 7.5, 9.5, 11.5, 13.5, 15.5}, ​​i.e. Figure 3 The y shown in k-2 =13.5 and y k-1 =15.5. Then, the received signal 14 located between 13.5 and 15.5 is taken as the candidate signal. The received signal whose sampling time is before the candidate signal and adjacent to the candidate signal is taken as the target signal. That is, from the received signals 13 and 15 whose sampling time is adjacent to the sampling time of the candidate signal, the received signal 13 located before the candidate signal 14 is found, and the received signal 13 is taken as the target signal.

[0080] Finally, the target signal, and the received signal whose sampling time is after that target signal, are used as the feedback signal. For example... Figure 3 As shown, after determining the target signal, the target signal 13 and all received signals whose sampling time is after the target signal 13 are used as feedback signals, thus obtaining the feedback signals 13 to 1016.

[0081] The logic for determining the feedback signal will be explained below. Taking the received signal example of 1 to 1016 as an example, the time span of a received signal of length 1016 is inevitably large, therefore, the feedforward timing synchronization algorithm cannot be used to calculate the timing synchronization signal for all of them. Considering that the synchronization header data defined by the protocol usually does not have a large time span, this application, based on the length specification of the synchronization header data in the communication protocol, extracts the first 16 received signals for the calculation of the feedforward timing synchronization algorithm, while the remaining 17 to 1016 received signals are calculated using a feedback timing synchronization algorithm without time constraints.

[0082] In implementation, the remaining received signals can be subjected to feedback timing synchronization calculations using a loop filter to obtain the corresponding feedback sampling points (i.e., timing synchronization signals 17 to 1016). To address the issue of long convergence time in the feedback timing synchronization calculation, which leads to low calculation accuracy, this embodiment selects the received signal between the two feedforward sampling points with the latest sampling time as the candidate signal, and uses the received signal with a sampling time adjacent to and preceding the candidate signal as the target signal. Thus, the values ​​of the sampling points between the target signal 13 and the last received signal 16 according to the feedforward timing synchronization calculation are known (i.e., the feedforward sampling points between target signals 13 and 16). By performing appropriate calculations on these known points, the parameter yiqk (representing the feedback sampling points output by the loop filter) can be obtained, providing the loop filter with an initial timing error. In this way, the loop filter performs feedback timing synchronization calculations on the feedback signal based on this initial timing error, significantly reducing its convergence time and improving calculation accuracy. The specific implementation process is described in the following steps.

[0083] Step 103: Set an initial feedback sampling point for the loop filter based on the feedforward sampling point, so that the loop filter determines the initial timing error according to the initial feedback sampling point and the preset oscillator initial value, and performs feedback timing synchronization operation on the feedback signal based on the initial timing error to determine the feedback sampling point of the feedback signal; wherein, the preset oscillator initial value is determined based on the feedforward timing error;

[0084] In this embodiment, the initial feedback sampling point Interp_IQ_value is set for the loop filter based on the above-mentioned feedforward sampling points. The initial feedback sampling points include the two feedforward sampling points with the latest sampling times and the interpolation point with the sampling time between these two feedforward sampling points. The interpolation point is obtained by performing linear interpolation on each feedforward sampling point. Furthermore, the preset initial value of the oscillator is determined based on the feedforward timing error, as shown in the following formula (3):

[0085]

[0086] Wherein, nk_nco is the preset initial value of the oscillator, and τ is the normalized timing error determined based on the feedforward timing error. Next, the loop filter determines the initial timing error using the above parameters nk_nco and Interp_IQ_value. Then, based on this initial timing error, the feedback signal is subjected to feedback timing calculation, which can significantly reduce its convergence time and thus improve the accuracy of the output feedback sampling point.

[0087] The loop filter performs two loop operations within one symbol period, therefore the initial value of the loop output vector wk is set to 0.5. Interp_IQ_value includes three points: two feedforward sampling points with the latest sampling times and an interpolation point between these two feedforward sampling points. Therefore, the initial value of the loop operation interpolation calculation count counter k is 3, and the initial value of the feedback sampling point count counter m is 2. The feedback sampling point identifier data_clk is set to 1. The initial value of the data counter i is 0. For each input data i = i + 1, the step decrement of nk_nco is calculated. M is the preset oversampling factor mentioned above.

[0088] Taking the aforementioned 1016 received signals as an example, since Interp_IQ_value contains two feedforward sampling points (13.5 and 15.5) between 13 and 16, the feedback sampling points obtained after assigning initial values ​​to the loop filter should correspond to the received signals between 17 and 1016.

[0089] Specifically, the feedback signals are sorted from earliest to latest based on their sampling time, which can be expressed by the expression {r s r s+1 ,...,r N-1} is represented as r s ~r N-1 The feedback signal is the first signal input into the loop filter, which is the feedback signal with the earliest sampling time, r. sAfter the signal is input to the loop filter, the loop filter updates nk_nco from the preset oscillator initial value to nk_nco - wk_tmp. If the updated value is greater than 0, the data counter executes i = i + 1, and then continues to update nk_nco. If nk_nco ≤ 0, it indicates that interpolation is needed. At this time, the interpolation calculation count counter executes k = k + 1, and the signal r is determined based on the interpolation coefficients. s The interpolation result, interpolation coefficient u k =nk_nco′*2, where nk_nco′ represents the nearest positive number before nk_nco ≤ 0. After interpolation, execute data_clk = 1 - data_clk on the feedback sampling point identifier. At this point, if data_clk = 1, it means that a feedback sampling point exists, and this feedback sampling point is the loop filter for signal r. s The output yiqk(r) s ), that is, signal r s The feedback sampling point. Otherwise, the input to the loop filter is located at the feedback signal r. s The next signal r s+1 .

[0090] If r is determined in the above judgment process s For the feedback sampling point, r needs to be determined using the following formula (4). s Corresponding feedback timing error:

[0091] time err(m) =[real(yiqk(k))-real(yiqk(k-2))]·real(yiqk(k-1))+[imag(yiqk(k))-imag(yiqk(k-2))]·imag(yiqk(k-1)) (4)

[0092] Among them, time err(m) For the aforementioned feedback timing error, the `real(x)` function calculates the real part of the complex number `x` within the parentheses, and the `imag(x)` function calculates the imaginary part of the complex number `x` within the parentheses. After determining the feedback timing error using the above formula, the parameter `wk` is updated, specifically to `wk′`, where `wk′` is `wk + c2[time_err(m) - time_err(m-1)] + c1time_err(m)`. Here, `c1` and `c2` are the loop coefficients of the loop filter, determined based on the loop filter's bandwidth and gain. Simultaneously, the loop output `loop_out` is assigned the value `c2[time_err(m) - time_err(m-1)] + c1time_err(m)`, and the feedback sampling point counter is incremented by `m = m + 1`. This process iterates through the feedback signals in `r2x` until all input data has been processed, yielding the corresponding feedback sampling points for each feedback signal.

[0093] Step 104: Determine the timing synchronization signal of the received signal based on the feedforward sampling point and the feedback sampling point.

[0094] In practice, the target sampling point whose sampling time is between the first signal and the second signal is used as the synchronization timing signal of the first signal; wherein, the target sampling point includes a feedforward sampling point and a feedback sampling point; the first signal and the second signal are received signals with adjacent sampling times, and the sampling time of the first signal is before that of the second signal.

[0095] Taking the aforementioned 1016 received signals as an example, for two received signals with adjacent sampling times, such as received signals 8 and 9, the feedforward sampling point with a sampling time between received signals 8 and 9 is used as the timing synchronization signal for received signal 8. As another example, if the adjacent received signals are 200 and 201, the feedback sampling point with a sampling time between received signals 200 and 201 is used as the timing synchronization signal for received signal 200.

[0096] The following describes the verification process of a signal timing synchronization algorithm provided in an embodiment of this application:

[0097] In this embodiment, signal bit data of length 100,000 bits is randomly generated, using BPSK modulation. The pilot signal is also BPSK modulated, and the pilot symbol is inserted at the beginning of the signal symbol as a frame header, resulting in the burst signal format of the baseband IQ signal as follows: Figure 4 As shown, Figure 4 The burst signal format shown includes two parts: pilot and data. The pilot is known and is usually a random sequence with good correlation characteristics. The oversampling factor at the receiver is set to 4. After the modulated signal passes through the channel, it is mixed, sample rate converted, low-pass filtered, and matched filtered to obtain the IQ data that needs to be timed and synchronized. Both the shaping filter and the matched filter use root-raised cosine filters with a roll-off factor of 0.35.

[0098] Next, a signal timing synchronization algorithm provided in this application embodiment is applied to the above data. In implementation, IQ sampling data containing complete pilot symbols with a length of 8192 is acquired as the input for feedforward timing error estimation for timing synchronization. Through the feedforward timing synchronization algorithm, 2048 feedforward sampling points of the pilot section are obtained by interpolation, and the initial value of the feedback loop Nco (i.e., the nk_nco parameter mentioned above) is calculated. Further, the feedback sampling points obtained by the feedback loop and the feedforward sampling points obtained by the feedforward timing synchronization algorithm are combined to obtain the final optimal sampling points. The obtained optimal sampling points are the timing synchronization signals for each received signal.

[0099] The following is based on Figures 5-12The convergence effect of the loop filter in this application is explained. The illustration uses a typical cross-correlation frame synchronization algorithm from related technologies as a comparison algorithm with this application for loop output comparison. Specifically, Figures 5-12 For the embodiments of this application in E s The simulation diagram obtained under the condition of / N0=10dB noise-free is shown. The loop output and constellation diagram are compared with the initial value of the oscillator determined by the normalized timing error of the feedforward sampling point in the embodiment of this application when the initial value of nco is set to 0 and 1 in the typical feedback timing synchronization algorithm.

[0100] First see Figures 5-8 , Figures 5-8 The diagram shows the loop filter output with and without the preset oscillator initial value provided in the embodiments of this application, as well as the comparison results of the constellation diagram. Figure 5 The loop output diagram is shown when the loop filter performs feedback timing synchronization calculations using the Nco value set in this application (i.e., the nk_nco parameter mentioned above). Figure 6 This is the loop output diagram for feedback timing synchronization calculation when Nco is initially set to 0. Figure 5 and Figure 6 The comparison shows that when Nco is initialized to the preset oscillator initial value calculated in the embodiment of this application, the loop converges immediately and outputs a stable value. In contrast, when Nco is set to 0 in a typical algorithm, the loop output takes about 30,000 symbol cycles to stabilize, indicating that the convergence speed of the loop filter in this application is significantly faster than that of a simple feedback loop. Figure 7 and Figure 8 The figures show the constellation diagrams when the feedback loop Nco is set to the preset initial value of the oscillator in this embodiment and when it is 0. It can be seen that when Nco is set to the preset initial value of the oscillator calculated in this embodiment, the constellation diagram converges quickly to the theoretical point. However, the simple feedback loop constellation diagram has a significant tailing effect, which directly leads to an increase in EVM and seriously affects the demodulation performance.

[0101] See next. Figures 9-12 , Figures 9-12 The diagram shows the loop filter output with the preset oscillator initial value provided in the embodiments of this application and the loop output with an initial value of 1, as well as the comparison results of the constellation diagram. Figure 9 and Figure 10 The figures show the loop outputs with Nco set to the preset initial oscillator value calculated in this embodiment and with an initial value of 1, respectively. The comparison shows that when Nco is set to the preset initial oscillator value calculated in this embodiment, the loop converges immediately and outputs a stable value. However, when Nco is set to 1, the loop output takes approximately 25,000 symbol cycles to stabilize, indicating that the convergence speed of this embodiment is significantly faster than that of a simple feedback loop. Figure 11 and Figure 12 The figures show the constellation diagrams when the feedback loop Nco is set to the preset initial value of the oscillator in this embodiment and when the initial value is 1. The comparison shows that when Nco is set to the preset initial value of the oscillator calculated in this embodiment, the constellation diagram converges quickly to the theoretical point, while the simple feedback loop constellation diagram has a significant tailing effect, which directly leads to an increase in EVM and thus seriously affects the demodulation performance.

[0102] Based on the same inventive concept, this application provides a signal timing synchronization device 1300, see details below. Figure 13 ,include:

[0103] The feedforward sampling module 1301 is configured to perform a feedforward timing error determination based on a feedforward timing synchronization algorithm for the received signal, and to determine the feedforward sampling point of the received signal based on the feedforward timing error; wherein the received signal is obtained by the signal receiving device based on communication signals sampled within a time period of a preset oversampling factor pair;

[0104] The feedback signal module 1302 is configured to select a specified signal from the received signal as a feedback signal based on the feedforward sampling point.

[0105] The feedback sampling module 1303 is configured to set an initial feedback sampling point for the loop filter based on the feedforward sampling point, so that the loop filter determines an initial timing error based on the initial feedback sampling point and a preset oscillator initial value, and performs a feedback timing synchronization operation on the feedback signal based on the initial timing error to determine the feedback sampling point of the feedback signal; wherein, the preset oscillator initial value is determined based on the feedforward timing error;

[0106] The timing synchronization module 1304 is configured to execute a timing synchronization signal for determining the received signal based on the feedforward sampling point and the feedback sampling point.

[0107] In some embodiments, when performing the feedforward timing error determination of the received signal based on the feedforward timing synchronization algorithm, the feedforward sampling module is configured to:

[0108] Synchronization header data is extracted from the received signal, and the carrier data of the synchronization header data is determined based on the square of the modulus of the synchronization header data.

[0109] The feedforward timing error is determined based on the preset oversampling factor and the carrier data.

[0110] In some embodiments, when performing the step of determining the feedforward sampling point of the received signal based on the feedforward timing error, the feedforward sampling module is configured to:

[0111] The normalized timing error is determined based on the preset oversampling factor and the feedforward timing error;

[0112] The synchronization header data is linearly interpolated based on the normalized timing error to obtain the feedforward sampling points.

[0113] In some embodiments, the step of selecting a specified signal as a feedback signal from the received signal based on the feedforward sampling point is performed, wherein the feedback signal module is configured to:

[0114] The candidate signal is determined based on the two feedforward sampling points with the latest sampling time; wherein, the candidate signal is the received signal whose sampling time is between the two feedforward sampling points;

[0115] The received signal preceding the candidate signal is taken as the target signal; and the target signal, along with the received signal whose sampling time is following the target signal, is taken as the feedback signal.

[0116] In some embodiments, the initial feedback sampling points include the two feedforward sampling points with the latest sampling time and an interpolation point with a sampling time between the two feedforward sampling points; wherein the interpolation point is obtained by performing linear interpolation on each of the feedforward sampling points.

[0117] In some embodiments, the timing synchronization module is configured to determine a timing synchronization signal for the received signal based on the feedforward sampling point and the feedback sampling point.

[0118] The target sampling point whose sampling time is between the first signal and the second signal is used as the synchronization timing signal of the first signal; wherein, the target sampling point includes the feedforward sampling point and the feedback sampling point; the first signal and the second signal are received signals with adjacent sampling times, and the sampling time of the first signal is before that of the second signal.

[0119] The following reference Figure 14 To describe an electronic device 130 according to this embodiment of the present application. Figure 14 The electronic device 130 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0120] like Figure 14 As shown, the electronic device 130 is presented in the form of a general-purpose electronic device. The components of the electronic device 130 may include, but are not limited to: at least one processor 131, at least one memory 132, and a bus 133 connecting different system components (including memory 132 and processor 131).

[0121] Bus 133 represents one or more of several bus structures, including a memory bus or memory controller, peripheral bus, processor, or local bus using any of the various bus structures.

[0122] The memory 132 may include a readable medium in the form of volatile memory, such as random access memory (RAM) 1321 and / or cache memory 1322, and may further include read-only memory (ROM) 1323.

[0123] The memory 132 may also include a program / utility 1325 having a set (at least one) of program modules 1324, including but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0124] Electronic device 130 can also communicate with one or more external devices 134 (e.g., keyboard, pointing device, etc.), and with one or more devices that enable a user to interact with electronic device 130, and / or with any device that enables electronic device 130 to communicate with one or more other electronic devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 135. Furthermore, electronic device 130 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 136. As shown, network adapter 136 communicates with other modules used in electronic device 130 via bus 133. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 130, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0125] In an exemplary embodiment, a computer-readable storage medium including instructions is also provided, such as a memory 132 including instructions, which can be executed by a processor 131 of the device 400 to perform the above-described method. Optionally, the computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0126] In an exemplary embodiment, a computer program product is also provided, including a computer program / instruction that, when executed by a processor 131, implements any one of the signal timing synchronization method or the method for acquiring embedded data provided in this application.

[0127] In an exemplary embodiment, various aspects of the signal timing synchronization method or the method for acquiring embedded data provided in this application can also be implemented in the form of a program product, which includes program code. When the program product is run on a computer device, the program code is used to cause the computer device to perform the steps in the signal timing synchronization method or the method for acquiring embedded data according to the various exemplary embodiments of this application described above.

[0128] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0129] The program product for signal timing synchronization or acquisition of embedded data according to the embodiments of this application can be a portable compact disc read-only memory (CD-ROM) and include program code, and can run on an electronic device. However, the program product of this application is not limited thereto. In this document, the readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0130] A readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying readable program code. This propagated data signal may take many forms, including—but not limited to—electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0131] The program code contained on the readable medium may be transmitted using any suitable medium, including—but not limited to—wireless, wired, fiber optic, RF, etc., or any suitable combination thereof.

[0132] Program code for performing the operations of this application can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as Java or similar languages. The program code can execute entirely on the user's electronic device, partially on the user's device, as a standalone software package, partially on the user's electronic device and partially on a remote electronic device, or entirely on a remote electronic device or server. In cases involving remote electronic devices, the remote electronic device can be connected to the user's electronic device via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external electronic device (e.g., via the Internet using an Internet service provider).

[0133] It should be noted that although several units or sub-units of the device have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of this application, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided and embodied by multiple units.

[0134] Furthermore, although the operations of the method of this application are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0135] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0136] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable image scaling device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable image scaling device, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0137] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable image scaling device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0138] These computer program instructions can also be loaded onto a computer or other programmable image scaling device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable device for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0139] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0140] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A signal timing synchronization method, characterized in that, The method includes: Synchronization header data is extracted from the received signal, and the carrier data of the synchronization header data is determined based on the square of the modulus of the synchronization header data. Based on the carrier data and the preset oversampling factor, the feedforward timing error is determined, and the feedforward sampling point of the received signal is determined according to the feedforward timing error; Based on the feedforward sampling points, a specified signal is selected from the received signal as a feedback signal; The loop filter sets an initial feedback sampling point based on the feedforward sampling point, so that the loop filter determines an initial timing error based on the initial feedback sampling point and a preset oscillator initial value, and performs a feedback timing synchronization operation on the feedback signal based on the initial timing error to determine the feedback sampling point of the feedback signal; wherein, the preset oscillator initial value is determined based on the feedforward timing error; The timing synchronization signal of the received signal is determined based on the feedforward sampling point and the feedback sampling point.

2. The method according to claim 1, characterized in that, Determining the feedforward sampling point of the received signal based on the feedforward timing error includes: The normalized timing error is determined based on the preset oversampling factor and the feedforward timing error; The synchronization header data is linearly interpolated based on the normalized timing error to obtain the feedforward sampling points.

3. The method according to claim 1, characterized in that, The step of selecting a specified signal from the received signal as a feedback signal based on the feedforward sampling point includes: The candidate signal is determined based on the two feedforward sampling points with the latest sampling time; wherein, the candidate signal is the received signal whose sampling time is between the two feedforward sampling points; The received signal preceding the candidate signal is taken as the target signal; and the target signal, along with the received signal whose sampling time is following the target signal, is taken as the feedback signal.

4. The method according to claim 3, characterized in that, The initial feedback sampling points include the two feedforward sampling points with the latest sampling time and the interpolation point with the sampling time between the two feedforward sampling points; wherein, the interpolation point is obtained by performing linear interpolation operation on each of the feedforward sampling points.

5. The method according to any one of claims 1-4, characterized in that, The step of determining the timing synchronization signal of the received signal based on the feedforward sampling point and the feedback sampling point includes: The target sampling point whose sampling time is between the first signal and the second signal is used as the synchronization timing signal of the first signal; wherein, the target sampling point includes the feedforward sampling point and the feedback sampling point; the first signal and the second signal are received signals with adjacent sampling times, and the sampling time of the first signal is before that of the second signal.

6. A signal timing and synchronization device, characterized in that, The device includes: The feedforward sampling module is configured to extract synchronization header data from the received signal and determine the carrier data of the synchronization header data based on the modulus square of the synchronization header data. Based on the carrier data and a preset oversampling factor, a feedforward timing error is determined, and the feedforward sampling point of the received signal is determined according to the feedforward timing error; wherein, the received signal is obtained by the signal receiving device sampling the communication signal within a time period based on the preset oversampling factor pair; The feedback signal module is configured to select a specified signal from the received signal as a feedback signal based on the feedforward sampling point. The feedback sampling module is configured to set an initial feedback sampling point for the loop filter based on the feedforward sampling point, so that the loop filter determines an initial timing error based on the initial feedback sampling point and a preset oscillator initial value, and performs a feedback timing synchronization operation on the feedback signal based on the initial timing error to determine the feedback sampling point of the feedback signal; wherein, the preset oscillator initial value is determined based on the feedforward timing error; The timing synchronization module is configured to execute a timing synchronization signal for determining the received signal based on the feedforward sampling point and the feedback sampling point.

7. An electronic device, characterized in that, include: Memory, used to store program instructions; A processor is configured to invoke program instructions stored in the memory and execute the method of any one of claims 1-5 according to the obtained program instructions.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a computer, cause the computer to perform the method as described in any one of claims 1-5.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1-5.

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