PLL circuit

Abstract

This invention provides a PLL circuit. The PLL circuit (1) includes a phase comparator (10), a charge pump (20), a loop filter (30), a voltage-controlled oscillator (40), a frequency divider (50), a frequency difference determination unit (60), and an FV characteristic adjustment unit (70). The frequency difference determination unit (60) determines whether the frequency difference between the feedback oscillation signal and the input signal is below a threshold. The FV characteristic adjustment unit (70) selects the frequency band of the voltage-controlled oscillator (40) to adjust the FV characteristic.

Description

Technical Field

[0001] This invention relates to PLL circuits. Background Technology

[0002] Generally, a PLL (Phase Locked Loop) circuit consists of a phase comparator, a charge pump, a loop filter, and a voltage-controlled oscillator (VCO), forming a loop. The PLL circuit acts as a frequency synthesizer for the output oscillation signal, which has a frequency that makes the frequency of the input oscillation signal a constant multiple. Furthermore, the PLL circuit can recover the clock from the digital signal embedded in the input CDR (Clock Data Recovery) device.

[0003] The PLL circuit operates as follows: When a control voltage value is input to the voltage-controlled oscillator, the oscillator outputs an oscillation signal with a frequency corresponding to that control voltage value. The oscillation signal output from the voltage-controlled oscillator, or a signal obtained by frequency division of the oscillation signal, is input as a feedback oscillation signal to the phase comparator. In addition to this feedback oscillation signal, other input signals (oscillation signals or digital signals) are also input to the phase comparator. The phase comparator detects the phase difference between the input signal and the feedback oscillation signal and outputs a phase difference signal representing the detected phase difference to the charge pump.

[0004] A charge pump that receives the input phase difference signal outputs a charging / discharging current corresponding to the phase difference represented by the phase difference signal. This charging / discharging current is input into a loop filter. The loop filter contains capacitive elements whose charge accumulation increases or decreases according to the charging / discharging current output from the charge pump. The loop filter outputs a control voltage value corresponding to the charge accumulation to a voltage-controlled oscillator. When the control voltage value output from the loop filter is input to the voltage-controlled oscillator, the voltage-controlled oscillator outputs an oscillation signal with a frequency corresponding to the control voltage value.

[0005] In a PLL circuit with such a loop, the control voltage value output from the loop filter and input to the voltage-controlled oscillator converges to a value that reduces the phase difference detected by the phase comparator. Then, the voltage-controlled oscillator outputs an oscillating signal with a frequency that makes the frequency of the input oscillation signal a constant multiple, or, alternatively, an output after recovering the clock embedded in the input digital signal.

[0006] Various types of voltage-controlled oscillators exist. Among them, the LC-VCO comprises inductors and capacitors. Through the resonance phenomenon of these inductors and capacitors, it outputs an oscillating signal with a frequency corresponding to the input control voltage value. When compared with other types of voltage-controlled oscillators, the LC-VCO exhibits less jitter. Therefore, at frequencies above 10 Gbps, the use of the LC-VCO is suitable among various types of voltage-controlled oscillators.

[0007] When compared with other types of voltage-controlled oscillators, the frequency of the output oscillation signal in an LC-VCO changes less with variations in the control voltage value. In an LC-VCO, changing the capacitor value alters the FV characteristic between the output oscillation signal frequency (F) and the control voltage value (V). Furthermore, the range of control voltage values ​​input to an LC-VCO is limited; when the control voltage value deviates from this range, the frequency ratio between the input and output does not hold.

[0008] However, the frequency of the transmitted signal sometimes varies over time due to spread spectrum (SS). When the signal frequency is constant, the energy of the electromagnetic waves emitted from the signal is concentrated at that frequency, thus electromagnetic interference (EMI) becomes a problem. In contrast, if the signal frequency is intentionally modulated using SS, the bandwidth of the electromagnetic wave energy emitted from the signal becomes wider and the peak value becomes smaller. SS can reduce EMI problems. SS is preferred for frequency modulation of signals with high bit rates or long transmission distances. The modulation depth for SS modulation is sometimes required to be ±1.0% or higher.

[0009] For example, a serializer device that converts parallel data into serial data latches the parallel data at a timing indicated by a first clock with a low frequency and outputs the serial data at a timing indicated by a second clock with a high frequency. In such a serializer device, sometimes a second clock (SS) is applied to output the serial data. In this case, the PLL circuit input used in the serializer device is given a first clock (SS), generates a frequency that is a constant multiple of the frequency of the first clock, and is given a second clock (SS) and output.

[0010] When the serial data bit rate is high and the second clock frequency is high, as mentioned above, an LC-VCO is preferably used as the voltage-controlled oscillator included in the PLL circuit. However, when the frequency modulation using the SS in the first clock input to the PLL circuit is large, the fluctuation of the control voltage value input to the LC-VCO also increases, resulting in a situation where the frequency of the second clock output from the PLL circuit is not proportional to the frequency of the first clock. To avoid this situation, in the LC-VCO, it is important to appropriately set the capacitor value and select any frequency band from multiple frequency bands to make the FV characteristic suitable.

[0011] Inventions aimed at appropriately setting the FV characteristics are disclosed in Patent Documents 1 and 2. In the invention disclosed in Patent Document 1, within the range of frequency variation of the first clock, the capacitance value of the capacitor in the LC-VCO is set such that the frequency of the first clock is always proportional to the frequency of the second clock. In the invention disclosed in Patent Document 2, the capacitance value of the capacitor in the LC-VCO is set such that within the range of frequency variation of the first clock, the control voltage value input to the LC-VCO always remains within a specified range.

[0012] Patent Document 1: Japanese Patent Application Publication No. 2003-78410

[0013] Patent Document 2: US Patent No. 7,102,446 Summary of the Invention

[0014] However, in the invention disclosed in Patent Document 1, even if the FV characteristics of the LC-VCO are appropriate at the initial setup, the FV characteristics of the LC-VCO may sometimes deteriorate in the presence of voltage or temperature variations. That is, the invention disclosed in Patent Document 1 sometimes fails to adequately ensure the voltage-temperature (VT) drift margin.

[0015] Furthermore, in the invention disclosed in Patent Document 2, when the range of the control voltage value input to the LC-VCO is large, the same problem as that described above exists in the invention disclosed in Patent Document 1. Conversely, when the range of the control voltage value input to the LC-VCO is narrow, and when the frequency modulation using SS is large and the fluctuation range of the control voltage value is large, it is sometimes impossible to find an FV characteristic that keeps the control voltage value within a specified range. Moreover, when an FV characteristic is selected when the range of the control voltage value input to the LC-VCO is narrow, if only a small portion of the control voltage value is within the specified range, the selected FV characteristic may not be suitable. Such problems exist not only in LC-VCOs but also in voltage-controlled oscillators that include a ring oscillator in which multiple delay elements having a delay set according to the input control voltage value are connected in a ring.

[0016] The present invention was made to overcome the above-mentioned problems, and its purpose is to provide a PLL circuit that can more appropriately set the FV characteristics of the voltage-controlled oscillator.

[0017] The PLL circuit of the present invention comprises: (1) a voltage-controlled oscillator, which includes an inductor and a capacitor, and outputs an oscillation signal having a frequency corresponding to the input control voltage value by utilizing the resonance phenomenon caused by these inductors and capacitors, and the FV characteristic between the frequency and the control voltage value is variable by selecting any frequency band from a plurality of frequency bands; (2) a phase comparator, which is input with the oscillation signal output from the voltage-controlled oscillator or a signal obtained by dividing the oscillation signal as a feedback oscillation signal, and is also input with an input signal, detects the phase difference between these feedback oscillation signals and the input signal, and outputs a phase difference signal representing the phase difference; (3) a charge pump, which is input with the phase difference signal output from the phase comparator. And outputs a charging and discharging current corresponding to the phase difference represented by the phase difference signal; (4) a loop filter, which is input with the charging and discharging current output from the charge pump, and outputs a control voltage value that increases or decreases according to the charging and discharging amount of the charging and discharging current to the voltage-controlled oscillator; (5) a frequency difference determination unit, which is input with the feedback oscillation signal and the input signal, and determines whether the frequency difference between these feedback oscillation signals and the input signal is below a threshold; and (6) an FV characteristic adjustment unit, which selects the frequency band of the voltage-controlled oscillator to adjust the FV characteristic based on the boundary between the frequency band determined by the frequency difference determination unit to have a frequency difference below a threshold and the frequency band determined by the frequency difference determination unit to have a frequency difference exceeding a threshold among the multiple frequency bands that can be set in the voltage-controlled oscillator.

[0018] Alternatively, the PLL circuit of the present invention comprises: (1) a voltage-controlled oscillator comprising a ring oscillator, the ring oscillator being constructed by connecting a plurality of delay elements having a delay set according to the input control voltage value in a ring, utilizing the oscillation phenomenon of the ring oscillator to output an oscillation signal having a frequency corresponding to the input control voltage value, and by selecting any frequency band from a plurality of frequency bands, making the FV characteristic between the frequency and the control voltage value variable; (2) a phase comparator, which is input with an oscillation signal output from the voltage-controlled oscillator or a signal obtained by dividing the oscillation signal as a feedback oscillation signal, and is also input with an input signal, detecting the phase difference between these feedback oscillation signals and the input signal, and outputting a phase difference signal representing the phase difference; (3) a charge (3) Pump, which is input with the phase difference signal output from the phase comparator and outputs a charging and discharging current corresponding to the phase difference represented by the phase difference signal; (4) Loop filter, which is input with the charging and discharging current output from the charge pump and outputs a control voltage value that increases or decreases according to the charging and discharging amount of the charging and discharging current to the voltage-controlled oscillator; (5) Frequency difference determination unit, which is input with the feedback oscillation signal and the input signal and determines whether the frequency difference between these feedback oscillation signals and the input signal is below a threshold; (6) FV characteristic adjustment unit, which selects the frequency band of the voltage-controlled oscillator to adjust the FV characteristic based on the boundary between the frequency band determined by the frequency difference determination unit to have a frequency difference below a threshold and the frequency band determined by the frequency difference determination unit to have a frequency difference exceeding a threshold among the multiple frequency bands that can be set in the voltage-controlled oscillator.

[0019] Preferably, the FV characteristic adjustment unit selects any frequency band from multiple frequency bands to adjust the FV characteristic based on both the high-frequency side boundary and the low-frequency side boundary. More preferably, the FV characteristic adjustment unit selects any frequency band from multiple frequency bands to adjust the FV characteristic based on either the high-frequency side boundary or the low-frequency side boundary.

[0020] The PLL circuit of this invention can more appropriately set the FV characteristics of the voltage-controlled oscillator. Attached Figure Description

[0021] Figure 1 This is a diagram showing the structure of PLL circuit 1.

[0022] Figure 2 This is a diagram showing a circuit example of a voltage-controlled oscillator 40.

[0023] Figure 3 This is a diagram illustrating an example of the FV characteristics of a voltage-controlled oscillator 40.

[0024] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4EThis is a graph illustrating cycle slip.

[0025] Figure 5 This is a diagram showing an example of the circuit structure of the frequency difference determination unit 60.

[0026] Figure 6 This is a diagram showing an example of the circuit structure of the frequency difference determination unit 60.

[0027] Figure 7 This is a circuit example of a voltage-controlled oscillator 40A.

[0028] Label Explanation

[0029] 1: PLL circuit; 10: Phase comparator; 20: Charge pump; 30: Loop filter; 31: Resistor; 32: Capacitor; 33: Capacitor; 34: Buffer; 40, 40A: Voltage controlled oscillator; 50: Frequency divider; 60: Frequency difference determination unit; 70: FV characteristic adjustment unit. Detailed Implementation

[0030] Hereinafter, the embodiments for carrying out the invention will be described in detail with reference to the accompanying drawings. Furthermore, in the description of the drawings, the same reference numerals are used to denote the same elements, and repeated descriptions are omitted. The invention is not limited to these illustrations, but is indicated by the claims, which are intended to include all modifications of the same meaning and scope as the claims.

[0031] Figure 1 This is a diagram showing the structure of PLL circuit 1. PLL circuit 1 includes a phase comparator 10, a charge pump 20, a loop filter 30, a voltage-controlled oscillator 40, a frequency divider 50, a frequency difference determination unit 60, and an FV characteristic adjustment unit 70.

[0032] The voltage-controlled oscillator 40 includes inductors and capacitors. Utilizing the resonance phenomenon of these inductors and capacitors, it outputs an oscillating signal with a frequency corresponding to the control voltage value input from the loop filter 30. The voltage-controlled oscillator 40 is an LC-VCO. The voltage-controlled oscillator 40 selects any frequency band from a plurality of frequency bands, thereby making the FV characteristic between the frequency (F) of the output oscillation signal and the control voltage value (V) variable.

[0033] The phase comparator 10 receives a feedback oscillation signal obtained by dividing the oscillation signal output from the voltage-controlled oscillator 40 by N using the frequency divider 50, and this signal is also input as an input signal. Alternatively, the frequency divider 50 may be omitted, in which case the oscillation signal output from the voltage-controlled oscillator 40 becomes the feedback oscillation signal input to the phase comparator 10. The input signal to the phase comparator 10 is a clock signal, or it may be a digital signal with an embedded clock. The phase comparator 10 detects the phase difference between these feedback oscillation signals and the input signal, and outputs a phase difference signal representing this phase difference to the charge pump 20.

[0034] The charge pump 20 is input with the phase difference signal output from the phase comparator 10, and outputs a charging and discharging current corresponding to the phase difference represented by the phase difference signal.

[0035] The loop filter 30 receives the charging and discharging current output from the charge pump 20 and outputs a control voltage value VC to the voltage-controlled oscillator 40, which increases or decreases according to the amount of charging and discharging. The loop filter 30 includes at least a capacitor, which stores charge in the capacitor in accordance with the charging and discharging current output from the charge pump 20, and outputs a control voltage value VC corresponding to the amount of stored charge.

[0036] The frequency difference determination unit 60 receives a feedback oscillation signal and an input signal, and determines whether the frequency difference between these feedback oscillation signals and the input signal is below a threshold. The FV characteristic adjustment unit 70 calculates the boundary between the frequency bands that can be set in the voltage-controlled oscillator 40, where the frequency difference determination unit 60 determines that the frequency difference is below the threshold, and the frequency bands that the frequency difference determination unit 60 determines that the frequency difference exceeds the threshold. Then, the FV characteristic adjustment unit 70 selects a frequency band in the voltage-controlled oscillator 40 to adjust the FV characteristic based on the calculated boundary. The details of the frequency difference determination unit 60 and the FV characteristic adjustment unit 70 will be described later.

[0037] Figure 2 This is a diagram illustrating a circuit example of a voltage-controlled oscillator 40. In the circuit example shown in this figure, the voltage-controlled oscillator 40 includes NMOS transistors M1 and M2, resistors R1 and R2, capacitors C11 to C15, capacitors C21 to C25, switches SW0 to SW2, and inductor L.

[0038] The sources of NMOS transistors M1 and M2 are connected to ground. The drain of NMOS transistor M1 is connected to the gate of NMOS transistor M2. The drain of NMOS transistor M2 is connected to the gate of NMOS transistor M1.

[0039] Capacitors C11, C12, C22, and C21 are connected in series in this order and positioned between the drains of NMOS transistors M1 and M2. The capacitance values ​​of capacitors C12 and C22 are variable. Resistors R1 and R2, connected in series, are positioned between the connection point of capacitors C11 and C12 and the connection point of capacitors C21 and C22. A voltage Vr is input to the connection point between resistors R1 and R2.

[0040] Capacitor C13, switch SW0, and capacitor C23 are connected in series in this order and are positioned between the drains of NMOS transistors M1 and M2. Capacitor C14, switch SW1, and capacitor C24 are connected in series in this order and are positioned between the drains of NMOS transistors M1 and M2. Capacitor C15, switch SW2, and capacitor C25 are connected in series in this order and are positioned between the drains of NMOS transistors M1 and M2.

[0041] For example, the following relationship exists between the capacitance values ​​of capacitors C13-C15 and C23-C25, where C is the capacitance value of capacitors C13 and C23.

[0042] C15 = C25 = 2 2 C

[0043] C14 = C24 = 2C

[0044] C13=C23=C

[0045] Inductor L is positioned between the drains of NMOS transistors M1 and M2. A power supply voltage VDD is applied to inductor L.

[0046] The on / off state of each of the three switches SW0 to SW2 is set using the FV characteristic control signal provided from the FV characteristic adjustment unit 70. The FV characteristic control signal can be represented by 3 bits of data. The overall capacitance value of the capacitor pool Cbank, including capacitors C13 to C15 and capacitors C23 to C25, corresponds to the FV characteristic control signal (i.e., the on / off setting state of each of the three switches SW0 to SW2). A control voltage value VC is input to the connection point between capacitors C12 and C22. An oscillation signal is output from the drain of NMOS transistor M2. The frequency of this output oscillation signal corresponds to the control voltage value VC. Furthermore, the FV characteristic corresponds to the FV characteristic control signal.

[0047] In Figure 2 In the structure shown, the number of frequency bands selectable in the voltage-controlled oscillator 40 is equal to the number of settable capacitance values ​​in the capacitor bank Cbank, which is 8 (=2). 3By increasing the number of settable capacitance values ​​in the capacitor bank Cbank, the number of frequency bands selectable in the voltage-controlled oscillator 40 can be increased. The voltage-controlled oscillator 40 selects any one of the multiple frequency bands, thereby possessing the FV characteristics of the selected frequency band.

[0048] Figure 3 This is a graph illustrating an example of the FV characteristics of a voltage-controlled oscillator 40. The horizontal axis represents the control voltage value VC input to the voltage-controlled oscillator 40. The vertical axis represents the frequency of the oscillation signal output from the voltage-controlled oscillator 40. In this graph, the FV characteristics between the frequency of the output oscillation signal and the control voltage value VC are shown for nine frequency bands B1 to B9.

[0049] Furthermore, in this figure, the solid line represents the central value V0 of the control voltage VC when SS is applied, and the dashed line represents the range of variation of the control voltage VC (V0±ΔV). The solid line represents the central value F0 of the frequency of the output oscillation signal when SS is applied, and the dashed line represents the range of variation of the frequency of the output oscillation signal (F0±ΔF).

[0050] The voltage-controlled oscillator 40 can select any frequency band from multiple frequency bands using an FV characteristic control signal, and output an oscillation signal with a frequency corresponding to the input control voltage value according to the FV characteristic of the selected frequency band. However, within any frequency band, the region where the frequency of the output oscillation signal has a roughly linear relationship with the control voltage value is limited, and nonlinear regions exist outside both sides of this linear region. Importantly, the variation range caused by SS is within the linear region.

[0051] exist Figure 3 Of the nine frequency bands B1 to B9 shown, the variation range caused by SS in the two end bands B1 and B9 includes a non-linear region. In frequency bands B2 to B8, the variation range caused by SS does not include a non-linear region, only a linear region. That is, frequency bands B2 to B8 encompass the entire range of frequency variation of the output oscillation signal caused by SS. When any frequency band from B2 to B8 is selected using the FV characteristic control signal, the frequency of the output oscillation signal is linearly related to the frequency or bit rate of the input signal. Therefore, any frequency band from B2 to B8 should be selected.

[0052] In the presence of multiple frequency bands encompassing the entire range of frequency variations in the output oscillation signal caused by SS, any one of these frequency bands can be selected. However, to adequately ensure the VT drift margin, it is preferable to select a more suitable frequency band from among the multiple bands. Figure 3 In the example, it is frequency band B5 located in the center.

[0053] Therefore, the frequency difference determination unit 60 is input with the feedback oscillation signal and the input signal, and determines whether the frequency difference between these feedback oscillation signals and the input signal is below a threshold. This is essentially equivalent to determining whether the frequency band selected in the voltage-controlled oscillator 40 includes the entire range of frequency variations in the output oscillation signal caused by SS.

[0054] Furthermore, the FV characteristic adjustment unit 70 determines the boundary between the frequency bands that the frequency difference determination unit 60 determines are below a threshold and the frequency bands that the frequency difference determination unit 60 determines are above a threshold, among the multiple frequency bands that can be set in the voltage-controlled oscillator 40. This is essentially equivalent to determining the boundary of whether the frequency band includes the entire range of frequency variations of the output oscillation signal caused by SS. Based on this determined boundary, the FV characteristic adjustment unit 70 selects an appropriate frequency band in the voltage-controlled oscillator 40 to adjust the FV characteristic.

[0055] The frequency difference determination unit 60 can determine whether the frequency difference between the feedback oscillation signal and the input signal is below a threshold by detecting the phenomenon that the phase error between the feedback oscillation signal and the input signal exceeds 2π (periodic slip).

[0056] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E This is a graph illustrating periodic slip. The horizontal axis represents time. In this graph, the rise time of the input signal is shown sequentially from top to bottom. Figure 4A ), the rise time of the feedback oscillation signal ( Figure 4B ), the current applied to the charge pump (CP) Figure 4C ), the original phase error between the feedback oscillation signal and the input signal ( Figure 4D ) and the phase error observed from the charge pump (CP) Figure 4E In the example shown in the figure, the frequency of the feedback oscillation signal is lower than that of the input signal, the rise time delay of the feedback oscillation signal relative to the rise time delay of the input signal gradually increases, and the current applied to the CP gradually increases. However, when the original phase error between the feedback oscillation signal and the input signal reaches 2π, resulting in a periodic slip, the rise time delay of the feedback oscillation signal relative to the rise time delay of the input signal temporarily decreases and then gradually increases again, and the current applied to the CP temporarily decreases and then gradually increases again.

[0057] The rise timing of the input signal and the rise timing of the feedback oscillation signal should alternate. However, if the rise timing of either signal occurs consecutively, a periodic slippage is generated. The frequency difference determination unit 60 determines whether the frequency difference between the feedback oscillation signal and the input signal is below a threshold by detecting such periodic slippage.

[0058] Figure 5 and Figure 6 This is a diagram showing an example of the circuit structure of the frequency difference determination unit 60. Figure 5 The circuitry of the frequency difference determination unit 60 (period slip detection section) is shown. Figure 6 The latter part (frequency difference determination part) is shown.

[0059] The Rn input of the D flip-flop 111 is connected to the output of the NOR gate 133. A signal of level H is input to the D input of the D flip-flop 111. The D flip-flop 111 latches according to the rising timing of the input signal INCLK.

[0060] The Rn input of D flip-flop 112 is reset by the input signal RSTn. The D input of D flip-flop 112 is connected to the Q output of D flip-flop 111. D flip-flop 112 latches according to the rising time of the input signal INCLK.

[0061] One input of NAND gate 113 is connected to the QN output of D flip-flop 112. The other input of NAND gate 113 is connected to the QN output of D flip-flop 115.

[0062] One input of selector 114 is connected to the output of NAND gate 113. The other input of selector 114 is input with a signal of level L. Selector 114 outputs a signal with the same level as the signal input to either of its two inputs, based on the logic level of the signal output from the output of OR gate 134.

[0063] The Rn input of D flip-flop 115 is fed with a reset indicator signal RSTn. The D input of D flip-flop 115 is connected to the output of selector 114. D flip-flop 115 latches according to the rising timing of the input signal INCLK.

[0064] The Rn input of D flip-flop 116 is fed with a reset indicator signal RSTn. The D input of D flip-flop 116 is connected to the Q output of D flip-flop 115. D flip-flop 116 latches according to the rising timing of the feedback oscillation signal FBCLK.

[0065] The Rn input of the D flip-flop 121 is connected to the output of the NOR gate 133. A signal of level H is input to the D input of the D flip-flop 121. The D flip-flop 121 latches according to the rising timing of the feedback oscillation signal FBCLK.

[0066] The Rn input of D flip-flop 122 is fed with a reset indicator signal RSTn. The D input of D flip-flop 122 is connected to the Q output of D flip-flop 121. D flip-flop 122 latches according to the rising timing of the feedback oscillation signal FBCLK.

[0067] One input of NAND gate 123 is connected to the QN output of D flip-flop 122. The other input of NAND gate 123 is connected to the QN output of D flip-flop 125.

[0068] One input of selector 124 is connected to the output of NAND gate 123. The other input of selector 124 is input with a signal of level L. Selector 124 outputs a signal with the same level as the signal input to either of its two inputs, based on the logic level of the signal output from OR gate 134.

[0069] The Rn input of the D flip-flop 125 is fed with a reset indicator signal RSTn. The D input of the D flip-flop 125 is connected to the output of the selector 124. The D flip-flop 125 latches according to the rising timing of the feedback oscillation signal FBCLK.

[0070] The Rn input of D flip-flop 126 is fed with a reset indicator signal RSTn. The D input of D flip-flop 126 is connected to the Q output of D flip-flop 125. D flip-flop 126 latches according to the rising timing of the feedback oscillation signal FBCLK.

[0071] One input of AND gate 131 is connected to the Q output of D flip-flop 111. The other input of AND gate 131 is connected to the Q output of D flip-flop 121. INV gate 132 outputs the signal after logically inverting the reset indicator signal RSTn. One input of NOR gate 133 is connected to the output of AND gate 131. The other input of NOR gate 133 is connected to the output of INV gate 132.

[0072] One input of OR gate 134 is connected to the Q output of D flip-flop 116. The other input of OR gate 134 is connected to the Q output of D flip-flop 126.

[0073] One input of OR gate 135 is connected to the Q output of D flip-flop 116. The other input of OR gate 135 is connected to the Q output of D flip-flop 126.

[0074] The Rn input of D flip-flop 117 is fed a reset indicator signal RSTn. The D input of D flip-flop 117 is connected to the Q output of D flip-flop 116. D flip-flop 117 latches according to the rising timing of the feedback oscillation signal FBCLK.

[0075] The Rn input of D flip-flop 127 is fed with a reset indicator signal RSTn. The D input of D flip-flop 127 is connected to the Q output of D flip-flop 126. D flip-flop 127 latches according to the rising timing of the feedback oscillation signal FBCLK.

[0076] The Rn input of the D flip-flop 137 is fed a reset indicator signal RSTn. The D input of the D flip-flop 137 is connected to the output of the OR gate 135. The D flip-flop 137 latches according to the rising timing of the feedback oscillation signal FBCLK.

[0077] The output of INV gate 141 is the signal obtained by logically inverting the signal output from the Q output of D flip-flop 137. One input of selector 142 is connected to the output of INV gate 141. The other input of selector 142 is connected to the output of counter 144. Selector 142 outputs a signal with the same logic level as the signal input to either of its two inputs, based on the logic level of the signal output from the Q output of D flip-flop 143.

[0078] The Rn input of D flip-flop 143 is fed with a reset indicator signal RSTn. The D input of D flip-flop 143 is connected to the output of selector 142. D flip-flop 143 latches according to the rising timing of the feedback oscillation signal FBCLK.

[0079] Counter 144 increments according to the rising timing of the feedback oscillation signal FBCLK. The incrementing operation of counter 144 is initialized using the reset indicator signal RSTn, and also by making the signal output from the Q output of D flip-flop 137 at a high level (H). Counter 144 outputs a low-level (L) signal until the count value reaches a certain threshold; once the count value reaches the threshold, it then outputs a high-level (H) signal.

[0080] The operation of the frequency difference determination unit 60 with such a circuit structure is as follows. At the start of operation, all D flip-flops and the counter 144 are initialized using the reset indicator signal RSTn. In the initialized state, the signal output from the Q output terminal of all D flip-flops is at level L, the signal output from the QN output terminal of all D flip-flops is at level H, and the count value of the counter 144 is 0.

[0081] When the signals output from the Q output terminals of D flip-flops 111 and 121 both become H level, the output signal of AND gate 131 becomes H level, and the output signal of NOR gate 133 becomes L level. Therefore, both D flip-flops 111 and 121 are initialized.

[0082] The signal output from the Q output of D flip-flop 111 is latched by D flip-flop 112 according to the rising timing of the input signal INCLK. The signal output from the Q output of D flip-flop 121 is latched by D flip-flop 122 according to the rising timing of the feedback oscillation signal FBCLK.

[0083] When the rising timing of the input signal INCLK and the rising timing of the feedback oscillation signal FBCLK alternate, the signals output from the Q output terminals of D flip-flops 111 and 121 are at level L, and the signals output from the QN output terminals of D flip-flops 112 and 122 are at level H. Furthermore, the signals output from the NAND gates 113 and 123 are at level L, the signals output from the selectors 114 and 124 are at level L, and the signals output from the QN output terminals of D flip-flops 115 and 125 are at level H.

[0084] When the rise timing of the input signal INCLK does not occur after the rise timing of the feedback oscillation signal FBCLK, but the rise timing of the input signal INCLK occurs continuously (i.e., when the feedback oscillation signal FBCLK is delayed), since the signal output from the Q output of D flip-flop 111 is at level H, the signal output from the QN output of D flip-flop 112 becomes level L. Furthermore, the signal output from the NAND gate 113 becomes level H, the signal output from the selector 114 becomes level H, the signal output from the QN output of D flip-flop 115 becomes level L, and the signal output from the Q output of D flip-flop 115 becomes level H. During the subsequent rise timing of the feedback oscillation signal FBCLK, the signal CSSlow output from the Q output of D flip-flop 116 becomes level H. This level H for the signal CSSlow indicates a periodic slip due to the delay of the feedback oscillation signal FBCLK.

[0085] Conversely, when the rising timing of the feedback oscillation signal FBCLK does not occur after the rising timing of the input signal INCLK, but the rising timing of the feedback oscillation signal FBCLK occurs continuously (i.e., the feedback oscillation signal FBCLK is advanced), since the signal output from the Q output of D flip-flop 121 is at level H, the signal output from the QN output of D flip-flop 122 becomes level L. Furthermore, the signal output from the NAND gate 123 becomes level H, the signal output from the selector 124 becomes level H, the signal output from the QN output of D flip-flop 125 becomes level L, and the signal output from the Q output of D flip-flop 125 becomes level H. During the subsequent rising timing of the feedback oscillation signal FBCLK, the signal CSfast output from the Q output of D flip-flop 126 becomes level H. This level H for the signal CSfast indicates a periodic slip due to the advanced timing of the feedback oscillation signal FBCLK.

[0086] When either signal CSslow or signal CSfast reaches a high level (H), the signal output from OR gate 134 also reaches a high level, and the input selection in selectors 114 and 124 changes. Consequently, both signals CSslow and CSfast become low (L). The period during which either signal CSslow or CSfast reaches a high level corresponds to two cycles of the feedback oscillation signal FBCLK.

[0087] When the signal CSslow becomes level H, the signal output from the Q output of the D flip-flop 117 becomes level H during the subsequent rise timing of the feedback oscillation signal FBCLK. The fact that the signal output from the Q output of the D flip-flop 117 becomes level H indicates that a periodic slip occurs due to the delay of the feedback oscillation signal FBCLK.

[0088] When the signal CSfast becomes level H, the signal output from the Q output of the D flip-flop 127 becomes level H during the subsequent rise timing of the feedback oscillation signal FBCLK. The fact that the signal output from the Q output of the D flip-flop 127 becomes level H indicates that a period slip occurs due to the advance of the feedback oscillation signal FBCLK.

[0089] When either signal CSslow or CSfast reaches level H, the signal output from OR gate 135 also reaches level H. Subsequently, during the rise timing of the feedback oscillation signal FBCLK, the signal output from the Q output of D flip-flop 137 also reaches level H. The level H signal from the Q output of D flip-flop 137 indicates the occurrence of periodic slip, regardless of whether the feedback oscillation signal FBCLK is advanced or delayed. The period during which the signal output from the Q output of D flip-flop 137 reaches level H is two cycles of the feedback oscillation signal FBCLK.

[0090] When the signal output from the Q output of D flip-flop 137 becomes H level, counter 144 is initialized, and its count value becomes 0. At this time, the count value of counter 144 has not reached the threshold, therefore, the signal output from counter 144 is L level, and the signal LOCK output from the Q output of D flip-flop 143 is also L level. During the period when the signal LOCK is L level, the signal output from selector 142 is the same signal output from counter 144.

[0091] Counter 144 increments according to the rising timing of the feedback oscillation signal FBCLK. If the signal output from the Q output of D flip-flop 137 becomes H level again before the counter value reaches the threshold, counter 144 is reinitialized. Therefore, in this case, the LOCK signal remains at L level.

[0092] When the counter 144 reaches its threshold value before the signal output from the Q output of the D flip-flop 137 becomes H level again, the signal output from the counter 144 is inverted to H level, and the LOCK signal is also inverted to H level. During the period when the LOCK signal is H level, the signal output from the selector 142 is obtained by logically inverting the signal output from the Q output of the D flip-flop 137 using the INV gate 141.

[0093] Thus, the frequency difference determination unit 60 can determine whether the frequency difference between the feedback oscillation signal FBCLK and the input signal INCLK is below a threshold based on whether the signal LOCK is at level H. The threshold in counter 144 corresponds to a threshold related to the frequency difference. Changing the threshold in counter 144 corresponds to changing the length of the period during which no periodic slippage occurs, which serves as a reference when it is determined that the feedback oscillation signal FBCLK and the input signal INCLK are in a locked state. A period during which no periodic slippage occurs is 10 times the period of the feedback oscillation signal FBCLK, which corresponds to a frequency difference between the feedback oscillation signal FBCLK and the input signal INCLK being less than 10%.

[0094] The FV characteristic adjustment unit 70, based on the determination result of the frequency difference determination unit 60, calculates whether the frequency difference between the feedback oscillation signal and the input signal is below a threshold boundary, and selects an appropriate frequency band from the multiple frequency bands that can be set in the voltage-controlled oscillator 40. Various methods may exist for calculating the boundary and selecting the preferred frequency band. Hereinafter, [the following will be discussed]. Figure 3 Taking the nine frequency bands B1 to B9 shown as examples, this paper explains the method for determining the boundaries and the method for selecting the preferred frequency bands.

[0095] The first method for determining the boundary is as follows: starting from one side of multiple frequency bands arranged sequentially from the high-frequency side to the low-frequency side, the frequency difference determination unit 60 sequentially determines whether the frequency difference between the feedback oscillation signal and the input signal is below a threshold, thereby determining the boundary. Figure 3 Taking the nine frequency bands B1 to B9 as an example, the frequency difference determination unit 60 first determines that the frequency difference of frequency band B1 exceeds the threshold, then determines that the frequency difference of frequency band B2 is below the threshold, then determines that the frequency differences of frequency bands B3 to B8 are below the threshold, and finally determines that the frequency difference of frequency band B9 exceeds the threshold. Based on these determination results, it can be seen that frequency bands B2 and B8 are located at the boundaries.

[0096] The second method for determining the boundary is as follows: Starting from one side of multiple frequency bands arranged sequentially from the high-frequency side to the low-frequency side, the frequency difference determination unit 60 sequentially determines whether the frequency difference is below the threshold, and starting from the other side, the frequency difference determination unit 60 sequentially determines whether the frequency difference is below the threshold, thereby determining the boundary. Figure 3 Taking the nine frequency bands B1 to B9 as an example, the frequency difference determination unit 60 determines that the frequency difference for frequency band B1 exceeds the threshold, and then determines that the frequency difference for frequency band B2 is below the threshold. Next, the frequency difference determination unit 60 determines that the frequency difference for frequency band B9 exceeds the threshold, and then determines that the frequency difference for frequency band B8 is below the threshold. Based on these determination results, it can be seen that frequency bands B2 and B8 are located at the boundary.

[0097] The third method for determining the boundary is as follows: Starting from one side of a plurality of frequency bands arranged sequentially from the high-frequency side to the low-frequency side, the frequency difference determination unit 60 sequentially determines whether the frequency difference is below a threshold, thereby determining one boundary. Then, the frequency difference determination unit 60 determines whether the frequency difference is below a threshold before and after a predetermined number of frequency bands preceding the frequency band located at the boundary, thereby determining another boundary. Figure 3 Taking the nine frequency bands B1 to B9 as an example, the frequency difference determination unit 60 determines that the frequency difference for frequency band B1 exceeds the threshold, and then determines that the frequency difference for frequency band B2 is below the threshold. Therefore, frequency band B2 is located at a boundary. Next, the frequency difference determination unit 60 determines whether the frequency difference before and after, for example, five frequency bands B7 preceding frequency band B2, is below the threshold. That is, when the frequency difference determination unit 60 determines that the frequency difference for frequency band B7 is below the threshold, it then determines that the frequency difference for the preceding frequency band B8 is below the threshold, and finally determines that the frequency difference for frequency band B9 exceeds the threshold. Therefore, frequency band B8 is located at another boundary. Furthermore, when the frequency difference determination unit 60 determines that the frequency difference for frequency band B7 exceeds the threshold, it determines whether the frequency difference is below the threshold in the order of the preceding frequency bands B6, B5, ...

[0098] The first method for selecting a preferred frequency band is to choose any preferred frequency band from multiple frequency bands based on two boundaries (the high-frequency side boundary and the low-frequency side boundary). When using... Figure 3 Taking the nine frequency bands B1 to B9 as an example, a frequency band that is sufficiently far away from either one boundary (frequency band B2) or the other boundary (frequency band B8) is selected, which can sufficiently ensure the VT drift margin. Preferably, frequency band B5, located in the middle between the two boundaries, is selected.

[0099] The second method for selecting a preferred frequency band is to select any preferred frequency band from multiple frequency bands based on either of two boundaries (the boundary on the high-frequency side and the boundary on the low-frequency side). When using... Figure 3 Taking the nine frequency bands B1 to B9 as an example, a frequency band is selected that is sufficiently far from either one boundary (frequency band B2) or the other boundary (frequency band B8) to adequately ensure the VT drift margin. Furthermore, in methods 1 to 3 for determining the aforementioned boundaries, two boundaries (B2 and B8) are determined. However, it is also possible to determine only one boundary by combining this method with method 2 for selecting the preferred frequency band.

[0100] As described above, the PLL circuit 1 of this embodiment can more appropriately set the FV characteristics of the voltage-controlled oscillator 40.

[0101] The above description addresses the use of an LC-VCO as a voltage-controlled oscillator. However, the present invention can also be applied to... Figure 1 The PLL circuit 1 shown uses a voltage-controlled oscillator that includes a ring oscillator. This ring oscillator is constructed by connecting multiple delay elements in a loop, each having a delay set according to the input control voltage value VC. This voltage-controlled oscillator utilizes the oscillation phenomenon of the ring oscillator to output an oscillating signal with a frequency corresponding to the control voltage value VC. Furthermore, by selecting any frequency band from a plurality of frequency bands, the frequency-to-voltage (FV) characteristic of this voltage-controlled oscillator is variable.

[0102] Generally speaking, compared to the LC-VCO described above, the voltage-controlled oscillator incorporating a ring oscillator has a steeper slope in its FV characteristic, making it easier to adequately ensure the VT drift margin. On the other hand, the voltage-controlled oscillator incorporating a ring oscillator tends to increase jitter during high-speed operation. This voltage-controlled oscillator is preferred because it can apply a larger SS in systems with relatively large jitter around several Gbps.

[0103] Figure 7 This is a circuit example diagram illustrating a voltage-controlled oscillator 40A. The voltage-controlled oscillator 40A is capable of... Figure 1In the PLL circuit 1 shown, the voltage-controlled oscillator 40 is used instead. In the circuit example shown in the figure, the voltage-controlled oscillator 40A includes a ring oscillator RO, a current mirror circuit CM, a current bank circuit CB, and an NMOS transistor M30 as a control switch.

[0104] The ring oscillator RO has a structure in which multiple (seven in this figure) delay elements D1 to D7 are connected in a ring. The delay elements D1 to D7 can be an inverter circuit or a differential buffer. The drive current I applied from the current mirror circuit CM is used... RO To set the delay of each delay element D1 to D7.

[0105] The current mirror circuit CM includes PMOS transistors M33 and M34, amplifier A30, capacitor C30, and resistor R30. The sources of PMOS transistors M33 and M34 are respectively connected to the input power supply voltage VDD. The drain of PMOS transistor M33 is connected to the non-inverting input terminal of amplifier A30. The drain of PMOS transistor M34 is connected to the inverting input terminal of amplifier A30, and both apply drive currents to the delay elements D1-D7 of the ring oscillator RO. The output terminal of amplifier A30 is connected to the gates of PMOS transistors M33 and M34, and further connected to the drain of PMOS transistor M33 via capacitor C30 and resistor R30.

[0106] The current-group circuit CB comprises multiple (three in this figure) units U1 to U3 arranged in parallel. Each unit includes a switch SW 30, an NMOS transistor M31, an NMOS transistor M32, a capacitor C31, and a capacitor C32. The drain of NMOS transistor M31 is connected to the drain of PMOS transistor M33 via switch SW 30. The source of NMOS transistor M31 is connected to the drain of NMOS transistor M32. The source of NMOS transistor M32 is set to ground potential. One end of capacitor C31 is connected to the gate of NMOS transistor M31, and the other end of capacitor C31 is set to ground potential. One end of capacitor C32 is connected to the gate of NMOS transistor M32, and the other end of capacitor C32 is set to ground potential. The gate of NMOS transistor M31 is biased by voltage VB1. The gate of NMOS transistor M32 is biased by voltage VB2. The on / off state of switch SW 30 in each unit U1 is set according to the value of the FV characteristic control signal.

[0107] The drain of NMOS transistor M30, which acts as a control switch, is connected to the drain of PMOS transistor M33. The source of NMOS transistor M30 is set to ground potential. The gate of NMOS transistor M30 is input with a control voltage value VC.

[0108] In this voltage-controlled oscillator 40A, the FV characteristic control signal is used to set the on / off state of the 3-bit switch SW 30 of the current bank circuit CB, thereby setting the amount I of the current flowing through the current bank circuit CB. DIG Through this current quantity I DIG The setting determines the amount of current I flowing through the PMOS transistors M33 and M34 in the current mirror circuit CM. RO Set the amount I of the drive current applied from the drain of PMOS transistor M34 to the delay elements D1 to D7 of the ring oscillator RO. RO Therefore, the frequency band is selected.

[0109] Furthermore, in the voltage-controlled oscillator 40A, the amount of current I flowing through the NMOS transistor M30 is adjusted by using the control voltage VC applied to the gate of the NMOS transistor M30, which serves as a control switch. ANA By adjusting this current I ANA Adjust the amount I of the drive current applied to the delay elements D1 to D7 of the ring oscillator RO respectively. RO Therefore, the oscillation frequency is adjusted to correspond to the control voltage value VC.

[0110] Furthermore, the PLL circuit of this embodiment can be applied to display interfaces used in display devices such as television receivers and monitor devices, and camera interfaces used in imaging devices such as cameras and camcorders, which transmit high-resolution image signals. Generally, in electronic devices using the image transmission interface described above, metal coverings are not used to reduce weight, and electromagnetic shielding of the substrate and cables is not feasible to control overall cost. Therefore, in order to reduce the impact of electromagnetic waves on the human body and surrounding electronic devices, an SS clock with a modulation strength (±1% or more) that is larger than that of other communication interfaces is required. Since the FV characteristics of the PLL circuit and voltage-controlled oscillator of this embodiment can be set more appropriately, even when applied to the image transmission interface described above, an SS clock with a modulation strength (±1% or more) that is larger than that of other communication interfaces can be generated to reduce the impact of electromagnetic waves on the human body and surrounding electronic devices.

[0111] As explained above, Figure 1The PLL circuit shown includes: a phase comparator 10 having a first input terminal and a second input terminal for input signals; a charge pump 20 having an input terminal connected to the output terminal of the phase comparator 10; a loop filter 30 (low-pass filter) having an input terminal connected to the output terminal of the charge pump 20; a voltage-controlled oscillator 40 having an input terminal connected to the output terminal of the loop filter 30; and a capacitor bank for resonance. Figure 2 The system includes: a capacitor bank (Cbank) and capacitors C11, C12, C21, C22, and a control terminal for the capacitance value of the capacitor bank (a terminal for receiving signals from the FV characteristic adjustment unit 70); a frequency divider 50 having an input terminal connected to the output terminal of the voltage-controlled oscillator 40 and an output terminal connected to the second input terminal; a frequency difference detector (frequency difference determination unit 60) having a first input terminal and a second input terminal connected to the first input terminal and the second input terminal of the phase comparator 10, respectively; and a capacitance adjuster (FV characteristic adjustment unit 70) having an input terminal connected to the output terminal of the frequency difference detector and an output terminal connected to the aforementioned control terminal for the capacitance value of the voltage-controlled oscillator 40.

[0112] Frequency difference determination unit 60 ( Figure 5 The frequency difference detector includes a phase difference detector. More specifically, a slip-edge detector (137) is connected to the output terminal of the frequency difference detector, and a counter (144) is connected to the output terminal of the slip-edge detector. Based on the output of the counter (144), the capacitor regulator outputs a multi-bit (3 bits in the example above) digital signal according to the algorithm described above, controlling the opening and closing of the switch for capacitor adjustment. The capacitor regulator can, for example, be constructed from an 8-bit microcomputer (logic circuit) with a memory storing the algorithm described above.

[0113] Figure 2 The voltage-controlled oscillator 40 shown is an LC-VCO, therefore it includes an LC energy storage (tank) circuit. That is, the inductor L resonates with the capacitor bank shown in the figure, forming an LC resonator (LC energy storage circuit). The capacitance value (combined capacitance value) C of the capacitors that contribute to resonance within the voltage-controlled oscillator 40 determines the inductance value L of the inductor L and the resonant frequency. In a typical LC circuit, the resonant frequency f = 1 / (2π(LC)) 0.5Therefore, if switches SW0, SW1, and SW2 are controlled, and the combined capacitor value C is controlled, the resonant frequency of the VCO's output signal (oscillation signal) can be controlled.

[0114] Figure 7 The voltage-controlled oscillator 40A(40) shown includes a ring oscillator RO, the resonant frequency of which depends on the capacitance value (combined capacitance value) of the capacitor that contributes to resonance in the current bank circuit CB. If the switch SW 30 is controlled and the combined capacitance value C in the current bank circuit CB is controlled, the resonant frequency of the VCO output signal (oscillation signal) can be controlled.

Claims

1. A PLL circuit, comprising: A voltage-controlled oscillator, comprising an inductor and a capacitor, utilizes the resonance phenomenon caused by these inductors and capacitors to output an oscillating signal having a frequency corresponding to the input control voltage value. By selecting any frequency band from a plurality of frequency bands, the FV characteristic between the frequency and the control voltage value is made variable. A phase comparator is input with an oscillation signal output from the voltage-controlled oscillator or a signal obtained by dividing the oscillation signal as a feedback oscillation signal, and is also input with an input signal. It detects the phase difference between these feedback oscillation signals and the input signal and outputs a phase difference signal representing the phase difference. A charge pump is input to a phase difference signal output from the phase comparator and outputs a charging / discharging current corresponding to the phase difference represented by the phase difference signal. A loop filter, which is input with the charging and discharging current output from the charge pump, outputs a control voltage value to the voltage-controlled oscillator that increases or decreases according to the amount of charging and discharging of the charging and discharging current; The frequency difference determination unit is input to the feedback oscillation signal and the input signal, and determines whether the frequency difference between the feedback oscillation signal and the input signal is below a threshold. The FV characteristic adjustment unit selects a frequency band of the voltage-controlled oscillator to adjust the FV characteristic based on the boundary between a frequency band determined by the frequency difference determination unit to have a frequency difference below the threshold and a frequency band determined by the frequency difference determination unit to have a frequency difference exceeding the threshold, which are among the multiple frequency bands that can be set in the voltage-controlled oscillator.

2. The PLL circuit according to claim 1, wherein, The FV characteristic adjustment unit selects any frequency band from the plurality of frequency bands to adjust the FV characteristic based on both the boundary on the high-frequency side and the boundary on the low-frequency side.

3. The PLL circuit according to claim 1, wherein, The FV characteristic adjustment unit selects any frequency band from the plurality of frequency bands to adjust the FV characteristic based on either the boundary on the high-frequency side or the boundary on the low-frequency side.

4. A PLL circuit, comprising: A voltage-controlled oscillator includes a ring oscillator constructed by connecting multiple delay elements in a ring with a delay set according to an input control voltage value. Utilizing the oscillation phenomenon of the ring oscillator, an oscillation signal with a frequency corresponding to the input control voltage value is output. By selecting any frequency band from multiple frequency bands, the FV characteristic between the frequency and the control voltage value is made variable. A phase comparator is input with an oscillation signal output from the voltage-controlled oscillator or a signal obtained by dividing the oscillation signal as a feedback oscillation signal, and is also input with an input signal. It detects the phase difference between these feedback oscillation signals and the input signal and outputs a phase difference signal representing the phase difference. A charge pump is input to a phase difference signal output from the phase comparator and outputs a charging / discharging current corresponding to the phase difference represented by the phase difference signal. A loop filter, which is input with the charging and discharging current output from the charge pump, outputs a control voltage value to the voltage-controlled oscillator that increases or decreases according to the amount of charging and discharging of the charging and discharging current; The frequency difference determination unit is input to the feedback oscillation signal and the input signal, and determines whether the frequency difference between the feedback oscillation signal and the input signal is below a threshold. The FV characteristic adjustment unit selects a frequency band of the voltage-controlled oscillator to adjust the FV characteristic based on the boundary between a frequency band determined by the frequency difference determination unit to have a frequency difference below the threshold and a frequency band determined by the frequency difference determination unit to have a frequency difference exceeding the threshold, which are among the multiple frequency bands that can be set in the voltage-controlled oscillator.

5. The PLL circuit according to claim 4, wherein, The FV characteristic adjustment unit selects any frequency band from the plurality of frequency bands to adjust the FV characteristic based on both the boundary on the high-frequency side and the boundary on the low-frequency side.

6. The PLL circuit according to claim 4, wherein, The FV characteristic adjustment unit selects any frequency band from the plurality of frequency bands to adjust the FV characteristic based on either the boundary on the high-frequency side or the boundary on the low-frequency side.

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