Semiconductor structure and mask structure

Abstract

This application belongs to the field of semiconductor manufacturing technology, specifically relating to a semiconductor structure and mask structure to solve the problem of reduced contact area between the capacitor plug and the active region in related technologies, which affects the performance of the semiconductor structure. The substrate has an active region and multiple parallel and spaced bit line structures disposed within the substrate. Multiple word line structures are disposed parallel and spaced on the substrate, intersecting with the bit line structures and forming multiple grids arranged in an array on the substrate. The capacitor plug is located within the grid, and its projection on the substrate covers a portion of the active region. In a cross-section parallel to the substrate surface, the cross-sectional shape of the capacitor plug is arc-shaped. With a certain distance between the capacitor plug and the bit line structures, compared to a rectangular cross-section capacitor plug, the arc-shaped cross-section increases the contact area between the capacitor plug and the active region, which is beneficial for improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a mask structure. Background Technology

[0002] With the gradual development of storage device technology, Dynamic Random Access Memory (DRAM) has been increasingly used in various electronic devices due to its high density and fast read / write speed. DRAM consists of many repeating memory cells. Each memory cell typically includes a capacitor structure and a transistor structure. The gate of the transistor structure is connected to the word line, one end of the transistor structure is connected to the bit line, and the other end of the transistor structure is connected to the capacitor structure.

[0003] In related technologies, the transistor structure is disposed within a substrate, and the capacitor structure is connected to one end of the transistor via a capacitor plug, thereby enabling the reading and writing of data information in the capacitor structure by switching the transistor. The projection shape of the capacitor plug on the substrate is typically rectangular. However, as the integration density of integrated circuits increases, the size of the capacitor plug also shrinks, leading to a reduction in the contact area between the capacitor plug and the active region, which affects the performance of the semiconductor structure. Summary of the Invention

[0004] This application provides a semiconductor structure and a mask structure that can solve the problem of reduced contact area between capacitor plugs and active regions in related technologies, which affects the performance of semiconductor structures.

[0005] According to some embodiments, a first aspect of this application provides a semiconductor structure, including:

[0006] A substrate having an active region and word line structures therein, with a plurality of word line structures arranged in parallel and spaced apart within the substrate;

[0007] Bit line structure, wherein multiple bit line structures are arranged parallel and spaced apart on the substrate, and word line structures intersect with the bit line structures and surround multiple grids arranged in an array on the substrate;

[0008] A capacitor plug is located within the grid, and the projection of the capacitor plug on the substrate covers a portion of the active region. In a cross-section parallel to the surface of the substrate, the cross-sectional shape of the capacitor plug is arc-shaped.

[0009] In one possible implementation, the grid includes a first grid located on one side of the bit line structure and a second grid located on the other side of the bit line structure, and the capacitor plug includes a first plug located in the first grid and a second plug located in the second grid;

[0010] In a cross section parallel to the surface of the substrate, the first plug has a first arc, and the second plug has a second arc, with the first arc and the second arc located within the same circle.

[0011] In one possible implementation, the centers of the first arc and the second arc are located on the center line of the bit line structure.

[0012] In one possible implementation,

[0013] There is a first distance between the center lines of any two adjacent word line structures in a direction parallel to the substrate surface, and there is a second distance between the center lines of any two adjacent bit line structures in a direction parallel to the substrate surface;

[0014] The radii of the first arc and the second arc are greater than half of the first distance, and the radii of the first arc and the second arc are less than half of the positive square root of the sum of the squares of the first distance and the second distance.

[0015] In one possible implementation, the first plug has a first cleavage in its cross-section, and the second plug has a second cleavage in its cross-section, the first cleavage and the second cleavage being parallel to the extension direction of the bit line structure.

[0016] In one possible implementation, the projections of the lengths of the first secant and the second secant onto the substrate both cover a portion of the word line structure.

[0017] According to some embodiments, a second aspect of this application also provides a mask structure, the mask including a mask assembly having a mask pattern, the mask assembly being used to cover a semiconductor structure so as to form capacitor plugs on the semiconductor structure through the mask assembly;

[0018] The semiconductor structure includes a substrate, a plurality of parallel and spaced bit line structures disposed within the substrate, and a plurality of parallel and spaced word line structures disposed on the substrate. The substrate has an active region, and the word line structures intersect with the bit line structures and are arranged in a plurality of grids arrayed on the substrate.

[0019] The capacitor plug is located within the grid, and the projection of the capacitor plug on the substrate covers a portion of the active region. In a cross-section parallel to the surface of the substrate, the cross-sectional shape of the capacitor plug is arc-shaped.

[0020] In one possible implementation, the mask assembly includes a first mask plate and a second mask plate. The first mask plate has a plurality of arrayed first hole groups. The first hole groups include first etched holes and second etched holes arranged opposite to each other. The first etched holes and the second etched holes are both arc-shaped. The first etched holes and the second etched holes are used to form the capacitor plugs on both sides of the bit line structure.

[0021] The second mask has a plurality of arrayed second hole groups, the second hole group including a third etched hole and a fourth etched hole arranged opposite to each other, the third etched hole and the fourth etched hole are both arc-shaped, the third etched hole and the fourth etched hole are used to form the capacitor plugs on both sides of the bit line structure;

[0022] The projection of the second etched hole on the substrate is located outside the projection of the first etched hole on the substrate.

[0023] In one possible implementation, the projections of the first and second hole groups onto the substrate are alternately arranged.

[0024] In one possible implementation, the centers of the arcs corresponding to the first etched hole, the second etched hole, the third etched hole, and the fourth etched hole are all located on the center line of the bit line structure.

[0025] In one possible implementation, there is a first distance between the center lines of any two adjacent word line structures in a direction parallel to the substrate surface, and a second distance between the center lines of any two adjacent bit line structures in a direction parallel to the substrate surface.

[0026] The radius of the corresponding arcs of the first etched hole, the second etched hole, the third etched hole, and the fourth etched hole is greater than half of the first distance. The radius of the corresponding arcs of the first etched hole, the second etched hole, the third etched hole, and the fourth etched hole is less than half of the positive square root of the sum of the squares of the first distance and the second distance. The secant lines of the first etched hole, the second etched hole, the third etched hole, and the fourth etched hole are all parallel to the extension direction of the bit line structure. The projections of the first etched hole, the second etched hole, the third etched hole, and the fourth etched hole on the substrate all cover part of the word line structure.

[0027] In one possible implementation, the mask assembly includes a first mask plate and a second mask plate, wherein the first mask plate has a plurality of arrayed first mask holes and the second mask plate has a plurality of arrayed second mask holes, both the first mask holes and the second mask holes being arc-shaped;

[0028] The projection of the first mask hole on the substrate is located on one side of the bit line structure, and the projection of the corresponding second mask hole on the substrate is located on the other side of the bit line structure.

[0029] In one possible implementation, the centers of the corresponding arcs of the first mask aperture and the corresponding second mask aperture coincide.

[0030] In one possible implementation, the centers of the corresponding arcs of the first and second mask holes are located on the center line of the bit line structure.

[0031] In one possible implementation, there is a first distance between the center lines of any two adjacent word line structures in a direction parallel to the substrate surface, and a second distance between the center lines of any two adjacent bit line structures in a direction parallel to the substrate surface.

[0032] The radius of the corresponding arc of the first mask hole and the second mask hole is greater than half of the first distance, the radius of the corresponding arc of the first mask hole and the second mask hole is less than half of the positive square root of the sum of the squares of the first distance and the second distance, the secant lines of the first mask hole and the second mask hole are parallel to the extension direction of the bit line structure, and the projections of the first mask hole and the second mask hole on the substrate cover part of the word line structure.

[0033] The semiconductor structure and mask structure provided in this application embodiment have an active region and bit line structures within the substrate. Multiple bit line structures are arranged parallel and spaced apart within the substrate, and multiple word line structures are arranged parallel and spaced apart on the substrate. The word line structures intersect with the bit line structures and form multiple grids arranged in an array on the substrate. A capacitor plug is located within the grid, and the projection of the capacitor plug onto the substrate covers a portion of the active region. In a cross-section parallel to the substrate surface, the cross-sectional shape of the capacitor plug is arc-shaped. With a certain distance between the capacitor plug and the bit line structures, compared to a rectangular cross-section capacitor plug, the arc-shaped cross-section increases the contact area with the active region, which is beneficial for improving the performance of the semiconductor structure. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A top view of a semiconductor structure provided in an embodiment of this application;

[0036] Figure 2 A partial enlarged view of point A of a semiconductor structure provided in an embodiment of this application;

[0037] Figure 3 A partial enlarged view of section B of a semiconductor structure provided in an embodiment of this application;

[0038] Figure 4 A schematic diagram of the structure of a first mask plate provided in an embodiment of this application. Figure 1 ;

[0039] Figure 5 A schematic diagram of the structure of a second mask plate provided in an embodiment of this application. Figure 1 ;

[0040] Figure 6 A schematic diagram of a mask pattern composed of a first mask and a second mask provided in an embodiment of this application. Figure 1 ;

[0041] Figure 7 A schematic diagram of the structure of a first mask plate provided in an embodiment of this application. Figure 2 ;

[0042] Figure 8 A schematic diagram of the structure of a second mask plate provided in an embodiment of this application. Figure 2 ;

[0043] Figure 9 A schematic diagram of a mask pattern composed of a first mask and a second mask provided in an embodiment of this application. Figure 2 . Detailed Implementation

[0044] To clearly understand the technical solution of this application, the solutions of related technologies will be described in detail first.

[0045] Dynamic Random Access Memory (DRAM) consists of many repeating memory cells. Each memory cell typically includes a capacitor structure and a transistor structure. The capacitor structure and the transistor structure are connected to each other so that data stored in the capacitor structure can be read from or written to the capacitor structure via the transistor structure. The gate of the transistor structure is connected to the word line, one end of the transistor structure is connected to the bit line, and the other end of the transistor structure is connected to the capacitor structure.

[0046] In related technologies, a transistor structure is disposed within a substrate, with one end of a capacitor structure connected to it, thereby enabling the reading and writing of data information in the capacitor structure via switching transistors. The projection shape of the capacitor plug on the substrate is typically rectangular. However, with technological advancements, the integration requirements for memory are becoming increasingly stringent, leading to a reduction in the size of the capacitor plug. This, in turn, reduces the contact area between the capacitor plug and the active region, impacting the performance of the semiconductor structure.

[0047] In view of this, embodiments of this application provide a semiconductor structure and a mask structure, wherein the projection of the capacitor plug on the substrate covers a portion of the active region, and the cross-sectional shape of the capacitor plug is arc-shaped in a section parallel to the substrate surface. When there is a certain distance between the capacitor plug and the bit line structure, compared to a rectangular cross-section capacitor plug, the arc-shaped cross-section capacitor plug has a larger contact area with the active region, which is beneficial for improving the performance of the semiconductor structure.

[0048] The following describes several alternative implementations of this application with reference to the accompanying drawings. Those skilled in the art should understand that the following implementations are merely illustrative and not an exhaustive list. Based on these implementations, those skilled in the art may replace, splice, or combine certain features or examples, and these should still be considered as the disclosure of this application.

[0049] For example, the semiconductor structure in this embodiment can be DRAM (Dynamic Random Access Memory). Of course, this embodiment is not limited to this, and the semiconductor structure in this embodiment can also be other structures.

[0050] like Figure 1 As shown ( Figure 1 (The dashed lines in the figure represent the projection of the active area covered by the word line structure). The semiconductor structure provided in this embodiment includes a substrate 10, a word line structure 30, a bit line structure 20, and a capacitor plug 40.

[0051] The substrate 10 may be made of monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound, or silicon-on-insulator, or other materials known to those skilled in the art. The substrate 10 has active regions and word line structures 30. The active regions are arranged in an array. An isolation structure may also be disposed within the substrate 10, located around the active regions to isolate adjacent active regions. The active regions may be made of silicon, and the isolation structure may be made of silicon oxide.

[0052] Multiple word line structures 30 are disposed parallel to each other and spaced apart within the substrate 10. In this embodiment, the word line structure 30 can be a buried word line, which intersects with the active region and extends along a surface parallel to the substrate 10. The buried word line may include a word line conductive layer and a gate electrode layer, with the gate electrode layer located in the region where the buried word line intersects with the active region, and the word line conductive layer located in other regions of the buried word line.

[0053] Multiple bit line structures 20 are arranged parallel to each other and spaced apart on the substrate 10. The word line structures 30 intersect with the projections of the bit line structures 20 onto the substrate and form multiple grids 11 arranged in an array on the substrate 10. In this embodiment, for example, the extending direction of the bit line structures 20 is perpendicular to the extending direction of the word line structures 30, that is, the multiple grids 11 formed by the word line structures 30 and the bit line structures 20 are rectangular.

[0054] The capacitor plug 40 is located within the grid 11. The projection of the capacitor plug 40 onto the substrate 10 covers a portion of the active region. The capacitor plug 40 extends along a direction perpendicular to the surface of the substrate 10 until it engages with the active region, allowing the capacitor structure to connect to the active region via the capacitor plug 40, thereby achieving the purpose of storing or retrieving data information within the capacitor structure. In a cross-section parallel to the surface of the substrate 10, the cross-sectional shape of the capacitor plug 40 is arc-shaped to increase the distance between the capacitor plug 40 and the adjacent bit line structure 20, reducing the parasitic capacitance generated between the capacitor plug 40 and the bit line structure 20, thus preventing leakage.

[0055] The semiconductor structure provided in this embodiment has an active region within a substrate 10. Multiple bit line structures 20 are arranged parallel and spaced apart on the substrate 10, and multiple word line structures 30 are also arranged parallel and spaced apart on the substrate 10. The word line structures 30 intersect with the bit line structures 20 and form multiple grids 11 arrayed on the substrate 10. A capacitor plug 40 is located within the grids 11. The projection of the capacitor plug 40 onto the substrate 10 covers a portion of the active region. In a cross-section parallel to the surface of the substrate 10, the cross-sectional shape of the capacitor plug 40 is arc-shaped. When the distance between the capacitor plug 40 and the bit line structures 20 is the same, compared to a rectangular cross-section capacitor plug 40, the arc-shaped cross-section increases the contact area with the active region, which is beneficial for improving the performance of the semiconductor structure.

[0056] Please refer to Figure 1 and Figure 2The grid 11 includes a first grid 113 located on one side of the bit line structure 20 and a second grid 115 located on the other side of the bit line structure 20. The capacitor plug 40 includes a first plug 41 located in the first grid 113 and a second plug 42 located in the second grid 115. In a cross section parallel to the surface of the substrate 10, the cross section of the first plug 41 has a first arc 413 and the cross section of the second plug 42 has a second arc 423. The first arc 413 and the second arc 423 are located in the same circle.

[0057] like Figure 1 and Figure 2 As shown, the first grid 113 and the second grid 115 are arranged in an array. Specifically, in the direction parallel to the extension direction of the bit line structure 20 and parallel to the surface of the substrate 10, the first grid 113 and the second grid 115 are alternately arranged; in the direction perpendicular to the extension direction of the bit line structure 20 and parallel to the surface of the substrate 10, the first grid 113 and the second grid 115 are still alternately arranged. The first plug 41 is located within the first grid 113, and the second plug 42 is located within the second grid 115, such that the first plug 41 and the second plug 42 are also alternately arranged in the above two directions. The cross-section of the first plug 41 has a first arc 413 and a first secant 415 connected to the first arc 413, and the cross-section of the second plug 42 has a second arc 423 and a second secant 425 connected to the second arc 423.

[0058] Continue to refer to Figure 2 For the same position line structure 20, if the distance between the arc of the first plug 41 and the position line structure 20 is less than the distance between the secant of the first plug 41 and the position line structure 20, then the distance between the secant of the second plug 42 and the position line structure 20 is less than the distance between the arc of the second plug 42 and the position line structure 20. The center of the first arc 413 coincides with the center of the second arc 423, that is, the first arc 413 and the second arc 423 are located within the same circle.

[0059] Optionally, the centers of the first arc 413 and the second arc 423 are located on the center line of the bit line structure 20. For example, the first arc 413 and the second arc 423 are equidistant from the center line of the bit line structure 20; that is, the distance between the first arc 413 and its adjacent bit line structure 20 is equal to the distance between the second arc 423 and its adjacent bit line structure 20. When the size of the conductive plug 40 is further reduced, the center positions of the first arc 413 and the second arc 423 remain unchanged, which helps to further increase the distance between the capacitor plug 40 and the adjacent bit line structure 20, thereby further preventing leakage.

[0060] Please refer to Figure 1 and Figure 3Optionally, the center lines of any two adjacent bit line structures 20 have a first distance L1 in a direction parallel to the surface of the substrate 10, and the center lines of any two adjacent word line structures 30 have a second distance L2 in a direction parallel to the surface of the substrate 10.

[0061] It should be noted that the projection of the capacitor plug 40 onto the substrate 10 can cover a portion of the active region. This portion of the active region covered by the capacitor plug 40 is considered an effective region, while the portion not covering the active region is considered an ineffective region. For example, the radii R of the first arc 413 and the second arc 423 are greater than half the first distance L1, ensuring that the capacitor plug 40 has a sufficient effective region to guarantee its connection to the active region, thereby facilitating the connection of the capacitor structure to the active region via the capacitor plug 40. The radii R of the first arc 413 and the second arc 423 are less than half the positive square root of the sum of the squares of the first distance L1 and the second distance L2. Figure 3 As shown, the distance between the center B1 on one side of the word line structure 30 and the center B2 on the other side of the word line structure 30 is the positive square root of the sum of the squares of the first distance L1 and the second distance L2. Half of the positive square root of the sum of the squares of the first distance L1 and the second distance L2 is the distance L3. The radius R of the first arc 413 and the second arc 423 is less than the distance L3 to prevent the capacitor plugs 40 on both sides of the word line structure 30 from overlapping due to the excessive radius R.

[0062] Optionally, the first plug 41 has a first cleavage 415 in its cross-section, and the second plug 42 has a second cleavage 425 in its cross-section. The first cleavage 415 and the second cleavage 425 are parallel to the extending direction of the bit line structure 20. For example, the first cleavage 415 and the second cleavage 425 are located on both sides of the bit line structure 20, and the first cleavage 415 and the second cleavage 425 are parallel to the extending direction of the bit line structure 20.

[0063] Optionally, the projections of the first cleaving line 415 and the second cleaving line 425 onto the substrate 10 cover a portion of the word line structure 30 so that the capacitor plug 40 has a sufficient effective area, thereby ensuring that the capacitor plug 40 can be connected to the active region, which in turn facilitates the connection of the capacitor structure to the active region through the capacitor plug 40.

[0064] This application also provides a mask structure, which includes a mask assembly having a mask pattern. The mask assembly is used to cover a semiconductor structure to form a capacitor plug on the semiconductor structure. In one possible implementation, the mask assembly can be placed on the semiconductor structure, and the semiconductor structure opposite to the mask pattern can be removed by an etching process, thereby forming a groove in the semiconductor structure. The groove is then filled with a conductive material to form a capacitor plug.

[0065] For example, the semiconductor structure in this embodiment can be DRAM (Dynamic Random Access Memory). Of course, this embodiment is not limited to this, and the semiconductor structure in this embodiment can also be other structures.

[0066] In this embodiment, the semiconductor structure includes a substrate, a plurality of parallel and spaced bit line structures disposed on the substrate, and a plurality of parallel and spaced word line structures disposed on the substrate. The substrate has an active region and word line structures, the bit line structures are disposed on the substrate, the word line structures and bit line structures intersect and surround a plurality of grids arranged in an array on the substrate.

[0067] The substrate may be made of monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound, or silicon-on-insulator, or other materials known to those skilled in the art. The substrate contains active regions and word line structures. The active regions are arranged in an array. An isolation structure may also be disposed within the substrate, located around the active regions, to isolate adjacent active regions. The active regions may be made of silicon, and the isolation structure may be made of silicon oxide.

[0068] The word line structure can be a buried word line, which intersects with the active region and extends parallel to the substrate surface. The buried word line may include a word line conductive layer and a gate electrode layer. The gate electrode layer is located in the region where the buried word line intersects with the active region, and the word line conductive layer is located in other regions of the buried word line. The extension direction of the bit line structure can be perpendicular to the extension direction of the word line structure, meaning the multiple grids enclosed by the word line structure and the bit line structure are rectangular. It should be noted that the extension direction of the active region has a certain angle with the extension direction of the bit line structure so that the projection of the bit line structure onto the substrate also intersects with the active region.

[0069] The capacitor plug is located within the grid, and its projection on the substrate partially covers the active region. The plug extends along a direction perpendicular to the substrate surface and engages with the active region, allowing the capacitor structure to connect to the active region via the plug, thereby achieving the purpose of storing or retrieving data information within the capacitor structure. In a cross-section parallel to the substrate surface, the capacitor plug has an arc-shaped cross-section to increase the distance between the plug and adjacent bitline structures, reducing parasitic capacitance between the plug and the bitline structures and thus preventing leakage.

[0070] The mask structure provided in this embodiment includes a mask assembly with a mask pattern. The mask assembly is used to cover a semiconductor structure to form capacitor plugs on the semiconductor structure. The capacitor plugs are located within a grid formed by word line structures and bit line structures. The projection of the capacitor plugs onto the substrate covers a portion of the active region. In a cross-section parallel to the substrate surface, the cross-sectional shape of the capacitor plugs is arc-shaped. When there is a certain distance between the capacitor plugs and the bit line structures, compared to capacitor plugs with rectangular cross-sections, the contact area between the arc-shaped capacitor plugs and the active region is increased, which is beneficial to improving the performance of the semiconductor structure.

[0071] like Figure 4 and Figure 5 As shown, in one possible implementation, the mask assembly may include a first mask 50 and a second mask 60. By overlapping the first mask 50 and the second mask 60, a mask pattern can be formed. Using the first mask 50 and the second mask 60, capacitor plugs can be formed through a double patterning process, which helps to improve process accuracy and ensure the working performance of the semiconductor structure.

[0072] The first mask plate 50 has a plurality of arrayed first hole groups 51. The first hole group 51 includes a first etched hole 513 and a second etched hole 515 arranged opposite to each other. The first etched hole 513 and the second etched hole 515 are both arc-shaped. The first etched hole 513 and the second etched hole 515 are used to form capacitor plugs on both sides of the bit line structure.

[0073] The second mask plate 60 has a plurality of arrayed second hole groups 61. The second hole group 61 includes a third etched hole 613 and a fourth etched hole 615 arranged opposite to each other. The third etched hole 613 and the fourth etched hole 615 are both arc-shaped and are used to form capacitor plugs on both sides of the bit line structure. The centers of the corresponding circles of the first etched hole 513 and the second etched hole 515 coincide, that is, the first hole group 51 is located in the same circle; similarly, the centers of the corresponding circles of the third etched hole 613 and the fourth etched hole 615 also coincide, that is, the second hole group 61 is also located in the same circle.

[0074] Figure 6 A schematic diagram of a mask pattern composed of a first mask plate and a second mask plate is shown, wherein the dashed lines are the projections of the word line structure and the bit line structure in the mask pattern.

[0075] Reference Figure 4 , Figure 5 as well as Figure 6The projection of the second hole group 61 on the substrate is located outside the projection of the first hole group 51 on the substrate, so that the first hole group 51 and the second hole group 61 together form a mask pattern, and a capacitor plug is formed through the first hole group 51 and the second hole group 61.

[0076] Optionally, the projections of the first hole group 51 and the second hole group 61 onto the substrate are alternately arranged. For example, since the first hole group 51 is arranged in an array, the centers of four adjacent first hole groups 51 can form a rectangle. When the first hole group 51 overlaps with the second hole group 61, the center of the second hole group 61 is located at the center of the rectangle, so that both the first hole group 51 and the second hole group 61 can cover the grid formed by the word line structure 30 and the bit line structure 20, which is beneficial for the subsequent formation of capacitor plugs.

[0077] Optionally, the centers of the arcs corresponding to the first etched hole 513, the second etched hole 515, the third etched hole 613, and the fourth etched hole 615 are all located on the center line of the bit line structure 20. For example, the distances between the first etched hole 513 and the second etched hole 515 and the center line of the bit line structure 20 are the same; that is, the distance between the first etched hole 513 and its adjacent bit line structure 20 is equal to the distance between the second etched hole 515 and its adjacent bit line structure 20. When the size of the conductive plug is further reduced, the center positions of the arcs corresponding to the first etched hole 513, the second etched hole 515, the third etched hole 613, and the fourth etched hole 615 remain unchanged, which helps to further increase the distance between the capacitor plug and the adjacent bit line structure 20, thereby further preventing leakage. Similarly, the equivalence of the distances between the third etched hole 613 and the fourth etched hole 615 and the center line of the bit line structure 20, when the size of the conductive plug is further reduced, also helps to further increase the distance between the capacitor plug and the adjacent bit line structure 20, thereby further preventing leakage.

[0078] Optionally, the center lines of any two adjacent bit line structures 20 have a first distance L1 in a direction parallel to the substrate surface, and the center lines of any two adjacent word line structures 30 have a second distance L2 in a direction parallel to the substrate surface.

[0079] It should be noted that the projection of the capacitor plug onto the substrate can cover part of the active area. Such capacitor plugs that can cover part of the active area are considered effective areas, while capacitor plugs that cannot cover the active area are considered ineffective areas.

[0080] Optionally, the radius R of the corresponding arcs of the first etched hole 513, the second etched hole 515, the third etched hole 613 and the fourth etched hole 615 is greater than half of the first distance L1, so that the formed capacitor plug has a sufficient effective area, thereby ensuring that the capacitor plug can be connected to the active area, which in turn facilitates the connection of the capacitor structure to the active area through the capacitor plug.

[0081] Optionally, the radius R of the corresponding arcs of the first etched hole 513, the second etched hole 515, the third etched hole 613, and the fourth etched hole 615 is less than half the positive square root of the sum of the squares of the first distance and the second distance, such as... Figure 5 As shown, the distance between the center B1 on one side of the word line structure 30 and the center B2 on the other side of the word line structure 30 is the positive square root of the sum of the squares of the first distance L1 and the second distance L2. Half of the positive square root of the sum of the squares of the first distance L1 and the second distance L2 is the distance L3. The radius R is smaller than the distance L3 to prevent the capacitor plugs on both sides of the word line structure 30 from overlapping due to excessive radius.

[0082] Optionally, the cleavage lines of the first etched hole 513, the second etched hole 515, the third etched hole 613 and the fourth etched hole 615 are all parallel to the extension direction of the bit line structure 20. The parallelism of the cleavage lines to the extension direction of the bit line structure 20 helps to prevent the distance between the capacitor plug and the bit line structure 20 from decreasing, thereby avoiding leakage.

[0083] Optionally, the projections of the first etched hole 513, the second etched hole 515, the third etched hole 613, and the fourth etched hole 615 on the substrate cover a portion of the word line structure 30, so that the formed capacitor plug has a sufficient effective area, thereby ensuring that the capacitor plug can be connected to the active region, which in turn facilitates the connection of the capacitor structure to the active region through the capacitor plug.

[0084] like Figure 7 and Figure 8 As shown, in another possible implementation, the mask assembly may include a first mask 70 and a second mask 80. The first mask 70 has a plurality of arrayed first mask holes 71, and the second mask 80 has a plurality of arrayed second mask holes 81. Both the first mask holes 71 and the second mask holes 81 are arc-shaped. The projection of the first mask holes 71 onto the substrate is located on one side of the bit line structure, and the corresponding projection of the second mask holes 81 onto the substrate is located on the other side of the bit line structure. By overlapping the first mask 70 and the second mask 80, a mask pattern can be formed. Using the first mask 70 and the second mask 80, a capacitor plug can be formed through a double patterning process, which is beneficial to improving process accuracy and ensuring the working performance of the semiconductor structure.

[0085] For example, the first mask hole 71 has alternating first arc-shaped holes 713 and second arc-shaped holes 715. The first arc-shaped hole 713 has an arc and a secant line connecting to the arc, and the second arc-shaped hole 715 also has an arc and a secant line connecting to the arc. For the same position line structure, if the distance between the arc of the first arc-shaped hole 713 and the position line structure is less than the distance between the secant line of the first arc-shaped hole 713 and the position line structure, then the distance between the secant line of the second arc-shaped hole 715 and the position line structure is less than the distance between the arc of the second arc-shaped hole 715 and the position line structure. In the illustrated position, the first row of the first mask hole 71 is the first arc-shaped hole 713, the second row is the second arc-shaped hole 715, and so on, with the first arc-shaped holes 713 and the second arc-shaped holes 715 arranged alternately.

[0086] Similarly, the second mask hole 81 also has alternating third arc-shaped holes 813 and fourth arc-shaped holes 815. The third arc-shaped hole 813 has an arc and a secant line connecting to the arc, and the fourth arc-shaped hole 815 also has an arc and a secant line connecting to the arc. For the same position line structure, if the distance between the arc of the third arc-shaped hole 813 and the position line structure is less than the distance between the secant line of the third arc-shaped hole 813 and the position line structure, then the distance between the secant line of the fourth arc-shaped hole 815 and the position line structure is less than the distance between the arc of the fourth arc-shaped hole 815 and the position line structure. In the illustrated position, the first row of the second mask hole 81 is the third arc-shaped hole 813, the second row is the fourth arc-shaped hole 815, and so on, with the third arc-shaped holes 813 and fourth arc-shaped holes 815 arranged alternately.

[0087] Figure 9 A schematic diagram of another mask pattern composed of a first mask and a second mask is shown, wherein the dashed lines are the projections of the word line structure and the bit line structure in the mask pattern.

[0088] Optionally, the centers of the corresponding arcs of the first mask hole 71 and the corresponding second mask hole 81 coincide, that is, the first mask hole 71 and the corresponding second mask hole 81 are located in the same circle. When the size of the conductive plug is further reduced, the distance between the capacitor plug and the adjacent bit line structure 20 is further increased, thereby further avoiding leakage.

[0089] Optionally, the centers of the corresponding arcs of the first mask hole 71 and the second mask hole 81 are located on the center line of the bit line structure 20. For example, the first mask hole 71 and the second mask hole 81 are equidistant from the center line of the bit line structure 20. That is, the distance between the first mask hole 71 and its adjacent bit line structure is equal to the distance between the second mask hole 81 and its adjacent bit line structure 20. When the size of the conductive plug is further reduced, it is beneficial to further increase the distance between the capacitor plug and the adjacent bit line structure, thereby further avoiding leakage.

[0090] Optionally, the center lines of any two adjacent bit line structures 20 have a first distance L1 in a direction parallel to the substrate surface, and the center lines of any two adjacent word line structures 30 have a second distance L2 in a direction parallel to the substrate surface.

[0091] It should be noted that the projection of the capacitor plug onto the substrate can cover part of the active area. Such capacitor plugs that can cover part of the active area are considered effective areas, while capacitor plugs that cannot cover the active area are considered ineffective areas.

[0092] Optionally, the radius R of the arc corresponding to the first mask hole 71 and the second mask hole 81 is greater than half of the first distance L1, so that the formed capacitor plug has a sufficient effective area, thereby ensuring that the capacitor plug can be connected to the active region, which in turn facilitates the connection of the capacitor structure to the active region through the capacitor plug.

[0093] Optionally, the radius R of the arc corresponding to the first mask hole 71 and the second mask hole 81 is less than half the positive square root of the sum of the squares of the first distance L1 and the second distance L2, such as... Figure 9 As shown, the distance between the center B1 on one side of the word line structure 30 and the center B2 on the other side of the word line structure 30 is the positive square root of the sum of the squares of the first distance L1 and the second distance L2. Half of the positive square root of the sum of the squares of the first distance L1 and the second distance L2 is the distance L3. The radius R is smaller than the distance L3, which helps to prevent the capacitor plugs on both sides of the word line structure 30 from overlapping.

[0094] Optionally, both the first mask hole 71 and the second mask hole 81 are parallel to the extension direction of the bit line structure 20. The secant line is parallel to the extension direction of the bit line structure 20, which helps to prevent the distance between the capacitor plug and the bit line structure 20 from decreasing, thereby avoiding leakage.

[0095] Optionally, the projections of the first mask hole 71 and the second mask hole 81 on the substrate cover a portion of the word line structure 30 so that the formed capacitor plug has a sufficient effective area, thereby ensuring that the capacitor plug can be connected to the active region, which in turn facilitates the connection of the capacitor structure to the active region through the capacitor plug.

[0096] It is worth noting that, unlike the two implementation methods mentioned above, for different process technologies, all mask patterns can also be directly formed on the mask plate.

[0097] For example, the photomask has an array of etched holes, all of which are arc-shaped. Each etched hole may include two corresponding through-holes, used to form capacitor plugs on both sides of the bit line structure, with the two through-holes located within the same circle. The etched holes are also located on both sides of the word line structure to form capacitor plugs on both sides of the word line structure. Using this photomask, capacitor plugs can be formed in the semiconductor structure in a single pattern transfer process, which improves production efficiency.

[0098] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional modules is merely an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having an active region and word line structures therein, with a plurality of word line structures arranged in parallel and spaced apart within the substrate; Bit line structure, wherein multiple bit line structures are arranged parallel and spaced apart on the substrate, and word line structures intersect with the bit line structures and surround multiple grids arranged in an array on the substrate; A capacitor plug is located within the grid, and the projection of the capacitor plug on the substrate covers a portion of the active region. In a cross-section parallel to the surface of the substrate, the cross-sectional shape of the capacitor plug is arc-shaped.

2. The semiconductor structure according to claim 1, characterized in that, The grid includes a first grid located on one side of the bit line structure and a second grid located on the other side of the bit line structure, and the capacitor plug includes a first plug located in the first grid and a second plug located in the second grid; In a cross section parallel to the surface of the substrate, the first plug has a first arc, and the second plug has a second arc, with the first arc and the second arc located within the same circle.

3. The semiconductor structure according to claim 2, characterized in that, The centers of the first and second arcs are located on the center line of the bit line structure.

4. The semiconductor structure according to claim 3, characterized in that, There is a first distance between the center lines of any two adjacent bit line structures in a direction parallel to the substrate surface, and there is a second distance between the center lines of any two adjacent word line structures in a direction parallel to the substrate surface; The radii of the first arc and the second arc are greater than half of the first distance, and the radii of the first arc and the second arc are less than half of the positive square root of the sum of the squares of the first distance and the second distance.

5. The semiconductor structure according to claim 4, characterized in that, The first plug has a first cleavage in its cross-section, and the second plug has a second cleavage in its cross-section. The first cleavage and the second cleavage are parallel to the extension direction of the bit line structure.

6. The semiconductor structure according to claim 5, characterized in that, The projections of the first secant line and the second secant line onto the substrate both cover a portion of the word line structure.

7. A mask structure, characterized in that, The mask includes a mask assembly having a mask pattern, the mask assembly being used to cover a semiconductor structure so as to form capacitor plugs on the semiconductor structure through the mask assembly; The semiconductor structure includes a substrate and a plurality of parallel and spaced word line structures disposed on the substrate. The substrate has an active region and a bit line structure. The plurality of bit line structures are disposed in parallel and spaced within the substrate. The word line structures intersect with the bit line structures and are arranged in a plurality of grids arrayed on the substrate. The capacitor plug is located within the grid, and the projection of the capacitor plug on the substrate covers a portion of the active region. In a cross-section parallel to the surface of the substrate, the cross-sectional shape of the capacitor plug is arc-shaped.

8. The mask structure according to claim 7, characterized in that, The mask assembly includes a first mask plate and a second mask plate. The first mask plate has a plurality of arrayed first hole groups. The first hole groups include first etched holes and second etched holes arranged opposite to each other. The first etched holes and the second etched holes are both arc-shaped. The first etched holes and the second etched holes are used to form the capacitor plugs on both sides of the bit line structure. The second mask has a plurality of arrayed second hole groups, the second hole group including a third etched hole and a fourth etched hole arranged opposite to each other, the third etched hole and the fourth etched hole are both arc-shaped, the third etched hole and the fourth etched hole are used to form the capacitor plugs on both sides of the bit line structure; The projection of the second hole group on the substrate is located outside the projection of the first hole group on the substrate.

9. The mask structure according to claim 8, characterized in that, The projections of the first and second hole groups on the substrate are alternately arranged.

10. The mask structure according to claim 9, characterized in that, The centers of the arcs corresponding to the first etched hole, the second etched hole, the third etched hole, and the fourth etched hole are all located on the center line of the bit line structure.

11. The mask structure according to claim 10, characterized in that, There is a first distance between the center lines of any two adjacent bit line structures in a direction parallel to the substrate surface, and there is a second distance between the center lines of any two adjacent word line structures in a direction parallel to the substrate surface; The radii of the corresponding arcs of the first, second, third, and fourth etched holes are greater than half of the first distance. The radii of the corresponding arcs of the first, second, third, and fourth etched holes are less than half of the positive square root of the sum of the squares of the first and second distances. The secant lines of the first, second, third, and fourth etched holes are all parallel to the extension direction of the bit line structure. The projections of the first, second, third, and fourth etched holes on the substrate all cover part of the word line structure.

12. The mask structure according to claim 7, characterized in that, The mask assembly includes a first mask plate and a second mask plate. The first mask plate has a plurality of arrayed first mask holes, and the second mask plate has a plurality of arrayed second mask holes. Both the first mask holes and the second mask holes are arc-shaped. The projection of the first mask hole on the substrate is located on one side of the bit line structure, and the projection of the corresponding second mask hole on the substrate is located on the other side of the bit line structure.

13. The mask structure according to claim 12, characterized in that, The centers of the corresponding arcs of the first mask hole and the corresponding second mask hole coincide.

14. The mask structure according to claim 13, characterized in that, The centers of the corresponding arcs of the first and second mask holes are located on the center line of the bit line structure.

15. The mask structure according to claim 14, characterized in that, There is a first distance between the center lines of any two adjacent bit line structures in a direction parallel to the substrate surface, and there is a second distance between the center lines of any two adjacent word line structures in a direction parallel to the substrate surface; The radius of the corresponding arc of the first mask hole and the second mask hole is greater than half of the first distance, the radius of the corresponding arc of the first mask hole and the second mask hole is less than half of the positive square root of the sum of the squares of the first distance and the second distance, the secant lines of the first mask hole and the second mask hole are parallel to the extension direction of the bit line structure, and the projections of the first mask hole and the second mask hole on the substrate cover part of the word line structure.

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