Semiconductor structure and method for manufacturing semiconductor structure

Abstract

The application relates to the technical field of semiconductors, and discloses a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure comprises the following steps: providing a substrate; forming a semiconductor column on the substrate; forming a gate on the middle sidewall of the semiconductor column; and performing reverse-type doping injection on the upper part and the lower part of the semiconductor column surrounded by the gate to form a source region and a drain region. Since the gate surrounding the semiconductor column is formed first, and then the doping injection is performed to form the source region and the drain region, the precise position of the doping injection can be ensured, the manufacturing precision of the semiconductor structure is improved, and the use performance of the semiconductor structure is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] With the increasing integration of semiconductor manufacturing process, it has become a trend to improve the integration density of memory.

[0003] Dynamic random access memory (DRAM) is a kind of semiconductor memory, which includes transistors. The transistors commonly used in the related art are planar crystal structures, while the use of vertical structure transistors is relatively small due to their greater process difficulty. SUMMARY

[0004] The present application provides a semiconductor structure and a manufacturing method thereof to improve the performance of the semiconductor structure.

[0005] According to a first aspect of the present application, a manufacturing method of a semiconductor structure is provided, comprising:

[0006] providing a substrate;

[0007] forming a semiconductor pillar on the substrate;

[0008] forming a gate on the middle sidewall of the semiconductor pillar;

[0009] performing reverse type doping implantation on the upper and lower parts of the semiconductor pillar with the gate to form source and drain regions.

[0010] In an embodiment of the present application, the semiconductor pillar is a p-type semiconductor material, and n-type doping implantation is performed on the upper and lower parts of the semiconductor pillar; or, the semiconductor pillar is an n-type semiconductor material, and p-type doping implantation is performed on the upper and lower parts of the semiconductor pillar.

[0011] In an embodiment of the present application, plasma doping is used to dope the upper and lower parts of the semiconductor pillar.

[0012] In an embodiment of the present application, the manufacturing method of the semiconductor structure further comprises:

[0013] After doping the upper and lower parts of the semiconductor pillar using plasma doping, annealing treatment is performed.

[0014] In an embodiment of the present application, the gate is a full-surrounding gate.

[0015] In an embodiment of the present application, a bit line is formed in the substrate, and the semiconductor pillar is located on the bit line. The manufacturing method of the semiconductor structure further comprises,

[0016] After forming the semiconductor pillars, before forming the gate,

[0017] The bit line metal silicide is formed in the substrate.

[0018] In one embodiment of the present application, the method for manufacturing the semiconductor structure further comprises:

[0019] Before forming the bit line metal silicide,

[0020] A sidewall protection layer is formed on the sidewall of the semiconductor pillar.

[0021] In one embodiment of the present application, after forming the sidewall protection layer, a metal material is deposited in the substrate and annealed to form the bit line metal silicide.

[0022] In one embodiment of the present application, the first trench and the second trench are formed on the substrate along the first direction and the second direction respectively to form a plurality of independently arranged semiconductor pillars, the substrate has a bit line extending along the first direction, and the semiconductor pillars are located on the bit line.

[0023] The depth of the first trench is greater than the depth of the second trench.

[0024] In one embodiment of the present application, the first direction is perpendicular to the second direction.

[0025] In one embodiment of the present application, the gate comprises a gate barrier layer and a gate metal layer formed on the semiconductor pillar in sequence.

[0026] In one embodiment of the present application, the gate formed on the sidewall of the semiconductor pillar comprises:

[0027] A sidewall protection layer is formed on the sidewall of the semiconductor pillar.

[0028] A barrier layer is formed on the sidewall protection layer.

[0029] Part of the sidewall protection layer is etched to expose the upper part and the middle part of the semiconductor pillar.

[0030] The gate barrier layer and the gate metal layer are formed on the middle part of the semiconductor pillar.

[0031] In one embodiment of the present application, the gate barrier layer is formed on the upper sidewall and the middle sidewall of the semiconductor pillar, the gate metal layer is formed on the gate barrier layer, the gate metal layer on the upper sidewall of the gate barrier layer is removed, the gate barrier layer on the upper sidewall of the semiconductor pillar is removed, and the remaining gate barrier layer and gate metal layer serve as the gate.

[0032] In one embodiment of the present application, before the upper part and the lower part of the semiconductor pillar are doped and implanted, the method further comprises:

[0033] The side wall protection layer and the barrier layer are removed.

[0034] In one embodiment of the present application, the side wall protection layer and the barrier layer are removed by using an ion beam etching process.

[0035] In one embodiment of the present application, the side wall protection layer is formed by comprising:

[0036] An initial protection layer is formed on the substrate so that the initial protection layer covers the semiconductor pillars;

[0037] Part of the initial protection layer is removed, and the initial protection layer covering the semiconductor pillars is used as the side wall protection layer.

[0038] In one embodiment of the present application, after the upper part and the lower part of the semiconductor pillars are doped and implanted, the method further comprises:

[0039] A termination protection layer is formed between the semiconductor pillars to cover the semiconductor pillars and the gate;

[0040] The termination protection layer is located on the initial protection layer below the semiconductor pillars.

[0041] According to a second aspect of the present application, a semiconductor structure is provided, comprising a semiconductor structure obtained by the method for manufacturing a semiconductor structure described above.

[0042] In one embodiment of the present application, the unit configuration size of the semiconductor pillars on the substrate is greater than or equal to 4 times the square of the minimum feature size.

[0043] The method for manufacturing a semiconductor structure according to the embodiments of the present application forms vertical semiconductor pillars on a substrate and forms a gate on the middle part of the side wall of the semiconductor pillars, so that the gate forms a protection for the middle part of the side wall of the semiconductor pillars, and thus the upper part and the lower part of the semiconductor pillars can be doped and implanted with the semiconductor pillars as a mask to form a vertical transistor. Since the gate surrounding the semiconductor pillars is formed first, and then the source region and the drain region are formed by doping and implantation, the doping and implantation can obtain an accurate position, so as to improve the manufacturing precision of the semiconductor structure, and thus improve the use performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0044] Various objects, features and advantages of the present application will become more apparent to those skilled in the art from the following detailed description of preferred embodiments of the present application, taken in conjunction with the accompanying drawings. The drawings are only schematic and are not drawn to scale. In the drawings, the same reference numerals are used to denote the same or similar parts throughout the various views. Among the other drawings:

[0045] Figure 1 is a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0046] Figure 2 is a schematic view of a first direction cross-sectional structure of forming a semiconductor pillar according to an exemplary embodiment of a method of manufacturing a semiconductor structure;

[0047] Figure 3 is a schematic view of a second direction cross-sectional structure of forming an initial protective layer according to an exemplary embodiment of a method of manufacturing a semiconductor structure;

[0048] Figure 4 is a schematic view of a first direction cross-sectional structure of forming a metal silicide according to an exemplary embodiment of a method of manufacturing a semiconductor structure;

[0049] Figure 5 is a schematic view of a first direction cross-sectional structure of forming a barrier layer according to an exemplary embodiment of a method of manufacturing a semiconductor structure;

[0050] Figure 6 is a schematic view of a first direction cross-sectional structure of partially removing a barrier layer according to an exemplary embodiment of a method of manufacturing a semiconductor structure;

[0051] Figure 7 is a schematic view of a first direction cross-sectional structure of forming a gate metal layer according to an exemplary embodiment of a method of manufacturing a semiconductor structure;

[0052] Figure 8 is a schematic view of a first direction cross-sectional structure of forming a gate electrode according to an exemplary embodiment of a method of manufacturing a semiconductor structure;

[0053] Figure 9 is a schematic view of a second direction cross-sectional structure of forming a gate electrode according to an exemplary embodiment of a method of manufacturing a semiconductor structure;

[0054] Figure 10 is a schematic view of a first direction cross-sectional structure of forming a source region and a drain region according to an exemplary embodiment of a method of manufacturing a semiconductor structure;

[0055] Figure 11 is a schematic view of a first direction cross-sectional structure of forming a termination protective layer according to an exemplary embodiment of a method of manufacturing a semiconductor structure;

[0056] Figure 12 is a schematic view of a second direction cross-sectional structure of forming a termination protective layer according to an exemplary embodiment of a method of manufacturing a semiconductor structure.

[0057] The following is a description of the reference numerals in the drawings:

[0058] 10, substrate; 20, bit line; 21, metal silicide; 30, vertical transistor; 31, semiconductor pillar; 311, source region; 312, drain region; 313, channel region; 32, gate; 321, gate barrier layer; 322, gate metal layer;

[0059] 50, sidewall protection layer; 51, barrier layer; 52, initial protection layer; 53, final protection layer. DETAILED DESCRIPTION

[0060] Embodiments embodying the principles of the application will now be described in detail, by way of example only. The application can vary, however, without departing from the scope of the application and thus, the description and drawings should not be construed as limiting the application.

[0061] In the following description of various example embodiments of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration various example structures, systems, and steps in which aspects of the present disclosure can be practiced. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps can be utilized and structural and functional modifications can be made without departing from the scope of the present disclosure. Also, while the terms "over," "between," "inside" or the like can be used in the present description and claims to describe one aspect of the present disclosure relative to another, such terms are used for convenience and are not intended to necessarily limit the scope of the disclosure to one or another possible arrangement or configuration of the described features. Nothing in this specification should be construed as requiring a specific three dimensional orientation of structures in order to fall within the scope of the present disclosure.

[0062] One embodiment of the present application provides a method for manufacturing a semiconductor structure, referring to Figure 1 The method for manufacturing a semiconductor structure comprises:

[0063] S101, providing a substrate 10;

[0064] S103, forming a semiconductor pillar 31 on the substrate 10;

[0065] S105, forming a gate 32 on the middle sidewall of the semiconductor pillar 31;

[0066] S107, performing a doping implantation opposite to the semiconductor pillar 31 on the upper and lower parts of the semiconductor pillar 31 with the gate 32 formed thereon, to form a source region 311 and a drain region 312.

[0067] The method for manufacturing the semiconductor structure in one embodiment of the present application forms the semiconductor column 31 on the substrate 10, and forms the gate 32 on the middle part of the sidewall of the semiconductor column 31, so that the gate 32 forms the protection for the middle part of the sidewall of the semiconductor column 31, and the upper part and the lower part of the semiconductor column 31 are implanted with the doping ions which are opposite to the semiconductor column 31 by using the gate 32 as the mask, so as to form the vertical transistor 30. Since the gate 32 surrounding the semiconductor column 31 is formed first, and then the source region 311 and the drain region 312 are formed by the doping implantation, the accurate position of the doping implantation can be ensured, so as to improve the manufacturing precision of the semiconductor structure, and improve the performance of the semiconductor structure.

[0068] It should be noted that the semiconductor column 31 formed on the substrate 10 is perpendicular to the substrate 10, and a plurality of independent semiconductor columns 31 are formed on the substrate 10 in a spaced manner, the middle part of the semiconductor column 31 is the channel region 313, the gate 32 is arranged around the channel region 313, and one of the upper part and the lower part of the semiconductor column 31 is the source region 311, and the other is the drain region 312, that is, the channel region 313 is located between the source region 311 and the drain region 312. Before the semiconductor column 31 is implanted with the doping ions, if the semiconductor column 31 is directly implanted, since the sidewall of the semiconductor column 31 is exposed, the problem of inaccurate implantation is prone to occur. In the embodiment, the gate 32 is first formed on the middle part of the semiconductor column 31, so that the gate 32 surrounds the channel region 313, and then the upper part and the lower part of the semiconductor column 31 are exposed, and then the doping implantation is performed, so that the gate 32 becomes the mask, and thus the accurate doping implantation can be ensured, and the upper part and the lower part of the semiconductor column 31 are not deviated, so as to form the reliable source region 311 and the drain region 312.

[0069] In one embodiment, the semiconductor column 31 is a p-type semiconductor material, and the n-type doping implantation is performed on the upper part and the lower part of the semiconductor column 31, so as to form the n-type vertical transistor. The n-type doping ions can include P, As, Sb, etc.

[0070] In one embodiment, the semiconductor column 31 is an n-type semiconductor material, and the p-type doping implantation is performed on the upper part and the lower part of the semiconductor column 31, so as to form the p-type vertical transistor. The p-type doping ions can include B or In, etc.

[0071] It should be noted that the vertical transistor 30 in the embodiment can be an n-type vertical storage transistor, or a p-type vertical storage transistor. In some embodiments, the method for manufacturing the semiconductor structure can form the semiconductor structure which simultaneously includes the n-type vertical storage transistor and the p-type vertical storage transistor.

[0072] In one embodiment, the upper and lower portions of the semiconductor pillar 31 are doped by plasma doping to form the source region 311 and the drain region 312. It is considered that plasma doping is isotropic, so that the upper and lower sidewalls of the semiconductor pillar 31 can be doped accurately after forming the gate 32 in the middle portion of the semiconductor pillar 31.

[0073] Optionally, the method for manufacturing the semiconductor structure further comprises: after doping the upper and lower portions of the semiconductor pillar 31 by plasma doping, performing annealing treatment, so as to ensure that the doping ions of the upper and lower sidewalls of the semiconductor pillar 31 can be redistributed due to high-temperature thermal diffusion, and ensure the doping depth.

[0074] Specifically, taking the semiconductor pillar 31 as a p-type semiconductor material as an example, after n-type doping implantation is performed on the upper and lower sidewalls of the semiconductor pillar 31 by plasma doping, high-temperature pushing of a furnace tube can be performed, so that the implanted ions in the source region 311 and the drain region 312 are redistributed due to high-temperature thermal diffusion, and the doping depth of the source region 311 and the doping depth of the drain region 312 are increased. Optionally, the temperature of the high-temperature pushing of the furnace tube can be 800-1200°C, and the pushing time can be 50-100 minutes. In some embodiments, other annealing methods can also be used, such as rapid thermal annealing, so as to ensure the diffusion ability of the ions.

[0075] Optionally, the doping depth of the upper and lower sidewalls of the semiconductor pillar 31 is greater than 5 nm.

[0076] In one embodiment, the gate 32 is a gate-all-around (GAA), which can effectively protect the middle sidewall of the semiconductor pillar 31, and avoid the problem of implantation deviation in subsequent doping implantation, so as to ensure accurate position of the doping implantation and improve the manufacturing precision of the semiconductor structure.

[0077] In some embodiments, the gate 32 can be a non-gate-all-around, that is, the gate 32 can expose part of the middle sidewall of the semiconductor pillar 31, so that the exposed part of the middle sidewall of the semiconductor pillar 31 can be avoided in the doping implantation, so as to also ensure accurate position of the doping implantation. It should be noted that the control ability of the electric field in the channel of the gate-all-around is greatly improved compared with the non-gate-all-around, and the upper and lower portions of the semiconductor pillar 31 can be doped by plasma doping without avoiding position implantation in the subsequent doping implantation, so as to improve the manufacturing efficiency of the semiconductor structure.

[0078] In one embodiment, a bit line 20 is formed in the substrate 10, and a semiconductor pillar 31 is located on the bit line 20. The method for manufacturing the semiconductor structure further includes forming a bit line metal silicide 21 of the bit line 20 in the substrate 10 after forming the semiconductor pillar 31 and before forming the gate 32 to meet the storage requirements of the semiconductor structure.

[0079] Specifically, the bit line 20 is a buried bit line. Before forming the bit line metal silicide 21, it is ensured that the gate 32 on the semiconductor pillar 31 has not been formed, thereby preventing the gate 32 from being affected when forming the bit line metal silicide 21. Optionally, the bit line metal silicide 21 may include, but is not limited to, at least one of nickel silicide, platinum silicide, and cobalt silicide.

[0080] A metal material is deposited in the substrate 10 on which the semiconductor pillars 31 are formed, so that the metal material reacts with the silicon in the substrate 10 to form a bit line metal silicide 21. The metal material can be deposited by adopting a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process, and the metal material can include one or more metals such as nickel, platinum, and cobalt. Optionally, after the metal material is deposited in the substrate 10, an annealing treatment is performed to form the bit line metal silicide 21. The annealing treatment can be performed by high-temperature advancement in a furnace tube or by an annealing method in related technologies such as rapid thermal annealing.

[0081] In one embodiment, the method for manufacturing a semiconductor structure further includes: before forming the bit line metal silicide 21, forming a sidewall protection layer 50 on the sidewall of the semiconductor pillar 31, wherein the sidewall protection layer 50 is used to protect the semiconductor pillar 31 and prevent the metal material from being deposited into the semiconductor pillar 31 when the metal material is deposited in the substrate 10.

[0082] In one embodiment, substrate 10 is cut along a first direction and a second direction, respectively, i.e., a first trench and a second trench are formed in substrate 10, respectively, to form a plurality of independently disposed semiconductor pillars 31. Bit lines 20 extending along the first direction are formed in substrate 10, and semiconductor pillars 31 are located on bit lines 20. The depth of the cut along the first direction of substrate 10 is greater than the depth of the cut along the second direction of substrate 10, i.e., the depth of the first trench is greater than the depth of the second trench. The first trench may be an STI trench.

[0083] Specific, combined Figure 2 and Figure 3 As shown, Figure 2 FIG. 1 is a schematic cross-sectional view of the substrate 10 and the semiconductor pillars 31 along the first direction. After the independent semiconductor pillars 31 are formed, an initial protection layer 52 is formed in the gaps between the semiconductor pillars 31. Figure 3 As shown, Figure 3A cross-sectional view of the substrate 10 and the semiconductor pillar 31 along the second direction is shown in FIG. 4. As shown in FIG. 4, the depth of the substrate 10 along the first direction is greater than the depth of the substrate 10 along the second direction. Optionally, the depth of the substrate 10 along the first direction can be 250-350 nm, i.e., the depth of the first trench can be 250-350 nm, and the depth of the substrate 10 along the second direction can be 100-200 nm, i.e., the depth of the second trench can be 100-200 nm, so as to form a plurality of independent semiconductor pillars 31. In this case, the height of the semiconductor pillar 31 can be considered as 100-200 nm.

[0084] An initial protective layer 52 is formed in the semiconductor pillar 31 by a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process, and part of the initial protective layer 52 is removed by an etching process, so as to form a sidewall protective layer 50 on the sidewall of the semiconductor pillar 31, as shown in FIG. 5. In this case, the initial protective layer 52 located below the semiconductor pillar 31 is not etched and still fills the gap below the semiconductor pillar 31. The thickness of the sidewall protective layer 50 can be 5-15 nm. Figure 4 After the initial protective layer 52 is formed, a metal material is deposited in the substrate 10, so as to form a bit line metal silicide 21 in the substrate 10, as shown in FIG. 6. The initial protective layer 52 can be silicon oxynitride (SiON), silicon oxide (SiON) or the like. Figure 4

[0085] It should be noted that the first direction and the second direction have an included angle, and further, the first direction is perpendicular to the second direction, so that the semiconductor pillar 31 forms a rectangular column.

[0086] In one embodiment, the gate 32 includes a gate barrier layer 321 and a gate metal layer 322 formed on the semiconductor pillar 31. The gate barrier layer 321 realizes isolation of the semiconductor pillar 31 and the gate metal layer 322.

[0087] The gate barrier layer 321 can include a silicon oxide film (SiO2) or a silicon nitride film (SiN), a silicon oxynitride film (SiON) or a high-k material. The high-k material is a material with high dielectric constant. The high-k material such as aluminum oxide (Al2O3), tantalum oxide (Ta2O5) and hafnium oxide (fO2) can be formed alone or in combination, or alternatively, by stacking a first high-k material and a second high-k material.

[0088] ​The gate metal layer 322 can include a conductive material or a metal layer formation. Polysilicon (poly-Si) can be used as the conductive material. Tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), molybdenum (Mo), cobalt (Co), nickel (Ni), copper (Cu), or aluminum (Al) can be used as the metal layer. Of course, these are merely example materials, and in other examples, other similar materials having similar properties can be used as the conductive material or the metal layer.

[0089] In one embodiment, the gate 32 is formed on the sidewall of the semiconductor pillar 31, including: forming a sidewall protection layer 50 on the sidewall of the semiconductor pillar 31; forming a barrier layer 51 on the sidewall protection layer 50; partially etching the sidewall protection layer 50 to expose the upper and middle portions of the semiconductor pillar 31; sequentially forming a gate barrier layer 321 and a gate metal layer 322 on the middle portion of the semiconductor pillar 31. After partially etching the sidewall protection layer 50, a gap is formed between the barrier layer 51 and the semiconductor pillar 31, so that the gate barrier layer 321 and the gate metal layer 322 can be sequentially formed in the gap.

[0090] In one embodiment, the gate barrier layer 321 is formed on the upper and middle sidewalls of the semiconductor pillar 31, the gate metal layer 322 is formed on the gate barrier layer 321, the gate metal layer 322 on the upper sidewall of the gate barrier layer 321 is removed to expose part of the gate barrier layer 321, and the gate barrier layer 321 on the upper sidewall of the semiconductor pillar 31 is removed, so that the remaining gate barrier layer 321 and the gate metal layer 322 cover the middle portion of the semiconductor pillar 31, i.e., the remaining gate barrier layer 321 and the gate metal layer 322 serve as the gate 32.

[0091] Specifically, after the etching process is used to remove part of the initial protection layer 52 to form the sidewall protection layer 50 on the sidewall of the semiconductor pillar 31 as shown in FIG. 4B, the barrier layer 51 can be covered on the sidewall protection layer 50, and the barrier layer 51 fills the gap formed by the sidewall protection layer 50 as shown in FIG. 4C. Figure 4 Figure 5 The barrier layer 51 can be silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), etc. After the barrier layer 51 is formed, dry etching or chemical mechanical polishing (CMP) planarization processing can be used to ensure the flatness of the top of the barrier layer 51. The formation of the barrier layer 51 can use physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc.

[0092] The sidewall protection layer 50 is etched back, and the etching back depth is 80-120 nm, so that the gate barrier layer 321 and the gate metal layer 322 are formed on the sidewall of the semiconductor pillar 31 as shown in FIG. 4D. Figure 6 ​The structure shown in FIG. 5 is a structure in which a gap is formed between the barrier layer 51 and the semiconductor pillar 31, and the upper and middle portions of the semiconductor pillar 31 are exposed. In this embodiment, a gate barrier layer 321 can be formed by thermal oxidation, and a gate metal layer 322 can be deposited. In this case, the gate barrier layer 321 covers the upper and middle portions of the semiconductor pillar 31, and the gate metal layer 322 covers the gate barrier layer 321. After etching back the gate metal layer 322, the gate barrier layer 321 on the upper portion of the semiconductor pillar 31 is exposed. Figure 7 As shown, the gate barrier layer 321 on the upper portion of the semiconductor pillar 31 is removed together with the gate metal layer 322 when the gate metal layer 322 is etched back, or the gate barrier layer 321 is etched back after the gate metal layer 322 is etched back to expose the upper portion of the semiconductor pillar 31. At this time, the height of the exposed upper portion of the semiconductor pillar 31 can be 20 nm to 60 nm, that is, the height of the source region 311 or the drain region 312 formed subsequently.

[0093] In one embodiment, before doping the upper and lower portions of the semiconductor pillars 31 , the process further includes: removing the sidewall protection layer 50 and the barrier layer 51 to expose the gate metal layer 322 , so that each independent semiconductor pillar 31 is surrounded by a gate 32 .

[0094] In one embodiment, forming the sidewall protection layer 50 includes: forming an initial protection layer 52 on the substrate 10 so that the initial protection layer 52 buries the semiconductor pillar 31; removing part of the initial protection layer 52, and the initial protection layer 52 covering the semiconductor pillar 31 serves as the sidewall protection layer 50. At this time, the initial protection layer 52 is filled under the semiconductor pillar 31, that is, the first trench is filled with the initial protection layer 52.

[0095] In one embodiment, after doping the upper and lower portions of the semiconductor pillars 31, the process further includes: forming a termination protection layer 53 between the semiconductor pillars 31 to bury the semiconductor pillars 31 and the gate 32; wherein the termination protection layer 53 is located on the initial protection layer 52 below the semiconductor pillars 31, so that the initial protection layer 52 and the termination protection layer 53 can reliably protect the semiconductor pillars 31 and the gate 32.

[0096] In one embodiment, the sidewall protection layer 50 and the barrier layer 51 are removed by an ion beam etching process to form Figure 8 and Figure 9 In the structure shown, etching of the sidewall protection layer 50 below the gate metal layer 322 can be completed by increasing the isotropy of etching and extending the etching time. Figure 8 is a cross-sectional schematic diagram along the first direction, Figure 9 3 is a schematic cross-sectional view along the second direction, from which it can be seen that after the gate 32 is formed, the bottom of the semiconductor pillar 31 is further filled with an initial protection layer 52 .

[0097] Then, the upper and lower parts of the semiconductor pillar 31 are doped by plasma doping and annealing, so as to form a structure as shown in FIG. 3. Figure 10 Finally, the semiconductor pillar 31 and the gate 32 are buried by using a termination protection layer 53, as shown in FIG. 4. Figure 11 Figure 12 The initial protection layer 52 and the termination protection layer 53 fill the gap above the substrate 10, as shown in FIG. 5. The material of the initial protection layer 52 and the termination protection layer 53 can be the same, for example, the initial protection layer 52 and the termination protection layer 53 can be silicon oxynitride (SiON), silicon oxide (SiON), etc.

[0098] The manufacturing method of the semiconductor structure of the embodiment of the present application does not perform any additional doping on the substrate before forming the bit line metal silicide, and after the manufacturing of the bit line metal silicide is completed, the manufacturing of the self-aligned gate is performed, and all the silicides (side wall protection layers) and nitrides (barrier layers) are removed by using the method of plasma etching, the source region and the drain region are doped by using the gate as a mask and by using plasma doping and annealing, and finally, the silicon oxide (termination protection layer) is backfilled, so as to form the vertical transistor.

[0099] An embodiment of the present application further provides a semiconductor structure, which comprises the semiconductor structure obtained by the manufacturing method of the semiconductor structure.

[0100] In an embodiment, the unit configuration size of the semiconductor pillar 31 on the substrate 10 is greater than or equal to 4 times the square of the minimum feature size.

[0101] The semiconductor structure manufactured in the embodiment can form the bit line 20 and the word line (i.e., the gate) with the minimum feature size F according to the related manufacturing process, and the line spacing between the adjacent bit lines 20 and the adjacent word lines is also greater than or equal to the minimum feature size F, so that the width size of the vertical transistor in the direction perpendicular to the bit line is 2F, and the width size of the vertical transistor in the direction perpendicular to the word line is also 2F, and thus the unit configuration size of the vertical transistor can be 4F 2 (2F*2F), i.e., the unit configuration size of the vertical transistor is greater than or equal to 4 times the square of the minimum feature size.

[0102] The "unit configuration size" refers to the unit configuration size of a storage unit on the substrate, which specifically includes the size actually occupied by the storage unit on the substrate and the interval size required to be reserved between the storage unit and the adjacent storage unit. For example, if N storage transistors occupy a size of M on the substrate, then the unit configuration size of one storage transistor on the substrate is N / M.

[0103] ​The semiconductor structure in this embodiment is a Gate-All-Around (GAA) transistor 4F 2 A vertical DRAM memory cell comprising a buried bit line with metal silicide, a precise word line wrapped around a silicon nanowire, and a silicon nanowire with the correct NPN or PNP doping.

[0104] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0105] It is to be understood that the application is not limited to the precise structures hereinabove described and shown in the drawings, for purposes of illustration and description, specific embodiments have been set forth and described. The scope of the application is not, however, to be limited to such specifically disclosed embodiments. Various modifications and changes can be made thereto without departing from the spirit and scope of the present application. The scope of the application is indicated by the following claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate, wherein a bit line is formed in the substrate; forming a semiconductor pillar on the substrate, wherein the semiconductor pillar is located on the bit line; forming a bit line metal silicide of the bit line in the substrate; forming a gate on a middle sidewall of the semiconductor column; Doping with an inverse type to that of the semiconductor column is performed on the upper and lower portions of the semiconductor column where the gate is formed, so as to form a source region and a drain region.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The semiconductor column is made of p-type semiconductor material, and n-type doping is performed on the upper and lower parts of the semiconductor column; or the semiconductor column is made of n-type semiconductor material, and p-type doping is performed on the upper and lower parts of the semiconductor column.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein: Plasma doping is used to dope the upper and lower portions of the semiconductor column.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein: Also includes: After the upper and lower parts of the semiconductor column are doped with plasma, an annealing process is performed.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The gate is a full-surround gate.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: Also includes: Before forming the bit line metal silicide, A sidewall protection layer is formed on the sidewall of the semiconductor pillar.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: After forming the sidewall protection layer, a metal material is deposited in the substrate and annealed to form the bit line metal silicide.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein: forming a first trench and a second trench on the substrate along a first direction and a second direction respectively to form a plurality of independently arranged semiconductor pillars, wherein a bit line extending along the first direction is formed in the substrate, and the semiconductor pillars are located on the bit line; Wherein, the depth of the first groove is greater than the depth of the second groove.

9. The method for manufacturing a semiconductor structure according to claim 8, wherein: The first direction is perpendicular to the second direction.

10. The method for manufacturing a semiconductor structure according to claim 1, wherein: The gate includes a gate barrier layer and a gate metal layer which are sequentially formed on the semiconductor pillar.

11. The method for manufacturing a semiconductor structure according to claim 10, wherein: Forming the gate on the sidewall of the semiconductor pillar comprises: forming a sidewall protection layer on the sidewall of the semiconductor column; forming a barrier layer on the sidewall protection layer; Partially etching the sidewall protection layer to expose the upper portion and the middle portion of the semiconductor column; The gate barrier layer and the gate metal layer are formed in the middle of the semiconductor column.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein: The gate barrier layer is formed on the upper side wall and the middle side wall of the semiconductor column, the gate metal layer is formed on the gate barrier layer, the gate metal layer on the upper side wall of the gate barrier layer is removed, and the gate barrier layer on the upper side wall of the semiconductor column is removed, and the remaining gate barrier layer and the gate metal layer serve as the gate.

13. The method for manufacturing a semiconductor structure according to claim 11, wherein: Before performing doping implantation on the upper and lower portions of the semiconductor column, the method further includes: The sidewall protection layer and the barrier layer are removed.

14. The method for manufacturing a semiconductor structure according to claim 13, wherein: The sidewall protection layer and the barrier layer are removed by an ion beam etching process.

15. The method for manufacturing a semiconductor structure according to claim 11, wherein: Forming the sidewall protection layer includes: forming an initial protection layer on the substrate so that the initial protection layer buries the semiconductor pillar; A portion of the initial protection layer is removed, and the initial protection layer covering the semiconductor column serves as the sidewall protection layer.

16. The method for manufacturing a semiconductor structure according to claim 15, wherein: After doping the upper and lower portions of the semiconductor column, the method further includes: forming a termination protection layer between the semiconductor pillars to bury the semiconductor pillars and the gate; Wherein, the termination protection layer is located on the initial protection layer below the semiconductor column.

17. A semiconductor structure, characterized in that A semiconductor structure obtained by the method for manufacturing a semiconductor structure according to any one of claims 1 to 16.

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