Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises: forming a first shallow trench isolation structure on a substrate. The first shallow trench isolation structure isolates a plurality of active regions extending along a first direction in the substrate, and the first shallow trench isolation structure comprises a sacrificial layer and a first dielectric layer which are sequentially stacked from bottom to top. A plurality of word line isolation trenches are formed in the substrate, the word line isolation trenches are located above the sacrificial layer, and extend along a second direction intersecting the first direction. A second dielectric layer is formed on the sidewall of the word line isolation trench, and the second dielectric layer has an aperture penetrating to the substrate. Based on the aperture, a lower part of the active region is metalized to form a bit line extending along the first direction. Based on the aperture, the sacrificial layer is removed to form an air gap between adjacent bit lines. The preparation method can reduce the inter-wire parasitic capacitance and effectively improve the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory commonly used in computers and other electronic devices. It is composed of multiple memory cells. Among them, the memory cell includes: a storage capacitor and a transistor electrically connected to the storage capacitor. The transistor includes a gate, a source region, and a drain region. The gate of the transistor is used to electrically connect to the word line. The source region of the transistor is used to form a bit line contact region, which is electrically connected to the bit line through the bit line contact structure. The drain region of the transistor is used to form a storage node contact region, which is electrically connected to the storage capacitor through the storage node contact structure.

[0003] However, as DRAM sizes continue to shrink, the use of vertical gate all around transistors (VGAA transistors) can effectively reduce DRAM size. However, this can also easily lead to coupling between the bit lines and word lines connected to the transistors, resulting in large parasitic capacitance between the DRAM lines, which can adversely affect the DRAM's electrical performance. Summary of the Invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which can reduce parasitic capacitance between lines to improve the electrical performance of the semiconductor structure.

[0005] Some embodiments of the present disclosure provide a method for preparing a semiconductor structure, which includes the following steps.

[0006] A substrate is provided, and a first shallow trench isolation structure is formed on the substrate. The first shallow trench isolation structure isolates multiple active regions within the substrate. The active regions extend along a first direction. The first shallow trench isolation structure includes a sacrificial layer and a first dielectric layer stacked sequentially from bottom to top.

[0007] A plurality of word line isolation grooves are formed in the substrate. The word line isolation grooves are located above the sacrificial layer and extend along a second direction intersecting the first direction.

[0008] A second dielectric layer is formed on the sidewall of the word line isolation trench, and the inner side of the second dielectric layer has a pore penetrating to the substrate.

[0009] Based on the hole, a lower portion of the active area is metallized to form a bit line, and the bit line extends along a first direction.

[0010] Based on the aperture, the sacrificial layer is removed to form an air gap between adjacent bit lines.

[0011] In some embodiments, the method for preparing a semiconductor structure further includes the following steps.

[0012] A third dielectric layer is formed on the sidewalls of the air gap and in the pores.

[0013] A portion of the first dielectric layer and a portion of the second dielectric layer are removed to form a plurality of first openings.

[0014] A fourth dielectric layer is formed in the first opening, wherein the fourth dielectric layer has a second opening.

[0015] Based on the second opening, a portion of the first dielectric layer and a portion of the second dielectric layer are continuously removed to form a word line trench.

[0016] A gate dielectric layer is formed on the sidewalls of the word line trench.

[0017] A gate word line is formed in the word line trench.

[0018] In some embodiments, forming a gate dielectric layer on the sidewall of the word line trench includes: forming the gate dielectric layer on the sidewall of the word line trench using a thermal oxidation process; the gate dielectric layer includes a silicon oxide layer.

[0019] In some embodiments, forming a gate word line in a word line trench includes: filling the word line trench with a titanium nitride material to form the gate word line.

[0020] In some embodiments, after forming the wordline trenches, portions of the active area are removed to form pillar structures between adjacent wordline trenches. Before forming a second dielectric layer on the sidewalls of the wordline isolation trenches, the method for fabricating the semiconductor structure further includes: ion implanting the lower and upper portions of the pillar structures to form a source, a drain, and a conductive channel between the source and drain; wherein the gate wordline surrounds the outer periphery of the conductive channel.

[0021] In some embodiments, the source, the conductive channel, and the drain are sequentially arranged from bottom to top along the columnar structure; the first opening exposes the drain, and the word line trench exposes the conductive channel.

[0022] In some embodiments, the total thickness of the first dielectric layer removed is one-third to two-thirds of the original thickness of the first dielectric layer.

[0023] In some embodiments, after forming the word line trenches, a portion of the active area is removed to form a columnar structure between adjacent word line trenches. The method for fabricating the semiconductor structure further includes the following steps.

[0024] A fifth dielectric layer is filled in the second opening, and an upper surface of the fifth dielectric layer is flush with an upper surface of the fourth dielectric layer.

[0025] A storage node contact structure is formed on the top surface of the columnar structure.

[0026] A storage capacitor is formed on the storage node contact structure.

[0027] In some embodiments, metallizing the lower portion of the active region based on the pores to form a bit line includes: injecting metal ions from the pores to metallize the lower portion of the active region to form the bit line; the metal ions include cobalt ions.

[0028] Some embodiments of the present disclosure also provide a semiconductor structure fabricated using the semiconductor structure fabrication methods described in some of the above embodiments. The semiconductor structure includes a substrate and a plurality of bit lines. The substrate includes a plurality of active regions spaced apart from each other, the active regions extending along a first direction. The plurality of bit lines are spaced apart and arranged in parallel below the active regions, with air gaps between adjacent bit lines.

[0029] In some embodiments, the semiconductor structure further includes an insulating isolation structure and a plurality of gate word lines. The plurality of gate word lines are located above the bit lines and are arranged parallel to and spaced apart from each other along a second direction. The second direction intersects the first direction. The insulating isolation structure is located between adjacent gate word lines and between a gate word line and a bit line.

[0030] In some embodiments, the semiconductor structure further comprises: a columnar structure, a source, a drain, and a conductive channel. The columnar structure is located within the active region, with the bottom of the columnar structure contacting the bit line, and the top of the columnar structure penetrating the gate word line and extending above the gate word line. The source is located within the columnar structure and between the gate word line and the bit line. The drain is located within the columnar structure and above the gate word line. The conductive channel is located within the columnar structure and between the source and drain. The gate word line is located outside the conductive channel.

[0031] In some embodiments, the semiconductor structure further includes a gate dielectric layer located between the conductive channel and the gate word line.

[0032] In some embodiments, the material of the gate word line includes titanium nitride.

[0033] In some embodiments, the semiconductor structure further includes a storage node contact structure and a storage capacitor. The storage node contact structure is located above the pillar structure and is in contact with the drain electrode. The storage capacitor is located above the storage node contact structure and is in contact with the storage node contact structure.

[0034] In some embodiments, the material of the bit line includes cobalt silicide.

[0035] The disclosed embodiment forms an air gap between adjacent bit lines, which can be used to effectively eliminate the mutual coupling between bit lines or between bit lines and gate word lines, thereby effectively reducing the parasitic capacitance between lines and improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 is a schematic structural diagram of a storage unit provided in one embodiment;

[0038] Figure 2 A schematic diagram of the distribution of bit lines and word lines in a semiconductor structure provided in one embodiment;

[0039] Figure 3 is a flow chart of a method for preparing a semiconductor structure provided in one embodiment;

[0040] Figure 4a is a cross-sectional view along line AA' of a structure obtained after forming the first shallow trench in step S11 provided in one embodiment;

[0041] Figure 4b is a cross-sectional view along line BB' of a structure obtained after forming the first shallow trench in step S11 provided in one embodiment;

[0042] Figure 4c A cross-sectional view of a structure obtained after forming the first shallow trench in step S11 along the CC' line provided in one embodiment;

[0043] Figure 4d is a cross-sectional view along the DD' direction of the structure obtained after forming the first shallow trench in step S11 provided in one embodiment;

[0044] Figure 5a A cross-sectional view of the structure obtained in step S11 along line AA' provided in one embodiment;

[0045] Figure 5b A cross-sectional view of the structure obtained in step S11 along line BB' provided in one embodiment;

[0046] Figure 5c A cross-sectional view of the structure obtained in step S11 along line CC' provided in one embodiment;

[0047] Figure 5dA cross-sectional view of the structure obtained in step S11 along the DD' direction provided in one embodiment;

[0048] Figure 6a is a cross-sectional view of the structure obtained in step S12 along line AA' provided in one embodiment;

[0049] Figure 6b is a cross-sectional view of the structure obtained in step S12 along line BB' provided in one embodiment;

[0050] Figure 6c is a cross-sectional view of the structure obtained in step S12 along the CC' line provided in one embodiment;

[0051] Figure 6d A cross-sectional view of the structure obtained in step S12 along the DD' direction provided in one embodiment;

[0052] Figure 7a is a cross-sectional view of the structure obtained in step S13 along line AA' provided in one embodiment;

[0053] Figure 7b is a cross-sectional view of the structure obtained in step S13 along line BB' provided in one embodiment;

[0054] Figure 7c is a cross-sectional view of the structure obtained in step S13 along the CC' line provided in one embodiment;

[0055] Figure 7d A cross-sectional view of the structure obtained in step S13 along the DD' direction provided in one embodiment;

[0056] Figure 8a is a cross-sectional view of the structure obtained in step S14 along line AA' provided in one embodiment;

[0057] Figure 8b A cross-sectional view of the structure obtained in step S14 along line BB' provided in one embodiment;

[0058] Figure 8c is a cross-sectional view of the structure obtained in step S14 along the CC' line provided in one embodiment;

[0059] Figure 8d A cross-sectional view of the structure obtained in step S14 along the DD' direction provided in one embodiment;

[0060] Figure 9a is a cross-sectional view of the structure obtained in step S15 along line AA' provided in one embodiment;

[0061] Figure 9b is a cross-sectional view of the structure obtained in step S15 along line BB' provided in one embodiment;

[0062] Figure 9c A cross-sectional view of the structure obtained in step S15 along the CC' line provided in one embodiment;

[0063] Figure 9d A cross-sectional view of the structure obtained in step S15 along the DD' direction provided in one embodiment;

[0064] Figure 10a is a cross-sectional view of the structure obtained in step S16 along line AA' provided in one embodiment;

[0065] Figure 10b is a cross-sectional view of the structure obtained in step S16 along line BB' provided in one embodiment;

[0066] Figure 10c is a cross-sectional view of the structure obtained in step S16 along the CC' line provided in one embodiment;

[0067] Figure 10d is a cross-sectional view of the structure obtained in step S16 along the DD' direction provided in one embodiment;

[0068] Figure 11a is a cross-sectional view of the structure obtained in step S17 along line AA' provided in one embodiment;

[0069] Figure 11b is a cross-sectional view of the structure obtained in step S17 along line BB' provided in one embodiment;

[0070] Figure 11c is a cross-sectional view of the structure obtained in step S17 along the CC' line provided in one embodiment;

[0071] Figure 11d is a cross-sectional view of the structure obtained in step S17 along the DD' direction provided in one embodiment;

[0072] Figure 12a A cross-sectional view of the structure obtained in step S18 along line AA' provided in one embodiment;

[0073] Figure 12b is a cross-sectional view of the structure obtained in step S18 along line BB' provided in one embodiment;

[0074] Figure 12c A cross-sectional view of the structure obtained in step S18 along the CC' line provided in one embodiment;

[0075] Figure 12d A cross-sectional view of the structure obtained in step S18 along the DD' direction provided in one embodiment;

[0076] Figure 13aA cross-sectional view of the structure obtained in step S19 along line AA' provided in one embodiment;

[0077] Figure 13b is a cross-sectional view of the structure obtained in step S19 along line BB' provided in one embodiment;

[0078] Figure 13c is a cross-sectional view of the structure obtained in step S19 along the CC' line provided in one embodiment;

[0079] Figure 13d A cross-sectional view of the structure obtained in step S19 along the DD' direction provided in one embodiment;

[0080] Figure 14a is a cross-sectional view of the structure obtained in step S20 along line AA' provided in one embodiment;

[0081] Figure 14b is a cross-sectional view of the structure obtained in step S20 along line BB' provided in one embodiment;

[0082] Figure 14c is a cross-sectional view of the structure obtained in step S20 along the CC' line provided in one embodiment;

[0083] Figure 14d A cross-sectional view of the structure obtained in step S20 along the DD' direction provided in one embodiment;

[0084] Figure 15a A cross-sectional view of the structure obtained in step S21 along line AA' provided in one embodiment;

[0085] Figure 15b is a cross-sectional view of the structure obtained in step S21 along line BB' provided in one embodiment;

[0086] Figure 15c A cross-sectional view of the structure obtained in step S21 along line CC' provided in one embodiment;

[0087] Figure 15d A cross-sectional view of the structure obtained in step S21 along the DD' direction provided in one embodiment;

[0088] Figure 16a A cross-sectional view of the structure obtained in step S22 along line AA' provided in one embodiment;

[0089] Figure 16b is a cross-sectional view of the structure obtained in step S22 along line BB' provided in one embodiment;

[0090] Figure 16c A cross-sectional view of the structure obtained in step S22 along the CC' line provided in one embodiment;

[0091] Figure 16d is a cross-sectional view of the structure obtained in step S22 along the DD' direction provided in one embodiment;

[0092] Figure 17a is a cross-sectional view of the structure obtained in steps S23 and S24 along line AA' provided in one embodiment; and Figure 17a It is also a schematic structural diagram of a semiconductor structure provided in an embodiment along the AA' direction;

[0093] Figure 17b is a cross-sectional view of the structure obtained in steps S23 and S24 along the CC' direction provided in one embodiment; and Figure 17b It is also a schematic structural diagram of a semiconductor structure provided in an embodiment along the CC' direction.

[0094] Description of reference numerals:

[0095] 1-memory cell, 2-vertical wrap-around gate transistor, 10-bit line, 3-storage capacitor, 20-column structure,

[0096] 201-source, 202-conductive channel, 203-drain, 30-gate word line, 11-substrate, 110-air gap,

[0097] 12-first shallow trench isolation structure, 120-first shallow trench, 121-sacrificial layer, 122-first dielectric layer, 210-barrier layer,

[0098] 21 - word line isolation trench, 22 - second dielectric layer, H - pore, 23 - third dielectric layer, K1 - first opening,

[0099] 24 - fourth dielectric layer, K2 - second opening, 25 - word line trench, 26 - gate dielectric layer, 260 - oxide layer, 27 - fifth dielectric layer,

[0100] T1-the total thickness of the first dielectric layer removed, T0-the initial thickness of the first dielectric layer,

[0101] 4-storage node contact structure, 5-insulation isolation structure. DETAILED DESCRIPTION

[0102] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0103] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0104] It should be understood that when an element or layer is referred to as being “on,” “adjacent,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0105] It should be understood that although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, a first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings of the present invention.

[0106] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0107] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0108] While embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature and their shapes are not intended to represent the actual shapes of regions of a device and are not intended to limit the scope of the invention.

[0109] Surround-gate transistors offer advantages in scalability, high performance, and low power consumption, and are considered a key core technology for next-generation integrated circuits. For example, vertical-surround-gate transistors offer greater integration freedom in the vertical direction, effectively reducing their footprint and making it easier to vertically stack multiple layers of devices. Furthermore, they can further increase integration density through novel wiring methods.

[0110] See also Figure 1 Some embodiments of the present disclosure provide a semiconductor structure, which includes, for example, a memory cell 1 in a DRAM. The memory cell 1 includes: a vertical wrap-around gate transistor 2, and a storage capacitor 3 located above and connected to the vertical wrap-around gate transistor 2. The vertical wrap-around gate transistor 2 includes a columnar structure 20, and the columnar structure 20 includes a source 201, a conductive channel 202, and a drain 203 arranged from bottom to top. The source 201 is connected to the bit line 10. The drain 203 is connected to the storage capacitor 3. A gate word line 30 is provided on the periphery of the conductive channel 202, and a gate dielectric layer ( Figure 1 (not shown). The portion of the gate word line 30 located on the outer periphery of the conductive channel 202 can be used as the gate of the vertical wrap-around gate transistor 2.

[0111] It is necessary to add that Figure 1 and Figure 2It is understood that the memory cells 1 described above can be distributed in an array on a substrate, with each row of memory cells 1 correspondingly connected to a gate word line 30, and each column of memory cells 1 connected to a bit line 10, to form a semiconductor structure. Multiple gate word lines 30 are distributed in parallel and spaced apart, and multiple bit lines 10 are distributed in parallel and spaced apart.

[0112] Based on this, see Figure 3 Some embodiments of the present disclosure provide a method for preparing a semiconductor structure, which includes the following steps.

[0113] S11: Provide a substrate and form a first shallow trench isolation structure on the substrate. The first shallow trench isolation structure isolates multiple active regions within the substrate. The active regions extend along a first direction. The first shallow trench isolation structure includes a sacrificial layer and a first dielectric layer stacked sequentially from bottom to top.

[0114] S12 , forming a plurality of word line isolation trenches in the substrate, wherein the word line isolation trenches are located above the sacrificial layer and extend along a second direction intersecting the first direction.

[0115] S13 , forming a second dielectric layer on the sidewalls of the word line isolation trench, wherein the second dielectric layer has pores extending through to the substrate.

[0116] S14 , metallizing a lower portion of the active area based on the pores to form a bit line, where the bit line extends along a first direction.

[0117] S15 , removing the sacrificial layer based on the pores to form air gaps between adjacent bit lines.

[0118] The disclosed embodiment forms an air gap between adjacent bit lines, which can effectively eliminate the mutual coupling between bit lines or between bit lines and gate word lines, thereby reducing the parasitic capacitance between lines and improving the electrical performance of the semiconductor structure.

[0119] In step S11, refer to Figure 3 S11 and Figure 2 、 Figure 4a to Figure 4d 、 Figure 5a to Figure 5d A substrate 11 is provided, and a first shallow trench isolation structure 12 is formed on the substrate 11. The first shallow trench isolation structure 12 isolates multiple active regions within the substrate 11. The active regions extend along a first direction, such as a column direction. The first shallow trench isolation structure 12 includes a sacrificial layer 121 and a first dielectric layer 122 stacked sequentially from bottom to top.

[0120] Optionally, forming a first shallow trench isolation structure 12 on the substrate 11 includes: forming a first shallow trench 120 on the substrate 11, such as Figure 4a to Figure 4dIn the first shallow trench 120, a sacrificial layer 121 and a first dielectric layer 122 are sequentially deposited, as shown in FIG. Figure 5a to Figure 5d As shown in .

[0121] In one example, the substrate 11 includes but is not limited to a silicon substrate or a silicon-based substrate.

[0122] In one example, the sacrificial layer 121 includes, but is not limited to, a nitride layer, such as a silicon nitride layer.

[0123] In one example, the first dielectric layer 122 includes but is not limited to an oxide layer, such as a silicon oxide layer.

[0124] Optional, see Figure 4a to Figure 4d A first shallow trench 120 is formed on the substrate 11, which can be achieved by using a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process.

[0125] Optional, see Figure 5a to Figure 5d After sequentially depositing the sacrificial layer 121 and the first dielectric layer 122 in the first shallow trench 120, the resulting structure may be subjected to chemical mechanical polishing (CMP) to ensure surface planarization. Deposition processes include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0126] In step S12, refer to Figure 3 S12 and Figure 2 、 Figure 6a to Figure 6d A plurality of word line isolation trenches 21 are formed in the substrate 11 . The word line isolation trenches 21 are located above the sacrificial layer 121 and extend along a second direction that intersects the first direction.

[0127] Optionally, the second direction is perpendicular to the first direction, and the second direction is, for example, a row direction.

[0128] Optionally, a plurality of word line isolation trenches 21 are formed in the substrate 11 , which may be achieved by using a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process.

[0129] It is understandable that after the word line isolation trench 21 is formed, a portion of the material of the substrate 11 located in the active area is removed, thereby obtaining a plurality of columnar structures 20 .

[0130] Based on this, in an example, see Figure 6a to Figure 6d The method for preparing the semiconductor structure further includes: performing ion implantation on the lower and upper portions of the columnar structure 20 to form a source electrode, a drain electrode, and a conductive channel located between the source electrode and the drain electrode. The source electrode is located at the lower portion of the columnar structure 20, and the drain electrode is located at the upper portion of the columnar structure 20. The types of ions implanted to form the source and drain electrodes vary, and this is not specifically limited in the presently disclosed embodiments. Furthermore, the depth of the ion implantation required to form the source and drain electrodes can be selected and set according to actual needs.

[0131] Optional, see Figure 6a to Figure 6d The method for preparing the semiconductor structure further includes depositing a barrier layer 210 on the upper surface of the substrate 11 after forming the word line isolation trench 21 before ion implantation of the pillar structure 20. The barrier layer 210 protects the upper surface of the substrate 11 from being affected by the ion implantation.

[0132] In step S13, refer to Figure 3 S13 and Figure 2 、 Figure 7a to Figure 7d A second dielectric layer 22 is formed on the sidewall of the word line isolation trench 21 . The inner side of the second dielectric layer 22 has a pore H penetrating to the substrate 11 .

[0133] In one example, the second dielectric layer 22 includes but is not limited to an oxide layer, such as a silicon oxide layer. The second dielectric layer 22 may be formed by a deposition process, such as an atomic layer deposition process.

[0134] Here, the pores H within the second dielectric layer 22 are used to expose a portion of the surface of the substrate 11. The size of the pores H can be set according to process requirements. After the second dielectric layer 22 is deposited, if the size of the pores H is smaller than the desired size, the desired size can be restored by etching away a portion of the second dielectric layer 22.

[0135] In step S14, refer to Figure 3 S14 and Figure 2 、 Figure 8a to Figure 8d Based on the hole H, the lower portion of the active area is metallized to form a bit line 10, and the bit line 10 extends along the first direction.

[0136] In one example, based on the pores H, the lower portion of the active region is metallized to form the bit line 10 , which includes: injecting metal ions from the pores H to metallize the lower portion of the active region to form the bit line 10 .

[0137] Here, the bit line 10 is prepared as described above, and the lower surface of the bit line 10 is wavy along its extending direction.

[0138] Optionally, the metal ions include, but are not limited to, cobalt (Co) ions. When substrate 11 is a silicon substrate or a silicon-based substrate, the bit line 10 material after the active area is metallized with cobalt ions is cobalt silicide. Thus, bit line 10 composed of a metal silicide, such as cobalt silicide, can have a lower resistance, thereby improving the electrical performance of the semiconductor structure.

[0139] In addition, the second dielectric layer 22 formed on the sidewalls of the word line isolation trench 21 in step S13 can effectively protect the portion of the substrate 11 located in the corresponding area from being metallized by metal ions during the execution of step S14 .

[0140] In step S15, refer to Figure 3 S15 and Figure 2 、 Figure 9a to Figure 9d Based on the hole H, the sacrificial layer 121 is removed to form an air gap 110 between adjacent bit lines 10 .

[0141] In one example, sacrificial layer 121 is, for example, a silicon nitride layer. Sacrificial layer 121 can be removed by wet etching, for example, using a phosphoric acid etching solution. Specifically, the phosphoric acid etching solution enters from the D-D' direction in FIG. 9 and then flows along the BB' direction to etch away sacrificial layer 121.

[0142] Please continue reading Figure 3 In some embodiments, the method for preparing a semiconductor structure further includes the following steps.

[0143] S16, forming a third dielectric layer on the sidewalls of the air gap and in the pores.

[0144] S17 , removing a portion of the first dielectric layer and a portion of the second dielectric layer to form a plurality of first openings.

[0145] S18 , forming a fourth dielectric layer in the first opening, wherein the fourth dielectric layer has a second opening.

[0146] S19 , based on the second opening, continue to remove a portion of the first dielectric layer and a portion of the second dielectric layer to form a word line trench.

[0147] S20 , forming a gate dielectric layer on the sidewalls of the word line trench.

[0148] S21 , forming a gate word line in the word line trench.

[0149] In the disclosed embodiment, the third dielectric layer can be used to effectively seal the air gap between adjacent bit lines, better insulate the bit lines from each other, or from the gate word lines, thereby further reducing the parasitic capacitance between lines and improving the electrical performance of the semiconductor structure.

[0150] In step S16, refer to Figure 3 S16 and Figure 2 、 Figures 10a to 10d , a third dielectric layer 23 is formed on the sidewalls of the air gap 110 and in the pore H.

[0151] Here, the third dielectric layer 23 may be formed by a deposition process, such as physical vapor deposition or atomic layer deposition.

[0152] Optionally, the depth-to-width ratio of the pore H is relatively large, and the third dielectric layer 23 is formed by a physical vapor deposition process.

[0153] Optionally, the depth-to-width ratio of the pore H is relatively small, and the third dielectric layer 23 is formed by an atomic layer deposition process.

[0154] In step S17, refer to Figure 3 S17 and Figure 2 、 Figures 11a to 11d , a portion of the first dielectric layer 122 and a portion of the second dielectric layer 22 are removed to form a plurality of first openings K1.

[0155] In one example, the first dielectric layer 122 and the second dielectric layer 22 are made of the same material, such as silicon oxide layers. The portions to be removed in the first dielectric layer 122 and the second dielectric layer 22 can be removed by the same etching process.

[0156] Here, the shape and size of the first opening K1 can be set according to actual needs. In combination with some of the above embodiments, it can be seen that the source, conductive channel and drain are arranged in sequence from bottom to top along the columnar structure 20; the first opening K1 is used to expose the drain.

[0157] In step S18, refer to Figure 3 S18 and Figure 2 、 Figures 12a to 12d A fourth dielectric layer 24 is formed in the first opening K1 , and the fourth dielectric layer 24 has a second opening K2 .

[0158] Here, the fourth dielectric layer 24 includes but is not limited to a nitride layer, such as a silicon nitride layer. The second opening K2 penetrates the fourth dielectric layer 24 along the thickness direction.

[0159] Optionally, the fourth dielectric layer 24 is formed by first forming a fourth dielectric material layer through a deposition process, and then removing the fourth dielectric material layer through etching to form the second opening K2, thereby obtaining the fourth dielectric layer 24. The fourth dielectric material layer is formed by, for example, an atomic layer deposition process.

[0160] In the embodiment of the present disclosure, the fourth dielectric layer 24 having the second opening K2 is formed in the first opening K1 , which can help the fourth dielectric layer effectively support the portion of the third dielectric layer 23 located in the pore H, thereby facilitating the subsequent word line trench formation process.

[0161] In step S19, refer to Figure 3 S19 and Figure 2 、 Figures 13a to 13d Based on the second opening K2 , a portion of the first dielectric layer 122 and a portion of the second dielectric layer 22 are continuously removed to form a word line trench 25 .

[0162] As can be seen from the aforementioned embodiments, the source, the conductive channel and the drain are sequentially arranged from bottom to top along the columnar structure 20 , and the word line trench 25 is used to expose the conductive channel.

[0163] In an example, see Figure 13b The total thickness T1 of the removed first dielectric layer 122 is one-third to two-thirds of the initial thickness T0 of the first dielectric layer 122. Optionally, T1 is one-third, two-fifths, one-half, three-fifths, or two-thirds of T0.

[0164] In step S20, refer to Figure 3 S20 and Figure 2 、 Figures 14a to 14d , a gate dielectric layer 26 is formed on the sidewalls of the word line trench 25 .

[0165] In one example, forming the gate dielectric layer 26 on the sidewalls of the word line trench 25 includes: using a thermal oxidation process to form the gate dielectric layer 26 on the sidewalls of the word line trench 25. The gate dielectric layer 26 is, for example, a silicon oxide layer.

[0166] Optional, see Figures 14a to 14d The structure obtained after forming the wordline trenches 25 is placed in an oxidizing environment. For example, an oxidant gas flow is introduced into the structure obtained after forming the wordline trenches 25. The structure is then placed in a high-temperature environment to convert the material of the sidewalls of the wordline trenches 25 from silicon to silicon oxide. The temperature of the high-temperature environment can be selected based on actual needs and is not limited in the present embodiment. Here, the upper surface of the substrate 11 is also easily oxidized to form an oxide layer 260.

[0167] In step S21, refer to Figure 3 S21 and Figure 2 、 Figures 15a to 15d , a gate word line 30 is formed in the word line trench 25 .

[0168] In one example, forming the gate word line 30 in the word line trench 25 includes filling the word line trench 25 with titanium nitride material to form the gate word line 30 .

[0169] Here, the titanium nitride material may be filled by an atomic layer deposition process, and after the filling process is completed, excess filling material may be removed by a wet etching process.

[0170] As can be seen from the aforementioned embodiments, the source, conductive channel, and drain are arranged sequentially from bottom to top along the columnar structure 20. After the gate word line 30 is formed, the gate word line 30 surrounds the conductive channel, and the aforementioned gate dielectric layer 26 is formed between the gate word line 30 and the conductive channel.

[0171] Please continue reading Figure 3 In some embodiments, the method for preparing a semiconductor structure further includes the following steps.

[0172] S22 , filling the second opening with a fifth dielectric layer, wherein the upper surface of the fifth dielectric layer is flush with the upper surface of the fourth dielectric layer.

[0173] S23 , forming a storage node contact structure on the top surface of the columnar structure.

[0174] S24 , forming a storage capacitor on the storage node contact structure.

[0175] In step S22, refer to Figure 3 S22 and Figure 2 、 Figures 16a to 6d A fifth dielectric layer 27 is filled in the second opening K2 , and the upper surface of the fifth dielectric layer 27 is flush with the upper surface of the fourth dielectric layer 24 .

[0176] In one example, the material of the fifth dielectric layer 27 is the same as that of the fourth dielectric layer 24 , such as silicon nitride.

[0177] Optionally, filling the second opening K2 with the fifth dielectric layer 27 includes: depositing a fifth dielectric material layer in the second opening K2, and performing chemical mechanical polishing on the resulting structure to ensure that the upper surface of the fifth dielectric layer 27 is flush with the upper surface of the fourth dielectric layer 24. In this way, the upper surface of the resulting structure after the fifth dielectric layer 27 is formed has good surface quality, facilitating the subsequent preparation of the storage node contact structure 4 and ensuring good contact between the storage node contact structure 4 and the drain.

[0178] In step S23, refer to Figure 3 S23 and Figure 2 、 Figure 17a 、 Figure 17b , a storage node contact structure 4 is formed on the top surface of the columnar structure 20 .

[0179] As can be seen from the above embodiments, the source, the conductive channel and the drain are arranged in sequence from bottom to top along the columnar structure 20. After the storage node contact structure 4 is formed, the storage node contact structure 4 is connected to the drain contact.

[0180] The structure of the storage node contact structure 4 can be selected and set according to actual needs. Optionally, the storage node contact structure 4 is a metal pad, such as a tungsten pad. This can ensure that the storage node contact structure 4 has a low resistance value and high stability.

[0181] In step S24, refer to Figure 3 S24 and Figure 2 、 Figure 17a 、 Figure 17b , a storage capacitor 3 is formed on the storage node contact structure 4.

[0182] The structure of the storage capacitor 3 can be selected and set according to actual needs. Optionally, the storage capacitor 3 is a columnar capacitor, but is not limited to this. The use of a columnar capacitor for the storage capacitor 3 is conducive to improving the distribution density of the storage capacitor 3 in the semiconductor structure.

[0183] Some embodiments of the present disclosure also provide a semiconductor structure, which is prepared using the semiconductor structure preparation method described in some of the above embodiments. Figure 1 、 Figure 2 、 Figure 17a and Figure 17b The semiconductor structure includes a substrate 11 and a plurality of bit lines 10. The substrate 11 has a plurality of active regions spaced apart from each other, extending along a first direction. The plurality of bit lines 10 are spaced apart and arranged in parallel below the active regions, with air gaps 110 between adjacent bit lines 10.

[0184] The embodiment of the present disclosure sets an air gap 110 between adjacent bit lines 10. The air gap 110 can be used to effectively eliminate the mutual coupling between bit lines 10 and bit lines 10, or between bit lines 10 and gate word lines, thereby effectively reducing the parasitic capacitance between lines and improving the electrical performance of the semiconductor structure.

[0185] Bit line 10 is fabricated using the fabrication methods described in some of the aforementioned embodiments. The lower surface of bit line 10 is wavy along its extension direction. Optionally, bit line 10 is made of cobalt silicide. This allows bit line 10 to have a lower resistance, thereby improving the electrical performance of the semiconductor structure.

[0186] In some embodiments, please refer to Figure 1 、 Figure 2 、 Figure 17a and Figure 17b The semiconductor structure further includes an insulating isolation structure 5 and a plurality of gate word lines 30. The plurality of gate word lines 30 are located above the bit lines 10 and are arranged parallel to and spaced apart from each other along a second direction. The second direction intersects the first direction, for example, is perpendicular to the first direction. The insulating isolation structure 5 is located between adjacent gate word lines 30 and between the gate word lines 30 and the bit lines 10.

[0187] Optionally, the first direction is a column direction, and the second direction is a row direction.

[0188] It is understood that the insulating isolation structure 5 is composed of dielectric layers located between adjacent gate word lines 30 and between the gate word lines 30 and the bit lines 10. Therefore, in combination with the preparation methods described in some of the aforementioned embodiments, it can be seen that the insulating isolation structure 5 includes: the first dielectric layer 122, the second dielectric layer 22, and the third dielectric layer 23 after removing some materials, as well as the fourth dielectric layer 24 and the fifth dielectric layer 27. The materials and structures of the dielectric layers in the insulating isolation structure 5 can be found in the relevant descriptions of some of the aforementioned embodiments and will not be detailed here.

[0189] In the embodiment of the present disclosure, the insulating isolation structure 5 can be used to effectively seal the air gap 110 between adjacent bit lines 10 and to well insulate the adjacent gate word lines 30, as well as the gate word lines 30 and the bit lines 10, thereby further reducing the parasitic capacitance between lines and improving the electrical performance of the semiconductor structure.

[0190] In some embodiments, please refer to Figure 1 、 Figure 2 、 Figure 17a and Figure 17b The semiconductor structure further includes: a columnar structure 20, a source 201, a drain 203, and a conductive channel 202. The columnar structure 20 is located in the active area, the bottom of the columnar structure 20 is in contact with the bit line 10, and the top of the columnar structure 20 passes through the gate word line 30 and extends above the gate word line 30. The source 201 is located in the columnar structure 20 and is located between the gate word line 30 and the bit line 10. The drain 203 is located in the columnar structure 20 and is located above the gate word line 30. The conductive channel 202 is located in the columnar structure 20 and is located between the source 201 and the drain 203. The gate word line 30 is located outside the conductive channel 202. The semiconductor structure further includes: a gate dielectric layer 26 located between the conductive channel 202 and the gate word line 30.

[0191] With reference to the preparation methods in some of the aforementioned embodiments, it can be seen that the source 201 and the drain 203 are respectively obtained by performing ion implantation on corresponding regions of the columnar structure 20 .

[0192] In one example, the gate word line 30 is made of titanium nitride and surrounds the conductive channel 202 .

[0193] In one example, the gate dielectric layer 26 is made of silicon oxide and can be formed by a thermal oxidation process.

[0194] In some embodiments, please refer to Figure 1 、 Figure 2 、 Figure 17a and Figure 17b The semiconductor structure further includes a storage node contact structure 4 and a storage capacitor 3. The storage node contact structure 4 is located above the columnar structure 20 and is in contact with the drain 203. The storage capacitor 3 is located above the storage node contact structure 4 and is in contact with the storage node contact structure 4.

[0195] The structure of the storage node contact structure 4 can be selected and set according to actual needs. Optionally, the storage node contact structure 4 is a metal pad, such as a tungsten pad. This can ensure that the storage node contact structure 4 has a low resistance value and high stability.

[0196] The structure of the storage capacitor 3 can be selected and set according to actual needs. Optionally, the storage capacitor 3 is a columnar capacitor, which is conducive to improving the distribution density of the storage capacitor 3 in the semiconductor structure.

[0197] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0198] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, forming a first shallow trench isolation structure on the substrate, wherein the first shallow trench isolation structure isolates a plurality of active regions in the substrate, and the active regions extend along a first direction; The first shallow trench isolation structure includes a sacrificial layer and a first dielectric layer stacked sequentially from bottom to top; forming a plurality of word line isolation trenches in the substrate, wherein the word line isolation trenches are located above the sacrificial layer and extend along a second direction intersecting the first direction; forming a second dielectric layer on the sidewall of the word line isolation trench, wherein the second dielectric layer has a pore extending through the substrate; Based on the pores, metallizing a lower portion of the active area to form a bit line, wherein the bit line extends along the first direction; The sacrificial layer is removed based on the pores to form air gaps between adjacent bit lines.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The preparation method further comprises: forming a third dielectric layer on the sidewalls of the air gap and in the pores; removing a portion of the first dielectric layer and a portion of the second dielectric layer to form a plurality of first openings; forming a fourth dielectric layer in the first opening, wherein the fourth dielectric layer has a second opening; Based on the second opening, continue to remove a portion of the first dielectric layer and a portion of the second dielectric layer to form a word line trench; forming a gate dielectric layer on the sidewalls of the word line trench; A gate word line is formed in the word line trench.

3. The method for preparing a semiconductor structure according to claim 2, wherein: The forming of a gate dielectric layer on the sidewall of the word line trench comprises: A thermal oxidation process is adopted to form a gate dielectric layer on the sidewall of the word line trench; the gate dielectric layer includes a silicon oxide layer.

4. The method for preparing a semiconductor structure according to claim 2, wherein: The forming of a gate word line in the word line trench comprises: The word line trench is filled with titanium nitride material to form the gate word line.

5. The method for preparing a semiconductor structure according to claim 2, wherein: After forming the word line trenches, a portion of the active area is removed to form a columnar structure between adjacent word line trenches; Before forming the second dielectric layer on the sidewalls of the word line isolation trench, the preparation method further includes: Performing ion implantation on the lower portion and the upper portion of the columnar structure to form a source electrode, a drain electrode, and a conductive channel between the source electrode and the drain electrode; Wherein, the gate word line surrounds the periphery of the conductive channel.

6. The method for preparing a semiconductor structure according to claim 5, wherein: The source, the conductive channel, and the drain are sequentially arranged from bottom to top along the columnar structure; the first opening exposes the drain, and the word line trench exposes the conductive channel.

7. The method for preparing a semiconductor structure according to claim 2, wherein: The total thickness of the removed first dielectric layer is one third to two thirds of the initial thickness of the first dielectric layer.

8. The method for preparing a semiconductor structure according to claim 2, wherein: After forming the word line trenches, a portion of the active area is removed to form a columnar structure between adjacent word line trenches; The preparation method further comprises: Filling the second opening with a fifth dielectric layer, wherein the upper surface of the fifth dielectric layer is flush with the upper surface of the fourth dielectric layer; forming a storage node contact structure on a top surface of the columnar structure; A storage capacitor is formed on the storage node contact structure.

9. The method for preparing a semiconductor structure according to any one of claims 1 to 8, wherein: The step of metallizing a lower portion of the active area based on the pores to form a bit line comprises: Metal ions are injected from the pores to metallize the lower portion of the active region to form the bit line; the metal ions include cobalt ions.

10. A vertical wrap-around gate transistor semiconductor structure, characterized in that: include: A substrate having a plurality of active regions arranged at intervals, wherein the active regions extend along a first direction; and, a plurality of bit lines arranged in parallel and spaced apart in a lower portion of the active region; There is an air gap between adjacent bit lines, and the first direction is an extension direction of the bit lines; a plurality of gate word lines, located above the bit lines, the gate word lines being arranged in parallel and spaced apart along a second direction, the second direction intersecting the first direction; The insulating isolation structure is located between adjacent gate word lines and between the gate word lines and the bit lines.

11. The vertical gate-all-around transistor semiconductor structure according to claim 10, wherein: The semiconductor structure further comprises: a columnar structure located in the active area; a bottom of the columnar structure contacts the bit line, and a top of the columnar structure passes through the gate word line and extends above the gate word line; a source electrode located in the columnar structure and between the gate word line and the bit line; a drain electrode, located in the columnar structure and above the gate word line; A conductive channel is located in the columnar structure and between the source and the drain; the gate word line is located outside the conductive channel.

12. The vertical gate-all-around transistor semiconductor structure according to claim 11, wherein: The semiconductor structure further includes a gate dielectric layer located between the conductive channel and the gate word line.

13. The vertical gate-all-around transistor semiconductor structure according to claim 11, wherein: The material of the gate word line includes titanium nitride.

14. The vertical gate-all-around transistor semiconductor structure according to claim 11, wherein: The semiconductor structure further comprises: a storage node contact structure, located above the columnar structure and connected to the drain contact; And, a storage capacitor is located above the storage node contact structure and is in contact with the storage node contact structure.

15. The vertical wrap-around gate transistor semiconductor structure according to any one of claims 11 to 14, wherein: The material of the bit line includes cobalt silicide.

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