Semiconductor structure and method of fabrication

Abstract

The application discloses a semiconductor structure and a preparation method thereof. The preparation method comprises the following steps: forming a first patterned mask layer on the upper surface of a first filling medium layer, wherein the first patterned mask layer comprises a plurality of pattern units, and the orthographic projection of each pattern unit on the substrate crosses the bit line and is partially located on the opposite sides of the bit line; etching the first filling medium layer based on the first patterned mask layer to form an etching groove; filling the etching groove with a second filling medium layer and covering the first patterned mask layer; removing the first patterned mask layer, the part of the second filling medium layer located on the first patterned mask layer and the part of the second filling medium layer located between the pattern units; removing the residual first filling medium layer to form a plurality of capacitor contact holes exposing the substrate; and forming capacitor contact structures located on the opposite sides of the bit line in the capacitor contact holes. The new half-moon-shaped capacitor contact structure always maintains a large effective contact area with the active region, and greatly reduces the BL parasitic capacitance.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] With the rapid development of semiconductor memory technology, device sizes are shrinking and device density is increasing, posing significant challenges to manufacturing processes. For dynamic random access memory (DRAM), the storage node contact (SNC) structure typically connects the substrate and shallow trench isolation structure at its lower portion, while its top portion connects to the bottom electrode plate of the storage capacitor, electrically connecting the transistor to the storage capacitor.

[0003] As device dimensions continue to shrink, the overlap between the SNC and the active area within the substrate becomes increasingly severe. Parasitic capacitance of the bitline structure on the substrate primarily arises between the SNC and the bitline structure (BL). To reduce BL parasitic capacitance, the SNC area is typically minimized. However, while this reduction in SNC area improves parasitic capacitance, it also reduces the contact area between the SNC and the active area, degrading semiconductor device performance. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor structure and preparation method to address the problems in the above-mentioned background technology, and propose a crescent-shaped capacitor contact structure distributed on both sides of the bit line structure. The capacitor contact structure and the active area always have a large effective contact area, which reduces the parasitic capacitance between the BL and the capacitor contact structure, improves the performance of the semiconductor structure, and effectively solves the problem of overlap between the capacitor contact structure and the active area.

[0005] To solve the above technical problems, the first aspect of the present application provides a method for preparing a semiconductor structure, comprising:

[0006] Providing a substrate having active regions spaced apart from each other, and forming a plurality of bit lines spaced apart from each other in parallel on the substrate;

[0007] forming a first filling dielectric layer, wherein the first filling dielectric layer fills the gaps between adjacent bit lines and covers the tops of the bit lines;

[0008] forming a first patterned mask layer on the upper surface of the first filling dielectric layer, wherein the first patterned mask layer includes a plurality of pattern units, wherein an orthographic projection of each of the pattern units on the substrate spans the bit line and is partially located on two opposite sides of the bit line;

[0009] etching the first filling dielectric layer based on the first patterned mask layer to form an etched groove, wherein the etched groove exposes the substrate;

[0010] forming a second filling dielectric layer, wherein the second filling dielectric layer fills the etched groove and covers the first patterned mask layer;

[0011] removing the first patterned mask layer and the second filling dielectric layer located on the first patterned mask layer and between the pattern units;

[0012] Removing the remaining first filling dielectric layer to form a plurality of capacitor contact holes, wherein the capacitor contact holes expose the substrate; each of the capacitor contact holes includes a first sub-contact hole and a second sub-contact hole respectively located on opposite sides of the bit line;

[0013] A capacitor contact structure is formed in the capacitor contact hole, wherein the capacitor contact structure includes a first sub-contact structure corresponding to the first sub-contact hole and a second sub-contact structure corresponding to the second sub-contact hole.

[0014] In one embodiment, forming a first patterned mask layer on the upper surface of the first filling dielectric layer includes:

[0015] forming a first mask dielectric layer, a first hard mask layer, a second mask dielectric layer, a third mask dielectric layer, a second hard mask layer and a fourth mask dielectric layer stacked sequentially from bottom to top on the upper surface of the first filling dielectric layer;

[0016] forming a second patterned mask layer on the upper surface of the fourth mask dielectric layer, wherein a plurality of first opening patterns arranged in multiple rows and columns are formed in the second patterned mask layer;

[0017] Etching the fourth mask dielectric layer and the second hard mask layer based on the second patterned mask layer, and performing a first etching on the third mask dielectric layer to form a second opening pattern corresponding to the first opening pattern in the third mask dielectric layer;

[0018] removing the second patterned mask layer, the fourth mask dielectric layer, and the second hard mask layer;

[0019] forming a third hard mask layer and a fifth mask dielectric layer stacked sequentially from bottom to top, wherein the third hard mask layer fills the second opening pattern and covers the third mask dielectric layer after the first etching;

[0020] forming a third patterned mask layer on the upper surface of the fifth mask dielectric layer, wherein a plurality of third opening patterns arranged in multiple rows and columns are formed in the third patterned mask layer, wherein an orthographic projection of the third opening patterns in each column on the upper surface of the third mask dielectric layer after the first etching is located between the second opening patterns in an adjacent column and the third opening patterns are arranged in a staggered manner relative to the second opening patterns in the adjacent column;

[0021] Sequentially etching the fifth mask dielectric layer and the third hard mask layer based on the third patterned mask layer, and performing a second etching on the third mask dielectric layer to transfer the third opening pattern into the third mask dielectric layer;

[0022] removing the third patterned mask layer, the fifth mask dielectric layer, and the third hard mask layer;

[0023] Etching the second mask dielectric layer and the first hard mask layer based on the third mask dielectric layer after the second etching to obtain a fourth patterned mask layer, wherein a fourth opening pattern corresponding to the second opening pattern and the third opening pattern is formed in the fourth patterned mask layer;

[0024] forming a third filling dielectric layer, wherein the third filling dielectric layer fills the fourth opening pattern and covers the fourth patterned mask layer;

[0025] The third filling dielectric layer on the fourth patterned mask layer is removed, and the fourth patterned mask layer is removed based on the retained third filling dielectric layer, and the first mask dielectric layer is etched to obtain the first patterned mask layer.

[0026] In one embodiment, after forming the first patterned mask layer, the method further includes:

[0027] The remaining third filling medium layer is removed.

[0028] In one embodiment, the shape of the first opening pattern, the shape of the second opening pattern, and the shape of the third opening pattern are all circular, and the shape of the first sub-contact hole, the shape of the second sub-contact hole, the shape of the first sub-contact structure, and the shape of the second sub-contact structure are all crescent-shaped.

[0029] In one embodiment, the capacitor contact structures are arranged in multiple rows and columns, and the capacitor contact structures in adjacent columns are staggered.

[0030] In one embodiment, forming a capacitor contact structure in the capacitor contact hole includes:

[0031] forming a capacitor contact material layer, wherein the capacitor contact material layer fills the capacitor contact hole and covers the bit line and the second filling dielectric layer;

[0032] The capacitor contact material layer located on the bit line and the second filling dielectric layer is removed, and the capacitor contact material layer located in the capacitor contact hole is etched back to obtain the capacitor contact structure; the upper surface of the capacitor contact structure is lower than the upper surface of the bit line.

[0033] In one embodiment, a shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure isolates a plurality of active areas arranged in an array in the substrate; the bottom of the capacitor contact structure is in contact with the active area.

[0034] In one embodiment, a covering dielectric layer is formed on the upper surface of the substrate; after removing the remaining first filling dielectric layer and before forming a capacitor contact structure in the capacitor contact hole, it also includes: removing the covering dielectric layer in the capacitor contact hole so that the capacitor contact hole passes through the covering dielectric layer to expose the active area.

[0035] In one embodiment, a plurality of buried gate word lines arranged in parallel and at intervals are further formed in the substrate, and an extension direction of the buried gate word lines intersects with an extension direction of the bit lines and an extension direction of the active region.

[0036] A second aspect of the present application provides a semiconductor structure, comprising:

[0037] A substrate having active regions spaced apart therein and a plurality of bit lines spaced apart and arranged in parallel thereon;

[0038] A filling dielectric layer is located between adjacent bit lines;

[0039] A capacitor contact structure is located in the filling dielectric layer. The capacitor contact structure includes a first sub-contact structure and a second sub-contact structure. The first sub-contact structure and the second sub-contact structure are respectively located on two opposite sides of the bit line.

[0040] In one embodiment, there are multiple capacitor contact structures, and the multiple capacitor contact structures are arranged in multiple rows and columns, and the capacitor contact structures in adjacent columns are staggered.

[0041] In one embodiment, the upper surface of the capacitor contact structure is lower than the upper surface of the bit line.

[0042] In one embodiment, the shape of the first sub-contact structure and the shape of the second sub-contact structure are both half-moon shaped.

[0043] In one embodiment, a shallow trench isolation structure is further included, wherein the shallow trench isolation structure isolates a plurality of active areas arranged in an array in the substrate; and the bottom of the capacitor contact structure contacts the active area.

[0044] In one embodiment, a plurality of buried gate word lines arranged in parallel and at intervals are further formed in the substrate, and an extension direction of the buried gate word lines intersects with an extension direction of the bit lines and an extension direction of the active region.

[0045] In one embodiment, the bit lines extend in a column direction, the buried gate word lines extend in a row direction, and the active region extends in a direction forming a preset angle with the bit lines.

[0046] In the semiconductor structure and preparation method provided in the above embodiment, a first patterned mask layer is formed on the upper surface of the first filling dielectric layer, including a plurality of pattern units. The orthographic projections of the plurality of pattern units on the substrate all cross the bit line and are partially located on opposite sides of the bit line. Based on the formed first patterned mask layer, etching is performed to form an etched groove, and the second filling dielectric layer fills the etched groove. The pattern units and the first filling dielectric layer are removed to obtain a plurality of capacitor contact holes exposing the substrate. The first sub-contact hole and the second sub-contact hole are respectively located on opposite sides of the bit line, and a capacitor contact structure is formed in the capacitor contact hole. The present application is based on the pattern units that cross opposite sides of the bit line. After masking, etching, and filling, a capacitor contact structure is finally formed on opposite sides of the bit line. Unlike the traditional capacitor contact structure located in the middle between the pattern unit and the bit line, as the size of the semiconductor structure decreases, this capacitor contact structure always maintains a large effective contact area with the active area, greatly reducing the parasitic capacitance between the BL and the capacitor contact structure, improving the performance of the semiconductor structure, and solving the increasingly serious overlap problem of the capacitor contact structure and the active area in the substrate.

[0047] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0049] Figure 1 A schematic flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present application;

[0050] Figure 2a is a top view of a semiconductor structure provided in one embodiment of the present application, Figure 2b for Figure 2a A three-dimensional view of the semiconductor structure taken along the AA' direction, Figure 2c for Figure 2b A partial enlarged view of area A in the middle. Figure 2d for Figure 2a Schematic diagram of the local cross-section structure taken along the AA' direction, Figure 2e for Figure 2d A partial enlarged view of the middle B area;

[0051] Figure 3a The structure obtained after forming the first mask dielectric layer, the first hard mask layer, the second mask dielectric layer, the third mask dielectric layer, the second hard mask layer and the fourth mask dielectric layer in one embodiment of the present application is as follows: Figure 2a The stereogram taken from the BB' direction, Figure 3b for Figure 3a A partial enlarged view of the middle C area. Figure 3c for Figure 2a Schematic diagram of the local cross-section structure taken along the BB' direction;

[0052] Figure 4a 1 is a top view of a structure obtained after forming a second patterned mask layer provided in one embodiment of the present application. Figure 4b for Figure 2a The stereogram taken along the BB' direction, Figure 4c for Figure 2a Schematic diagram of the local cross-section structure taken along the BB' direction;

[0053] Figure 5a 1 is a top view of a second opening pattern formed in a third mask dielectric layer provided in an embodiment of the present application. Figure 5b for Figure 2a The stereogram taken along the BB' direction, Figure 5c for Figure 2a Schematic diagram of the local cross-section structure taken along the BB' direction;

[0054] Figure 6a The structure obtained after the third hard mask layer and the fifth mask dielectric layer provided in an embodiment of the present application is along Figure 2a The stereogram taken from the BB' direction, Figure 6b for Figure 2a Schematic diagram of the local cross-section structure taken along the BB' direction;

[0055] Figure 7a 1 is a top view of forming a third patterned mask layer provided in one embodiment of the present application. Figure 7b for Figure 2a The stereogram taken along the BB' direction, Figure 7c for Figure 2a Schematic diagram of the local cross-section structure taken along the BB' direction;

[0056] Figure 8a 1 is a top view of forming a fourth patterned mask layer provided in one embodiment of the present application. Figure 8b for Figure 2a The stereogram taken along the BB' direction, Figure 8c for Figure 2a Schematic diagram of the local cross-section structure taken along the BB' direction;

[0057] Figure 9a The structure obtained after forming the third filling dielectric layer provided in an embodiment of the present application is along Figure 2a The stereogram taken from the BB' direction, Figure 9b for Figure 2a Schematic diagram of the local cross-section structure taken along the BB' direction;

[0058] Figure 10a 1 is a top view of a structure obtained after removing the third filling dielectric layer on the fourth patterned mask layer provided in an embodiment of the present application. Figure 10b for Figure 2a The stereogram taken along the BB' direction, Figure 10c for Figure 2a Schematic diagram of the local cross-section structure taken along the BB' direction;

[0059] Figure 11a This is a top view of a structure obtained after forming an etched trench according to an embodiment of the present application. Figure 11b for Figure 2a The stereogram taken along the BB' direction, Figure 11c for Figure 2a Schematic diagram of the local cross-section structure taken along the BB' direction;

[0060] Figure 12a The structure obtained after forming the second filling dielectric layer provided in an embodiment of the present application is along Figure 2a The stereogram taken from the BB' direction, Figure 12b for Figure 2a Schematic diagram of the local cross-section structure taken along the BB' direction;

[0061] Figure 13a FIG2 is a top view of a structure obtained after removing the first patterned mask layer and the portion of the second filling dielectric layer located on the first patterned mask layer and between the pattern units provided in one embodiment of the present application. Figure 13b for Figure 2a The stereogram taken along the BB' direction, Figure 13c for Figure 2a Schematic diagram of the local cross-section structure taken along the BB' direction;

[0062] Figure 14a The structure obtained after removing the remaining first filling dielectric layer provided in an embodiment of the present application is along Figure 2a The stereogram taken from the BB' direction, Figure 14b for Figure 2a Schematic diagram of the local cross-section structure taken along the BB' direction;

[0063] Figure 15a The structure obtained by removing the covering dielectric layer in the capacitor contact hole provided in one embodiment of the present application is along the Figure 2a The stereogram taken from the BB' direction, Figure 15b for Figure 2a Schematic diagram of the local cross-section structure taken along the BB' direction;

[0064] Figure 16a The structure obtained after forming the capacitor contact material layer provided in one embodiment of the present application is along Figure 2a The stereogram taken from the BB' direction, Figure 16b for Figure 2a Schematic diagram of the local cross-section structure taken along the BB' direction;

[0065] Figure 17a 1 is a top view of a structure obtained after forming a capacitor contact structure provided in an embodiment of the present application. Figure 17b for Figure 2a The stereogram taken along the BB' direction, Figure 17c for Figure 2a Schematic diagram of the local cross-section structure taken along the BB' direction.

[0066] Description of reference numerals: 10 - substrate, 11 - shallow trench isolation structure, 12 - active area, 13 - buried gate word line, 14 - bit line contact structure;

[0067] 15 - insulating dielectric layer, 151 - first insulating dielectric layer, 152 - second insulating dielectric layer;

[0068] 16-covering dielectric layer;

[0069] 20 - bit line, 21 - bit line, 211 - intrinsic polysilicon layer, 212 - first bit line conductive layer, 213 - second bit line conductive layer, 214 - third bit line conductive layer, 215 - fourth bit line conductive layer, 216 - bit line dielectric layer; 22 - bit line isolation structure, 221 - first isolation dielectric layer, 222 - second isolation dielectric layer, 223 - third isolation dielectric layer;

[0070] 23 - first filling dielectric layer, 231 - first sub-filling dielectric layer, 232 - second sub-filling dielectric layer, 233 - third sub-filling dielectric layer;

[0071] 31 - first mask dielectric layer, 32 - first hard mask layer, 33 - second mask dielectric layer, 34 - third mask dielectric layer, 35 - second hard mask layer, 36 - fourth mask dielectric layer;

[0072] 37-second patterned mask layer, 371-first opening pattern, 372-second opening pattern;

[0073] 38-a third hard mask layer, 39-a fifth mask dielectric layer;

[0074] 41-third patterned mask layer, 411-third opening pattern;

[0075] 42 - fourth patterned mask layer, 421 - fourth opening pattern, 43 - third filling dielectric layer;

[0076] 44-first patterned mask layer, 441-patterning unit;

[0077] 45-etching grooves;

[0078] 46-second filling dielectric layer;

[0079] 47 - capacitor contact hole, 471 - first sub-contact hole, 472 - second sub-contact hole;

[0080] 48-capacitor contact material layer;

[0081] 49 - capacitor contact structure, 491 - first sub-contact structure, 492 - second sub-contact structure. DETAILED DESCRIPTION

[0082] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0083] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0084] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0085] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0086] Embodiments of the present invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present invention. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the present invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. The regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device and are not intended to limit the scope of the present invention.

[0087] Nowadays, SNC is manufactured using the self-aligned double patterning (SDAP) process. During the manufacturing process, a graphic unit is formed in the same direction as the extension of the gate word line. The graphic unit and the bit line together form a checkerboard-shaped multiple capacitor contact holes. The SNC is square and fills the capacitor contact holes. It is located in the middle position between the graphic unit and the bit line, while the active area at the bottom is on one side. The contact area between the SNC and the active area is rapidly reduced. When ensuring a larger contact area between the SNC and the active area, the traditional SNC will prepare a larger SNC area, which will increase the ineffective area of ​​the SNC. The larger ineffective area will also lead to a larger BL parasitic capacitance. Therefore, the present application proposes a semiconductor structure in which the SNC is located on two opposite sides of the bit line and is in a half-moon shape. It always has a large effective contact area with the active area, improving the performance of the semiconductor structure while reducing the parasitic capacitance between the BL and the capacitor contact structure. Moreover, as the size of the device structure decreases, the effective contact area of ​​the SNC will also increase, solving the increasingly serious overlap problem between the SNC and the active area in the substrate.

[0088] In one embodiment of the present application, Figure 1 As shown, a method for preparing a semiconductor structure is provided, comprising the following steps:

[0089] Step S10: providing a substrate, wherein active regions are arranged at intervals in the substrate, and a plurality of bit lines are formed on the substrate in parallel and spaced apart arrangements;

[0090] Step S20: forming a first filling dielectric layer, the first filling dielectric layer filling the gaps between adjacent bit lines and covering the tops of the bit lines;

[0091] Step S30: forming a first patterned mask layer on the upper surface of the first filling dielectric layer, wherein the first patterned mask layer includes a plurality of pattern units, wherein the orthographic projection of each pattern unit on the substrate spans the bit line and is partially located on opposite sides of the bit line;

[0092] Step S40: etching the first filling dielectric layer based on the first patterned mask layer to form an etched groove, wherein the etched groove exposes the substrate;

[0093] Step S50: forming a second filling dielectric layer, the second filling dielectric layer filling the etched groove and covering the first patterned mask layer;

[0094] Step S60: removing the first patterned mask layer and the second filling dielectric layer located on the first patterned mask layer and between the pattern units;

[0095] Step S70: removing the remaining first filling dielectric layer to form a plurality of capacitor contact holes, wherein the capacitor contact holes expose the substrate; each capacitor contact hole includes a first sub-contact hole and a second sub-contact hole located on opposite sides of the bit line;

[0096] Step S80 : forming a capacitor contact structure in the capacitor contact hole, the capacitor contact structure including a first sub-contact structure corresponding to the first sub-contact hole and a second sub-contact structure corresponding to the second sub-contact hole.

[0097] The present application is based on graphic units spanning opposite sides of the bit line. After masking, etching, and filling steps, a capacitor contact structure is finally formed on opposite sides of the bit line. Unlike traditional capacitor contact structures located in the middle between the graphic unit and the bit line, as the size of the semiconductor structure decreases, this capacitor contact structure always maintains a large effective contact area with the active area, greatly reducing the parasitic capacitance between the BL and the capacitor contact structure, improving the performance of the semiconductor structure, and solving the increasingly serious overlap problem between the capacitor contact structure and the active area in the substrate.

[0098] In one embodiment, Figure 2a As shown, the substrate 10 provided in step S10 includes but is not limited to a silicon substrate; a shallow trench isolation structure 11 is formed in the substrate 10, and the shallow trench isolation structure 11 isolates a plurality of active regions 12 arranged in an array in the substrate 10. Ions are implanted into the active region 12 using IMP technology to form a source region and a drain region ( Figure 2a A plurality of buried gate word lines 13 are formed in the substrate 10 and arranged in parallel and spaced apart. The extending direction of the buried gate word lines 13 intersects with the extending direction of the bit lines 20 and the extending direction of the active region 12.

[0099] As an example, Figure 2b 、 Figure 2c 、 Figure 2d and Figure 2e As shown, a cover dielectric layer 16 is formed on the upper surface of the substrate 10. The material of the cover dielectric layer 16 includes, but is not limited to, Si3N4 or SiO2. A portion of the bit line 20 is formed on the upper surface of the cover dielectric layer 16. An insulating dielectric layer 15 is also provided between the bit line 20 and the shallow trench isolation structure 11. The insulating dielectric layer 15 includes a first insulating dielectric layer 151 and a second insulating dielectric layer 152. The second insulating dielectric layer 152 is located within the first insulating dielectric layer 151 and is in contact with the substrate 10, the shallow trench isolation structure 11, and the cover dielectric layer 16.

[0100] As an example, the bitline 20 includes a bitline 21 and a bitline isolation structure 22 located on the sidewalls of the bitline 21. The bitline 21 includes, from bottom to top, an intrinsic polysilicon layer 211, a first bitline conductive layer 212, a second bitline conductive layer 213, a third bitline conductive layer 214, a fourth bitline conductive layer 215, and a bitline dielectric layer 216. A bitline contact structure 14 is also provided between the substrate 10 and the bitline 21. The bitline contact structure 14 is located between the first bitline conductive layer 212 and the substrate 10. The bitline contact structure 14 includes, but is not limited to, a doped polysilicon layer. The material of the first bit line conductive layer 212 includes but is not limited to Ti, the material of the second bit line conductive layer 213 includes but is not limited to TSN, the material of the third bit line conductive layer 214 includes but is not limited to WSi, and the material of the fourth bit line conductive layer 215 includes but is not limited to W; the material of the bit line dielectric layer 216 includes but is not limited to Si3N4, and can be prepared using low pressure chemical vapor deposition technology (LPCVD).

[0101] As an example, the bit line isolation structure 22 includes a first isolation dielectric layer 221, a second isolation dielectric layer 222, and a third isolation dielectric layer 223, which are sequentially distributed from the bit line 21 outward. The bit line isolation structure 22 can be a Si3N4-SiO2-Si3N4, i.e., a "NON" sandwich structure, or an "ONO" structure. The bit line isolation structure 22 can be a sandwich structure sequentially stacked from the bit line 21 outward, or the first isolation dielectric layer 221 and the third isolation dielectric layer 223 can be in contact. Figure 2b and Figure 2c As an example, the top of the first isolation dielectric layer 221 contacts the top of the second isolation dielectric layer 222. The material of the first isolation dielectric layer 221 and the material of the third isolation dielectric layer 223 may include, but are not limited to, Si3N4, and may be prepared using atomic deposition (ALD).

[0102] In one embodiment, please refer to Figure 2b and Figure 2c The first filling dielectric layer 23 formed in step S20 includes a first sub-filling dielectric layer 231, a second sub-filling dielectric layer 232, and a third sub-filling dielectric layer 233. The first sub-filling dielectric layer 231 covers the sidewalls of the bitline isolation structure 22; the second sub-filling dielectric layer 232 fills the gaps between adjacent bitlines 20; and the third sub-filling dielectric layer 233 covers the tops of the bitlines 20, the first sub-filling dielectric layer 231, and the second sub-filling dielectric layer 232. The materials of the first sub-filling dielectric layer 231 and the third sub-filling dielectric layer 233 include, but are not limited to, SiO2, and can be prepared using TEOS, LTO, or ALD technology; the material of the second sub-filling dielectric layer 232 includes, but is not limited to, spin-on dielectrics (SOD).

[0103] In one embodiment, step S30: forming a first patterned mask layer on the upper surface of the first filling dielectric layer includes the following steps:

[0104] Step S301: forming a first mask dielectric layer 31, a first hard mask layer 32, a second mask dielectric layer 33, a third mask dielectric layer 34, a second hard mask layer 35 and a fourth mask dielectric layer 36 stacked in sequence from bottom to top on the upper surface of the first filling dielectric layer 23, as shown in FIG. Figure 3a 、 Figure 3b and Figure 3c As shown;

[0105] Step S302: forming a second patterned mask layer 37 on the upper surface of the fourth mask dielectric layer 36, wherein a plurality of first opening patterns 371 arranged in multiple rows and columns are formed in the second patterned mask layer 37. Figure 4a 、 Figure 4b and Figure 4c As shown;

[0106] Step S303: etching the fourth mask dielectric layer 36 and the second hard mask layer 35 based on the second patterned mask layer 37, and performing a first etching on the third mask dielectric layer 34 to form a second opening pattern 372 corresponding to the first opening pattern 371 in the third mask dielectric layer 34. Figure 5a 、 Figure 5b and Figure 5c As shown;

[0107] Step S304: Remove the second patterned mask layer 37, the fourth mask dielectric layer 36 and the second hard mask layer 35. Figure 5b and Figure 5c ;

[0108] Step S305: forming a third hard mask layer 38 and a fifth mask dielectric layer 39 stacked from bottom to top, wherein the third hard mask layer 38 fills the second opening pattern 372 and covers the third mask dielectric layer 34 after the first etching. Figure 6a 、 Figure 6b As shown;

[0109] Step S306: A third patterned mask layer 41 is formed on the upper surface of the fifth mask dielectric layer 39. A plurality of third opening patterns 411 arranged in multiple rows and columns are formed in the third patterned mask layer 41. The orthographic projection of each column of the third opening patterns 411 on the upper surface of the third mask dielectric layer 34 after the first etching is located between the adjacent columns of the second opening patterns 372, and the third opening patterns 411 are arranged in a staggered manner with respect to the adjacent columns of the second opening patterns 372, as shown in FIG. Figure 7a 、 Figure 7b and Figure 7c As shown;

[0110] Step S307 : etching the fifth mask dielectric layer 39 and the third hard mask layer 38 sequentially based on the third patterned mask layer 41 , and performing a second etching on the third mask dielectric layer 34 to transfer the third opening pattern 411 into the third mask dielectric layer 34 ;

[0111] Step S308: removing the third patterned mask layer 41, the fifth mask dielectric layer 39 and the third hard mask layer 38;

[0112] Step S309: etching the second mask dielectric layer 33 and the first hard mask layer 32 based on the third mask dielectric layer 34 after the second etching to obtain a fourth patterned mask layer 42, wherein a fourth opening pattern 421 corresponding to the second opening pattern 372 and the third opening pattern 411 is formed in the fourth patterned mask layer 42. Figure 8a 、 Figure 8b and Figure 8c As shown;

[0113] Step S310: forming a third filling dielectric layer 43, the third filling dielectric layer 43 fills the fourth opening pattern 421 and covers the fourth patterned mask layer 42, as shown in FIG. Figure 9a 、 Figure 9b As shown;

[0114] Step S311: removing the third filling dielectric layer 43 on the fourth patterned mask layer 42, as shown in FIG. Figure 10a 、 Figure 10b and Figure 10c and based on the retained third filling dielectric layer 43 to remove the fourth patterned mask layer 42, and etch the first mask dielectric layer 31 to obtain a first patterned mask layer 44, as shown Figure 11a 、 Figure 11b and Figure 11c As shown;

[0115] As an example, the materials of the first mask dielectric layer 31, the second mask dielectric layer 33 and the fourth mask dielectric layer 36 formed in step S301 include but are not limited to SiON; the materials of the first hard mask layer 32 and the second hard mask layer 35 include but are not limited to hard mask layers (HM); the materials of the third mask dielectric layer 34 include but are not limited to SiO2.

[0116] As an example, multiple rows and columns of first opening patterns 371 and second opening patterns 372 are arranged in the column direction, and third opening patterns 411 are arranged in the row direction; or multiple rows and columns of first opening patterns 371 and second opening patterns 372 are arranged in the row direction, and third opening patterns 411 are arranged in the column direction. The first opening patterns 371 expose the fourth mask dielectric layer 36; the second opening patterns 372 expose the second mask dielectric layer 33 underneath.

[0117] As an example, in steps S303 and S304, a dry etching technique is used to etch the fourth mask dielectric layer 36, the second hard mask layer 35, and the third mask dielectric layer 34; a chemical mechanical polishing (CMP) or dry etching process can be used to remove the second patterned mask layer 37, the remaining fourth mask dielectric layer 36, and the remaining second hard mask layer 35. Since the dry etching process is used to remove the fourth mask dielectric layer 36, the exposed portion of the second mask dielectric layer 33 is etched and thinned. As a result, the top of the second mask dielectric layer 33 finally exposed is slightly lower than the top of the second mask dielectric layer 33 located below the third mask dielectric layer 34. Please refer to Figure 5c .

[0118] As an example, see Figure 6b The material of the third hard mask layer 38 formed in step S305 may include, but is not limited to, HM; the material of the fifth mask dielectric layer 39 may include, but is not limited to, SiON. The third opening pattern 411 in the third patterned mask layer 41 formed in step S306 exposes the fifth mask dielectric layer 39.

[0119] As an example, see Figure 7b and Figure 7c In steps S307 and S308, a dry etching process may be used. With a high etching selectivity of greater than 1 between the fifth mask dielectric layer 39 and the third patterned mask layer 41, and a high etching selectivity of greater than 1 between the third hard mask layer 38 and the third patterned mask layer 41, the fifth mask dielectric layer 39 and the third hard mask layer 38 are etched. The third patterned mask layer 41 and the fifth mask dielectric layer 39 are removed using CMP or push etching techniques, and then the remaining third hard mask layer 38 is removed by dry or wet etching.

[0120] As an example, see Figure 8a and Figure 8b In step S309, the second mask dielectric layer 33 and the first hard mask layer 32 are etched to obtain a fourth patterned mask layer 42. The fourth patterned mask layer 42 is formed with a fourth opening pattern 421 that exposes the first mask dielectric layer 31. The fourth opening pattern is arranged in row and column directions. The row direction is the same as the extension direction of the buried gate word line 13, and the column direction is the same as the extension direction of the bit line 20.

[0121] As an example, see Figure 9a and Figure 9bThe third filling dielectric layer 43 is formed in step S310 because the deposition rate of the third filling dielectric layer 43 is the same directly above the fourth opening pattern 421 as in other areas. A depression appears directly above the fourth opening pattern 421, and the upper surface of the third filling dielectric layer 43 directly above the fourth opening pattern 421 is lower than the upper surface of the third filling dielectric layer 43 located on the fourth patterned mask layer 42. The material of the third filling dielectric layer 43 may include, but is not limited to, SiO2, and may be fabricated using TEOS, LTO, or ALD techniques.

[0122] As an example, see Figure 10b and Figure 10c In step S311, the third filling dielectric layer 43 on the fourth patterned mask layer 42 is removed by CMP process, and the upper surface of the remaining third filling dielectric layer 43 is lower than the upper surface of the fourth patterned mask layer 42. Figure 11b and Figure 11c The etching selectivity ratio of the fourth patterned mask layer 42 to the third filling dielectric layer 43 is greater than 1, the fourth patterned mask layer 42 is removed, and based on the difference in material between the third filling dielectric layer 43 and the first mask dielectric layer 31, the first mask dielectric layer 31 is etched to convert the first mask dielectric layer 31 into a first patterned mask layer 44, and the first patterned mask layer 44 exposes the first filling dielectric layer 23 underneath.

[0123] In one embodiment, please refer to Figure 11a The first patterned mask layer 44 includes a plurality of pattern units 441. The orthographic projection of each pattern unit 441 on the substrate 10 spans across the bit line 20, and is partially located on opposite sides of the bit line 20. The shapes of the first opening pattern 371, the second opening pattern 372, the third opening pattern 411, and the fourth opening pattern 421 are all circular. The orthographic projections of the first opening pattern 371, the second opening pattern 372, and the third opening pattern 411 on the substrate 10 span across some of the bit lines; the orthographic projection of the fourth opening pattern 421 on the substrate 10 spans across all of the bit lines.

[0124] In one embodiment, after forming the first patterned mask layer 44 in step S311, the following steps are further included:

[0125] Step S312 : removing the remaining third filling dielectric layer 43 .

[0126] Specifically, the remaining third filling dielectric layer 43 is removed by using dry etching technology or CMP technology without affecting the exposed first filling dielectric layer 23 .

[0127] In one embodiment, please refer to Figure 11b and Figure 11cIn step S40, the first filling dielectric layer 23 between each pattern unit 441 is etched using a dry etching technique based on the first patterned mask layer 44 to form etched grooves 45. The etched grooves 45 expose the underlying cover dielectric layer 16. When removing the first filling dielectric layer 23, the first filling dielectric layer 23 on both sides of the adjacent bit line 20 is not etched. In other words, the first filling dielectric layer 23 below each pattern unit 441 remains, allowing for subsequent formation of capacitor contact holes.

[0128] In one embodiment, Figure 12a and Figure 12b As shown, in step S50, openings (not shown) are formed between each pattern unit 441. Due to the influence of the openings and the etched grooves 45, the upper surface of the formed second filling dielectric layer 46 is recessed. The upper surface of the second filling dielectric layer 46 located above the pattern unit 441 is higher than the upper surface of the second filling dielectric layer 46 located above the etched grooves 45. The etched grooves 45 expose the cover dielectric layer 16. The second filling dielectric layer 46 isolates the adjacent capacitor contact structures 49 to be formed subsequently, effectively reducing the parasitic capacitance between the bit line 20 and the capacitor contact structures 49. As an example, the material of the second filling dielectric layer 46 may include, but is not limited to, Si3N4, and can be prepared using ALD technology.

[0129] In one embodiment, Figure 13a 、 Figure 13b and Figure 13c As shown, in step S60, the first patterned mask layer 44 and the second filling dielectric layer 46 are polished away using a CMP process until the first filling dielectric layer 23 is exposed, while eliminating the depressions formed by etching the grooves in FIG12. The shape of the remaining top surface of the first filling dielectric layer 23 is the same as that of each pattern unit 441, arranged in multiple rows and columns.

[0130] In one embodiment, Figure 14a 、 Figure 14b As shown, in step S70, a wet etching process can be used to remove the remaining first filling dielectric layer 23 to form capacitor contact holes 47 arranged in multiple rows and columns. Adjacent columns of capacitor contact holes 47 are staggered, and the capacitor contact holes 47 expose the covering dielectric layer 16. Each capacitor contact hole 47 includes a first sub-contact hole 471 and a second sub-contact hole 472 located on opposite sides of the bit line 20, respectively. The shape of the first sub-contact hole 471 and the shape of the second sub-contact hole 472 are both half-moon shaped.

[0131] In one embodiment, Figure 15a 、 Figure 15b As shown, after step S70: removing the remaining first filling dielectric layer and before step S80: forming a capacitor contact structure in the capacitor contact hole, the following steps are also included:

[0132] Step S71 : removing the covering dielectric layer 16 in the capacitor contact hole 47 so that the capacitor contact hole 47 penetrates the covering dielectric layer 16 to expose the active area 12 , and the covering dielectric layer 16 between the bit line 20 and the substrate 10 is still retained.

[0133] In one embodiment, step S80: forming a capacitor contact structure in the capacitor contact hole includes the following steps:

[0134] Step S81: forming a capacitor contact material layer 48, the capacitor contact material layer 48 fills the capacitor contact hole 47 and covers the bit line 20 and the second filling dielectric layer 46. Figure 16a 、 Figure 16b As shown;

[0135] Step S82: remove the capacitor contact material layer 48 on the bit line 20 and the second filling dielectric layer 46, and perform back etching on the capacitor contact material layer 48 in the capacitor contact hole 47 to obtain a capacitor contact structure 49, as shown in FIG. Figure 17a 、 Figure 17b and Figure 17c As shown; the upper surface of the capacitor contact structure 49 is lower than the upper surface of the bit line 20, and the capacitor contact hole 47 reserves part of the space for the subsequent preparation of the capacitor contact plug (not shown in the figure).

[0136] As an example, in step S82, the capacitor contact material layer 48 located on the bit line 20 and the second filling dielectric layer 46 is thinned using CMP technology until the second filling dielectric layer 46 is exposed. The material of the capacitor contact material layer 48 includes but is not limited to polysilicon.

[0137] In one embodiment, please refer to Figure 17c Capacitor contact structure 49 includes a first sub-contact structure 491 corresponding to first sub-contact hole 471 and a second sub-contact structure 492 corresponding to second sub-contact hole 472. Both first sub-contact structure 491 and second sub-contact structure 492 are half-moon shaped. Capacitor contact structures 49 are arranged in multiple rows and columns, with adjacent columns of capacitor contact structures 49 staggered. Capacitor contact structures 49 contact active area 12.

[0138] In one embodiment of the present application, a semiconductor structure is also provided, including: a substrate 10, having active areas 12 arranged at intervals in the substrate 10, and having a plurality of bit lines 20 arranged in parallel and at intervals on the substrate 10; a filling dielectric layer located between adjacent bit lines 20; a capacitor contact structure 49 located in the filling dielectric layer, the capacitor contact structure 49 including a first sub-contact structure 491 and a second sub-contact structure 492, the first sub-contact structure 491 and the second sub-contact structure 492 being respectively located on opposite sides of the bit line 20.

[0139] Specifically, the filling dielectric layer may be a second filling dielectric layer 46 , which isolates adjacent capacitor contact structures 49 and reduces parasitic capacitance between the bit line 20 and the capacitor contact structure 49 .

[0140] In one embodiment, there are multiple capacitor contact structures 49 , and the multiple capacitor contact structures 49 are arranged in multiple rows and columns, and the capacitor contact structures 49 in adjacent columns are staggered.

[0141] In one embodiment, the upper surface of the capacitor contact structure 49 is lower than the upper surface of the bit line 20 .

[0142] In one embodiment, the first sub-contact structure 491 and the second sub-contact structure 492 are both half-moon shaped.

[0143] In one embodiment, the semiconductor structure further includes a shallow trench isolation structure 11 , which isolates a plurality of active regions 12 arranged in an array in the substrate 10 ; the bottom of the capacitor contact structure 49 contacts the active region 12 .

[0144] In one embodiment, a plurality of buried gate word lines 13 arranged in parallel and spaced apart are further formed in the substrate 10 . The extending direction of the buried gate word lines 13 intersects with the extending direction of the bit lines 20 and the extending direction of the active region 12 .

[0145] In one embodiment, the bit lines 20 extend along the column direction, the buried gate word lines 13 extend along the row direction, and the active region 12 extends along a direction forming a predetermined angle with the bit lines 20 .

[0146] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present application.

[0147] It should be understood that, unless otherwise expressly stated herein, the steps described are not strictly limited in order of execution, and the steps may be executed in other orders. Furthermore, at least a portion of the steps described may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. The sub-steps or stages are not necessarily executed sequentially, but may be executed in rotation or alternation with other steps or at least a portion of the sub-steps or stages of other steps.

[0148] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0149] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate having active regions spaced apart from each other, and forming a plurality of bit lines spaced apart from each other in parallel on the substrate; forming a first filling dielectric layer, wherein the first filling dielectric layer fills the gaps between adjacent bit lines and covers the tops of the bit lines; forming a first patterned mask layer on the upper surface of the first filling dielectric layer, wherein the first patterned mask layer includes a plurality of pattern units, wherein an orthographic projection of each of the pattern units on the substrate spans the bit line and is partially located on two opposite sides of the bit line; etching the first filling dielectric layer based on the first patterned mask layer to form an etched groove, wherein the etched groove exposes the substrate; forming a second filling dielectric layer, wherein the second filling dielectric layer fills the etched groove and covers the first patterned mask layer; removing the first patterned mask layer and the second filling dielectric layer located on the first patterned mask layer and between the pattern units; Removing the remaining first filling dielectric layer to form a plurality of capacitor contact holes, wherein the capacitor contact holes expose the substrate; each of the capacitor contact holes includes a first sub-contact hole and a second sub-contact hole respectively located on opposite sides of the bit line; A capacitor contact structure is formed in the capacitor contact hole, wherein the capacitor contact structure includes a first sub-contact structure corresponding to the first sub-contact hole and a second sub-contact structure corresponding to the second sub-contact hole.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The forming of a first patterned mask layer on the upper surface of the first filling dielectric layer includes: forming a first mask dielectric layer, a first hard mask layer, a second mask dielectric layer, a third mask dielectric layer, a second hard mask layer and a fourth mask dielectric layer stacked sequentially from bottom to top on the upper surface of the first filling dielectric layer; forming a second patterned mask layer on the upper surface of the fourth mask dielectric layer, wherein a plurality of first opening patterns arranged in multiple rows and columns are formed in the second patterned mask layer; Etching the fourth mask dielectric layer and the second hard mask layer based on the second patterned mask layer, and performing a first etching on the third mask dielectric layer to form a second opening pattern corresponding to the first opening pattern in the third mask dielectric layer; removing the second patterned mask layer, the fourth mask dielectric layer, and the second hard mask layer; forming a third hard mask layer and a fifth mask dielectric layer stacked sequentially from bottom to top, wherein the third hard mask layer fills the second opening pattern and covers the third mask dielectric layer after the first etching; forming a third patterned mask layer on the upper surface of the fifth mask dielectric layer, wherein a plurality of third opening patterns arranged in multiple rows and columns are formed in the third patterned mask layer, wherein an orthographic projection of the third opening patterns in each column on the upper surface of the third mask dielectric layer after the first etching is located between the second opening patterns in an adjacent column and the third opening patterns are arranged in a staggered manner relative to the second opening patterns in the adjacent column; Sequentially etching the fifth mask dielectric layer and the third hard mask layer based on the third patterned mask layer, and performing a second etching on the third mask dielectric layer to transfer the third opening pattern into the third mask dielectric layer; removing the third patterned mask layer, the fifth mask dielectric layer, and the third hard mask layer; Etching the second mask dielectric layer and the first hard mask layer based on the third mask dielectric layer after the second etching to obtain a fourth patterned mask layer, wherein a fourth opening pattern corresponding to the second opening pattern and the third opening pattern is formed in the fourth patterned mask layer; forming a third filling dielectric layer, wherein the third filling dielectric layer fills the fourth opening pattern and covers the fourth patterned mask layer; The third filling dielectric layer on the fourth patterned mask layer is removed, and the fourth patterned mask layer is removed based on the retained third filling dielectric layer, and the first mask dielectric layer is etched to obtain the first patterned mask layer.

3. The method for preparing a semiconductor structure according to claim 2, wherein: After forming the first patterned mask layer, the method further includes: The remaining third filling medium layer is removed.

4. The method for preparing a semiconductor structure according to claim 3, wherein: The shapes of the first opening pattern, the second opening pattern and the third opening pattern are all circular, and the shapes of the first sub-contact hole, the second sub-contact hole, the first sub-contact structure and the second sub-contact structure are all half-moon shaped.

5. The method for preparing a semiconductor structure according to claim 2, wherein: The capacitor contact structures are arranged in multiple rows and columns, and the capacitor contact structures in adjacent columns are staggered.

6. The method for preparing a semiconductor structure according to claim 1, wherein: The forming of the capacitor contact structure in the capacitor contact hole includes: forming a capacitor contact material layer, wherein the capacitor contact material layer fills the capacitor contact hole and covers the bit line and the second filling dielectric layer; The capacitor contact material layer located on the bit line and the second filling dielectric layer is removed, and the capacitor contact material layer located in the capacitor contact hole is etched back to obtain the capacitor contact structure; the upper surface of the capacitor contact structure is lower than the upper surface of the bit line.

7. The method for preparing a semiconductor structure according to any one of claims 1 to 6, characterized in that: A shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure isolates a plurality of active areas arranged in an array in the substrate; the bottom of the capacitor contact structure contacts the active area.

8. The method for preparing a semiconductor structure according to claim 7, wherein: A covering dielectric layer is formed on the upper surface of the substrate; after removing the remaining first filling dielectric layer and before forming a capacitor contact structure in the capacitor contact hole, it also includes: removing the covering dielectric layer in the capacitor contact hole so that the capacitor contact hole passes through the covering dielectric layer to expose the active area.

9. The method for preparing a semiconductor structure according to claim 7, wherein: A plurality of buried gate word lines arranged in parallel and at intervals are also formed in the substrate. The extending directions of the buried gate word lines intersect with the extending directions of the bit lines and the active regions.

10. A semiconductor structure, characterized in that include: A substrate having active areas spaced apart in the substrate and a plurality of bit lines spaced apart and arranged in parallel; A filling dielectric layer is located between adjacent bit lines; a capacitor contact structure located in the filling dielectric layer, the capacitor contact structure comprising a first sub-contact structure and a second sub-contact structure, the first sub-contact structure and the second sub-contact structure being located on opposite sides of the bit line, respectively; Wherein, the upper surface of the capacitor contact structure is lower than the upper surface of the bit line.

11. The semiconductor structure according to claim 10, wherein: There are a plurality of capacitor contact structures, and the plurality of capacitor contact structures are arranged in multiple rows and columns, and the capacitor contact structures in adjacent columns are staggered.

12. The semiconductor structure according to claim 10, wherein: The first sub-contact structure and the second sub-contact structure are both half-moon shaped.

13. The semiconductor structure according to any one of claims 10 to 12, characterized in that It also includes a shallow trench isolation structure, which isolates a plurality of active areas arranged in an array in the substrate; the bottom of the capacitor contact structure is in contact with the active area.

14. The semiconductor structure according to claim 13, wherein: A plurality of buried gate word lines arranged in parallel and at intervals are also formed in the substrate. The extending directions of the buried gate word lines intersect with the extending directions of the bit lines and the active regions.

15. The semiconductor structure according to claim 14, wherein: The bit lines extend along a column direction, the buried gate word lines extend along a row direction, and the active region extends along a direction forming a preset angle with the bit lines.

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