Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises the following steps: after forming a plurality of capacitor holes in a support layer and a sacrificial layer, an external electrode layer is formed on the side wall surface of the capacitor hole; a dielectric layer is formed on the side wall surface of the external electrode layer; the remaining sacrificial layer between the external electrode layers is removed, and a cavity is formed at the position where the remaining sacrificial layer is removed; an internal electrode layer is formed on the surface of the dielectric layer and the bottom surface of the capacitor hole; a first conductive layer is formed to fill the cavity, and the first conductive layer is in contact with the external electrode layer; and a second conductive layer is formed on the internal electrode layer to fill the remaining capacitor hole. Since the external electrode layer is first formed on the side wall of the capacitor hole, and then the dielectric layer is formed on the surface of the external electrode layer, after the cavity is formed, the internal electrode layer is formed on the surface of the dielectric layer and the bottom surface of the capacitor hole, so that one side surface of the internal electrode can be supported by the double-layer structure of the dielectric layer and the external electrode layer, and thus the internal electrode layer will not or is not likely to bend and cause a short circuit.

Description

Technical Field

[0001] The present application relates to the field of memory manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers, consisting of many repeated storage cells. Each storage cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.

[0003] In the prior art DRAM forming method, the internal electrodes of the formed capacitors are easily bent and cause short circuits. Summary of the invention

[0004] In view of this, the present application provides a semiconductor structure and a method for forming the same, which can prevent short circuits caused by bending of internal electrodes.

[0005] To this end, some embodiments of the present application provide a method for forming a semiconductor structure, including:

[0006] providing a substrate;

[0007] forming a sacrificial layer and a supporting layer on the sacrificial layer on the substrate;

[0008] Removing part of the support layer and the sacrificial layer, and forming a plurality of capacitor holes in the support layer and the sacrificial layer;

[0009] forming an outer electrode layer on the side wall surface of the capacitor hole;

[0010] forming a dielectric layer on the side wall surface of the outer electrode layer;

[0011] Removing the remaining sacrificial layer between the outer electrode layers, and forming a cavity at the position where the remaining sacrificial layer is removed;

[0012] forming an inner electrode layer on the surface of the dielectric layer and the bottom surface of the capacitor hole;

[0013] forming a first conductive layer filling the cavity, wherein the first conductive layer is in contact with the outer electrode layer;

[0014] forming a second conductive layer on the inner electrode layer to fill the remaining capacitor holes;

[0015] forming an isolation layer covering the second conductive layer, the dielectric layer, the outer electrode layer, the inner electrode layer and the support layer;

[0016] forming a plurality of openings in the isolation layer to expose the first conductive layer and the outer electrode layer;

[0017] A connection structure electrically connected to the first conductive layer and the external electrode layer is formed on the surface of the isolation layer and in the opening.

[0018] In some embodiments, a plurality of electrode contact structures are formed in the substrate, adjacent electrode contact structures are isolated by an insulating layer, and the plurality of capacitor holes expose corresponding electrode contact structures.

[0019] In some embodiments, the material of the sacrificial layer is different from the material of the supporting layer and the insulating layer.

[0020] In some embodiments, the process of forming a plurality of capacitor holes in the supporting layer and the sacrificial layer includes: using a dry etching process to remove a portion of the supporting layer and the sacrificial layer to form initial capacitor holes in the supporting layer and the sacrificial layer; using a first wet etching process to thin the sacrificial layer on the side wall of the initial capacitor hole to increase the size of the initial capacitor hole; using a second wet etching process to remove a portion of the supporting layer and the insulating layer to form capacitor holes.

[0021] In some embodiments, the minimum thickness of the sacrificial layer between adjacent capacitor holes is less than one fifth of the diameter of the capacitor hole.

[0022] In some embodiments, the process of forming the external electrode layer includes: forming an external electrode material layer on the side wall and bottom surface of the capacitor hole and the surface of the support layer; using a maskless etching process to remove the external electrode material layer located on the bottom surface of the capacitor hole and the surface of the support layer, and the remaining external electrode material layer on the side wall of the capacitor hole serves as the external electrode layer.

[0023] In some embodiments, the process of forming the dielectric layer includes: forming a dielectric material layer on the side wall surface of the outer electrode layer, the bottom surface of the capacitor hole, and the surface of the support layer; using a maskless etching process to remove the dielectric material layer located on the bottom surface of the capacitor hole and the surface of the support layer, and the remaining dielectric material layer on the side wall surface of the outer electrode layer serves as the dielectric layer.

[0024] In some embodiments, the step of forming an inner electrode layer on the surface of the dielectric layer and the bottom surface of the capacitor hole and the step of forming a first conductive layer filling the cavity are performed simultaneously.

[0025] In some embodiments, the process of forming an inner electrode layer on the surface of the dielectric layer and the bottom surface of the capacitor hole and forming a first conductive layer filling the cavity includes: forming an inner electrode material layer in the cavity, on the surface of the support layer, on the surface of the dielectric layer and at the bottom of the capacitor hole; after forming the inner electrode material layer, forming a second conductive layer on the inner electrode material layer to fill the remaining capacitor holes; after forming the second conductive layer, disconnecting the inner electrode material layer in the cavity from the inner electrode material layer in the capacitor hole, and the remaining inner electrode material layer in the cavity serves as the first conductive layer, and the remaining inner electrode material layer in the capacitor hole serves as the inner electrode layer.

[0026] In some embodiments, after the dielectric layer is formed, the remaining sacrificial layer between the external electrode layers is removed, and the process of forming a cavity at the position where the sacrificial layer is removed includes: forming a mask layer on the surface of the support layer, on the top surface of the external electrode layer and the dielectric layer, and above the capacitor hole, and forming a first opening in the mask layer to expose a portion of the surface of the support layer between adjacent capacitor holes; using the mask layer as a mask, etching the exposed support layer along the first opening to expose the surface of the sacrificial layer at the bottom; removing all sacrificial layers along the position of the exposed sacrificial layer to form a cavity at the position where the sacrificial layer is removed; and removing the mask layer.

[0027] Some embodiments of the present application further provide a semiconductor structure, including:

[0028] substrate;

[0029] A plurality of discrete annular outer electrode layers located on the substrate;

[0030] a dielectric layer located on the inner side wall of the outer electrode;

[0031] an inner electrode layer located on the inner sidewall of the dielectric layer and on the surface of the substrate within the ring of the outer electrode layer;

[0032] A first conductive layer filling the outer ring space of the outer electrode layer, wherein the first conductive layer is in contact with the outer electrode layer;

[0033] A second conductive layer filling the inner ring space of the inner electrode layer, wherein the second conductive layer is connected to the inner electrode layer;

[0034] an isolation layer covering the second conductive layer, the dielectric layer, the outer electrode layer and the inner electrode layer, wherein the isolation layer is formed with an opening exposing the first conductive layer and the outer electrode layer;

[0035] A connection structure is located on the surface of the isolation layer and in the opening and is connected to the first conductive layer and the outer electrode layer.

[0036] In some embodiments, the substrate has a plurality of electrode contact structures, adjacent electrode contact structures are isolated by an insulating layer, and the outer electrode layer is connected to corresponding electrode contact structures.

[0037] In some embodiments, the outer electrode layer, the first conductive layer, and the inner electrode layer are made of the same material.

[0038] In some embodiments, the material of the outer electrode layer, the first conductive layer and the inner electrode layer is titanium nitride.

[0039] In some embodiments, the material of the second conductive layer is doped polysilicon, and the material of the dielectric layer is a high dielectric constant material.

[0040] In some embodiments, a support layer is further provided between the outer electrode layers, and the support layer is in contact with the outer sidewalls of the outer electrode layers.

[0041] The method for forming a semiconductor structure in some of the aforementioned embodiments of the present application is as follows: after forming a number of capacitor holes in the support layer and the sacrificial layer, an external electrode layer is formed on the side wall surface of the capacitor hole; a dielectric layer is formed on the side wall surface of the external electrode layer; the remaining sacrificial layer between the external electrode layers is removed, and a cavity is formed at the position where the remaining sacrificial layer is removed; an internal electrode layer is formed on the surface of the dielectric layer and the bottom surface of the capacitor hole; a first conductive layer filling the cavity is formed, and the first conductive layer is in contact with the external electrode layer; a second conductive layer filling the remaining capacitor holes is formed on the internal electrode layer; an isolation layer covering the second conductive layer, the dielectric layer, the external electrode layer, the internal electrode layer and the support layer is formed; a number of openings exposing the first conductive layer and the external electrode layer are formed in the isolation layer; and a connection structure electrically connected to the first conductive layer and the external electrode layer is formed on the surface of the isolation layer and in the opening. Since an outer electrode layer is first formed on the side wall of the capacitor hole and then a dielectric layer is formed on the surface of the outer electrode layer, after the remaining sacrificial layer is removed to form a cavity, although one side surface of the outer electrode layer is suspended (a cavity), the other side surface of the outer electrode has a dielectric layer, and the dielectric layer and the outer electrode layer support each other, so that the outer electrode layer will not or is not likely to bend and cause a short circuit. After the cavity is formed, an inner electrode layer is formed on the surface of the dielectric layer and the bottom surface of the capacitor hole. Since one side surface of the inner electrode can be supported by the double-layer structure of the dielectric layer and the outer electrode layer, the inner electrode layer will not or is not likely to bend and cause a short circuit, thereby improving the electrical performance of the capacitor.

[0042] Further, in some embodiments, the process of forming the inner electrode layer on the surface of the dielectric layer and the bottom surface of the capacitor hole and forming the first conductive layer that fills the cavity includes: forming an inner electrode material layer in the cavity, on the surface of the support layer, on the surface of the dielectric layer and at the bottom of the capacitor hole; after forming the inner electrode material layer, forming a second conductive layer that fills the remaining capacitor hole on the inner electrode material layer; after forming the second conductive layer, disconnecting the inner electrode material layer in the cavity from the inner electrode material layer in the capacitor hole, and using the remaining inner electrode material layer in the cavity as the first conductive layer and the remaining inner electrode material layer in the capacitor hole as the inner electrode layer. Through the aforementioned process, the formation process of the first conductive layer and the outer electrode layer can be carried out simultaneously, saving process steps, and after forming the second conductive layer, the second conductive layer and the dielectric layer can directly define the portion of the outer electrode material layer that needs to be removed, so that the outer electrode material layer can be directly etched and disconnected without forming a mask layer, thereby further saving process steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1-Figure 16 It is a structural schematic diagram of the formation process of the semiconductor structure in some embodiments of the present application. DETAILED DESCRIPTION

[0044] As mentioned in the background art, during the formation of a DRAM, the inner electrodes are prone to bend and cause a short circuit.

[0045] Research has found that in the existing DRAM manufacturing process, after the inner electrode is formed, the remaining sacrificial layer needs to be removed to form a cavity. At this time, both sides of the inner electrode are suspended, and the inner electrode material (generally TiN) will produce stress. The generated stress can easily cause the inner electrodes suspended on both sides to bend, causing the two adjacent inner electrodes to contact and cause a short circuit. In particular, in order to increase the capacitance value of the capacitor, when the height of the capacitor hole is very high, the inner electrode is more likely to bend and cause a short circuit.

[0046] In this regard, the present application provides a semiconductor structure and a method for forming the same, which can prevent the inner electrode from bending and prevent the formed capacitor from short-circuiting during the process of forming a memory.

[0047] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present application in detail, for the convenience of explanation, the schematic diagram will not be partially enlarged according to the general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0048] refer to Figure 1, providing a substrate 200 ; forming a sacrificial layer 205 and a supporting layer 206 located on the sacrificial layer 205 on the substrate 200 .

[0049] The substrate 200 serves as a platform for subsequent processes.

[0050] In some embodiments, the base 200 may include a semiconductor substrate 201 and an insulating layer 202 located on the semiconductor substrate 201. The material of the semiconductor substrate 201 may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator (GOI); or it may also be other materials, such as III-V compounds such as gallium arsenide. The semiconductor substrate is doped with certain impurity ions as needed. The impurity ions may be N-type impurity ions or P-type impurity ions. The N-type impurity ions are one or more of phosphorus ions, arsenic ions or antimony ions, and the P-type impurity ions are one or more of boron ions, gallium ions or indium ions. In this embodiment, the material of the semiconductor substrate 201 is silicon. Several trench transistors may be formed in the semiconductor substrate, and the several trench transistors are used as part of a DRAM storage device. Specifically, the trench transistor includes an active region located in the semiconductor substrate, at least one buried gate located in the active region, a middle drain region of the active region located on both sides of the buried gate, and at least one source region.

[0051] The insulating layer 202 may be a single layer or a multi-layer stacked structure. A plurality of electrode contact structures 203 are formed in the insulating layer 202 , and the electrode contact structures 203 may be used to connect the inner electrode layer of the capacitor formed subsequently and the source of the trench transistor formed in the semiconductor substrate 201 .

[0052] In some embodiments, the insulating layer 202 may be a single-layer structure formed by one of silicon oxide, silicon nitride, silicon oxynitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide) or BPSG (boron-phosphorus-doped silicon dioxide), low-k materials, or a stacked-layer structure formed by two or more materials in the group consisting of the above materials. In this embodiment, the insulating layer 202 is a single-layer structure of silicon nitride, or a stacked-layer structure in which at least the topmost layer is a silicon nitride layer.

[0053] The material of the electrode contact structure 203 is metal. In some embodiments, the electrode contact structure 203 may be a single-layer structure formed by one material selected from W, Al, Cu, Ag, Au, Co, Pt, Ni, Ti, Ta, TiN, and TaN, or a stacked structure formed by two or more materials selected from the group consisting of the above materials (e.g., a double-layer stacked structure consisting of a TiN layer and a W layer on the TiN layer).

[0054] In some embodiments, the formed electrode contact structure 203 is completely located in the insulating layer 202 , that is, the top surface of the electrode contact structure 203 is lower than the top surface of the insulating layer 202 .

[0055] The sacrificial layer 205 is subsequently used to form capacitor holes and capacitors. The sacrificial layer can be a single layer or a multi-layer stacked structure. The material of the sacrificial layer 205 is different from the material of the support layer 206 and the insulating layer 202. When the sacrificial layer 205 is subsequently etched (such as when the initial capacitor hole is subsequently formed, the size of the initial capacitor hole is enlarged, and the remaining sacrificial layer is removed), the etching amount of the support layer 206 and the insulating layer 202 is very small or negligible. In some embodiments, the sacrificial layer 205 can be a single layer structure formed by one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon, silicon carbonitride, carbon, boron-doped silicon oxide, phosphorus-doped silicon oxide, boron nitride, silicon germanium, polycrystalline silicon, amorphous silicon, amorphous carbon, or a stacked structure formed by two or more materials in the group consisting of the above materials. In this embodiment, the sacrificial layer 205 is a single layer structure of silicon oxide.

[0056] The support layer 206 is used to support the capacitor hole and the various layers of the capacitor in the subsequent process of forming the capacitor, maintain the mechanical stability of the capacitor and prevent the capacitor from collapsing. The support layer 206 can be a single layer or a multi-layer stacked structure. In some embodiments, the support layer 206 can be a single layer structure formed by one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride, or a stacked structure formed by two or more materials in the group consisting of the above materials. In this embodiment, the support layer 206 is a single layer structure of silicon nitride.

[0057] refer to Figure 4-Figure 5 , Figure 4 for Figure 5 The schematic cross-sectional structure diagram along the cutting line AB shows that a portion of the support layer 206 and the sacrificial layer 205 are removed, and a plurality of capacitor holes 208 are formed in the support layer 206 and the sacrificial layer 205 .

[0058] The capacitor holes 208 are subsequently used to form capacitors. In some embodiments, the capacitor holes 208 are arranged in a staggered manner, and the bottom of each capacitor hole 208 exposes the surface of the corresponding electrode contact structure 203 .

[0059] In some embodiments, the formation process of the capacitor hole 208 may include: after forming a mask layer having a plurality of openings on the support layer 206, using the mask layer as a mask, etching the support layer 206 and the sacrificial layer 205 along the openings to directly form capacitor holes in the support layer 206 and the sacrificial layer 205.

[0060] In this embodiment, the capacitor hole 208 is formed by using specific process steps. Figure 2-Figure 5 The formation process of the capacitor hole 208 is described in detail.

[0061] refer to Figure 2 , a dry etching process is used to remove part of the support layer 206 and the sacrificial layer 205 , and an initial capacitor hole 207 is formed in the support layer 206 and the sacrificial layer 205 .

[0062] The dry etching process is an anisotropic dry etching process, including an anisotropic plasma etching process. In this embodiment, the gas used in the anisotropic plasma etching process includes a carbon-fluorine-containing gas, specifically CF 4 , CHF 3 , C 4 F 8 or C 4 F 6 One or more of the .

[0063] In some embodiments, before performing the dry etching process, a patterned mask layer (such as a patterned photoresist layer) is formed on the supporting layer 206, and the patterned mask layer has a plurality of discrete etching openings that expose a portion of the surface of the supporting layer; using the patterned mask layer as a mask, the supporting layer 206 and the sacrificial layer 205 are etched along the etching openings to form initial capacitor holes 207 in the supporting layer 206 and the sacrificial layer 205; and the patterned mask layer is removed.

[0064] The size of the initial capacitor hole formed is much smaller than the size of the capacitor hole that will be finally formed subsequently. The bottom of the initial capacitor hole 207 formed can expose part of the surface of the electrode contact structure 203. Therefore, when the initial capacitor hole is formed, the side wall of the initial capacitor hole 207 formed can be kept perpendicular to the surface of the semiconductor substrate or the inclination of the side wall is very small, which is conducive to the side wall of the capacitor hole that will be finally formed subsequently also being perpendicular to the surface of the semiconductor substrate or the inclination of the side wall is very small, preventing the formation of a capacitor hole with an inverted trapezoidal morphology. In addition, since the size of the initial capacitor hole formed is small, the energy of the plasma during etching can be relatively small, so that the etching damage to the bottom electrode contact structure 203 is also small.

[0065] In some other embodiments, the bottom of the formed initial capacitor hole 207 can expose a portion of the surface of the insulating layer 202 on the top surface of the electrode contact structure 203 (when forming the initial capacitor hole 207, the insulating layer 202 on the top surface of the electrode contact structure 203 will not be etched or only a portion of the thickness will be removed), so in the process of forming the initial capacitor hole 207 and subsequent wet etching to increase the size of the initial capacitor hole 207, the remaining insulating layer 202 protects the electrode contact structure 203 from being etched and damaged.

[0066] refer to Figure 3 , a first wet etching process is used to thin the sacrificial layer 205 on the sidewall of the initial capacitor hole 207, so that the size of the initial capacitor hole 207 becomes larger.

[0067] The first wet etching process is an isotropic wet etching process. When etching, the lateral etching rates at different positions of the sacrificial layer can be kept consistent or have a small difference, so that the sidewalls of the initial capacitor hole 207 after the size is enlarged are still perpendicular to the surface of the semiconductor substrate or the inclination of the sidewalls is very small. In the process of thinning the sacrificial layer 205 by the first wet etching process, the sacrificial layer 205 has a high etching selectivity relative to the support layer 206 and the insulating layer 202, and the etching amount of the support layer 206 and the insulating layer 202 is small or can be ignored.

[0068] In this embodiment, the etching solution used in the first wet etching process includes a hydrofluoric acid solution.

[0069] refer to Figure 4 and Figure 5 , a second wet etching process is used to remove a portion of the support layer 206 and the insulating layer 202 , and a capacitor hole 208 is formed in the support layer 206 and the insulating layer 202 .

[0070] The second wet etching process is an isotropic wet etching process. When etching, the lateral etching rates at different positions of the support layer 206 and the insulating layer 202 can be kept consistent or have a small difference, so that the size of the remaining support layer 206 and the size of the remaining sacrificial layer 205 at the bottom can be kept consistent or have a small difference. After removing part of the insulating layer 202, the surface of the electrode contact structure 203 is more exposed. In the process of removing part of the support layer 206 and the insulating layer 202 by the second wet etching process, the support layer 206 and the insulating layer 202 have a high etching selectivity relative to the sacrificial layer 205, and the etching amount of the sacrificial layer 205 is small or negligible.

[0071] In this embodiment, the etching solution used in the second wet etching process includes a concentrated phosphoric acid solution.

[0072] In some embodiments, after a portion of the insulating layer 202 is removed by a second wet etching process, the bottom of the remaining sacrificial layer 205 is higher than the surface of the electrode contact structure 203, and the surface of the remaining insulating layer 202 between the bottom of the remaining sacrificial layer 205 and the surface of the electrode contact structure 203 is inclined. The inclined insulating layer surface allows a larger distance between the bottom of an outer electrode layer subsequently formed on the side wall surface of the remaining sacrificial layer 205 and the bottom of an inner electrode layer formed on the surface of the electrode contact structure 203, which can more effectively prevent leakage between the bottom of the outer electrode layer and the bottom of the inner electrode layer.

[0073] In some embodiments, reference Figure 5 The capacitor holes 208 are arranged in rows, and the capacitor holes in adjacent rows are staggered. In other embodiments, the capacitor holes may be arranged in other ways, such as an array arrangement.

[0074] The capacitor holes formed by the aforementioned multi-step specific process in the present application can maintain a relatively large size (the thickness of the remaining sacrificial layer between adjacent capacitor holes will be relatively thin, and the minimum thickness is generally less than one-fifth of the diameter of the capacitor hole, and the capacitor hole morphology is "cylindrical", and the side wall surface morphology uniformity of the capacitor hole will be better, so that the outer electrode layer and the inner electrode layer formed in the subsequent capacitor hole can have a higher area, thereby increasing the capacitance value of the capacitor, and the surface morphology uniformity of the outer electrode layer and the inner electrode layer will be better, thereby improving the electrical performance of the capacitor. In addition, in the process of forming the capacitor hole, the etching damage to the electrode contact structure can also be reduced.

[0075] refer to Figure 6 , an external electrode layer 209 is formed on the side wall surface of the capacitor hole 208.

[0076] In some embodiments, the external electrode layer 209 may be a single-layer structure formed by one of the materials selected from W, Al, Cu, Ag, Au, Co, Pt, Ni, Ti, Ta, TiN, TaN, TaC, TaSiN, NiSi, CoSi, TiAl, and WSi, or a stacked-layer structure formed by two or more materials selected from the group consisting of the above materials. In this embodiment, the external electrode layer 209 is a TiN layer.

[0077] In some embodiments, the process of forming the external electrode layer includes: forming an external electrode material layer on the side wall and bottom surface of the capacitor hole 208 and the surface of the support layer 206; using a maskless etching process to remove the external electrode material layer located on the bottom surface of the capacitor hole 206 and the surface of the support layer 208, and the remaining external electrode material layer on the side wall of the capacitor hole 208 is used as the external electrode layer 209. The external electrode material layer can be formed by a physical vapor deposition process, sputtering, sputtering, electroplating, or chemical plating process. The maskless etching process can be an anisotropic plasma etching process.

[0078] refer to Figure 7 A dielectric layer 210 is formed on the side wall surface of the outer electrode layer 209 .

[0079] In some embodiments, the material of the dielectric layer 210 is a high-K (K greater than 2.8) dielectric material to increase the capacitance of the capacitor per unit area. In a specific embodiment, the dielectric layer 210 may be HfO 2 、TiO 2 、HfZrO、HfSiNO、Ta 2 O 5 、ZrO 2 、ZrSiO 2 、Al 2 O 3 、SrTiO 3 or BaSrTiO, or a stacked structure formed by two or more materials in the group of the above materials. In this embodiment, the dielectric layer 210 is HfO 2 layer.

[0080] In some embodiments, the formation process of the dielectric layer 210 includes: forming a dielectric material layer on the side wall surface of the external electrode layer 209, the bottom surface of the capacitor hole 208, and the surface of the support layer 206; using a maskless etching process to remove the dielectric material layer located on the bottom surface of the capacitor hole 208 and the surface of the support layer 206, and the remaining dielectric material layer on the side wall surface of the external electrode layer 209 is used as the dielectric layer 210. The dielectric material layer can be formed by a physical vapor deposition process, sputtering, sputtering, electroplating, or chemical plating process. The maskless etching process can be an anisotropic plasma etching process.

[0081] refer to Figure 8 and Fig. 9A mask layer is formed on the surface of the support layer 206, on the top surface of the outer electrode layer 209 and the dielectric layer 310, and above the capacitor hole 208, wherein a first opening is formed in the mask layer to expose a portion of the surface of the support layer 206 between adjacent capacitor holes; using the mask layer as a mask, removing the exposed support layer along the first opening (refer to Fig. 9 ), exposing the bottom sacrificial layer 205 (refer to Fig. 9 ) surface; removing the mask layer.

[0082] The purpose of removing part of the support layer 206 is to facilitate the subsequent removal of all the sacrificial layers through the exposed sacrificial layers, while ensuring that the overall structure of the support layer 206 is not damaged and still can play a supporting role.

[0083] The mask layer may be a single layer or a multi-layer stacked structure. In the present embodiment, the mask layer includes a first mask layer 211 and a second mask layer 212 located on the first mask layer 211. The material of the first mask layer 211 is different from the material of the support layer 206, the external electrode layer 209, the dielectric layer 310, the insulating layer 202 and the electrode contact structure 203. The material of the first mask layer 211 may be one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide and silicon carbonitride. The material of the second mask layer 212 is photoresist. After the second mask layer 212 is patterned by a photolithography process (including exposure and development processes), the first mask layer 211 is etched to form an opening.

[0084] The number of the first openings may be multiple (greater than or equal to 2), and the first openings are distributed separately, and each first opening exposes the support layer 206 between corresponding adjacent capacitor holes.

[0085] In some embodiments, the support layer is removed along the first opening by anisotropic dry etching, including anisotropic plasma etching. It should be noted that when the support layer is removed along the first opening, part of the outer electrode layer 209 and the dielectric layer 210 at the bottom of the first opening will also be removed.

[0086] refer to Fig.10 , remove the remaining sacrificial layer 205 between the outer electrode layers 209 (refer to Fig. 9 ), a cavity 213 is formed at the position where the remaining sacrificial layer 213 is removed.

[0087] The remaining sacrificial layer 205 between the outer electrode layers 209 is removed along the exposed surface of the sacrificial layer, and an isotropic wet etching process is used to remove the sacrificial layer 205. In this embodiment, the etching solution used in the wet etching is hydrofluoric acid.

[0088] In the present application, since the outer electrode layer 209 is first formed on the side wall of the capacitor hole, and then the dielectric layer 210 is formed on the surface of the outer electrode layer 209, after the remaining sacrificial layer 205 is removed to form the cavity 213, although one side surface of the outer electrode layer 209 is suspended (forming the cavity 213), the other side surface of the outer electrode 209 has the dielectric layer 210, and the dielectric layer 210 and the outer electrode layer 209 have a mutual support effect, so that the outer electrode layer 209 will not or is not likely to bend and cause a short circuit. After the cavity 213 is formed, the inner electrode layer is subsequently formed on the surface of the dielectric layer 210 and the bottom surface of the capacitor hole 208. Since one side surface of the inner electrode can be supported by the double-layer structure of the dielectric layer 210 and the outer electrode layer 209, the inner electrode layer will not or is not likely to bend and cause a short circuit, thereby improving the electrical performance of the capacitor.

[0089] refer to Figure 11-13 , on the surface of the dielectric layer 210 and the capacitor hole 208 (reference Fig.10 ) forms an inner electrode layer 217 (reference Fig.13 ); forming a cavity 213 filled with (reference Fig.10 ) of the first conductive layer 218 (reference Fig.13 ), the first conductive layer 218 contacts the outer electrode layer 209; a second conductive layer 216 (reference Fig.12 ).

[0090] In this embodiment, the step of forming the inner electrode layer 217 on the surface of the dielectric layer 210 and the bottom surface of the capacitor hole and the step of forming the first conductive layer 218 filling the cavity are performed simultaneously. The specific process includes: Fig.10 and Fig.11 , an outer electrode material layer 215 is formed in the cavity 213, on the surface of the support layer 206, on the surface of the dielectric layer 210, and at the bottom of the capacitor hole 208; Fig.12 After forming the outer electrode material layer 215, a second conductive layer 216 is formed on the outer electrode material layer 215 to fill the remaining capacitor holes; Fig.13After forming the second conductive layer 216, the outer electrode material layer in the cavity is disconnected from the outer electrode material layer in the capacitor hole, and the remaining outer electrode material layer in the cavity is used as the first conductive layer 218, and the remaining outer electrode material layer in the capacitor hole is used as the outer electrode layer 217. Through the above process, the formation process of the first conductive layer 218 and the outer electrode layer 217 can be carried out simultaneously, saving process steps, and after forming the second conductive layer 216, the second conductive layer 216 and the dielectric layer 210 can directly define the part of the outer electrode material layer that needs to be removed, so that the outer electrode material layer is directly etched and disconnected without forming a mask layer, thereby further saving process steps.

[0091] In some embodiments, the outer electrode material layer 215 may be a single-layer structure formed by one of W, Al, Cu, Ag, Au, Co, Pt, Ni, Ti, Ta, TiN, TaN, TaC, TaSiN, NiSi, CoSi, TiAl, and WSi, or a stacked-layer structure formed by two or more materials in the group consisting of the above materials. In this embodiment, the outer electrode material layer 215 is a TiN layer.

[0092] In some embodiments, the material of the second conductive layer 216 may be different from the material of the external electrode material layer 215 , and the material of the second conductive layer 216 may be doped polysilicon, specifically N-type polysilicon or P-type polysilicon.

[0093] In some embodiments, the formation process of the second conductive layer 216 includes: forming a second conductive material layer on the external electrode material layer 215, and the second conductive material layer fills the remaining capacitor holes; etching back to remove a portion of the thickness of the second conductive material layer, and forming a second conductive layer 216 on the external electrode material layer 215 to fill the remaining capacitor holes.

[0094] The first conductive layer 218 contacts the external electrode layer 209 and together form an external electrode of the capacitor. The second conductive layer 216 contacts the internal electrode layer 217 and together form an internal electrode of the capacitor.

[0095] refer to Fig.14 , forming an isolation layer 219 covering the second conductive layer 216 , the dielectric layer 210 , the outer electrode layer 209 , the inner electrode layer 217 and the support layer 216 .

[0096] The isolation layer 219 is used for electrical isolation between the capacitor structures. In some embodiments, the isolation layer 219 can be a single layer structure formed by one of the high-K dielectric materials, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride, or a stacked layer structure formed by two or more materials in the group consisting of the above materials. The high-K dielectric material can be HfO2 、TiO 2 、HfZrO、HfSiNO、Ta 2 O 5 、ZrO 2 、ZrSiO 2 、Al 2 O 3 、SrTiO 3 or BaSrTiO. The isolation layer 219 may be formed by atmospheric pressure or low pressure chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), thermal chemical vapor deposition (Thermal CVD), high density plasma chemical vapor deposition (HDPCVD), high aspect ratio deposition process (HARPCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or plasma vapor deposition process (Chemical Vapor Deposition).

[0097] refer to Fig.15 , forming a plurality of openings 220 in the isolation layer 219 to expose the first conductive layer 218 and the external electrode 209; Fig.16 A connection structure 219 electrically connected to the first conductive layer 218 and the external electrode layer 209 is formed on the surface of the isolation layer 219 and in the opening 220 .

[0098] The connection structure 219 connects all the separate external electrodes 209 together. The material of the connection structure 219 is metal. In some embodiments, the connection structure 219 can be a single-layer structure formed by one of the materials selected from W, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, WN, and WSi, or a stacked-layer structure formed by two or more materials selected from the group consisting of the above materials.

[0099] Some embodiments of the present application also provide a semiconductor structure, referring to Fig.16 ,include:

[0100] Base 200;

[0101] A plurality of discrete annular outer electrode layers 209 located on the substrate 200;

[0102] A dielectric layer 210 located on the inner side wall of the outer electrode 210;

[0103] An inner electrode layer 217 located on the inner sidewall of the dielectric layer 210 and on the substrate surface within the ring of the outer electrode layer 209;

[0104] A first conductive layer 218 filling the outer ring space of the outer electrode layer 209, wherein the first conductive layer 218 is in contact with the outer electrode layer 209;

[0105] A second conductive layer 216 filling the inner ring space of the inner electrode layer 217, wherein the second conductive layer 216 is connected to the inner electrode layer 217;

[0106] an isolation layer 219 covering the second conductive layer 216, the dielectric layer 209, the outer electrode layer 209 and the inner electrode layer 217, wherein the isolation layer 219 is formed with an opening exposing the first conductive layer 218 and the outer electrode layer 209;

[0107] A connection structure 220 is located on the surface of the isolation layer 219 and in the opening and is connected to the first conductive layer 218 and the external electrode layer 209 .

[0108] In some embodiments, the substrate 200 has a plurality of electrode contact structures 203 , adjacent electrode contact structures 203 are isolated by an insulating layer 202 , and the outer electrode layer 217 is connected to corresponding electrode contact structures 203 .

[0109] In some embodiments, the outer electrode layer 209 , the first conductive layer 218 , and the inner electrode layer 217 are made of the same material.

[0110] In some embodiments, the outer electrode layer, the first conductive layer and the inner electrode layer are a single-layer structure formed by one material selected from the group consisting of W, Al, Cu, Ag, Au, Co, Pt, Ni, Ti, Ta, TiN, TaN, TaC, TaSiN, NiSi, CoSi, TiAl, and WSi, or a stacked-layer structure formed by two or more materials selected from the group consisting of the above materials.

[0111] In some embodiments, the material of the second conductive layer 216 is doped polysilicon, and the material of the dielectric layer 210 is a high dielectric constant (K) material.

[0112] In some embodiments, a support layer 206 is further provided between the outer electrode layers 209 , and the support layer 206 is in contact with the outer sidewalls of the outer electrode layers 209 .

[0113] Although the present application has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present application. Any technical personnel in this field can use the methods and technical contents disclosed above to make possible changes and modifications to the technical solution of the present application without departing from the spirit and scope of the present application. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are within the protection scope of the technical solution of the present application.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a sacrificial layer and a supporting layer on the sacrificial layer on the substrate; Removing part of the support layer and the sacrificial layer, and forming a plurality of capacitor holes in the support layer and the sacrificial layer; forming an outer electrode layer on the side wall surface of the capacitor hole; forming a dielectric layer on the side wall surface of the outer electrode layer; Removing the remaining sacrificial layer between the outer electrode layers, and forming a cavity at the position where the remaining sacrificial layer is removed; forming an inner electrode layer on the surface of the dielectric layer and the bottom surface of the capacitor hole; forming a first conductive layer filling the cavity, wherein the first conductive layer is in contact with the outer electrode layer; forming a second conductive layer on the inner electrode layer to fill the remaining capacitor holes; forming an isolation layer covering the second conductive layer, the dielectric layer, the outer electrode layer, the inner electrode layer and the support layer; A plurality of openings exposing the first conductive layer and the external electrode layer are formed in the isolation layer; and connection structures electrically connected to the first conductive layer and the external electrode layer are formed on the surface of the isolation layer and in the openings.

2. The method for forming a semiconductor structure according to claim 1, wherein: A plurality of electrode contact structures are formed in the substrate, adjacent electrode contact structures are isolated by an insulating layer, and the plurality of capacitor holes expose corresponding electrode contact structures.

3. The method for forming a semiconductor structure according to claim 2, wherein: The material of the sacrificial layer is different from the materials of the supporting layer and the insulating layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: The process of forming a plurality of capacitor holes in the support layer and the sacrificial layer includes: using a dry etching process to remove part of the support layer and the sacrificial layer to form initial capacitor holes in the support layer and the sacrificial layer; using a first wet etching process to thin the sacrificial layer on the side wall of the initial capacitor hole to increase the size of the initial capacitor hole; using a second wet etching process to remove part of the support layer and the insulating layer to form capacitor holes.

5. The method for forming a semiconductor structure according to claim 4, wherein: The minimum thickness of the sacrificial layer between adjacent capacitor holes is less than one fifth of the diameter of the capacitor hole.

6. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the external electrode layer includes: forming an external electrode material layer on the side wall and bottom surface of the capacitor hole and the surface of the support layer; using a maskless etching process to remove the external electrode material layer located on the bottom surface of the capacitor hole and the surface of the support layer, and the remaining external electrode material layer on the side wall of the capacitor hole serves as the external electrode layer.

7. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the dielectric layer includes: forming a dielectric material layer on the side wall surface of the external electrode layer, the bottom surface of the capacitor hole and the surface of the support layer; using a maskless etching process to remove the dielectric material layer located on the bottom surface of the capacitor hole and the surface of the support layer, and the remaining dielectric material layer on the side wall surface of the external electrode layer is used as the dielectric layer.

8. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the inner electrode layer on the surface of the dielectric layer and the bottom surface of the capacitor hole and the step of forming the first conductive layer filling the cavity are performed simultaneously.

9. The method for forming a semiconductor structure according to claim 8, wherein: The process of forming an inner electrode layer on the surface of the dielectric layer and the bottom surface of the capacitor hole and forming a first conductive layer that fills the cavity includes: forming an inner electrode material layer in the cavity, on the surface of the support layer, on the surface of the dielectric layer and at the bottom of the capacitor hole; after forming the inner electrode material layer, forming a second conductive layer on the inner electrode material layer that fills the remaining capacitor holes; after forming the second conductive layer, disconnecting the inner electrode material layer in the cavity from the inner electrode material layer in the capacitor hole, and using the remaining inner electrode material layer in the cavity as the first conductive layer and the remaining inner electrode material layer in the capacitor hole as the inner electrode layer.

10. The method for forming a semiconductor structure according to claim 1, wherein: After forming the dielectric layer, the remaining sacrificial layer between the external electrode layers is removed, and the process of forming a cavity at the position where the sacrificial layer is removed includes: forming a mask layer on the surface of the support layer, on the top surface of the external electrode layer and the dielectric layer, and above the capacitor hole, and forming a first opening in the mask layer to expose a portion of the surface of the support layer between adjacent capacitor holes; using the mask layer as a mask, etching the exposed support layer along the first opening to expose the surface of the sacrificial layer at the bottom; removing all sacrificial layers along the position of the exposed sacrificial layer to form a cavity at the position where the sacrificial layer is removed; and removing the mask layer.

Images