Method for forming capacitor, capacitor, and semiconductor device

Abstract

Embodiments of the present application provide a capacitor forming method, a capacitor and a semiconductor device. The method comprises: providing a semiconductor structure, the semiconductor structure comprising a substrate, a stack structure, a protection layer, a first mask layer and a photoetching layer stacked in sequence; wherein the photoetching layer has a plurality of cross patterns arranged in a square close-packed manner; patterning the first mask layer based on the photoetching layer until the protection layer is exposed; based on the patterned first mask layer, etching to form a plurality of through holes penetrating through the protection layer and the stack structure to expose the substrate; wherein in a direction perpendicular to a surface of the substrate, a projection pattern of the through holes is a cross pattern, and the plurality of through holes are arranged in the square close-packed manner; sequentially forming a first electrode layer, a dielectric layer and a second electrode layer covering inner walls of the through holes to form the capacitor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and relates to but is not limited to a forming method of a capacitor, the capacitor and a semiconductor device. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device of a computer and is composed of many repeated memory cells. Each memory cell contains a transistor and a capacitor, the gate of the transistor is connected with a word line, the drain is connected with a bit line, and the source is connected with the capacitor. A voltage signal on the word line can control the opening or closing of the transistor, and then data information stored in the capacitor is read through the bit line or the data information is written into the capacitor through the bit line for storage.

[0003] With the size of the DRAM device becoming smaller and smaller, the capacitance area and the capacitance of the capacitor are required to be higher and higher. Therefore, how to provide a capacitor structure with higher density capacitance is an urgent problem to be solved. SUMMARY

[0004] Therefore, the present application provides a forming method of a capacitor, the capacitor and a semiconductor device.

[0005] In a first aspect, the present application provides a forming method of a capacitor, comprising:

[0006] providing a semiconductor structure, the semiconductor structure comprising a substrate, a stack structure, a protection layer, a first mask layer and a photoetching layer stacked in sequence; wherein the photoetching layer has a plurality of cross patterns, and the plurality of cross patterns are arranged in a square close-packed manner;

[0007] patterning the first mask layer based on the photoetching layer until the protection layer is exposed;

[0008] based on the patterned first mask layer, etching to form a plurality of through holes penetrating through the protection layer and the stack structure to expose the substrate; wherein, in a direction perpendicular to the surface of the substrate, the projection pattern of the through hole is a cross pattern, and the plurality of through holes are arranged in the square close-packed manner;

[0009] sequentially forming a first electrode layer, a dielectric layer and a second electrode layer covering the inner wall of the through hole to form the capacitor.

[0010] In some embodiments, every four adjacent cross patterns in the photoetching layer are connected to form a square at the position points.

[0011] In some embodiments, the plurality of cross patterns in the photoetching layer are arranged in a hexagonal close-packed manner.

[0012] In some embodiments, the first mask layer comprises: a polysilicon layer, an oxidation layer and a first hard mask layer stacked in sequence;

[0013] The patterning of the first mask layer based on the photoresist layer comprises:

[0014] The patterning of the first hard mask layer based on the photoresist layer forms a patterned first hard mask layer;

[0015] Based on the patterned first hard mask layer, the oxidation layer and the polysilicon layer are etched in sequence to complete the patterning process of the polysilicon layer, the oxidation layer and the first hard mask layer, and form the patterned first mask layer.

[0016] In some embodiments, the semiconductor structure is formed by the following steps:

[0017] The substrate is provided;

[0018] On the surface of the substrate, a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer and a third support layer are sequentially deposited to form a laminated structure covering the substrate;

[0019] On the surface of the laminated structure, the protective layer and the first mask layer are sequentially deposited;

[0020] The photoresist layer covering the first mask layer is formed.

[0021] In some embodiments, the first electrode layer, the dielectric layer and the second electrode layer covering the inner wall of the via hole are sequentially formed, comprising:

[0022] An initial electrode layer covering the protective layer and the inner wall of the via hole is formed;

[0023] The protective layer and the initial electrode layer covering the protective layer are removed to expose the third support layer; wherein the remaining initial electrode layer after the protective layer and the initial electrode layer covering the protective layer are removed constitutes the first electrode layer;

[0024] In the radial direction of the first electrode layer, the dielectric layer and the second electrode layer covering the first electrode layer are sequentially formed.

[0025] In some embodiments, after the first electrode layer is formed, the method further comprises:

[0026] In any direction parallel to the substrate, part of the third support layer is etched to form a first opening, and the first opening exposes the second sacrificial layer;

[0027] Through the first opening, while removing the remaining second sacrificial layer and exposing the first electrode layer and the second support layer, etching part of the second support layer in the either direction forms a second opening, which exposes the first sacrificial layer;

[0028] Through the second opening, removing the remaining first sacrificial layer exposes the first support layer, forming a void.

[0029] In some embodiments, the forming, in the radial direction of the first electrode layer, a dielectric layer covering the first electrode layer and a second electrode layer in sequence comprises:

[0030] The forming, in the radial direction of the first electrode layer, the dielectric layer covering the first electrode layer in sequence while forming the dielectric layer in the void, wherein the dielectric layer covers the first electrode layer, the remaining first support layer, the remaining second support layer and the remaining third support layer;

[0031] The forming of the second electrode layer covering the dielectric layer.

[0032] In some embodiments, the second electrode layer has a plurality of gaps; after the forming of the second electrode layer, the method further comprises:

[0033] Filling a semiconductor material in the gap of the second electrode layer forms a filling structure to support the capacitor through the filling structure.

[0034] In some embodiments, the substrate has a plurality of contact points; after the forming of the first electrode layer, the first electrode layer is connected with the contact points.

[0035] In a second aspect, the embodiments of the present application provide a capacitor, which at least comprises:

[0036] A substrate;

[0037] A first support layer, a second support layer and a third support layer arranged on the substrate, the second support layer being between the first support layer and the third support layer;

[0038] A first electrode layer arranged perpendicularly to the substrate and penetrating through the first support layer, the second support layer and the third support layer; wherein in the direction perpendicular to the surface of the substrate, the projection pattern of the first electrode layer is a cross pattern, and a plurality of the first electrode layers are arranged in a square close-packed manner;

[0039] A dielectric layer covering the surface of each of the first electrode layers;

[0040] A second electrode layer covering the surface of each of the dielectric layers.

[0041] In some embodiments, the plurality of first electrode layers are arranged in a hexagonal close-packed manner.

[0042] In some embodiments, the substrate is provided with a plurality of contact points; each of the contact points is connected with a first electrode layer.

[0043] In some embodiments, the capacitor further comprises: a filling structure filled in the gap of the second electrode layer, the filling structure is used to support the capacitor.

[0044] In some embodiments, the material of the first support layer, the second support layer and the third support layer comprises at least one of: silicon oxide, silicon nitride, silicon carbon nitride and silicon oxynitride.

[0045] In some embodiments, the material of the first electrode layer comprises at least one of: metal nitride and metal silicide;

[0046] The material of the second electrode layer comprises at least one of: metal nitride and metal silicide;

[0047] The material of the dielectric layer comprises at least one of: zirconium oxide, hafnium oxide, titanium zirconium oxide, ruthenium oxide, antimony oxide and aluminum oxide.

[0048] In a third aspect, the embodiments of the present application provide a semiconductor device, which at least comprises any one of the capacitors.

[0049] The capacitor forming method, capacitor and semiconductor device provided by the embodiments of the present application provide a semiconductor structure comprising a substrate, a stacked structure, a protection layer, a first mask layer and a photoetching layer which are stacked in sequence, then the first mask layer is patterned by the photoetching layer having a plurality of cross-shaped patterns, based on the patterned first mask layer, a plurality of cross-shaped through holes arranged in a square close-packed manner are etched to form through the protection layer and the stacked structure, so as to expose the substrate; then, the first electrode layer, the dielectric layer and the second electrode layer covering the inner wall of the cross-shaped through hole are formed in sequence, so as to form the capacitor. The embodiments of the present application form the electrode layer with cross-shaped structure arranged in a square close-packed manner, so that the utilization rate of the capacitor is increased while the capacitance area and the capacitance of the capacitor are increased, the capacitance density of the capacitor is higher, and the performance of the capacitor is improved. BRIEF DESCRIPTION OF DRAWINGS

[0050] In the drawings, which are not necessarily drawn to scale, like numerals can describe similar components in different views. Like numerals having different letter suffixes can represent different instances of similar components. The drawings illustrate generally, by way of example, various embodiments discussed herein.

[0051] Figure 1AFigure 1 is a partial structure schematic diagram of a capacitor provided by an embodiment of the present application;

[0052] Figure 1B Figure 2 is a cross-sectional schematic diagram of a capacitor provided by an embodiment of the present application;

[0053] Figure 2 Figure 3 is a flow schematic diagram of a forming method of a capacitor provided by an embodiment of the present application;

[0054] Figures 3A to 3N Figure 4 is a partial structure schematic diagram of a forming method of a capacitor provided by an embodiment of the present application;

[0055] Figure 4 Figure 5 is a partial top view of a semiconductor structure provided by an embodiment of the present application;

[0056] Figure 5A and Figure 5B Figure 6 is a partial structure schematic diagram of a forming method of a capacitor provided by an embodiment of the present application;

[0057] Figure 6 Figure 7 is a partial structure schematic diagram of a capacitor provided by an embodiment of the present application;

[0058] Figure 7 Figure 8 is a partial structure schematic diagram of a capacitor with a contact point provided by an embodiment of the present application. DETAILED DESCRIPTION

[0059] The specific technical solutions of the present disclosure will be further described in detail below with reference to the drawings in the embodiments of the present application. The following embodiments are used to illustrate the present application, but not to limit the scope of the present application.

[0060] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid obscuring the present application, some technical features known in the art are not described; that is, not all features of the actual embodiments are described here, and well-known functions and structures are not described in detail.

[0061] In the drawings, the size and relative size of layers, regions, elements, and the like can be exaggerated for clarity. Identical reference signs represent identical elements throughout.

[0062] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected", or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application.

[0063] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0064] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0065] The cross section of the capacitor hole in the prior art is circular, and the traditional capacitor hole arrangement is 6F 2The honeycomb-like close arrangement of the DRAM capacitor leads to a small capacitance and a low capacitance density of the capacitor in the related art, and the performance of the capacitor is low.

[0066] Based on the problems in the related art, the application provides a capacitor, please refer to Figure 1A and Figure 1B , wherein Figure 1A is a partial structure diagram of the capacitor provided by the application, Figure 1B is a cross-sectional schematic diagram of the capacitor provided by the application, as Figure 1A shown, the capacitor 10 comprises a substrate 101, a first support layer 102, a second support layer 103, a third support layer 104, a first electrode layer 105, a dielectric layer 106 and a second electrode layer 107.

[0067] The first support layer 102, the second support layer 103 and the third support layer 104 are arranged on the substrate 101, wherein the second support layer 103 is located between the first support layer 102 and the third support layer 104.

[0068] The first electrode layer 105 is arranged perpendicular to the substrate 101, and the first electrode layer 105 penetrates the first support layer 102, the second support layer 103 and the third support layer 104; wherein in the direction perpendicular to the surface of the substrate 101, the projection pattern of the first electrode layer 105 is a cross pattern, and a plurality of the first electrode layer 105 is arranged in a square close-packed manner.

[0069] The dielectric layer 106 covers the surface of each first electrode layer 105.

[0070] The second electrode layer 107 covers the surface of each dielectric layer 106.

[0071] The application has an electrode layer arranged in a square close-packed manner, and the electrode layer has a cross structure, which increases the capacitance area and the capacitance of the capacitor, increases the utilization rate of the capacitor, makes the capacitance density of the capacitor higher, and improves the performance of the capacitor.

[0072] The electrode layer arranged in a square close-packed manner and having a cross structure provided by the application can be used for vertical gate-all-around array (VGAA Array) arrangement, that is, the capacitor is directly connected to the transistor, and the capacitor does not need to be connected through the storage node (Node Contact, NC) to be misaligned, which solves the 6F 2 The size of the DRAM can be smaller due to the problem of the storage node occupying the DRAM plane area.

[0073] In some embodiments, the capacitor provided by the embodiments of the present application is not only suitable for a double-layer capacitor, but also suitable for a single-layer capacitor. The forming method of the capacitor provided by the embodiments of the present application is described below by taking a double-layer capacitor as an example.

[0074] The embodiments of the present application provide a forming method of a capacitor, Figure 2 is a flowchart of the forming method of the capacitor provided by the embodiments of the present application. As shown in Figure 2 , the capacitor can be formed by the following steps:

[0075] Step S201, providing a semiconductor structure, the semiconductor structure comprising a substrate, a laminated structure, a protection layer, a first mask layer and a photoetching layer stacked in sequence; wherein the photoetching layer has a plurality of cross patterns, and the plurality of cross patterns are arranged in a square close-packed manner.

[0076] Step S202, patterning the first mask layer based on the photoetching layer until the protection layer is exposed.

[0077] Step S203, based on the patterned first mask layer, etching to form a plurality of through holes penetrating through the protection layer and the laminated structure to expose the substrate; wherein the projection pattern of the through hole in the direction perpendicular to the surface of the substrate is a cross pattern, and the plurality of through holes are arranged in the square close-packed manner.

[0078] Step S204, sequentially forming a first electrode layer, a dielectric layer and a second electrode layer covering the inner wall of the through hole to form the capacitor.

[0079] The forming method of the capacitor provided by the embodiments of the present application is described in detail below. Figures 3A to 3N

[0080] As shown in Figure 3A , step S201 is performed to provide a semiconductor structure, and the semiconductor structure comprises a substrate 301, a laminated structure 302, a protection layer 303, a first mask layer 304 and a photoetching layer 305 stacked in sequence.

[0081] In some embodiments, the semiconductor structure can be formed by the following steps:

[0082] Step S2011, providing the substrate.

[0083] In some embodiments, the substrate 301 in the semiconductor structure can be made of a semiconductor material, such as one or more of silicon, germanium, silicon-germanium compound and silicon-carbon compound.

[0084] ​Step S2012, sequentially depositing a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer and a third support layer on the substrate surface to form the stack structure.

[0085] In the embodiments of the present application, the stack structure 302 covering the substrate 301 can be formed by a physical vapor deposition (PVD), a chemical vapor deposition (CVD) or an atomic layer deposition process, wherein the stack structure 302 can include a first support layer 3021, a first sacrificial layer 3022, a second support layer 3023, a second sacrificial layer 3024 and a third support layer 3025 which are sequentially deposited on the substrate 301.

[0086] Here, in order to facilitate etching of the stack structure 302, the first sacrificial layer 3022 and the second sacrificial layer 3024 can be a material with a soft material such as phosphoro silicate glass (PSG), boro-phospho-silicate glass (BPSG) or fluoro silicate glass (FSG); the first support layer 3021, the second support layer 3023 and the third support layer 3025 can be a nitride such as silicon nitride, silicon carbon nitride, silicon oxynitride or silicon boron nitride.

[0087] Step S2013, sequentially depositing the protective layer and the first mask layer on the surface of the stack structure.

[0088] In some embodiments, the protective layer 303 and the first mask layer 304 are sequentially deposited on the surface of the stack structure 302. Here, the protective layer 303 protects the third support layer 3025 in the stack structure 302 from damage in the subsequent etching process. The material of the protective layer 303 can be an oxide such as silicon oxide. It should be noted that the thickness of the protective layer 303 can be between 50 nm and 100 nm.

[0089] Step S2014, forming the photoresist layer covering the first mask layer.

[0090] In some embodiments, the photoresist layer 305 covering the first mask layer 304 is deposited, the photoresist layer 305 has a plurality of cross patterns, and the plurality of cross patterns are arranged in a square close-packed manner, as shown in Figure 3B Figure 3B is a top view of the semiconductor structure provided in the embodiments of the present application.

[0091] Next, please refer to​Figure 3C and Figure 3D In step S202, the first mask layer 304 is patterned based on the photoresist layer 305, to obtain a patterned first mask layer 304', until the protective layer 303 is exposed.

[0092] In some embodiments, the first mask layer 304 can be patterned by a dry etching process or a wet etching process. When the dry etching process is used, the etching gas can be any one of hydrogen bromide (HBr), nitrogen trifluoride (NF3) or trifluoromethane (CHF3), and the etching temperature of the dry etching can be set between 30-90°C. By limiting the etching gas and the etching temperature of the dry etching, the etching precision of the first mask layer is improved.

[0093] In some embodiments, the patterned first mask layer 304' has the same pattern as the photoresist layer 305, as shown in Figure 3D .

[0094] In the embodiments of the present application, the photoresist layer 305 is removed at the same time when the first mask layer 304 is patterned.

[0095] Next, refer to Figure 3E and Figure 3F In step S203, based on the patterned first mask layer 304', a plurality of through holes 306 are etched to form through the protective layer 303 and the laminated structure 302, to obtain an etched protective layer 303' and an etched laminated structure 302', to expose the substrate 301. Here, the etched laminated structure 302' includes an etched first support layer 3021', an etched first sacrificial layer 3022', an etched second support layer 3023', an etched second sacrificial layer 3024' and an etched third support layer 3025'.

[0096] In some embodiments, the protective layer 303 and the laminated structure 302 can be etched by a dry etching process or a wet etching process to form the through holes 306, and the patterned first mask layer 304' is removed at the same time when the through holes 306 are formed.

[0097] Figure 3F is a top view of the semiconductor structure after the through holes are formed, as shown in Figure 3F The through holes 306 expose the substrate 301, the structure of the through holes 306 is a cross pattern, and a plurality of through holes 306 are arranged in a square close-packed manner, and each adjacent four through holes 306 form a square.

[0098] Next, refer to Figure 3G and Figure 3NS204, sequentially forming a first electrode layer, a dielectric layer and a second electrode layer covering the inner wall of the via hole.

[0099] In some embodiments, step S204 can be formed by the following steps:

[0100] S2041, forming an initial electrode layer covering the protective layer and the inner wall of the via hole.

[0101] Please refer to Figure 3G The initial electrode layer 307' can be formed on the inner wall of the via hole 306 and the surface of the etched protective layer 303' by physical vapor deposition, chemical vapor deposition or atomic layer deposition process.

[0102] S2042, removing the protective layer and the initial electrode layer covering the protective layer to expose the third support layer; wherein the remaining initial electrode layer after removing the protective layer and the initial electrode layer covering the protective layer constitutes the first electrode layer.

[0103] Please refer to Figure 3H The etched protective layer 303' and the part of the initial electrode layer 307' covering the surface of the etched protective layer 303' can be removed by dry etching or wet etching to form the first electrode layer 307.

[0104] In some embodiments, the material of the first electrode layer 307 can include metal nitride and / or metal silicide.

[0105] In some embodiments, when etching part of the initial electrode layer 307', the upper surface of the etched first electrode layer 307 can be lower than the upper surface of the remaining third support layer (i.e. the etched third support layer 3025') in the stack structure 302 in the direction perpendicular to the surface of the substrate 301, as shown in Figure 3H .

[0106] In some embodiments, when etching part of the initial electrode layer 307', the upper surface of the etched first electrode layer 307 can be flush with the upper surface of the etched third support layer 3025' in the stack structure 302 in the direction perpendicular to the surface of the substrate, as shown in Figure 3I .

[0107] S2043, etching part of the third support layer in any direction parallel to the substrate to form a first opening, the first opening exposing the second sacrificial layer.

[0108] Please refer to Figure 3JIn any direction parallel to the substrate, the third support layer 3025' is partially etched to form a first opening 308 penetrating the third support layer 3025', and the first opening 308 exposes the etched second sacrificial layer 3024'. In the embodiments of the present application, one first opening 308 can be formed between every four adjacent through holes, or one first opening 308 can be formed between every two adjacent through holes, and the present application does not limit the position of the first opening.

[0109] In some embodiments, dry etching or wet etching can be used to remove part of the third support layer 3025.

[0110] In step S2043, through the first opening, the remaining second sacrificial layer is removed to expose the first electrode layer and the second support layer, and at the same time, part of the second support layer is etched in any direction to form a second opening, and the second opening exposes the first sacrificial layer.

[0111] Please refer to Figure 3K After the first opening 308 is formed, dry etching or wet etching can be used to remove the remaining second sacrificial layer (i.e. the etched second sacrificial layer 3024'), and part of the etched second support layer 3023' is etched to form a second opening 309 penetrating the etched second support layer 3023'.

[0112] In some embodiments, when wet etching is used to remove the etched second sacrificial layer 3024', the wet etching solution can be a mixed solution including dilute hydrofluoric acid (DHF) and ammonia water (NH4OH), or a mixed solution including dilute hydrofluoric acid (DHF) and tetramethylammonium hydroxide (TMAH).

[0113] In some embodiments, the projection position of the first opening 308 and the projection position of the second opening 309 can be the same or different in the direction perpendicular to the surface of the substrate 301.

[0114] In step S2044, through the second opening, the remaining first sacrificial layer is removed to expose the first support layer, and a void is formed.

[0115] Please refer to Figure 3L The remaining first sacrificial layer (i.e. the etched first sacrificial layer 3022') can be removed by dry etching or wet etching to form a void 310, and the void 310 exposes part of the outer wall of the first electrode layer 307 and the etched first support layer 3021', the etched second support layer 3023' and the etched third support layer 3025'.

[0116] In some embodiments, the void 310 penetrates through the whole etched stack structure 302', and thus the second opening 309 is located in the void 310.

[0117] In step S2045, the dielectric layer is formed in the void along the radial direction of the first electrode layer while sequentially forming the dielectric layer covering the first electrode layer, wherein the dielectric layer covers the first electrode layer, the remaining first support layer, the remaining second support layer and the remaining third support layer.

[0118] Please refer to Figure 3M The dielectric layer 311 covering the first electrode layer 307, the etched first support layer 3021', the etched second support layer 3023' and the etched third support layer 3025' can be formed by a physical vapor deposition, a chemical vapor deposition or an atomic layer deposition process.

[0119] In some embodiments, the material of the dielectric layer 311 includes at least one of zirconium oxide, hafnium oxide, titanium zirconium oxide, ruthenium oxide, antimony oxide and aluminum oxide.

[0120] In step S2046, the second electrode layer covering the dielectric layer is formed.

[0121] Please refer to Figure 3N The second electrode layer 312 covering the dielectric layer 311 is formed by a deposition process to form the capacitor.

[0122] In some embodiments, the material of the second electrode layer 312 includes at least one of metal nitride and metal silicide.

[0123] The embodiments of the present application form a first mask layer by patterning a plurality of cross patterns of a photoetching layer, form a plurality of cross-shaped through holes arranged in a square close-packed manner penetrating through the protective layer and the stack structure based on the patterned first mask layer to expose the substrate, sequentially form a first electrode layer, a dielectric layer and a second electrode layer covering the inner wall of the cross-shaped through hole to form the capacitor. The capacitor forming method provided by the embodiments of the present application forms an electrode layer with a cross structure arranged in a square close-packed manner, which increases the utilization rate of the capacitor, makes the capacitance density of the capacitor higher and improves the performance of the capacitor.

[0124] In some embodiments, the plurality of cross patterns in the photoetching layer 305 in step S2014 can also be arranged in a hexagonal close-packed manner, as shown in Figure 4 Figure 4 is a partial top view of a semiconductor structure provided by the embodiments of the present application, wherein the position points where every four adjacent cross patterns in the photoetching layer 305 are connected to form a rhombus. ​

[0125] In some embodiments, the first mask layer 304 can include a polysilicon layer 3041, an oxidation layer 3042 and a first hard mask layer 3043 stacked in sequence. Next, refer to Figure 5A and Figure 5B , step S202 can be implemented by the following steps:

[0126] Step S2021, patterning the first hard mask layer based on the photoetching layer, to form a patterned first hard mask layer.

[0127] Step S2022, etching the oxidation layer and the polysilicon layer in sequence based on the patterned first hard mask layer, to complete the patterning process of the polysilicon layer, the oxidation layer and the first hard mask layer, and form the patterned first mask layer.

[0128] As shown in Figure 5A and Figure 5B , the first hard mask layer 3043 is patterned by the photoetching layer 305 to form a patterned first hard mask layer 3043'. Here, the first hard mask layer 3043 can be a single-layer structure or a stacked structure, and the first hard mask layer 3043 provided by the embodiments of the present application is a stacked structure. Here, the material of the first hard mask layer 3043 can be any one of free silicon carbide, bottom anti-reflection coating (BARC) and spin-on carbon (SOC).

[0129] After the first hard mask layer 3043 is patterned, the photoetching layer 305 is removed, and the oxidation layer 3042 and the polysilicon layer 3041 are etched in sequence based on the patterned first hard mask layer 3043' to form an etched oxidation layer 3042' and an etched polysilicon layer 3041'.

[0130] In some embodiments, after step S204, the gap and the surface of the second electrode layer 312 can be filled with a semiconductor material to form a filling structure 601, so as to support the capacitor through the filling structure 601, as shown in Figure 6 , Figure 6 is a partial structure schematic diagram of the capacitor provided by the embodiments of the present application. Here, the filling structure can be formed by physical vapor deposition, chemical vapor deposition or atomic layer deposition process, and the filling structure can be silicon germanium or lanthanum oxide.

[0131] In some embodiments, the substrate 301 has a plurality of contact points 701, and after the first electrode layer 307 is formed, the first electrode layer 307 is connected with the contact points 701, as shown in Figure 7As shown, the contact point 701 is used to connect the capacitor and the source or drain of the transistor in the substrate.

[0132] The capacitor provided by the embodiment of the present application increases the capacitor area through the electrode layer of cross structure, and increases the capacitance of the capacitor, and the specific electrode layer dense arrangement manner makes the capacitance density of the capacitor higher, and meanwhile, the filling structure improves the support and stability of the capacitor, and improves the performance of the capacitor.

[0133] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The above-described device embodiments are merely exemplary. For example, the division of units is merely a logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling between the components shown or discussed can be indirect coupling through some interfaces.

[0134] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, they can be located in one place, or distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0135] The features disclosed in several method or device embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

[0136] The above is only some embodiments of the present disclosure, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application to achieve the purpose of the embodiments. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for forming a capacitor, the method comprising: providing a semiconductor structure, the semiconductor structure comprising, in sequence, a substrate, a stack structure, a protection layer, a first mask layer, and a photoresist layer, wherein the photoresist layer has a plurality of cross patterns arranged in a square close-packed manner; patterning the first mask layer based on the photoresist layer until the protection layer is exposed; etching a plurality of through holes penetrating through the protection layer and the stack structure based on the patterned first mask layer to expose the substrate, wherein a projection pattern of the through holes in a direction perpendicular to a surface of the substrate is a cross pattern, and the plurality of through holes are arranged in the square close-packed manner or a hexagonal close-packed manner; forming, in sequence, a first electrode layer, a dielectric layer, and a second electrode layer covering inner walls of the through holes to form the capacitor; and wherein the stack structure is formed by sequentially depositing, on the surface of the substrate, a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer, and a third support layer to form the stack structure. 2.The method of claim 1, wherein each of four adjacent cross patterns in the photoresist layer is connected to form a square, or each of four adjacent cross patterns in the photoresist layer is connected to form a rhombus. 3.The method of claim 1, wherein the first mask layer comprises, in sequence, a polysilicon layer, an oxide layer, and a first hard mask layer; and wherein the patterning the first mask layer based on the photoresist layer comprises: patterning the first hard mask layer based on the photoresist layer to form a patterned first hard mask layer; and etching, in sequence, the oxide layer and the polysilicon layer based on the patterned first hard mask layer to complete the patterning of the polysilicon layer, the oxide layer, and the first hard mask layer to form the patterned first mask layer. 4.The method of claim 1, wherein the semiconductor structure is formed by: providing the substrate; forming the stack structure on the surface of the substrate; sequentially depositing the protection layer and the first mask layer on the surface of the stack structure; and forming the photoresist layer covering the first mask layer. 5.The method of claim 4, wherein the forming, in sequence, the first electrode layer, the dielectric layer, and the second electrode layer covering the inner walls of the through holes comprises: forming an initial electrode layer covering the protection layer and the inner walls of the through holes; removing the protection layer and the initial electrode layer covering the protection layer to expose the third support layer, wherein the remaining initial electrode layer after the removal of the protection layer and the initial electrode layer covering the protection layer constitutes the first electrode layer; and sequentially forming, in a radial direction of the first electrode layer, the dielectric layer and the second electrode layer covering the first electrode layer. 6.The method of claim 5, wherein after the forming of the first electrode layer, the method further comprises: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ etching part of the third support layer in any direction parallel to the substrate to form a first opening, the first opening exposing the second sacrificial layer; through the first opening, etching part of the second support layer in any direction parallel to the substrate to form a second opening, the second opening exposing the first sacrificial layer, while removing the remaining second sacrificial layer and exposing the first electrode layer and the second support layer; through the second opening, removing the remaining first sacrificial layer to expose the first support layer, forming a void.

7. The method of claim 6, wherein forming a dielectric layer and a second electrode layer in sequence along the radial direction of the first electrode layer to cover the first electrode layer comprises: forming the dielectric layer in the void in sequence along the radial direction of the first electrode layer to cover the first electrode layer, wherein the dielectric layer covers the first electrode layer, the remaining first support layer, the remaining second support layer, and the remaining third support layer; and forming the second electrode layer to cover the dielectric layer.

8. The method of claim 1, wherein the second electrode layer has a plurality of gaps; and after forming the second electrode layer, the method further comprises: filling a semiconductor material in the gaps of the second electrode layer to form a filling structure to support the capacitor through the filling structure.

9. The method of claim 1, wherein the substrate has a plurality of contact points; and after forming the first electrode layer, the first electrode layer is connected to the contact points.

10. A capacitor prepared by the method of any one of claims 1-9, wherein the capacitor comprises: a substrate; a first support layer, a second support layer, and a third support layer disposed on the substrate, the second support layer being between the first support layer and the third support layer; a first electrode layer disposed perpendicularly to the substrate and penetrating through the first support layer, the second support layer, and the third support layer; wherein in a direction perpendicular to the surface of the substrate, the projection of the first electrode layer is a cross-shaped pattern, and a plurality of the first electrode layers are arranged in a square close-packed or hexagonal close-packed manner; a dielectric layer covering the surface of each of the first electrode layers; and a second electrode layer covering the surface of each of the dielectric layers.

11. The capacitor of claim 10, wherein the substrate has a plurality of contact points; and each of the contact points is connected to one of the first electrode layers.

12. The capacitor of claim 10, wherein the capacitor further comprises: a filling structure filled in the gaps of the second electrode layer, the filling structure being used to support the capacitor.

13. The capacitor of claim 10, wherein the material of the first support layer, the second support layer, and the third support layer comprises at least one of silicon oxide, silicon nitride, silicon carbon nitride, and silicon oxynitride.

14. The capacitor of claim 10, wherein The material of the first electrode layer includes at least one of metal nitride and metal silicide; The material of the second electrode layer includes at least one of metal nitride and metal silicide; The material of the dielectric layer includes at least one of zirconium oxide, hafnium oxide, titanium zirconium oxide, ruthenium oxide, antimony oxide and aluminum oxide.

15. A semiconductor device, comprising: The semiconductor device includes at least one capacitor formed by the method of any one of claims 1 to 9.

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