Semiconductor structure and method of fabricating the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to solve the technical problem of high parasitic capacitance of a semiconductor structure. The manufacturing method comprises the following steps: providing a substrate, wherein a plurality of first grooves are formed in the substrate in a spaced manner; forming a sacrificial layer in each first groove and a first protective layer on the sacrificial layer, wherein the sacrificial layer and the first protective layer fill the first groove, and the first protective layer in each first groove is provided with an etching hole penetrating through the first protective layer; removing the sacrificial layer by using the etching hole to form an air gap; and performing a siliconization reaction on the substrate located between adjacent first grooves and close to the groove bottom of the first groove to form a bit line in the substrate, wherein a side surface part of the bit line is exposed in the air gap. By forming the air gap and exposing part of the side surface of the bit line in the air gap, the dielectric constant of the structure between the bit lines is reduced, thereby reducing the parasitic capacitance of the semiconductor structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] With the advancement of semiconductor technology, the integration density of semiconductor structures (such as memory) continues to increase, and the spacing between devices in the semiconductor structure continues to decrease. This, in turn, causes the spacing between adjacent conductive devices (such as bit lines) in the semiconductor structure to also decrease. Adjacent conductive devices and the insulating material between them form parasitic capacitance. The parasitic capacitance is proportional to the dielectric constant of the insulating material and inversely proportional to the distance between the two conductive devices. As the spacing between bit lines decreases, the parasitic capacitance continues to increase, causing resistance and capacitance (RC) delays in the semiconductor structure, affecting the operating efficiency of the semiconductor structure. Summary of the Invention

[0003] In view of the above problems, embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, which are used to reduce the parasitic capacitance of the semiconductor structure and improve the working efficiency of the semiconductor structure.

[0004] A first aspect of an embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising:

[0005] Providing a substrate, wherein a plurality of first trenches are formed in the substrate and are spaced apart from each other, and the first trenches extend along a first direction;

[0006] forming a sacrificial layer in each of the first trenches and a first protective layer on the sacrificial layer, wherein the sacrificial layer and the first protective layer completely fill the first trenches, and an etching hole penetrating through the first protective layer is provided in the first protective layer in each of the first trenches;

[0007] removing the sacrificial layer by using the etched hole to form an air gap;

[0008] The substrate located between adjacent first trenches and close to the bottom of the first trench undergoes a silicidation reaction to form a bit line extending along the first direction in the substrate, with a side surface portion of the bit line exposed in the air gap.

[0009] The method for manufacturing a semiconductor structure provided by the embodiments of the present application has at least the following advantages:

[0010] In the method for manufacturing a semiconductor structure provided in an embodiment of the present application, an air gap is formed between bit lines extending along a first direction by removing a sacrificial layer, and part of the side surface of the bit line is exposed in the air gap. By utilizing the characteristic that the dielectric constant of air is approximately 1, the dielectric constant of the structure located between the bit lines is reduced, thereby reducing the parasitic capacitance of the semiconductor structure and improving the working efficiency of the semiconductor structure.

[0011] A second aspect of an embodiment of the present application provides a semiconductor structure comprising: a substrate, wherein a plurality of spaced-apart bit lines are formed in the substrate, the bit lines extending along a first direction, a first trench formed between two adjacent bit lines, at least one active region being provided on each bit line, the active region comprising a source region, a channel region, and a drain region stacked in sequence, one of the source region and the drain region being electrically connected to the bit line; a protective layer provided in the first trench, an air gap being formed between the protective layer and the bottom of the first trench, the side surface of the bit line being partially exposed in the air gap; a plurality of spaced-apart first insulating layers provided on the protective layer, the first insulating layer extending along a second direction, the first insulating layer being located between two adjacent rows of active regions in the second direction and spaced apart from the active regions; a gate structure provided between the first insulating layer and the active region, the gate structure extending along the second direction and surrounding the active region, the gate structure being opposite to at least a portion of the channel region; a second insulating layer and a third insulating layer covering the gate structure.

[0012] The semiconductor structure in the embodiment of the present application has at least the following advantages:

[0013] In the semiconductor structure in the embodiment of the present application, the bit line extends along a first direction, and a first trench is formed between two adjacent bit lines. A protective layer is provided in the first trench, and an air gap is formed between the protective layer and the bottom of the first trench. The side surface portion of the bit line is retained in the air gap. By utilizing the characteristic that the dielectric constant of air is approximately 1, the dielectric constant of the structure located between the bit lines is reduced, thereby reducing the parasitic capacitance of the semiconductor structure and improving the working efficiency of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0015] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure in an embodiment of the present application;

[0016] Figure 2 is a top view of a semiconductor structure in an embodiment of the present application;

[0017] Figures 3 to 6 They are schematic cross-sectional views of the substrate at points AA, BB, CC, and DD in the embodiments of the present application;

[0018] Figures 7 to 10 They are schematic cross-sectional views at AA, BB, CC and DD respectively after the first trench is formed in the embodiment of the present application;

[0019] Figures 11 to 14 They are schematic cross-sectional views of points AA, BB, CC, and DD after forming the first protective layer in an embodiment of the present application;

[0020] Figures 15 to 18 They are schematic cross-sectional views of points AA, BB, CC and DD after the etching holes are formed in the embodiment of the present application;

[0021] Figure 19 This is a top view after the etching hole is formed in the embodiment of the present application;

[0022] Figures 20 to 23 They are schematic cross-sectional views of points AA, BB, CC, and DD after forming air gaps in an embodiment of the present application;

[0023] Figures 24 to 27 They are schematic cross-sectional views at AA, BB, CC and DD after the second trench is formed in the embodiment of the present application;

[0024] Figures 28 to 31 They are schematic cross-sectional views of points AA, BB, CC, and DD after the second protective layer is formed in the embodiment of the present application;

[0025] Figures 32 to 35 They are schematic cross-sectional views of points AA, BB, CC, and DD after forming the third protective layer in an embodiment of the present application;

[0026] Figures 36 to 39 Another cross-sectional schematic diagram of points AA, BB, CC, and DD after forming the second protective layer in the embodiment of the present application;

[0027] Figures 40 to 43 They are schematic cross-sectional views at AA, BB, CC and DD after the bit lines are formed in the embodiment of the present application;

[0028] Figures 44 to 47They are schematic cross-sectional views of points AA, BB, CC and DD after the first insulating layer is formed in the embodiment of the present application;

[0029] Figures 48 to 51 They are schematic cross-sectional views of points AA, BB, CC, and DD after forming a filled trench in an embodiment of the present application;

[0030] Figures 52 to 55 They are schematic cross-sectional views of points AA, BB, CC and DD after the second insulating layer is formed in the embodiment of the present application;

[0031] Figures 56 to 59 They are schematic cross-sectional views of points AA, BB, CC, and DD after forming the filling space in the embodiment of the present application;

[0032] Figures 60 to 63 They are schematic cross-sectional views of positions AA, BB, CC, and DD, respectively, in which a conductive layer is formed in an embodiment of the present application;

[0033] Figures 64 to 67 They are schematic cross-sectional views of points AA, BB, CC and DD after the third insulating layer is formed in the embodiment of the present application;

[0034] Figure 68 and Figure 69 They are schematic cross-sectional views of points AA and CC after capacitors are formed in an embodiment of the present application.

[0035] Description of reference numerals:

[0036] 10-substrate; 11-first trench; 12-second trench;

[0037] 13-active region; 20-sacrificial layer; 21-air gap;

[0038] 30-first protective layer; 31-etched hole; 40-third protective layer;

[0039] 50 - second protection layer; 51 - third trench; 52 - bit line;

[0040] 61-first insulating layer; 62-second insulating layer; 63-third insulating layer;

[0041] 71-filling channel; 72-filling space; 80-gate structure;

[0042] 81- oxide layer; 82- conductive layer; 83- word line;

[0043] 91-contact node; 92-capacitor. DETAILED DESCRIPTION

[0044] An embodiment of the present application provides a method for manufacturing a semiconductor structure, by forming an air gap between bit lines, with the side surface of the bit line partially exposed in the air gap, and utilizing the dielectric constant of air being 1 to reduce the dielectric constant of the structure located between the two bit lines, thereby reducing the parasitic capacitance of the semiconductor structure and improving the working efficiency of the semiconductor structure.

[0045] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0046] refer to Figure 1 , an embodiment of the present application provides a method for manufacturing a semiconductor structure, the manufacturing method comprising the following steps:

[0047] Step S101: providing a substrate, wherein a plurality of first trenches are formed in the substrate and are spaced apart from each other, and the first trenches extend along a first direction.

[0048] refer to Figure 2 , Figure 2 This is a top view of a semiconductor structure in an embodiment of the present application, in which a word line 83 (WL) and a bit line 52 (BL) are formed. The bit line 52 extends along a first direction, and the word line 83 extends along a second direction. The first direction and the second direction have an angle, for example, the first direction and the second direction may be perpendicular. Specifically, as shown in FIG. Figure 2 As shown, the bit line 52 extends in the vertical direction (Y direction), the word line 83 extends in the horizontal direction (X direction), and the gate structure is formed in the word line 83. The word line 83 or the bit line 52 can be a straight line or a broken line.

[0049] Figure 2 There are cross sections at different positions in the image. Specifically, the cross section at AA is parallel to the extending direction of the bit line 52 and located on the bit line 52. The cross section at BB is parallel to the extending direction of the bit line 52 and located between adjacent bit lines 52. The cross section at CC is parallel to the extending direction of the word line 83 and located on the word line 83. The cross section at DD is parallel to the extending direction of the word line 83 and located between adjacent word lines 83.

[0050] refer to Figures 3 to 6The substrate 10 may be a semiconductor substrate containing silicon. For example, the substrate may be a silicon substrate, a silicon-germanium substrate, or a silicon-on-insulator (SOI) substrate. For ease of description, the present embodiment and the following embodiments are described in detail using a silicon substrate as an example.

[0051] refer to Figures 7 to 10 A plurality of first trenches 11 are formed in the substrate 10. The plurality of first trenches 11 extend along a first direction and are spaced apart from each other. Exemplarily, the substrate 10 is etched to form the plurality of first trenches 11 in the substrate 10. Specifically, the plurality of first trenches 11 are formed by a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process to increase the density of the first trenches 11.

[0052] Step S102: forming a sacrificial layer and a first protective layer on the sacrificial layer in each first trench, wherein the sacrificial layer and the first protective layer fill the first trench, and an etching hole penetrating the first protective layer is provided in the first protective layer in each first trench.

[0053] refer to Figures 7 to 14 The bottom of each first trench 11 is filled with a sacrificial layer 20, and the remaining portion of each first trench 11 is filled with a first protective layer 30. The material of the sacrificial layer 20 is different from that of the first protective layer 30. For example, the sacrificial layer 20 has a large selectivity with the first protective layer 30, which reduces etching of the first protective layer 30 when the sacrificial layer 20 is subsequently removed. Exemplarily, the material of the first protective layer 30 can be silicon oxide, and the material of the sacrificial layer 20 can be silicon nitride.

[0054] refer to Figures 15 to 19 Each first protective layer 30 separated by the first trench 11 is provided with an etching hole 31, which penetrates the first protective layer 30 and exposes the sacrificial layer 20. The cross-sectional shape of the etching hole 31 can be circular, elliptical, square, rectangular or other polygonal, as shown in FIG. Figure 19 As shown, part of the hole wall of the etched hole 31 may also serve as the sidewall of the first trench 11. The etched hole 31 may be provided at the edge of the first trench 11, away from the region for forming the word line 83. The number of etched holes 31 in each first trench 11 may be single or multiple. For example, one etched hole 31 may be formed at each end of the first trench 11.

[0055] In order to increase the surface area of ​​the sacrificial layer 20 exposed in the etched hole 31, so as to facilitate the subsequent removal of the etched layer, as shown in FIG. Figure 16 As shown, the etched hole 31 may extend into the sacrificial layer 20 . For example, the bottom of the etched hole 31 is located in the sacrificial layer 20 , or the etched hole 31 penetrates the sacrificial layer 20 .

[0056] In one possible example, refer to Figures 7 to 18 , forming a sacrificial layer 20 in each first trench 11 and a first protective layer 30 on the sacrificial layer 20 , wherein the sacrificial layer 20 and the first protective layer 30 completely fill the first trench 11 , and the first protective layer 30 in each first trench 11 is provided with an etched hole 31 penetrating the first protective layer 30 , may include:

[0057] Step S1021 : depositing a sacrificial layer in each first trench, wherein the sacrificial layer fills the bottom of the first trench.

[0058] refer to Figures 7 to 14 A sacrificial layer 20 is formed in the first trench 11 by a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The thickness direction of the sacrificial layer 20 is the same as the depth direction of the first trench 11, both of which are perpendicular to the substrate 10 ( Figure 12 Z direction as shown).

[0059] Step S1022 : depositing a first protective layer on the sacrificial layer, wherein the first protective layer fills the first trench.

[0060] refer to Figures 11 to 14 , a first protective layer 30 is deposited on the sacrificial layer 20 and the substrate 10 , and the first protective layer 30 fills the first trench 11 and covers the top surface of the substrate 10 , as shown in FIG. Figures 11 to 14 As shown, the top surface of the substrate 10 refers to the upper surface of the substrate 10. The first protective layer 30 located on the top surface of the substrate 10 is then removed to expose the substrate 10. Exemplarily, the first protective layer 30 located on the top surface of the substrate 10 is removed by chemical mechanical polishing (CMP). After the first protective layer 30 is removed, the top surface of the substrate 10 is exposed.

[0061] Step S1023 , etching the first protection layer at the edge of each first trench to form an etching hole.

[0062] like Figures 15 to 18As shown, in some possible examples, a mask plate is deposited on the substrate 10 and the first protective layer 30; the first protective layer 30 is dry-etched or wet-etched using the mask plate as a mask to form Figure 16 The etching hole 31 is shown; and then the mask is removed.

[0063] Step S103: removing the sacrificial layer by etching holes to form air gaps.

[0064] refer to Figures 20 to 23 , the sacrificial layer 20 is removed by etching gas or etching liquid in the etching hole 31. After the sacrificial layer 20 in each first trench is removed, an air gap 21 is formed in each first trench. Figure 21 As shown, the air gap 21 is located below the etched hole 31 and communicates with the etched hole 31 .

[0065] Step S104 , performing a silicidation reaction on the substrate located between adjacent first trenches and close to the bottom of the first trenches to form a bit line extending along the first direction in the substrate, with a side surface portion of the bit line exposed in the air gap.

[0066] refer to Figures 24 to 43 , a bit line 52 is formed in the substrate 10, and the bit line 52 extends along the first direction. The bit line 52 is located between adjacent first trenches, and the bit line 52 is close to the bottom of the first trench. The width of the bit line 52 is equal to the width of the substrate 10 located between adjacent first trenches, so that the side surface of the bit line 52 is partially exposed in the air gap 21. Figures 40 to 43 As shown, a lower portion of the side surface of the bit line 52 is exposed in the air gap 21 , and an upper portion of the side surface of the bit line 52 is in contact with the first protection layer 30 .

[0067] The bit line 52 can be formed by a silicidation reaction, and the material of the bit line 52 includes a metal silicide, such as cobalt silicide, tungsten silicide, titanium silicide, platinum silicide or nickel silicide, so as to reduce the resistance of the bit line 52. For example, Figures 24 to 43 As shown, the step of performing a silicidation reaction on the substrate 10 located between adjacent first trenches 11 and near the bottom of the first trench 11 to form a bit line 52 extending along a first direction in the substrate 10, with the side surface of the bit line 52 partially exposed in the air gap 21, includes:

[0068] Step S1041 , etching the substrate and the first protective layer to form a plurality of second trenches spaced apart from each other, wherein the second trenches extend along a second direction and are not connected to the air gap.

[0069] refer to Figures 24 to 27The substrate 10 and the first protective layer 30 are etched to form a plurality of second trenches 12. The second trenches 12 are spaced apart and extend along the second direction. The second trenches 12 are not connected to the air gap 21. That is, the bottoms of the second trenches 12 are located within the substrate 10 and the first protective layer 30 and do not penetrate the first protective layer 30. In this configuration, the remaining first protective layer 30 seals the top of the air gap 21, preventing other materials from falling into the air gap 21 during subsequent processing, thereby ensuring that the air gap 21 effectively reduces parasitic capacitance.

[0070] Step S1042: forming a second protection layer on the sidewall of the second trench, and the second protection layer in the second trench encloses a third trench.

[0071] refer to Figures 24 to 31 A second protective layer 50 is formed on the sidewalls of the second trench 12, covering the sidewalls of the second trench 12. The second protective layer 50 within the second trench 12 encloses a third trench 51, which partially exposes the bottom of the second trench 12. The material of the first protective layer 30 can be the same as that of the second protective layer 50, so that the first protective layer 30 and the second protective layer 50 form a single unit.

[0072] In a possible embodiment, a second initial protective layer is deposited on the sidewalls and bottom of the second trench 12, the substrate 10, and the first protective layer 30, and the second initial protective layer located in the second trench 12 encloses a third trench 51; then, the second initial protective layer is etched along the third trench 51 to remove part of the second initial protective layer at the bottom of the second trench 12, and the remaining second initial protective layer forms a second protective layer 50.

[0073] In another possible embodiment, reference Figures 32 to 35 A third protective layer 40 is further deposited on the substrate 10 and the first protective layer 30, that is, the top surface of the substrate 10 is covered with the third protective layer 40. The material of the third protective layer 40, the material of the second protective layer 50, and the material of the first protective layer 30 can be the same, so that the three can form a whole.

[0074] refer to Figures 32 to 39 , a second initial protective layer is deposited on the sidewalls and bottom of the second trench 12, and on the third protective layer 40; then the second initial protective layer located on the third protective layer 40 and a portion of the second initial protective layer located at the bottom of the second trench 12 are removed by etching to expose the bottom of the second trench 12, and the retained second initial protective layer forms a second protective layer 50.

[0075] It is understandable that when the second initial protective layer is etched along the third trench 51 using anisotropic etching to remove a portion of the second initial protective layer at the bottom of the second trench 12, the second initial protective layer on the third protective layer 40 will inevitably be etched. By providing the third protective layer 40, the top surface of the substrate 10 can be prevented from being exposed, so that only the substrate 10 located in the second trench 12 is exposed, thereby ensuring the formation position of the bit line 52.

[0076] like Figures 36 to 37 As shown, a plurality of pillars are formed on the upper portion of the substrate 10. The outer circumference of the pillars is covered with a second protective layer 50, and the top surface of the pillars is covered with a third protective layer 40. The substrate 10 located at the bottom of the third trench 51 is exposed. For ease of description, the present embodiment and the following embodiments are described in detail using the example of the substrate 10 having the third protective layer 40 formed thereon.

[0077] It should be noted that the step of depositing the third protective layer 40 on the substrate 10 and the first protective layer 30 can be placed before the step (step S1041) of etching the substrate 10 and the first protective layer 30 to form a plurality of spaced second trenches 12, wherein the second trenches 12 extend along the second direction and are not connected to the air gap 21. That is, this step is placed before step S104. Specifically, this step can be placed after step S1022, after step S1023, or after step S103.

[0078] Preferably, after depositing the first protective layer 30 on the sacrificial layer 20 and filling the first trench 11 (step S1023), a third protective layer 40 is deposited on the substrate 10 and the first protective layer 30. This arrangement, on the one hand, facilitates fabrication and reduces the difficulty of fabricating the third protective layer 40; on the other hand, it prevents the third protective layer 40 from falling into the etched holes 31 or air gaps 21, thereby improving the performance of the semiconductor structure.

[0079] Correspondingly, etching the substrate 10 and the first protective layer 30 to form a plurality of spaced second grooves 12, wherein the second grooves 12 extend along the second direction and are not connected to the air gap 21 (step S1041) includes: etching the substrate 10, the first protective layer 30 and the third protective layer 40 to form a plurality of spaced second grooves 12, and retaining the third protective layer 40 located between adjacent second grooves 12.

[0080] Step S1043 : depositing metal at the bottom of the third trench and performing annealing to perform a silicidation reaction to form a bit line.

[0081] refer to Figures 40 to 43The metal can be cobalt, titanium, tantalum, nickel, or tungsten, or a refractory metal. The metal reacts with substrate 10 to form a metal silicide, completely silicideing the portion of substrate 10 located between adjacent first trenches. The metal silicide is connected along a first direction to form bit lines 52. The top surface of bit lines 52 is partially exposed within third trenches 51, and the side surfaces of bit lines 52 are partially exposed within air gaps 21.

[0082] The annealing process includes rapid thermal annealing (RTA), and the annealing temperature matches the material of the metal and the material of the substrate 10. For example, when the material of the substrate 10 is silicon and the metal is cobalt, the annealing temperature can be 400°C-800°C.

[0083] In summary, in the method for fabricating a semiconductor structure provided in the embodiments of the present application, the sacrificial layer 20 is removed to form an air gap 21 between the bit lines 52 extending along the first direction, with portions of the side surfaces of the bit lines 52 exposed within the air gap 21. By utilizing the dielectric constant of air being approximately 1, the dielectric constant of the structure between the bit lines 52 is reduced, thereby reducing the parasitic capacitance of the semiconductor structure and improving the operating efficiency of the semiconductor structure.

[0084] It should be noted that, before the step of forming a second protective layer 50 on the sidewall of the second trench 12 and enclosing the third trench 51 with the second protective layer 50 located in the second trench 12, the method for manufacturing the semiconductor structure also includes: forming an active area 13 in the substrate 10 away from the bottom of the first trench 11, the active area 13 including a source area, a drain area and a channel area, and the source area, the channel area and the drain area are arranged in sequence along a direction perpendicular to the bottom of the first trench 11.

[0085] Before forming the bit line 52, a plurality of spaced active regions are formed in the substrate 10, each active region including a source region, a drain region and a channel region, and the channel region is located between the source region and the drain region. In an embodiment of the present application, the source region, the channel region and the drain region are arranged vertically, that is, they are arranged in sequence in a direction perpendicular to the bottom of the first trench 11 to form a vertical transistor. The source region or the drain region is close to the bottom of the first trench 11, and the source region or the drain region close to the bottom of the first trench 11 is electrically connected to the subsequently formed bit line 52, that is, the source region or the drain region is electrically connected to the bit line 52. In this way, under the premise of occupying the same area of ​​the substrate 10, the effective length of the channel region can be increased by increasing the height of the active region, thereby reducing or avoiding the short channel effect and improving the performance of the semiconductor structure.

[0086] In some possible embodiments of the present application, the substrate 10 and the first protective layer 30 are etched to form a plurality of spaced second trenches 12, which extend along the second direction and are not connected to the air gap 21 (step S1041). Then, the first trench 11 and the second trench 12 separate the substrate 10 into a plurality of spaced columnar structures; each columnar structure is then doped to form a source region and a drain region in the columnar structure, thereby forming an active region in the substrate 10 away from the bottom of the first trench 11.

[0087] In some other possible embodiments of the present application, a substrate 10 is provided, and a plurality of first trenches 11 are formed in the substrate 10 at intervals. After the first trenches 11 extend along a first direction (step S101), the substrate 10 is doped between adjacent first trenches 11 to form active regions. That is, the active regions are strip-shaped and extend along the first direction. Second trenches 12 are then formed, and the second trenches 12 cut through the active regions, forming a plurality of spaced-apart columnar active regions.

[0088] It should be noted that the reference Figures 44 to 67 After depositing metal at the bottom of the third trench 51 and performing annealing to perform a silicidation reaction to form the bit line 52, the method for manufacturing the semiconductor structure further includes:

[0089] Step a: forming a first insulating layer in the third trench, wherein the first insulating layer fills the third trench.

[0090] refer to Figures 40 to 47 , a first insulating layer 61 is formed in the third trench 51 by a deposition process, the first insulating layer 61 extends along the second direction, and the first insulating layer 61 fills the third trench 51. For example, the first insulating layer 61 fills the third trench 51. Figures 40 to 47 As shown, the third protective layer 40 on the substrate 10 is removed, the substrate 10 is exposed, and the surface of the first insulating layer 61 away from the air gap 21 is flush with the substrate 10, or in other words, the top surface of the first insulating layer 61 is flush with the top surface of the substrate 10, so that the first insulating layer 61 and the substrate 10 form a relatively flat surface, which is convenient for the production of other structures.

[0091] The material of the first insulating layer 61 is different from that of the second protective layer 50, and the material of the first insulating layer 61 is also different from that of the first protective layer 30, so that the second protective layer 50 or the first protective layer 30 can be removed separately later. For example, the material of the first insulating layer 61 can be silicon nitride, and the material of the first protective layer 30 and / or the second protective layer 50 can be silicon oxide.

[0092] Step b: removing the first protection layer and the second protection layer to a preset depth along a direction perpendicular to the substrate to form a filling space, wherein the filling space exposes the side surface of the active area.

[0093] refer to Figures 48 to 59 The first protective layer 30 and the second protective layer 50 are partially removed by an etching process in a direction perpendicular to the substrate 10, thereby forming a recess having a predetermined depth in the substrate 10. The recess includes a filling space 72, and the side surface of the active area is exposed in the filling space 72. Specifically, at least a portion of the channel region is exposed in the filling space 72.

[0094] In some possible embodiments, such as Figures 48 to 59 As shown, the first protection layer 30 and the second protection layer 50 are removed to a predetermined depth along a direction perpendicular to the substrate 10 to form a filling space 72. The filling space 72 exposes the side surface of the active area 13, including the following processes:

[0095] The second protection layer 50 and the first protection layer 30 are etched to the initial depth to form a filled trench 71. Figures 48 to 51 The first protective layer 30 and the second protective layer 50 are etched in a direction perpendicular to the substrate 10 to form a filled trench 71 having an initial depth. The upper one of the source region and the drain region faces the filled trench 71. There are multiple filled trenches 71, and the multiple filled trenches 71 are separated by the first insulating layer 61.

[0096] After forming the filling trench 71, a second insulating layer 62 is deposited in the filling trench 71. The second insulating layer 62 fills the filling trench 71 between the substrate 10 and the first insulating layer 61. Figures 52 to 55 A second insulating layer 62 is deposited in the filled trench 71. The second insulating layer 62 completely fills the filled trench 71 between the substrate 10 and the first insulating layer 61. Specifically, the second insulating layer 62 is formed on the sidewalls of the filled trench 71. The second insulating layer 62 blocks the filled trench 71 between the active area and the first insulating layer 61. After the second insulating layer 62 is formed, the filled trench 71 is isolated into a plurality of openings spaced apart from each other.

[0097] After depositing the second insulating layer 62, the remaining first protection layer 30 and the second protection layer 50 are etched to a predetermined depth to form a filling space 72. Figures 56 to 59 , continue to etch the first protective layer 30 and the second protective layer 50 to a preset depth through the remaining filling trench 71, and form a filling space 72 after removing the remaining portion of the first protective layer 30 and the second protective layer 50. The filling space 72 is located below the filling trench 71 and is connected to the filling trench 71.

[0098] Step c: forming a gate structure in the filling space, wherein the gate structure extends along the second direction and surrounds the active area.

[0099] Exemplary, reference Figures 60 to 67, forming a gate structure 80 in the filling space 72 , wherein the gate structure 80 extends along the second direction and surrounds the active area and includes:

[0100] An oxide layer 81 is formed on the inner surface of the filling space 72. Figures 56 to 63 An oxide layer 81 is deposited on the inner surface of the fill space 72. Oxide layer 81 covers the exposed outer periphery of the active area, part of the side surface of the first insulating layer 61, and the bottom surface of the second insulating layer 62. Oxide layer 81, which surrounds the outer periphery of the active area, forms the gate oxide layer of the vertical transistor. Oxide layer 81 can be a silicon oxide layer.

[0101] Then, a conductive layer 82 is formed in the filling space 72 after the oxide layer 81 is formed, and the conductive layer 82 is opposite to at least a portion of the channel region. Figures 60 to 63 A conductive layer 82 is deposited in the fill space 72 and etched back. The conductive layer 82 fills at least a portion of the fill space 72. The oxide layer 81 and the conductive layer 82 form a gate structure 80. The gate structure 80 extends along the second direction and surrounds the active area. The gate structure 80 is formed in the word line 83, that is, the gate structure 80 is part of the word line 83.

[0102] It should be noted that after the step of forming a gate structure 80 in the filling space 72, the gate structure 80 extends along the second direction and surrounds the active area, it also includes: depositing a third insulating layer 63 on the gate structure 80, the third insulating layer 63 covers the gate structure 80, and fills the remaining filling channel 71.

[0103] refer to Figures 64 to 67 , a third insulating layer 63 is deposited in the remaining filled trench 71, and the third insulating layer 63 completely fills the filled trench 71. The gate structure 80 is covered by the third insulating layer 63 to insulate the gate structure 80. The third insulating layer 63, the second insulating layer 62, and the first insulating layer 61 can be made of the same material so that the three form a whole, thereby electrically isolating the gate structure 80. Figure 68 and Figure 69 After forming the third insulating layer 63 , a contact node 91 and a capacitor 92 are formed on the substrate 10 , and the vertical transistor is electrically connected to the capacitor 92 through the contact node 91 .

[0104] refer to Figure 2 ,as well as Figures 64 to 67 The present invention also provides a semiconductor structure including a substrate 10. The substrate 10 may be a silicon-containing substrate, such as a silicon substrate, a silicon germanium substrate, or a silicon-on-insulator substrate. A plurality of spaced-apart bit lines 52 are formed in the substrate 10. The bit lines 52 extend along a first direction, and a first trench is formed between two adjacent bit lines 52. That is, the first trench also extends along the first direction. Figure 2As shown, the first direction is the Y direction, and the material of the bit line 52 includes metal silicide, such as cobalt silicide, tungsten silicide, titanium silicide, platinum silicide, or nickel silicide, so as to reduce the resistance of the bit line 52 .

[0105] Each bit line 52 has at least one active region 13 disposed on it. The active region 13 includes a source region, a channel region, and a drain region stacked in sequence. That is, the source region, the channel region, and the drain region are arranged vertically. One of the source region and the drain region is electrically connected to the bit line 52. For example, the source region is located above the channel region, while the drain region is located below the channel region. The drain region is electrically connected to the bit line 52.

[0106] A protective layer (including a first protective layer 30 and a second protective layer 50) is provided in the first trench, and an air gap 21 is formed between the protective layer and the bottom of the first trench. The side surface of the bit line 52 is partially exposed in the air gap 21. Figure 66 As shown, a lower portion of the side surface of the bit line 52 is exposed in the air gap 21 , and an upper portion of the side surface of the bit line 52 is in contact with the protection layer.

[0107] The protection layer is also filled between adjacent active areas, such as Figure 66 As shown, the top surface of the protection layer is higher than the top surface of the bit line 52, wherein the top surface refers to the surface away from the bottom of the first trench. A plurality of first insulating layers 61 are provided on the protection layer. The first insulating layers 61 are provided along the second direction ( Figure 2 The active areas 13 located in the second direction form a row. A first insulating layer 61 is disposed between two adjacent rows of active areas 13, with a gap between the first insulating layer 61 and the active areas 13. The first insulating layer 61 separates the two adjacent rows of active areas 13, so that a row of active areas 13 along the second direction is connected to a gate structure 80.

[0108] The gate structure 80 is disposed between the first insulating layer 61 and the active region 13. The gate structure 80 extends along the second direction and surrounds the active region 13. The gate structure 80 corresponds to at least a portion of the channel region. The gate structure 80 includes an oxide layer and a conductive layer 82. The oxide layer covers the outer surface of the conductive layer 82. Figure 66 As shown, the side surface, bottom surface and part of the top surface of the conductive layer 82 are covered with an oxide layer 81 .

[0109] The gate structure 80 is further covered with a second insulating layer 62 and a third insulating layer 63. Figure 66As shown, the second insulating layer 62 is opposite to the edge region of the gate structure 80, and the third insulating layer 63 is opposite to the middle region of the gate structure 80. The second insulating layer 62 and the third insulating layer 63 form a whole layer, thereby covering the gate structure 80. The first insulating layer 61, the second insulating layer 62, and the third insulating layer 63 can be made of the same material, such as silicon nitride, so that the three form a whole to electrically insulate the gate structure 80.

[0110] refer to Figure 68 and Figure 69 Active region 13 is also provided with a contact node 91, and contact node 91 is provided with a capacitor 92. Capacitor 92 is electrically connected to active region 13 via contact node 91. One of the source region and the drain region is in contact with contact node 91, for example, the source region is in contact with the contact structure. Contact node 91 may be polysilicon, and capacitor 92 is used to store data information.

[0111] In the semiconductor structure in the embodiment of the present application, the bit line 52 extends along a first direction, and a first trench 11 is formed between two adjacent bit lines 52. A protective layer is provided in the first trench 11, and an air gap 21 is formed between the protective layer and the bottom of the first trench 11. The side surface portion of the bit line 52 remains in the air gap 21. By utilizing the characteristic that the dielectric constant of air is approximately 1, the dielectric constant of the structure located between the bit lines 52 is reduced, thereby reducing the parasitic capacitance 92 of the semiconductor structure and improving the working efficiency of the semiconductor structure.

[0112] In this specification, each embodiment or implementation method is described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between the embodiments can be referred to in conjunction with each other. In the description of this specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "example," "specific example," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. Finally, it should be noted that the above embodiments are intended only to illustrate the technical solutions of the present application and are not intended to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may be modified or some or all of the technical features therein may be replaced with equivalents. However, such modifications or replacements do not deviate from the essence of the corresponding technical solutions within the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, wherein a plurality of first trenches are formed in the substrate and are spaced apart from each other, and the first trenches extend along a first direction; forming a sacrificial layer in each of the first trenches and a first protective layer on the sacrificial layer, wherein the sacrificial layer and the first protective layer completely fill the first trenches, and an etching hole penetrating through the first protective layer is provided in the first protective layer in each of the first trenches; removing the sacrificial layer by using the etched hole to form an air gap; Etching the substrate and the first protective layer to form a plurality of second trenches spaced apart from each other, wherein the second trenches extend along a second direction and are not connected to the air gap; forming a second protection layer on the sidewalls of the second trench, wherein the second protection layer in the second trench encloses a third trench; A metal is deposited at the bottom of the third trench and annealed to perform a silicidation reaction to form a bit line, wherein a side surface of the bit line is partially exposed in the air gap.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The step of forming a sacrificial layer in each of the first trenches and a first protective layer on the sacrificial layer, wherein the sacrificial layer and the first protective layer completely fill the first trench, and providing the first protective layer in each of the first trenches with an etched hole penetrating the first protective layer comprises: Depositing the sacrificial layer in each of the first trenches, wherein the sacrificial layer fills the bottom of the first trench; Depositing the first protective layer on the sacrificial layer, wherein the first protective layer fills the first trench; The first protection layer at the edge of each first trench is etched to form the etched hole.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: The step of depositing the first protective layer on the sacrificial layer and the substrate, wherein the first protective layer fills the first trench comprises: Depositing the first protection layer on the sacrificial layer and the substrate, wherein the first protection layer fills the first trench and covers the top surface of the substrate; The first protection layer on the top surface of the substrate is removed to expose the substrate.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: The etched hole extends into the sacrificial layer.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The material of the bit line includes metal silicide.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: Before the step of etching the substrate and the first protective layer to form a plurality of second trenches spaced apart from each other, wherein the second trenches extend along the second direction and are not connected to the air gap, the method further includes: Depositing a third protective layer on the substrate and the first protective layer; The step of etching the substrate and the first protective layer to form a plurality of second trenches spaced apart includes: etching the substrate, the first protective layer and the third protective layer to form a plurality of second trenches spaced apart, and retaining the third protective layer between adjacent second trenches.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: The step of forming a second protective layer on the sidewall of the second trench, wherein the second protective layer in the second trench encloses a third trench comprises: Depositing a second initial protection layer on the sidewalls and bottom of the second trench and on the third protection layer; The second initial protection layer located on the third protection layer and at the bottom of the second trench is removed by etching to expose the bottom of the second trench, and the remaining second initial protection layer forms the second protection layer.

8. The method for manufacturing a semiconductor structure according to claim 6 or 7, wherein: The first protective layer, the second protective layer and the third protective layer are made of the same material.

9. The method for manufacturing a semiconductor structure according to claim 1, wherein: Before forming a second protection layer on the sidewall of the second trench and enclosing the third trench with the second protection layer in the second trench, the method further includes: An active region is formed in the substrate away from the bottom of the first trench. The active region includes a source region, a drain region and a channel region. The source region, the channel region and the drain region are arranged in sequence along a direction perpendicular to the bottom of the first trench.

10. The method for manufacturing a semiconductor structure according to claim 9, wherein: After depositing metal at the bottom of the third trench and performing annealing to perform a silicidation reaction to form the bit line, the method further includes: forming a first insulating layer in the third trench, wherein the first insulating layer fills the third trench; removing the first protection layer and the second protection layer to a predetermined depth along a direction perpendicular to the substrate to form a filling space, wherein the filling space exposes a side surface of the active area; A gate structure is formed in the filling space, wherein the gate structure extends along the second direction and surrounds the active area.

11. The method for manufacturing a semiconductor structure according to claim 10, wherein: The first protection layer and the first insulating layer are made of different materials.

12. The method for manufacturing a semiconductor structure according to claim 10, wherein: The step of removing the first protection layer and the second protection layer to a predetermined depth in a direction perpendicular to the substrate to form a filling space, wherein the filling space exposes the side surface of the active area comprises: Etching the second protective layer and the first protective layer to an initial depth to form a filled trench; Depositing a second insulating layer in the filling trench, wherein the second insulating layer fills the filling trench between the substrate and the first insulating layer; The remaining first protection layer and the second protection layer are etched to a preset depth to form the filling space.

13. The method for manufacturing a semiconductor structure according to claim 10, wherein: The step of forming a gate structure in the filling space, wherein the gate structure extends along the second direction and surrounds the active area, comprises: forming an oxide layer on the inner surface of the filling space; A conductive layer is formed in the filling space after the oxide layer is formed, and the conductive layer is opposite to at least a portion of the channel region.

14. The method for manufacturing a semiconductor structure according to claim 12, wherein: After forming a gate structure in the filling space, wherein the gate structure extends along the second direction and surrounds the active area, the method further includes: A third insulating layer is deposited on the gate structure, where the third insulating layer covers the gate structure and fills the remaining filling trench.

15. The method for manufacturing a semiconductor structure according to claim 14, wherein: The first insulating layer, the second insulating layer and the third insulating layer are made of the same material.

16. A semiconductor structure, characterized in that The semiconductor structure is manufactured according to the manufacturing method according to any one of claims 1 to 15, and the semiconductor structure comprises: a substrate, wherein a plurality of spaced-apart bit lines are formed in the substrate, the bit lines extending along a first direction, a first trench being formed between two adjacent bit lines, at least one active region being provided on each bit line, the active region comprising a source region, a channel region, and a drain region stacked in sequence, one of the source region and the drain region being electrically connected to the bit line; a protective layer disposed in the first trench, an air gap being formed between the protective layer and a bottom of the first trench, and a side surface of the bit line being partially exposed in the air gap; a plurality of first insulating layers disposed on the protective layer at intervals, the first insulating layers extending along the second direction, being located between two adjacent rows of active regions in the second direction and spaced apart from the active regions; a gate structure disposed between the first insulating layer and the active region, the gate structure extending along the second direction and surrounding the active region, the gate structure being opposite to at least a portion of the channel region; A second insulating layer and a third insulating layer covering the gate structure.

17. The semiconductor structure according to claim 16, wherein: Also includes: A contact node is located on the other of the source region and the drain region, and a capacitor is located on the contact node.

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