Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

The application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a plurality of trenches are arranged in the substrate in a cross manner, so that the substrate forms a plurality of silicon columns, and an isolation layer is filled in the trenches; wherein a conductive layer is arranged at the top of the silicon column, the conductive layer covers the top surface of the silicon column and part of the side surface adjacent to the top surface, and the conductive layer is used to contact the capacitor. Through the above design, the semiconductor structure can increase the contact area of the indirect electrical contact between the silicon column and the capacitor by using the design that the conductive layer covers the top surface and part of the side surface of the silicon column, thereby reducing the contact resistance between the silicon column and the capacitor and improving the device performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, to a semiconductor structure and a manufacturing method of the semiconductor structure. BACKGROUND

[0002] In the existing VGAA (Vertical Gate All Around) technology, the mainstream design of the capacitor contact is: using an exposure alignment sequence, only the top surface of the transistor silicon column is in contact with the capacitor metal. However, due to the small area of the top surface of the silicon column, the contact resistance between the silicon column and the capacitor is large, which affects the performance of the device. SUMMARY

[0003] One of the main purposes of the present application is to overcome at least one of the defects of the prior art, and to provide a semiconductor structure with small contact resistance between the silicon column and the capacitor.

[0004] Another main purpose of the present application is to overcome at least one of the defects of the prior art, and to provide a manufacturing method of a semiconductor structure capable of reducing the contact resistance between the silicon column and the capacitor.

[0005] To achieve the above purpose, the present application adopts the following technical solutions:

[0006] According to one aspect of the present application, a semiconductor structure is provided, comprising a substrate, the substrate is cross-arranged with a plurality of grooves, so that the substrate forms a plurality of silicon columns, and the grooves are filled with an isolation layer; wherein, a conductive layer is arranged on the top of the silicon column, the conductive layer covers the top surface of the silicon column and part of the side surface adjacent to the top surface, and the conductive layer is used to contact with the capacitor.

[0007] According to one of the embodiments of the present application, the top surface of the isolation layer is flush with the top surface of the conductive layer.

[0008] According to one of the embodiments of the present application, the material of the isolation layer is silicon nitride.

[0009] According to one of the embodiments of the present application, the material of the conductive layer is titanium nitride or tungsten.

[0010] According to one of the embodiments of the present application, a ring gate structure is arranged around the silicon column, and a dielectric layer is arranged between the ring gate structure and the silicon column.

[0011] According to one of the embodiments of the present application, the dielectric layer covers the remaining side surface of the silicon column which is not covered by the conductive layer.

[0012] According to one of the embodiments of the present application, the thickness of the dielectric layer is equal to the thickness of the conductive layer.

[0013] According to one of the embodiments of the present application, the silicon pillar has an upper portion and a lower portion, the upper portion is connected to an upper end of the lower portion, and the upper portion has a smaller size than the lower portion, and the ring gate structure is disposed around the upper portion and is spaced below the conductive layer.

[0014] According to one of the embodiments of the present application, the ring gate structure is made of titanium nitride or tungsten.

[0015] According to one of the embodiments of the present application, the dielectric layer is made of silicon oxide.

[0016] According to another aspect of the present application, a method for manufacturing a semiconductor structure is provided, which includes: providing a substrate, the substrate is arranged with a plurality of trenches crossing each other, so that the substrate forms a plurality of silicon pillars; forming an isolation layer, the isolation layer is filled in the trenches, and a top surface of the isolation layer is exposed in the trenches; removing the isolation layer on the top surface of the silicon pillar and a portion of the side surface adjacent to the top surface, to form a recess around the top end of the silicon pillar; and forming a conductive layer on the surface of the substrate, the conductive layer covers the top surface of the silicon pillar and a portion of the side surface adjacent to the top surface.

[0017] According to one of the embodiments of the present application, the method for manufacturing a semiconductor structure further includes: forming a ring gate structure and a dielectric layer, the ring gate structure surrounds the silicon pillar, and a dielectric layer is arranged between the ring gate structure and the silicon pillar, the dielectric layer covers the side surface and the top surface of the silicon pillar and is located between the ring gate structure and the silicon pillar.

[0018] According to one of the embodiments of the present application, in the step of forming the ring gate structure, the dielectric layer and the isolation layer, the method includes: forming a first dielectric layer by covering the top surface and the side surface of the silicon pillar with a dielectric material; forming a first isolation layer by filling an isolation material in the trench; removing the first dielectric layer on the top surface of the silicon pillar and a portion of the side surface adjacent to the top surface; partially removing the side surface of the silicon pillar which is not covered by the first dielectric layer, and forming a second dielectric layer on the top surface and the partially removed side surface of the silicon pillar, the second dielectric layer has a gap with the first isolation layer, and the remaining first dielectric layer and the second dielectric layer together constitute the dielectric layer; forming a ring gate structure around the silicon pillar in the lower space of the gap; and forming a second isolation layer by filling an isolation material in the upper space of the gap, the first isolation layer and the second isolation layer together constitute the isolation layer.

[0019] According to one of the embodiments of the present application, before the step of forming the second dielectric layer, the method further includes cleaning the semiconductor structure.

[0020] According to one of the embodiments of the present application, the thickness of the second dielectric layer formed on the top surface of the silicon pillar is less than the thickness of the first dielectric layer formed on the top surface of the silicon pillar, so that the top of the first isolation layer is higher than the top surface of the second dielectric layer; wherein before the step of removing the dielectric layer on the top surface of the silicon pillar and the part of the side surface adjacent to the top surface, the method further comprises grinding the top of the first isolation layer to be flush with the top surface of the second dielectric layer.

[0021] From the above technical solutions, the semiconductor structure and the manufacturing method of the semiconductor structure provided by the present application have the following advantages and positive effects:

[0022] The semiconductor structure provided by the present application sets a conductive layer on the top of the silicon pillar, and the conductive layer covers the top surface of the silicon pillar and part of the side surface adjacent to the top surface, and the conductive layer is used to contact the capacitor. Through the above design, the present application can increase the contact area of the indirect electrical contact between the silicon pillar and the capacitor by using the design of the conductive layer covering the top surface and part of the side surface of the silicon pillar, thereby reducing the contact resistance between the silicon pillar and the capacitor and improving the device performance. BRIEF DESCRIPTION OF DRAWINGS

[0023] The various objects, features and advantages of the present application will become more apparent from the following detailed description of preferred embodiments of the present application, when taken in conjunction with the accompanying drawings. The drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale. Like reference numerals in the drawings denote like elements throughout the several views. Among other things:

[0024] Figure 1 is a plan view of a semiconductor structure according to an example embodiment;

[0025] Figure 2 is a cross-sectional view taken along the straight line A-A in Figure 1

[0026] Figure 3 is a cross-sectional view taken along the straight line B-B in Figure 1

[0027] Figure 4 is a flow chart of a manufacturing method of a semiconductor structure according to an example embodiment;

[0028] Figures 5 to 13 are cross-sectional views of the semiconductor structure under the structure step of the manufacturing method of the semiconductor structure, respectively. Figure 4

[0029] The reference signs are explained as follows:

[0030] 100. substrate;

[0031] 110. trench; ​​​

[0032] 111. first trench;

[0033] 112. second trench;

[0034] 120. silicon pillar;

[0035] 121. upper portion;

[0036] 122. lower portion;

[0037] 123. recessed region;

[0038] 200. isolation layer;

[0039] 210. first isolation layer;

[0040] 220. second isolation layer;

[0041] 300. conductive layer;

[0042] 301. conductive material;

[0043] 400. ring gate structure;

[0044] 401. conductive material;

[0045] 500. dielectric layer;

[0046] 510. first dielectric layer;

[0047] 520. second dielectric layer;

[0048] BL. bit line;

[0049] WL. word line;

[0050] G. gap;

[0051] P. pit;

[0052] S1-S4. steps. DETAILED DESCRIPTION

[0053] Embodiments in accordance with the present application will now be described in detail with reference to the drawings, of which:

[0054] In the following description of various example embodiments of the application, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration various example structures, systems, and steps in which aspects of the application can be practiced. It is understood that other specific arrangements of parts, structures, example devices, systems, and steps can be utilized and structural and functional modifications can be made without departing from the scope of the present application. Also, while the term "over," "between," "inside," and the like, can be used in the description, these terms are used in the specification for the convenience of the reader and are not intended to limit the scope of the application. Nothing in this specification should be construed as requiring a specific three dimensional orientation of structures as a prerequisite to falling within the scope of the application.

[0055] Referring to Figure 1 , a plan view of a semiconductor structure according to the present application is schematically shown. In this example embodiment, the semiconductor structure according to the present application is described in the context of a 4F2 VGAA DRAM device. It will be readily understood by those skilled in the art that various modifications, additions, substitutions, deletions, and other changes can be made to the specific embodiments described below without departing from the principles of the semiconductor structure according to the present application.

[0056] As shown in Figure 1 , in this embodiment, the present application is a 4F2 VGAA DRAM device with word lines WL and buried bit lines BL in a single device, for example. Referring to Figure 2 and Figure 3 , Figure 2 , cross-sectional views along the line A-A in Figure 1 are schematically shown; Figure 3 , cross-sectional views along the line B-B in Figure 1 are schematically shown. The structure, arrangement, and functional relationships of the various components of the semiconductor structure according to the present application will be described below in conjunction with the above-described figures.

[0057] As shown in Figures 1 to 3As shown in the figure, in the embodiment, the semiconductor structure provided by the present application comprises a substrate 100, a plurality of trenches 110 are arranged on the substrate 100 in a cross manner, so that the substrate 100 is formed with a plurality of silicon pillars 120, and the trenches 110 are filled with an isolation layer 200. Specifically, the plurality of trenches 110 can comprise a plurality of first trenches 111 extending along a first direction and a plurality of second trenches 112 extending along a second direction, the first trenches 111 correspond to word lines WL, and the second trenches 112 correspond to bit lines BL. The silicon pillars 120 are provided with a conductive layer 300 on the top thereof, the conductive layer 300 covers the top surface of the silicon pillars 120 and part of the side surface adjacent to the top surface, and the conductive layer 300 is used to contact the capacitor. Accordingly, the conductive layer 300 not only contacts the top surface of the silicon pillars 120, but also contacts part of the side surface adjacent to the top surface of the silicon pillars 120, and the silicon pillars 120 contact the capacitor through the conductive layer 300, which is equivalent to increasing the electrical contact area between the silicon pillars 120 and the capacitor, thereby reducing the contact resistance between the silicon pillars 120 and the capacitor, and effectively improving the device performance of the semiconductor structure.

[0058] As shown in the figure, Figure 2 and Figure 3 in the embodiment, the top surface of the isolation layer 200 can be flush with the top surface of the conductive layer 300.

[0059] In the embodiment, the material of the isolation layer 200 can be silicon nitride (SiN).

[0060] In the embodiment, the material of the conductive layer 300 can be titanium nitride (TiN). In some embodiments, the material of the conductive layer 300 can also be other metal materials, such as tungsten (W), without being limited thereto.

[0061] As shown in the figure, Figure 2 and Figure 3 in the embodiment, the silicon pillars 120 can be provided with a ring gate structure 400 therearound, and a dielectric layer 500 is arranged between the ring gate structure 400 and the silicon pillars 120.

[0062] As shown in the figure, Figure 2 and Figure 3 based on the design that the dielectric layer 500 is arranged between the ring gate structure 400 and the silicon pillars 120, in the embodiment, the dielectric layer 500 can cover the remaining side surface of the silicon pillars 120 which is not covered by the conductive layer 300.

[0063] In this embodiment, the dielectric layer 500 may have a thickness approximately equal to that of the conductive layer 300. In some embodiments, the thicknesses of the dielectric layer 500 and the conductive layer 300 may also be unequal; for example, the thickness of the dielectric layer 500 may be greater than the thickness of the conductive layer 300, or the thickness of the dielectric layer 500 may be less than the thickness of the conductive layer 300. Furthermore, in the above description, the thickness of the conductive layer 300 specifically refers to the thickness of the conductive layer 300 covering the side surface of the silicon pillar 120. The thickness of the conductive layer 300 covering the top surface of the silicon pillar 120 may be equal or unequal.

[0064] like Figure 2 and Figure 3 As shown, in this embodiment, the silicon pillar 120 may have an upper portion 121 and a lower portion 122. Specifically, the upper portion 121 is connected to the upper end of the lower portion 122, and the size of the upper portion 121 is smaller than the size of the lower portion 122. Based on this, the ring gate structure 400 may be disposed around the upper portion 121 and spaced apart below the conductive layer 300. The upper portion 121 can be understood as the outer wall of the portion including the top of the silicon pillar 120 being reduced inward, and the formed upper portion 121, compared to this portion of the original silicon pillar 120, is equivalent to forming a recessed region 123 surrounding the silicon pillar 120.

[0065] like Figure 2 and Figure 3 As shown, in this embodiment, the thickness of the dielectric layer 500 covering the upper part 121 is approximately equal to the thickness of the recessed region 123 of the silicon pillar 120. In some embodiments, the thickness of the dielectric layer 500 covering the upper part 121 may also be greater than or less than the thickness of the recessed region 123 of the silicon pillar 120, as long as a gap G is maintained between the dielectric layer 500 and the isolation layer 200 at this position to allow the ring gate structure 400 to be arranged.

[0066] In this embodiment, the ring gate structure 400 can be made of titanium nitride. In some embodiments, the ring gate structure 400 can also be made of other metallic materials, such as tungsten, but is not limited thereto.

[0067] In this embodiment, the dielectric layer 500 can be made of silicon oxide (SiO2). In some embodiments, the dielectric layer 500 can also be made of other materials, such as other oxides, and is not limited thereto.

[0068] It should be noted that the semiconductor structures shown in the accompanying drawings and described in this specification are merely a few examples among many semiconductor structures capable of employing the principles of this application. It should be clearly understood that the principles of this application are by no means limited to any detail or component of the semiconductor structures shown in the accompanying drawings or described in this specification.

[0069] Based on the above detailed description of the exemplary embodiment of the semiconductor structure proposed in the present application, the following will describe an exemplary embodiment of the method for manufacturing the semiconductor structure proposed in the present application.

[0070] Referring to Figure 4 , a flowchart schematically showing the method for manufacturing the semiconductor structure proposed in the present application is shown. In this exemplary embodiment, the method for manufacturing the semiconductor structure proposed in the present application is described by taking a 4F2 VGA AD RAM device as an example. It is easy for those skilled in the art to understand that various modifications, additions, substitutions, deletions or other changes can be made to the following specific embodiment in order to apply the relevant design of the present application to the manufacturing method of other types of semiconductor structures, and these changes are still within the scope of the principle of the method for manufacturing the semiconductor structure proposed in the present application.

[0071] As Figure 4 shown, in this embodiment, the method for manufacturing the semiconductor structure proposed in the present application comprises at least the following steps:

[0072] Step S1: providing a substrate 100, the substrate 100 is cross-arranged with a plurality of trenches 110, so that the substrate 100 forms a plurality of silicon pillars 120;

[0073] Step S2: forming an isolation layer 200, the isolation layer 200 is filled in the trenches 110, and the top surface of the isolation layer 200 is exposed in the trenches 110;

[0074] Step S3: removing the dielectric layer 500 on the top surface of the silicon pillars 120 and the part of the side surface adjacent to the top surface, forming a notch P around the top end of the silicon pillars 120;

[0075] Step S4: providing a conductive layer 300 on the surface of the substrate 100, the conductive layer 300 covers the top surface of the silicon pillars 120 and the part of the side surface adjacent to the top surface.

[0076] Referring to Figures 5 to 13 , Figures 5 to 13 respectively Figure 4 schematically show the cross-sectional view of the semiconductor structure under the structure step of the method for manufacturing the semiconductor structure. The following will describe the structure, manufacturing method and process relationship of the semiconductor structure under several main steps of the method for manufacturing the semiconductor structure proposed in the present application in combination with the above-described drawings.

[0077] As Figures 5 to 11 shown, in this embodiment, step S2 can further comprise: forming a ring gate structure 400 and a dielectric layer, the ring gate structure 400 surrounds the silicon pillars 120, and the dielectric layer 500 is provided between the ring gate structure 400 and the silicon pillars 120, the dielectric layer 500 covers the side surface and the top surface of the silicon pillars 120 and is located between the ring structure and the silicon pillars 120.

[0078] As Figures 5 to 11 shown, in the present embodiment, step S2 can specifically include the following steps:

[0079] Step S21: forming a first dielectric layer 510 by covering the top surface and the side surface of the silicon pillar 120 with a dielectric material;

[0080] Step S22: forming a first isolation layer 210 by filling the trench 110 with an isolation material;

[0081] Step S23: removing the first dielectric layer 510 located on the top surface and the part of the side surface adjacent to the top surface of the silicon pillar 120;

[0082] Step S24: partially removing the side surface of the silicon pillar 120 which is not covered by the first dielectric layer 510, and forming a second dielectric layer 520 on the top surface and the partially removed side surface of the silicon pillar 120, the second dielectric layer 520 having a gap G with the first isolation layer 210, the remaining first dielectric layer 510 and the second dielectric layer 520 together constituting a dielectric layer 500;

[0083] Step S25: forming a ring gate structure 400 surrounding the silicon pillar 120 in the lower space of the gap G;

[0084] Step S26: forming a second isolation layer 220 by filling the isolation material in the upper space of the gap G, the first isolation layer 210 and the second isolation layer 220 together constituting an isolation layer 200.

[0085] As Figure 5 shown, it specifically shows the cross-sectional schematic diagram of the semiconductor structure under step S21, the direction of cutting is referred to Figure 2 . Among them, the semiconductor structure under step S1 includes a substrate 100, a bit line BL, a silicon pillar 120 and a first dielectric layer 510. Specifically, the bit line BL is embedded in the substrate 100, a plurality of trenches 110 are etched on the substrate 100, so that the substrate 100 forms a plurality of silicon pillars 120, and the first dielectric layer 510 covers the top surface and the side surface of the silicon pillar 120.

[0086] In step S21, after depositing the first dielectric layer 510, the first dielectric layer 510 covers the bottom wall of the trench 110 in addition to the top surface and the side surface of the silicon pillar 120. The first dielectric layer 510 covering the bottom wall of the trench 110 can be etched and removed after depositing the first dielectric layer 510, so as to obtain the first dielectric layer 510 in step S21.

[0087] As Figure 6The diagram shows a cross-sectional view of the semiconductor structure in step S22. The semiconductor structure in step S22 includes a substrate 100, bit lines BL, silicon pillars 120, a first dielectric layer 510, and a first isolation layer 210. Specifically, the first isolation layer 210 fills the trench 110. It should be noted that since the first dielectric layer 510 is formed on the top surface of the silicon pillars 120, the trench 110 filled by the first isolation layer 210 includes the space defined by that portion of the first dielectric layer 510.

[0088] like Figure 7 The diagram shows a cross-sectional view of the semiconductor structure in step S23. The semiconductor structure in step S23 includes a substrate 100, bit lines BL, silicon pillars 120, a first dielectric layer 510 remaining after etching, and a first isolation layer 210. Specifically, dry etching or wet etching processes can be used to remove the first dielectric layer 510 from the top surface of the silicon pillar 120 and a portion of the side surfaces adjacent to the top surface. Furthermore, after the partial removal of the first dielectric layer 510, a gap exists between the side surface of the silicon pillar 120 not covered by the first dielectric layer 510 and the first isolation layer 210.

[0089] like Figure 8 The diagram shows a cross-sectional view of the semiconductor structure in step S24. The semiconductor structure in step S24 includes a substrate 100, bit lines BL, a silicon pillar 120, a first dielectric layer 510 remaining after etching, a first isolation layer 210, and a second dielectric layer 520. Specifically, in step S24, the side of the silicon pillar 120 not covered by the first dielectric layer 510 is partially removed, making the size of the portion of the silicon pillar 120 not covered by the first dielectric layer 510 smaller than the size of the remaining portion. After step S24, the silicon pillar 120 includes an upper portion 121 and a lower portion 122. The upper portion 121 is connected to the upper end of the lower portion 122, and the size of the upper portion 121 is smaller than the size of the lower portion 122. The upper portion 121 can be understood as the outer wall of the portion of the silicon pillar 120 including the top end being reduced inwards. Compared to the original portion of the silicon pillar 120, the formed upper portion 121 is equivalent to forming a recessed region 123 surrounding the silicon pillar 120. Based on this, the second dielectric layer 520 covers the top surface of the silicon pillar 120 and the partially removed side surface (i.e., the top surface and side surface of the upper part 121). The second dielectric layer 520 and the first isolation layer 210 have a gap G, and the remaining first dielectric layer 510 and the second dielectric layer 520 together constitute the dielectric layer 500.

[0090] In this embodiment, the materials of the first dielectric layer 510 and the second dielectric layer 520 may be, but are not limited to, the same.

[0091] In this embodiment, prior to step S24, the application may also include a step of cleaning the semiconductor structure.

[0092] like Figure 10 The diagram shows a cross-sectional view of the semiconductor structure in step S25. The semiconductor structure in step S25 includes a substrate 100, bit lines BL, silicon pillars 120, a first isolation layer 210, a dielectric layer 500, and a gate ring structure 400. Specifically, the gate ring structure 400 is formed in the lower space of the gap G. A conductive material 401 can be first applied to the surface of the semiconductor structure, filling the aforementioned gap G (e.g., ...). Figure 9 (As shown), and then the conductive material 401 is etched back to remove part of the conductive material 401, leaving the conductive material 401 in the lower space of the gap G, thereby forming a ring gate structure 400 around the outer periphery of the silicon pillar 120.

[0093] like Figure 11 The diagram shows a cross-sectional view of the semiconductor structure in step S26. The semiconductor structure in step S26 includes a substrate 100, bit lines BL, silicon pillars 120, a first isolation layer 210, a dielectric layer 500, a gate ring structure 400, and a second isolation layer 220. Specifically, after the gate ring structure 400 is formed by etch-back, the upper space of the gap G is empty due to the removal of some conductive material 401. The second isolation layer 220 is formed by filling this upper space of the gap G with isolation material, and the first isolation layer 210 and the second isolation layer 220 together constitute the isolation layer 200.

[0094] like Figure 12 The diagram shows a cross-sectional view of the semiconductor structure in step S3. The semiconductor structure in step S3 includes a substrate 100, bit lines BL, silicon pillars 120, a dielectric layer 500, a gate ring structure 400, and an isolation layer 200. Specifically, in step S3, the dielectric layer 500 on the top surface and a portion of the side surface adjacent to the top surface of the silicon pillar 120 is etched away, forming a recess P around the top of the silicon pillar 120. The sidewalls of the recess P are defined by the isolation layer 200 (second isolation layer 220) and the side surface of the silicon pillar 120, and the bottom wall is defined by the top surface of the partially removed dielectric layer 500 (second dielectric layer 520) in step S3.

[0095] like Figure 5 , Figure 8 As shown, the thickness of the second dielectric layer 520 formed on the top surface of the silicon pillar 120 in step S21 can be less than the thickness of the first dielectric layer 510 formed on the top surface of the silicon pillar 120 in step S24, so that the top of the first insulating layer 210 is higher than the top surface of the second dielectric layer 520. Based on this, as... Figure 11As shown, after step S26 and before step S3, the top of the isolation layer 200 can be polished, for example, chemical mechanical polishing, so that the top surface of the polished isolation layer 200 is flush with the top surface of the second dielectric layer 520.

[0096] With reference to Figure 2 which specifically shows a cross-sectional schematic view of the semiconductor structure under step S4. In step S4, the semiconductor structure includes the substrate 100, the bit line BL, the silicon pillar 120, the dielectric layer 500, the ring gate structure 400, the isolation layer 200, and the conductive layer 300. Specifically, as shown, the conductive material 301 can be first coated on the surface of the semiconductor structure, which fills the recess P, and then a polishing process is performed to remove the conductive material 301 above the isolation layer 200, leaving only the conductive material 301 coated on the top surface of the silicon pillar 120 and filled in the recess P, thereby forming the conductive layer 300 covering the top surface of the silicon pillar 120 and the part of the side surface adjacent to the top surface, and the top surface of the remaining conductive layer 300 is flush with the top surface of the isolation layer 200. Figure 13

[0097] It should be noted that the method of manufacturing the semiconductor structure shown in the drawings and described in the specification is only a few examples of the many methods that can employ the principles of the present application. It should be clearly understood that the principles of the present application are by no means limited to any details or any steps of the manufacturing method shown in the drawings or described in the specification.

[0098] In summary, the semiconductor structure proposed in the present application sets the conductive layer 300 on the top of the silicon pillar 120, which covers the top surface of the silicon pillar 120 and the part of the side surface adjacent to the top surface, and the conductive layer 300 is used to contact the capacitor. Through the above design, the present application can increase the contact area of the indirect electrical contact between the silicon pillar 120 and the capacitor by using the design of the conductive layer 300 covering the top surface and part of the side surface of the silicon pillar 120, thereby reducing the contact resistance between the silicon pillar 120 and the capacitor and improving the device performance.

[0099] ​The exemplary embodiments of the semiconductor structure and the method of fabricating a semiconductor structure presented herein are described and / or illustrated in detail using a variety of components, devices, and methods. This should in no way be construed that a description of the semiconductor structure and the method of fabricating a semiconductor structure presented herein is limited to including these components, devices, and methods. The exemplary embodiments presented herein are susceptible to modifications in the components, devices, and methods. Similarly, other embodiments of the semiconductor structure and the method of fabricating a semiconductor structure presented herein can have fewer than or more than the number of components, devices, and methods shown herein. Each of the components, devices, and methods presented herein can also be used in combination with each other. Each of the components, devices, and methods presented herein can also be used with other components, devices, and methods that are not presented herein. The present disclosure is not an exhaustive list of all possible components, devices, and methods associated with the semiconductor structure and the method of fabricating a semiconductor structure presented herein. The present disclosure is intended to be a thorough and complete presentation of the semiconductor structure and the method of fabricating a semiconductor structure presented herein.

[0100] Although the semiconductor structure and the method of fabricating a semiconductor structure presented herein have been described in accordance with various embodiments, one of ordinary skill in the art will recognize that modifications can be made to the semiconductor structure and the method of fabricating a semiconductor structure without departing from the spirit and scope of the claims.

Claims

1. A semiconductor structure comprising a substrate, the substrate being cross-arranged with a plurality of trenches such that the substrate forms a plurality of silicon pillars, the trenches being filled with an isolation layer; characterized in that, The top of the silicon column is provided with a conductive layer, the conductive layer covers the top surface and part of the side surface adjacent to the top surface of the silicon column, and the conductive layer is used to contact the capacitor.

2. The semiconductor structure of claim 1, wherein, The top surface of the isolation layer is flush with the top surface of the conductive layer.

3. The semiconductor structure of claim 1, wherein, The material of the isolation layer is silicon nitride.

4. The semiconductor structure of claim 1, wherein, The material of the conductive layer is titanium nitride or tungsten.

5. The semiconductor structure of claim 1, wherein, The silicon column is provided with a ring gate structure around, and a dielectric layer is arranged between the ring gate structure and the silicon column.

6. The semiconductor structure of claim 5, wherein, The dielectric layer covers the remaining side surface of the silicon column which is not covered by the conductive layer.

7. The semiconductor structure of claim 6, wherein, The thickness of the dielectric layer is equal to the thickness of the conductive layer.

8. The semiconductor structure of claim 5, wherein, The silicon column has an upper part and a lower part, the upper part is connected to the upper end of the lower part, and the size of the upper part is smaller than the size of the lower part, the ring gate structure is arranged around the upper part and is spaced below the conductive layer.

9. The semiconductor structure of claim 5, wherein, The material of the ring gate structure is titanium nitride or tungsten.

10. The semiconductor structure of claim 5, wherein, The material of the dielectric layer is silicon oxide.

11. A method of fabricating a semiconductor structure, the method comprising: Comprising: A substrate is provided, the substrate is cross-arranged with a plurality of grooves, so that the substrate forms a plurality of silicon columns; An isolation layer is formed, the isolation layer is filled in the groove, and the top surface of the isolation layer is exposed in the groove; The isolation layer on the top surface and part of the side surface adjacent to the top surface of the silicon column is removed, and a notch is formed around the top end of the silicon column; A conductive layer is formed on the surface of the substrate, the conductive layer covers the top surface and part of the side surface adjacent to the top surface of the silicon column.

12. The method of fabricating a semiconductor structure of claim 11, wherein, Also comprising: A ring gate structure and a dielectric layer are formed, the ring gate structure surrounds the silicon column, and a dielectric layer is arranged between the ring gate structure and the silicon column, the dielectric layer covers the side surface and the top surface of the silicon column and is located between the ring gate structure and the silicon column.

13. The method of fabricating a semiconductor structure of claim 12, wherein, In the step of forming the ring gate structure, the dielectric layer and the isolation layer, comprising: A first dielectric layer is formed by covering the dielectric material on the top surface and the side surface of the silicon column; A first isolation layer is formed by filling the isolation material in the groove; The first dielectric layer located on the top surface and part of the side surface adjacent to the top surface of the silicon column is removed; Part of the side surface of the silicon column which is not covered by the first dielectric layer is partially removed, and a second dielectric layer is formed on the top surface and the partially removed side surface of the silicon column, the second dielectric layer has a gap with the first isolation layer, and the remaining first dielectric layer and the second dielectric layer together constitute the dielectric layer; A ring gate structure surrounding the silicon column is formed in the lower space of the gap; A second isolation layer is formed by filling the isolation material in the upper space of the gap, and the first isolation layer and the second isolation layer together constitute the isolation layer.

14. The method of fabricating a semiconductor structure of claim 13, wherein, Before the step of forming the second dielectric layer, the semiconductor structure is also cleaned.

15. The method of fabricating a semiconductor structure of claim 13, wherein, The thickness of the second dielectric layer formed on the top surface of the silicon column is less than the thickness of the first dielectric layer formed on the top surface of the silicon column, so that the top of the first isolation layer is higher than the top surface of the second dielectric layer; wherein, before the step of removing the dielectric layer on the top surface and part of the side surface adjacent to the top surface of the silicon column, the top of the first isolation layer is ground to be flush with the top surface of the second dielectric layer.

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