Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprising: a plurality of semiconductor pillars, the semiconductor pillars are arranged along a first direction and a second direction, and extend along a third direction, and along the third direction, the semiconductor pillars comprise a first region, a second region and a third region arranged in sequence; a plurality of word lines, the word lines extend along the first direction, and along the first direction, the word lines surround the second regions of the plurality of semiconductor pillars; a plurality of bit lines, the bit lines extend along the second direction, and along the second direction, the bit lines are in electrical contact with the third regions of the plurality of semiconductor pillars; along the first direction, the distance between the central axes of adjacent semiconductor pillars is a first pitch; along the second direction, the distance between the central axes of adjacent semiconductor pillars is a second pitch, and the ratio of the second pitch to the first pitch is provided by the embodiment of the present disclosure. The semiconductor structure and the manufacturing method thereof provided by the embodiment of the present disclosure are at least beneficial to improving the stability of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of semiconductor, and in particular, to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] Memory is a memory component used to store programs and various data information. The random access memory (RAM) used by a general computer system can be divided into dynamic random access memory (DRAM) and static random access memory (SRAM). Dynamic random access memory is a commonly used semiconductor memory device in computers, which is composed of many repeated memory cells.

[0003] A memory cell generally includes a capacitor and a transistor. The drain of the transistor is connected to a bit line structure, and the source is connected to the capacitor. The word line structure of the memory cell can control the opening or closing of the channel region of the transistor, thereby reading the data information stored in the capacitor through the bit line structure or writing the data information into the capacitor through the bit line structure for storage. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which at least facilitate to improve the reliability of the semiconductor structure.

[0005] According to some embodiments of the present disclosure, the embodiments of the present disclosure provide a semiconductor structure, comprising: a plurality of semiconductor pillars, the semiconductor pillars are arranged along a first direction and a second direction, and extend along a third direction, in the third direction, the semiconductor pillars comprise a first region, a second region and a third region arranged in sequence; a plurality of word lines, the word lines extend along the first direction, and in the first direction, the word lines surround the second regions of the plurality of semiconductor pillars; a plurality of bit lines, the bit lines extend along the second direction, and in the second direction, the bit lines are in electrical contact with the third regions of the plurality of semiconductor pillars; wherein the first direction is perpendicular to the second direction, in the first direction, the distance between the center axes of adjacent semiconductor pillars is a first pitch; in the second direction, the distance between the center axes of adjacent semiconductor pillars is a second pitch, and the ratio of the second pitch to the first pitch is √3-2.

[0006] In some embodiments, the size of the semiconductor pillar in the first direction is smaller than the size of the semiconductor pillar in the second direction.

[0007] In some embodiments, the size of the semiconductor pillar in the first direction ranges from 15 nm to 25 nm; and the size of the semiconductor pillar in the second direction ranges from 30 nm to 40 nm.

[0008] In some embodiments, the first distance is 30-40 nm; and the second distance is 52-80 nm.

[0009] In some embodiments, the semiconductor pillar further comprises: a trench structure extending along the first direction, and in the first direction, the trench structure passes through the first region and the second region of the plurality of semiconductor pillars, and the trench structure divides the semiconductor pillar into a first semiconductor sub-pillar and a second semiconductor sub-pillar.

[0010] In some embodiments, the memory device further comprises: a plurality of capacitor structures, each capacitor structure extending along a third direction, and each capacitor structure being in electrical contact with the first region of a first semiconductor sub-pillar or a second semiconductor sub-pillar.

[0011] In some embodiments, when the ratio of the second distance to the first distance is 2, the capacitor structures are arranged along the first direction and the second direction, and in the first direction, the distance between the center axes of adjacent capacitor structures is equal to the first distance; and in the second direction, the distance between the center axes of adjacent capacitor structures is equal to the first distance.

[0012] In some embodiments, when the ratio of the second distance to the first distance is , the capacitor structures are arranged along the first direction and a fourth direction, the fourth direction forms an angle of 60° with the first direction, and in the first direction, the distance between the center axes of adjacent capacitor structures is equal to the first distance; and in the fourth direction, the distance between the center axes of adjacent capacitor structures is equal to the first distance.

[0013] In some embodiments, in a plane perpendicular to the center axis of the capacitor structure, the normal projection of the capacitor structure is a circle, and the ratio of the diameter of the capacitor structure to the size of the semiconductor pillar in the first direction is

[0014] In some embodiments, in the second direction, the ratio of the size of the semiconductor pillar to the size of the trench structure is 1.4-2.

[0015] In some embodiments, the word line comprises: a first sub-word line and a second sub-word line, the first sub-word line surrounds the second region of the first semiconductor sub-pillar away from the trench structure, the second sub-word line surrounds the second region of the second semiconductor sub-pillar away from the trench structure, and the first sub-word line and the second sub-word line are spaced apart from each other.

[0016] In some embodiments, in the second direction, the ratio of the distance between adjacent word lines to the second distance is 0.07-0.13.

[0017] In some embodiments, the size of the bit line in the first direction is equal to the size of the semiconductor pillar in the first direction.

[0018] In some embodiments, the base is further included, the first direction and the second direction are parallel to a surface of the base, and the third direction is perpendicular to the surface of the base; the first region, the second region, and the third region of the semiconductor pillar are arranged in a direction away from the surface of the base, and the bit line is located at an end of the semiconductor pillar away from the surface of the base; or the first region, the second region, and the third region of the semiconductor pillar are arranged in a direction pointing to the surface of the base, and the bit line is located at an end of the semiconductor pillar close to the surface of the base.

[0019] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a manufacturing method of a semiconductor structure, comprising: providing a base; forming a plurality of semiconductor pillars on the base, the semiconductor pillars are arranged along a first direction and a second direction, and extend along a third direction, and in the third direction, the semiconductor pillars comprise a first region, a second region, and a third region arranged in sequence; forming a plurality of word lines, the word lines extend along the first direction, and in the first direction, the word lines surround the second regions of the plurality of semiconductor pillars; forming a plurality of bit lines, the bit lines extend along the second direction, and in the second direction, the bit lines are in electrical contact with the third regions of the plurality of semiconductor pillars; wherein the first direction is perpendicular to the second direction, in the first direction, the distance between the center axes of adjacent semiconductor pillars is a first pitch; in the second direction, the distance between the center axes of adjacent semiconductor pillars is a second pitch, and the ratio of the second pitch to the first pitch is

[0020] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages: by arranging a plurality of semiconductor pillars along the perpendicular first direction and the second direction, a 4F 2 The semiconductor pillars arranged in sequence, the word lines surround the second regions of the plurality of semiconductor pillars along the first direction, and the bit lines are in electrical contact with the third regions of the plurality of semiconductor pillars along the second direction, so that the semiconductor pillars can form transistors of a VGG A structure. Wherein, in the first direction, the distance between the center axes of adjacent semiconductor pillars is a first pitch, in the second direction, the distance between the center axes of adjacent semiconductor pillars is a second pitch, and when the ratio of the second pitch to the first pitch is less than 2, it will cause insufficient arrangement space for the corresponding capacitor structure; when the ratio of the second pitch to the first pitch is greater than 2, it is not conducive to increasing the size of the corresponding capacitor structure, and will cause waste of space of the semiconductor structure in the second direction. The ratio of the second pitch to the first pitch is set to be 2. ​The distance between the capacitors can be beneficial for arranging the capacitors and the first region of the semiconductor column to be electrically connected, improving the space utilization of the semiconductor structure; meanwhile, the capacitors can be set as a cylindrical structure when the capacitors have a large area, the capacitors in the cylindrical structure can avoid uneven electric field in the capacitor dielectric layer, thereby avoiding the formation of leakage in the local area of the capacitor structure, and the large distance between the capacitors can avoid the generation of parasitic capacitance between adjacent capacitors, improving the stability of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0021] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are illustrative, but not restrictive, of the present embodiments, unless otherwise specified; in order to clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the drawings needed to be used in the embodiments will be briefly introduced below, obviously, the drawings in the following description are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can be obtained from these drawings without creative labor.

[0022] Figure 1 A schematic diagram of a first semiconductor structure provided by an embodiment of the present disclosure is shown in the figure.

[0023] Figure 2 A schematic diagram of a second semiconductor structure provided by an embodiment of the present disclosure is shown in the figure. Figure 1 A schematic diagram of a cross-sectional structure along the AA1 direction is shown in the figure.

[0024] Figure 3 A schematic diagram of a third semiconductor structure provided by an embodiment of the present disclosure is shown in the figure.

[0025] Figure 4 A schematic diagram of a third semiconductor structure provided by an embodiment of the present disclosure is shown in the figure.

[0026] Figure 5 A schematic diagram of a fourth semiconductor structure provided by an embodiment of the present disclosure is shown in the figure. Figure 4 A schematic diagram of a cross-sectional structure along the BB1 direction is shown in the figure.

[0027] Figure 6 A schematic diagram of a fifth semiconductor structure provided by an embodiment of the present disclosure is shown in the figure.

[0028] Figure 7 A schematic diagram of a fifth semiconductor structure provided by an embodiment of the present disclosure is shown in the figure. DETAILED DESCRIPTION

[0029] It is found that, in order to better adapt to the requirement of scaling down the size of semiconductor devices, semiconductor processes gradually begin to transit from planar transistors to three-dimensional transistors with higher efficiency, such as Gate-all-around (GAA) transistors. In the GAA transistor, the gate surrounds the channel from all directions. Compared with the planar transistor, the GAA transistor has stronger control ability of the gate to the channel, and can better suppress the short channel effect. The GAA transistor includes a Lateral Gate-all-around (LGAA) transistor and a Vertical Gate-all-around (VGAA) transistor. Among them, the channel of the VGAA extends in the direction perpendicular to the surface of the substrate, which is beneficial to improve the area utilization efficiency of the semiconductor structure, and thus is beneficial to realize further scaling down of the feature size. However, in different 4F 2 The arrangement of the semiconductor pillars forming the vertical channel on the substrate in the array will affect the shape and arrangement of the capacitor. When the shape of the capacitor is not a cylinder, it will easily cause the electric field in the capacitor dielectric layer to be uneven, thereby forming a leakage in the local area. Therefore, the size of the semiconductor pillar in the VGAA structure is of great significance to the arrangement and shape of the capacitor.

[0030] According to some embodiments of the present disclosure, an embodiment of the present disclosure provides a semiconductor structure, which at least helps to improve the reliability of the semiconductor structure.

[0031] The embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present disclosure, many technical details are proposed in order to make the readers better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be realized even without these technical details and various changes and modifications based on the following embodiments.

[0032] Figure 1 A schematic diagram of a first semiconductor structure provided by an embodiment of the present disclosure is shown in FIG. 1, Figure 2 A schematic diagram of a second semiconductor structure provided by an embodiment of the present disclosure is shown in FIG. 2, Figure 1 A schematic diagram of a cross-sectional structure along the AA1 direction is shown in FIG. 3, Figure 3 A schematic diagram of a second semiconductor structure provided by an embodiment of the present disclosure is shown in FIG. 2, Figure 4 A schematic diagram of a third semiconductor structure provided by an embodiment of the present disclosure is shown in FIG. 3, Figure 5 A schematic diagram of a fourth semiconductor structure provided by an embodiment of the present disclosure is shown in FIG. 4, Figure 4 A schematic diagram of a cross-sectional structure along the BB1 direction is shown in FIG. 5, Figure 6 A schematic diagram of a fourth semiconductor structure provided by an embodiment of the present disclosure is shown in FIG. 4, Figure 7 A schematic diagram of a fifth semiconductor structure provided by an embodiment of the present disclosure is shown in FIG. 5, which will be described in detail below with reference to the drawings. Specifically, the semiconductor structure provided by the embodiment includes:

[0033] Reference Figure 1 and Figure 2 The semiconductor structure comprises: a plurality of semiconductor pillars 101 arranged along a first direction X and a second direction Y and extending along a third direction Z, wherein, along the third direction Z, the semiconductor pillars 101 comprise a first region I, a second region II and a third region III arranged in sequence; a plurality of word lines 102 extending along the first direction X, and, along the first direction X, the word lines 102 surround the second regions II of the plurality of semiconductor pillars 101; a plurality of bit lines 103 extending along the second direction Y, and, along the second direction Y, the bit lines 103 are in electrical contact with the third regions III of the plurality of semiconductor pillars 101; wherein the first direction X is perpendicular to the second direction Y, along the first direction X, the distance between the central axes of adjacent semiconductor pillars 101 is a first pitch L1; along the second direction Y, the distance between the central axes of adjacent semiconductor pillars 101 is a second pitch L2, and the ratio of the second pitch L2 to the first pitch L1 is For example, the ratio of the second pitch L2 to the first pitch L1 can be 1.75, 1.8, 1.85, 1.9, 1.99 or 2.

[0034] By arranging the plurality of semiconductor pillars 101 along the perpendicular first direction X and the second direction Y, a 4F 2 The semiconductor pillars 101 are arranged along the third direction Z, the semiconductor pillars 101 comprise a first region I, a second region II and a third region III arranged in sequence, the word lines surround the second regions II of the plurality of semiconductor pillars 101 along the first direction X, and the bit lines are in electrical contact with the third regions III of the plurality of semiconductor pillars 101 along the second direction Y, then the semiconductor pillars 101 can form a transistor of a VGG A structure. Wherein, along the first direction X, the distance between the central axes of adjacent semiconductor pillars 101 is a first pitch L1, along the second direction Y, the distance between the central axes of adjacent semiconductor pillars 101 is a second pitch L2, and the ratio of the second pitch L2 to the first pitch L1 is Figure 3 When the ratio of the second pitch L2 to the first pitch L1 is less than , it will cause insufficient space for the corresponding capacitor structure 104; when the ratio of the second pitch L2 to the first pitch L1 is greater than 2, it is not conducive to increasing the size of the corresponding capacitor structure 104, and it will cause waste of space of the semiconductor structure along the second direction Y. The ratio of the second pitch L2 to the first pitch L1 is set to The distance between the capacitors can be large enough to arrange the capacitors 104 and the first region I of the semiconductor column 101, improve the space utilization of the semiconductor structure, and satisfy the condition that the capacitors 104 have a large area and are in a cylindrical structure. The capacitors 104 in the cylindrical structure can avoid uneven electric field in the capacitor dielectric layer, thereby avoiding the formation of local leakage in the capacitors 104, and the large distance between the capacitors can avoid the formation of parasitic capacitance between adjacent capacitors, thereby improving the stability of the semiconductor structure.

[0035] In some embodiments, the material of the semiconductor column 101 includes at least one of IGZO (Indium Gallium Zinc Oxide), IWO (Indium Tungsten Oxide), or ITO (Indium Tin Oxide). When the semiconductor column 101 is composed of the above-mentioned materials, the carrier mobility of the semiconductor column 101 can be improved, thereby improving the efficiency of the semiconductor column 101 in transmitting electrical signals. For example, when the material of the semiconductor column 101 is IGZO, the carrier mobility of IGZO is 20-50 times that of polysilicon, which can improve the carrier mobility of the semiconductor column 101, thereby reducing the leakage current of the semiconductor structure during operation, reducing the power consumption of the semiconductor structure, and improving the working efficiency of the semiconductor structure.

[0036] It should be noted that in the drawings provided in the present embodiment, the semiconductor column 101 is a quadrangular prism, which does not limit the shape of the semiconductor column. In other embodiments, the semiconductor column can also be a cylinder, an elliptical cylinder, or a multi-prism. It can be understood that when the semiconductor column is a cylinder or an elliptical cylinder, the surface of the semiconductor column can avoid the formation of sharp corners to cause the sharp-end discharge effect. When the semiconductor column is a quadrangular prism or a multi-prism, the corners of the semiconductor column can be chamfered to avoid the sharp-end discharge effect.

[0037] In some embodiments, the size of the semiconductor column 101 along the first direction X is smaller than the size of the semiconductor column 101 along the second direction Y. It can be understood that, with reference to FIG. 1, the size of the semiconductor column 101 along the first direction X is the length of the semiconductor column 101 along the first direction X, and the size of the semiconductor column 101 along the second direction Y is the length of the semiconductor column 101 along the second direction Y. Figure 3When the capacitor structure 104 is arranged along the first direction X and the fifth direction W, the orthographic projection of the capacitor structure 104 partially overlaps with the orthographic projection of the semiconductor pillar 101 in a plane perpendicular to the third direction Z, and the overlapping area corresponds to the electrical contact area between the capacitor structure 104 and the semiconductor pillar 101. When the size of the semiconductor pillar 101 along the first direction X is smaller than the size of the semiconductor pillar 101 along the second direction Y, the capacitor structure 104 can have a larger electrical contact area with the semiconductor pillar 101, thereby improving the electrical transmission performance between the capacitor structure 104 and the semiconductor pillar 101.

[0038] For example, in some embodiments, the size of the semiconductor pillar 101 along the first direction X ranges from 15 nm to 25 nm, for example, the size of the semiconductor pillar 101 along the first direction X can be 15 nm, 18 nm, 20 nm, 21.5 nm, 23 nm, 24.8 nm or 25 nm; the size of the semiconductor pillar 101 along the second direction Y ranges from 30 nm to 40 nm, for example, the size of the semiconductor pillar 101 along the second direction Y can range from 30 nm, 32 nm, 35 nm, 36.5 nm, 38 nm or 40 nm. It can be understood that the size of the semiconductor pillar 101 along the first direction X and the size of the semiconductor pillar 101 along the second direction Y need to meet appropriate conditions so that the semiconductor pillar 101 can constitute a semiconductor channel of a transistor structure; however, the larger the size of the semiconductor pillar 101 along the first direction X and the size of the semiconductor pillar 101 along the second direction Y, the larger the volume of the corresponding semiconductor pillar 101, which is not conducive to improving the arrangement density of the semiconductor pillar 101, thereby leading to a decrease in the integration density of the semiconductor structure. Therefore, the size of the semiconductor pillar 101 along the first direction X and the size of the semiconductor pillar 101 along the second direction Y need to be set in combination with the overall size requirement of the semiconductor structure to improve the integration density of the semiconductor structure.

[0039] In some embodiments, the height of the semiconductor pillar 101 along the third direction Z can be 200-300 nm, for example, 200 nm, 224 nm, 250 nm, 276 nm or 300 nm. In some embodiments, the height of the first region I along the third direction Z can be 50-70 nm, specifically, 50 nm, 55 nm, 60 nm, 65 nm or 70 nm; the height of the second region II along the third direction Z can be 100-120 nm, specifically, 100 nm, 105 nm, 110 nm, 115 nm or 120 nm; and the height of the third region III along the third direction Z can be 70-90 nm, specifically, 70 nm, 75 nm, 80 nm, 85 nm or 90 nm. It can be understood that the height of the semiconductor pillar 101 corresponds to the size of the transistor structure formed by the semiconductor pillar 101, and the height of the first region I, the second region II and the third region III correspond to the size of the source region, the channel region and the drain region of the transistor structure. The transistor structure and the corresponding source region, channel region and drain region need to meet appropriate sizes to facilitate the formation of a stable transistor and improve the stability of the semiconductor structure.

[0040] In some embodiments, the first distance L1 is 30-40 nm, for example, the first distance L1 can be 30 nm, 32 nm, 35 nm, 36.5 nm, 38 nm or 40 nm; and the second distance L2 is 52-80 nm, for example, the second distance L2 can be 52 nm, 60.1 nm, 65.5 nm, 70 nm, 75.8 nm or 80 nm. The first distance L1 is the distance between the center axes of adjacent semiconductor pillars 101 along the first direction X. The smaller the first distance L1, the closer the distance between adjacent semiconductor pillars 101 along the first direction X, which is prone to cause leakage between adjacent semiconductor pillars 101. The larger the first distance L1, the farther the distance between adjacent semiconductor pillars 101 along the first direction X, which reduces the arrangement density of the semiconductor pillars 101 and further reduces the integration density of the semiconductor structure. Similarly, the second distance L2 is the distance between the center axes of adjacent semiconductor pillars 101 along the second direction Y. The smaller the second distance L2, the closer the distance between adjacent semiconductor pillars 101 along the second direction Y, which is prone to cause leakage between adjacent semiconductor pillars 101. The larger the second distance L2, the farther the distance between adjacent semiconductor pillars 101 along the second direction Y, which reduces the arrangement density of the semiconductor pillars 101 and further reduces the integration density of the semiconductor structure. Therefore, the first distance L1 and the second distance L2 need to be adjusted within an appropriate range to avoid leakage between adjacent semiconductor pillars 101 and improve the integration density of the semiconductor structure.

[0041] In some embodiments, the semiconductor pillar 101 further comprises a trench structure 105 extending along the first direction X, and the trench structure 105 at least passes through the first region I and the second region II of the plurality of semiconductor pillars 101 along the first direction X, and the trench structure 105 divides the semiconductor pillar 101 into a first sub-semiconductor pillar 111 and a second sub-semiconductor pillar 121. For example, referring to Figure 4 and Figure 5 By the trench structure 105 passing through only the first region I and the second region II of the semiconductor pillar 101, the semiconductor pillar 101 is divided into the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121, the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121 can form transistor structures respectively, and the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121 share the third region III of the same semiconductor pillar 101 and are connected with the bit line 103, thereby improving the control ability of the bit line 103.

[0042] In some embodiments, the trench structure can also pass through the first region, the second region and the third region of the plurality of semiconductor pillars, i.e., the entire semiconductor pillar is divided into two relatively independent sub-semiconductor pillars, which can be beneficial for ion implantation doping of the third region of the sub-semiconductor pillar after forming the trench. In some embodiments, the trench structure can pass through the first region, the second region and the third region of the plurality of semiconductor pillars, and the trench structure is also located in the substrate, which is beneficial for ion implantation doping of the substrate through the trench, and further refilling the trench structure in the substrate to form a complete bit line and ion implantation doping of the third region of the sub-semiconductor pillar.

[0043] In some embodiments, the height of the trench structure 105 along the third direction Z can be 150nm-170nm, and specifically can be 150nm, 155nm, 160nm, 165nm or 170nm. The higher the height of the trench structure 105, the higher the height of the corresponding first sub-semiconductor pillar 111 and second sub-semiconductor pillar 121, which in turn easily leads to the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121 to be tilted; the lower the height of the trench structure 105, the lower the height of the corresponding first sub-semiconductor pillar 111 and second sub-semiconductor pillar 121, which is not conducive to forming a complete transistor structure, therefore, the height of the trench structure 105 needs to be adjusted within an appropriate range.

[0044] In some embodiments, the trench structure 105 can be filled with insulating materials such as silicon oxide or silicon nitride, so as to separate the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121, and avoid leakage between the corresponding transistor structures of the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121, thereby improving the stability of the semiconductor structure.

[0045] In some embodiments, the ratio of the size of the semiconductor pillar 101 to the size of the trench structure 105 in the second direction Y is 1.4-2, for example, the ratio of the size of the semiconductor pillar 101 to the size of the trench structure 105 can be 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2. It can be understood that the trench structure 105 divides the first region I and the second region II of the semiconductor pillar 101 into the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121, the greater the ratio of the size of the semiconductor pillar 101 to the size of the trench structure 105, the smaller the size of the trench structure 105, the closer the distance between the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121, and thus it is easy to generate parasitic capacitance; the smaller the ratio of the size of the semiconductor pillar 101 to the size of the trench structure 105, the greater the size of the trench structure 105, the smaller the size of the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121, and thus it is not conducive to form a transistor structure. Therefore, the ratio of the size of the semiconductor pillar 101 to the size of the trench structure 105 needs to be in an appropriate range, so as to facilitate the division of the semiconductor pillar 101 into two semiconductor pillars 101 to form two transistor structures, while avoiding reducing the performance of the semiconductor structure.

[0046] In some embodiments, the ratio of the size of the first sub-semiconductor pillar 111 or the second sub-semiconductor pillar 121 to the size of the trench structure 105 in the second direction Y is 0.2-0.5, for example, it can be 0.2, 0.3, 0.35, 0.4, 0.45 or 0.5. The ratio of the size of the first sub-semiconductor pillar 111 or the second sub-semiconductor pillar 121 to the size of the trench structure 105 reflects the size of the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121. In some embodiments, the size of the first sub-semiconductor pillar 111 ranges from 5-8 nm in the first direction X or the second direction Y, and specifically can be 5 nm, 5.3 nm, 6 nm, 6.4 nm, 7 nm, 7.6 nm or 8 nm. In some embodiments, the size of the second sub-semiconductor pillar 121 ranges from 5-8 nm in the first direction X or the second direction Y, and specifically can be 5 nm, 5.3 nm, 6 nm, 6.4 nm, 7 nm, 7.6 nm or 8 nm. The ratio of the size of the first sub-semiconductor pillar 111 or the second sub-semiconductor pillar 121 to the size of the trench structure 105, and the size of the first sub-semiconductor pillar 111 or the second sub-semiconductor pillar 121 all need to be in an appropriate range, so that the size of the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121 needs to meet the requirements of forming a transistor structure, while avoiding the size of the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121 being too large to cause mutual leakage.

[0047] Further, in some embodiments, with reference to Figure 6 and Figure 7The semiconductor structure also includes a plurality of capacitor structures 106, which extend in a third direction Z, and each capacitor structure 106 is electrically contacted with a first region I of a first sub-semiconductor pillar 111 or a second sub-semiconductor pillar 121. When the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121 respectively constitute a transistor structure, the first region I of the first sub-semiconductor pillar 111 and the first region I of the second sub-semiconductor pillar 121 can be respectively connected to the capacitor structure 106 to form two memory cells, thereby further improving the integration density of the semiconductor structure.

[0048] For capacitor structure 106, capacitor structure 106 can be a cylindrical capacitor or a cylindrical capacitor. In some embodiments, capacitor structure 106 may include a lower electrode, a capacitor dielectric layer, and an upper electrode stacked sequentially. The materials of the lower electrode and the upper electrode include at least one of platinum nickelide, titanium, tantalum, cobalt, polycrystalline silicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium; the materials of the capacitor dielectric layer include high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate.

[0049] In some embodiments, reference Figure 6 When the ratio of the second spacing L2 to the first spacing L1 is 2, the capacitor structures 106 are arranged along the first direction X and the second direction Y. Along the first direction X, the distance between the central axes of adjacent capacitor structures 106 is equal to the first spacing L1; along the second direction Y, the distance between the central axes of adjacent capacitor structures 106 is equal to the first spacing L1. When the ratio of the second spacing L2 to the first spacing L1 is 2, the spacing between adjacent first sub-semiconductor pillars 111 along the first direction X is equal to the spacing between adjacent first sub-semiconductor pillars 111 and second sub-semiconductor pillars 121 along the second direction Y. That is, the corresponding capacitor structures 106 can be arranged along the first direction X and the second direction Y at a 4F... 2 The array is closely arranged, which improves the space utilization of the semiconductor structure and also helps the capacitor structure 106 to be cylindrical, reducing local leakage current of the capacitor structure 106.

[0050] In some embodiments, reference Figure 7 When the ratio of the second spacing L2 to the first spacing L1 is At this time, the capacitor structures 106 are arranged along the first direction X and the fourth direction N, with the angle between the fourth direction N and the first direction X being 60°. Along the first direction X, the distance between the central axes of adjacent capacitor structures 106 is equal to the first spacing L1, and along the fourth direction N, the distance between the central axes of adjacent capacitor structures 106 is equal to the first spacing L1. When the ratio of the second spacing L2 to the first spacing L1 is... At that time, the spacing between adjacent first sub-semiconductor pillars 111 along the first direction X is equal to the spacing between adjacent first sub-semiconductor pillars 111 and second sub-semiconductor pillars 121 along the fourth direction N. That is to say, the corresponding capacitor structure 106 can be coupled along the first direction X and the fourth direction N at a distance of 6F. 2 The array is closely arranged, which improves the space utilization of the semiconductor structure and also helps the capacitor structure 106 to be cylindrical, reducing local leakage current of the capacitor structure 106.

[0051] It is understandable that when the ratio of the second spacing L2 to the first spacing L1 is... When the distance between the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121 is adjusted accordingly, the corresponding capacitor structure 106 can be appropriately adjusted to improve the space utilization of the semiconductor structure, while also making the capacitor structure 106 cylindrical and reducing local leakage current of the capacitor structure 106.

[0052] In some embodiments, the orthographic projection of the capacitor structure 106 on a plane perpendicular to the central axis of the capacitor structure 106 is circular, and the ratio of the diameter of the capacitor structure 106 to the dimension of the semiconductor pillar along the first direction is [value missing]. The capacitor structure 106 is circular in the plane perpendicular to its central axis, thus forming a cylindrical capacitor structure 106. This avoids uneven electric field within the capacitor dielectric layer, thereby preventing leakage in localized areas of the capacitor structure 106. It is understood that the ratio between the diameter of the capacitor structure 106 and the dimension of the semiconductor pillar along the first direction needs to meet appropriate conditions to prevent the capacitor structure 106 from becoming too large, thus avoiding the connection of multiple sub-semiconductor pillars to a single capacitor structure 106.

[0053] In some embodiments, reference Figures 4 to 7The word line 102 comprises a first sub-word line 112 and a second sub-word line 122, the first sub-word line 112 encircles the second region II surface of the first sub-semiconductor pillar 111 away from the one side of the trench structure 105, the second sub-word line 122 encircles the second region II surface of the second sub-semiconductor pillar 121 away from the one side of the trench structure 105, and the first sub-word line 112 and the second sub-word line 122 are spaced apart from each other. That is, the trench structure 105 can also extend along the first direction X to divide the word line 102 into the first sub-word line 112 and the second sub-word line 122 to control the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121, respectively, to correspond to two independent transistor structures, thereby increasing the integration density of the semiconductor structure. In addition, since the third region III of the first sub-semiconductor pillar 111 and the third region III of the second sub-semiconductor pillar 121 are not separated by the trench structure 105, the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121 can share the same bit line 103, and under the cooperation of the same bit line 103 and different sub-word lines, the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121 can be controlled respectively.

[0054] For the word line 102, the material of the word line 102 comprises at least one of doped polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium, or tungsten.

[0055] In some embodiments, the ratio of the distance between adjacent word lines 102 to the second spacing L2 along the second direction Y is 0.07-0.13, and can be 0.07, 0.09, 0.11, or 0.13. The larger the ratio of the distance between adjacent word lines 102 to the second spacing L2, the smaller the size of the corresponding word line 102, which is not conducive to the word line 102 encircling the semiconductor pillar 101; the smaller the ratio of the distance between adjacent word lines 102 to the second spacing L2, the larger the size of the corresponding word line 102, which is easy to cause leakage between adjacent word lines 102. For example, in some embodiments, the distance between adjacent word lines 102 is 5-10 nm along the second direction Y, and can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm. The distance between adjacent word lines 102 and the ratio of the distance between adjacent word lines 102 to the second spacing L2 need to be adjusted within an appropriate range to facilitate the word line 102 encircling the semiconductor pillar 101 to increase the contact area of the word line 102 and the semiconductor pillar 101, thereby increasing the control ability of the word line 102, while avoiding the distance between adjacent word lines 102 being too close to cause leakage.

[0056] For the bit line 103, the material of the bit line 103 includes at least one of metal silicide, titanium nitride or tungsten. In some embodiments, the material forming the first bit line can be a single metal, a metal compound or an alloy. The single metal can be aluminum, tungsten, gold or silver, etc.; the metal compound can be tungsten nitride, tantalum nitride or titanium nitride; and the alloy can be an alloy material formed by at least two of aluminum, tungsten, gold or silver.

[0057] In some embodiments, the size of the bit line 103 in the first direction X is equal to the size of the semiconductor column 101 in the first direction X. That is, the end surface of the third region III of the semiconductor column 101 can be in complete electrical contact with the bit line 103, thereby increasing the electrical contact area of the bit line 103 with the semiconductor column 101, improving the control ability and electrical transmission performance of the bit line 103 on the semiconductor column 101.

[0058] In some embodiments, the semiconductor structure further includes: a substrate, the first direction and the second direction are parallel to the substrate surface, and the third direction is perpendicular to the substrate surface; the first region, the second region and the third region of the semiconductor column are arranged in a direction away from the substrate surface, and the bit line is located at one end of the semiconductor column away from the substrate surface; or the first region, the second region and the third region of the semiconductor column are arranged in a direction pointing to the substrate surface, and the bit line is located at one end of the semiconductor column close to the substrate surface. That is, when the bit line is located at one end of the semiconductor column away from the substrate surface, the capacitor structure can be formed on the substrate first, and then the semiconductor column and the bit line are formed on the capacitor structure; when the bit line is located at one end of the semiconductor column close to the substrate surface, the bit line and the semiconductor column can be formed on the substrate first, and then the capacitor structure is formed on the top of the semiconductor column. Different structures correspond to different manufacturing methods, which increases the selectability of the semiconductor structure.

[0059] Further, in some embodiments, when the semiconductor column includes a trench structure, the first region, the second region and the third region of the semiconductor column are arranged in a direction pointing to the substrate surface, and the bit line is located at one end of the semiconductor column close to the substrate surface. It can be understood that when the first region and the second region are arranged in a direction pointing to the substrate surface, it is convenient to form the trench structure after forming the semiconductor column, so as to reduce the difficulty of manufacturing the semiconductor structure.

[0060] It should be noted that the different semiconductor structures provided in the above embodiments can be combined arbitrarily to obtain new embodiments without conflict.

[0061] The semiconductor structure provided by the embodiments of the present disclosure can be arranged by arranging a plurality of semiconductor columns 101 in the perpendicular first direction X and the second direction Y, and can constitute a 4F 2The semiconductor pillars 101 are arranged in a third direction Z. Each pillar includes a first region I, a second region II, and a third region III arranged sequentially. A word line surrounds the second region II of the multiple semiconductor pillars 101 along a first direction X. A bit line makes electrical contact with the third region III of the multiple semiconductor pillars 101 along a second direction Y. Thus, the semiconductor pillars 101 can form a VGAA structure transistor. Specifically, along the first direction X, the distance between the central axes of adjacent semiconductor pillars 101 is a first spacing L1, and along the second direction Y, the distance between the central axes of adjacent semiconductor pillars 101 is a second spacing L2. The ratio of the second spacing L2 to the first spacing L1 is less than [value missing]. When the ratio of the second spacing L2 to the first spacing L1 is greater than 2, it will result in insufficient space for the corresponding capacitor structure 104; when the ratio of the second spacing L2 to the first spacing L1 is greater than 2, it is not conducive to increasing the size of the corresponding capacitor structure 104, and it will lead to wasted space of the semiconductor structure along the second direction Y. Setting the ratio of the second spacing L2 to the first spacing L1 to 2 is... The spacing between them allows for sufficient space to be arranged when the capacitor structure 104 is electrically connected to the first region I of the semiconductor pillar 101, thus improving the space utilization of the semiconductor structure. At the same time, the capacitor structure 104 is set as a cylindrical structure when it has a large area. The cylindrical structure of the capacitor structure 104 can avoid the uneven electric field in the capacitor dielectric layer, thereby avoiding leakage in local areas of the capacitor structure 104. In addition, the large distance between the capacitors can avoid the generation of parasitic capacitance between adjacent capacitors, thus improving the stability of the semiconductor structure.

[0062] According to some embodiments of this disclosure, another embodiment provides a method for manufacturing a semiconductor structure, which can be used to form the above-described semiconductor structure to improve the stability of the semiconductor structure. It should be noted that the parts that are the same as or corresponding to those in the above embodiments can be referred to the corresponding descriptions in the foregoing embodiments, and will not be described in detail below.

[0063] The semiconductor structure manufacturing method provided in this embodiment will be described in detail below with reference to the accompanying drawings.

[0064] Continue to refer to Figure 1 and Figure 2, a method for manufacturing a semiconductor structure, comprising: providing a substrate (not shown in the figure); forming a plurality of semiconductor pillars 101 on the substrate, the semiconductor pillars 101 are arranged along a first direction X and a second direction Y, and extend along a third direction Z, along the third direction Z, the semiconductor pillars 101 comprise a first region I, a second region II and a third region III arranged in sequence; forming a plurality of word lines 102, the word lines 102 extend along the first direction X, and along the first direction X, the word lines 102 surround the second regions II of the plurality of semiconductor pillars 101; forming a plurality of bit lines 103, the bit lines 103 extend along the second direction Y, and along the second direction Y, the bit lines 103 are in electrical contact with the third regions III of the plurality of semiconductor pillars 101; wherein the first direction X is perpendicular to the second direction Y, along the first direction X, the distance between the center axes of adjacent semiconductor pillars 101 is a first pitch L1; along the second direction Y, the distance between the center axes of adjacent semiconductor pillars 101 is a second pitch L2, the ratio of the second pitch L2 to the first pitch L1 is For example, the ratio of the second pitch L2 to the first pitch L1 can be 1.75, 1.8, 1.85, 1.9, 1.99 or 2.

[0065] The method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure sets the ratio of the second pitch L2 to the first pitch L1 to be between 1.75 and 2, which can facilitate the capacitor structure 104 to have sufficient space to arrange when being electrically connected with the first region I of the semiconductor pillar 101, and improve the space utilization of the semiconductor structure; at the same time, the capacitor structure 104 can be set as a cylindrical structure when having a larger area, the cylindrical capacitor structure 104 can avoid the non-uniform electric field in the capacitor dielectric layer, thereby avoiding the formation of local leakage in the capacitor structure 104, and the larger distance between capacitors can avoid the generation of parasitic capacitance between adjacent capacitors, and improve the stability of the semiconductor structure.

[0066] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized by, The semiconductor pillar comprises: a plurality of semiconductor pillars arranged along a first direction and a second direction and extending along a third direction, wherein the semiconductor pillars comprise, along the third direction, a first region, a second region and a third region arranged in sequence; a plurality of word lines extending along the first direction, and, along the first direction, the word lines surround the second regions of a plurality of the semiconductor pillars; a plurality of bit lines extending along the second direction, and, along the second direction, the bit lines are in electrical contact with the third regions of a plurality of the semiconductor pillars; wherein the first direction is perpendicular to the second direction, along the first direction, the distance between the central axes of adjacent semiconductor pillars is a first pitch, and along the second direction, the distance between the central axes of adjacent semiconductor pillars is a second pitch, and the ratio of the second pitch to the first pitch is √3-2.

2. The semiconductor structure of claim 1, wherein, The dimension of the semiconductor pillar along the first direction is less than the dimension of the semiconductor pillar along the second direction.

3. The semiconductor structure of claim 2, wherein, The dimension of the semiconductor pillar along the first direction ranges from 15 nm to 25 nm, and the dimension of the semiconductor pillar along the second direction ranges from 30 nm to 40 nm.

4. The semiconductor structure of claim 1, wherein, The first pitch ranges from 30 nm to 40 nm, and the second pitch ranges from 52 nm to 80 nm.

5. The semiconductor structure of claim 1, wherein, The semiconductor pillar further comprises: a trench structure extending along the first direction, and, along the first direction, the trench structure at least passes through the first region and the second region of a plurality of the semiconductor pillars, and the trench structure divides the semiconductor pillars into first sub-semiconductor pillars and second sub-semiconductor pillars.

6. The semiconductor structure of claim 5, wherein, Further comprising: a plurality of capacitor structures extending along the third direction, and each capacitor structure is in electrical contact with the first region of a first sub-semiconductor pillar or a second sub-semiconductor pillar.

7. The semiconductor structure of claim 6, wherein, When the ratio of the second pitch to the first pitch is 2, the capacitor structures are arranged along the first direction and the second direction, and along the first direction, the distance between the central axes of adjacent capacitor structures is equal to the first pitch, and along the second direction, the distance between the central axes of adjacent capacitor structures is equal to the first pitch.

8. The semiconductor structure of claim 6, wherein, when the ratio of the second pitch to the first pitch is when the ratio of the second pitch to the first pitch is when the ratio of the second pitch to the first pitch is 9. The semiconductor structure of any of claims 6-8, wherein, In a plane perpendicular to a central axis of the capacitor structure, a normal projection of the capacitor structure is circular, and a ratio of a diameter of the capacitor structure to a size of the semiconductor pillar in the first direction is 10. The semiconductor structure of claim 5, wherein, Along the second direction, the ratio of the dimension of the semiconductor pillar to the dimension of the trench structure is 1.4-2.

11. The semiconductor structure of claim 5, wherein, The word line comprises: a first sub-word line and a second sub-word line, the first sub-word line surrounds the second region surface of the first sub-semiconductor pillar away from the trench structure, and the second sub-word line surrounds the second region surface of the second sub-semiconductor pillar away from the trench structure, and the first sub-word line and the second sub-word line are spaced apart from each other.

12. The semiconductor structure of claim 1, wherein, Along the second direction, the ratio of the distance between adjacent word lines to the second pitch is 0.07-0.

13.

13. The semiconductor structure of claim 1, wherein, The dimension of the bit line along the first direction is equal to the dimension of the semiconductor pillar along the first direction.

14. The semiconductor structure of claim 13, wherein, Further comprising: a substrate, the first direction and the second direction are parallel to the surface of the substrate, and the third direction is perpendicular to the surface of the substrate; The first region, the second region and the third region of the semiconductor pillar are arranged in a direction away from the substrate surface, and the bit line is located at an end of the semiconductor pillar away from the substrate surface; or the first region, the second region and the third region of the semiconductor pillar are arranged in a direction pointing to the substrate surface, and the bit line is located at an end of the semiconductor pillar close to the substrate surface.

15. A method of manufacturing a semiconductor structure, characterized by, Comprise: providing a substrate; forming a plurality of semiconductor pillars on the substrate, the semiconductor pillars being arranged in a first direction and a second direction and extending in a third direction, in the third direction, the semiconductor pillars comprising a first region, a second region and a third region arranged in sequence; forming a plurality of word lines, the word lines extending in the first direction, and in the first direction, the word lines surrounding the second regions of a plurality of the semiconductor pillars; forming a plurality of bit lines, the bit lines extending in the second direction, and in the second direction, the bit lines being in electrical contact with the third regions of a plurality of the semiconductor pillars; The first direction is perpendicular to the second direction. In the first direction, the distance between the center axes of adjacent semiconductor pillars is a first pitch. In the second direction, the distance between the center axes of adjacent semiconductor pillars is a second pitch. The ratio of the second pitch to the first pitch is

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