A method of manufacturing a semiconductor structure and a semiconductor structure

Abstract

The embodiments of the present disclosure disclose a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method comprises: providing a substrate, the substrate comprising a first sub-region and a second sub-region; forming a first trench in the substrate, the first trench passing through the first sub-region and the second sub-region; forming a gate dielectric layer covering the inner surface of the first trench; forming a first word line material layer, the first word line material layer covering the gate dielectric layer and filling in the first trench; performing an etching process to etch the first word line material layer, so that the upper surface of the first word line material layer located in the second sub-region is lowered by a preset distance, while a first hole is formed on the first word line material layer located in the first sub-region.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] Dynamic Random Access Memory (DRAM) comprises multiple repeating memory cells, each typically including a capacitor and a transistor. Voltage signals on the word lines control the transistors to turn on or off. As DRAM feature sizes continue to shrink, word line widths become increasingly narrow, resulting in smaller contact areas between the conductive structures connected to the word lines and the word lines themselves. This leads to higher contact resistance and increased fabrication complexity. Furthermore, with decreasing feature sizes, gate-induced drain leakage (GIDL) is more likely to occur between the gate and drain of the transistors, affecting memory reliability. Therefore, optimizing the fabrication process and reducing contact resistance and GIDL effects are pressing technical challenges. Summary of the Invention

[0003] In view of the above, this disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure in order to solve or improve the technical problems existing in the prior art.

[0004] According to a first aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising:

[0005] A substrate is provided, the substrate comprising a first partition and a second partition;

[0006] A first trench is formed within the substrate, the first trench passing through the first partition and the second partition;

[0007] A gate dielectric layer is formed covering the inner surface of the first trench;

[0008] A first word line material layer is formed, which covers the gate dielectric layer and fills the first trench;

[0009] An etching process is performed to etch the first character line material layer, causing the upper surface of the first character line material layer located in the second partition to drop by a predetermined distance, while simultaneously forming a first hole in the first character line material layer located in the first partition.

[0010] In some embodiments, performing an etching process includes:

[0011] A mask layer is formed on the first word line material layer;

[0012] The mask layer is patterned to form a first opening in the first partition and a second opening in the second partition, wherein the area of ​​the second opening is larger than the area of ​​the first opening;

[0013] Using the mask layer as a barrier, the first word line material layer is etched to form the first hole and cause the upper surface of the first word line material layer located in the second partition to drop by a predetermined distance, wherein the etching rate of the first word line material layer exposed to the first opening is less than the etching rate of the first word line material layer exposed to the second opening.

[0014] In some embodiments, performing the etching process further includes:

[0015] By controlling the etching parameters, the contour of the bottom of the first hole is made into a curved shape.

[0016] In some embodiments, after performing the etching process, the remaining first word line material layer is defined as the first word line layer, and the method further includes:

[0017] A second word line material layer is formed, which fills the first hole and covers the first word line layer;

[0018] The second word line material layer is etched to remove the second word line material layer located in the first partition. The remaining second word line material layer located in the second partition is defined as the second word line layer. The upper surface of the second word line layer is lower than the upper surface of the first word line layer located in the first partition.

[0019] In some embodiments, after forming the second word line layer, the method further includes:

[0020] An isolation layer is formed, which fills the first trench and covers the first letter line layer and the second letter line layer; the upper surface of the isolation layer is flush with the upper surface of the substrate.

[0021] In some embodiments, after forming the isolation layer, the method further includes:

[0022] The isolation layer is etched to form a second hole, which is connected to the first hole, and the isolation layer located in the first hole is removed.

[0023] A contact structure is formed in the second hole and the first hole.

[0024] According to a second aspect of the present disclosure, a semiconductor structure is provided, comprising:

[0025] The substrate includes a first partition and a second partition;

[0026] A first trench located within the substrate, the first trench passing through the first partition and the second partition;

[0027] A gate dielectric layer covering the inner surface of the first trench;

[0028] A first word line layer covering the gate dielectric layer and filling the first trench, wherein the upper surface of the first word line layer located above the first partition is higher than the upper surface of the first word line layer located in the second partition;

[0029] The contact structure is located in the first partition, and the bottom of the contact structure extends into the first word line layer.

[0030] In some embodiments, the bottom surface of the contact structure is curved; and / or,

[0031] Along a direction perpendicular to the upper surface of the substrate, the ratio of the thickness of the first word line layer in the first partition to the thickness of the first word line layer in the second partition is greater than 1.5; and / or,

[0032] The contact structure includes a contact sub-part located within the first letter line layer; the aspect ratio of the contact sub-part ranges from 0.7 to 1.65; and / or,

[0033] The bottom of the contact structure is higher than the upper surface of the first word line layer located in the second partition; and / or,

[0034] The ratio of the area of ​​the upper surface of the first letter bar layer located in the second partition to the area of ​​the cross-section of the contact structure at the upper surface of the first letter bar layer is 2 × 10. 6 Up to 5×10 6 .

[0035] In some embodiments, the semiconductor structure further includes:

[0036] A second word line layer covers the first word line layer located in the second partition, wherein the upper surface of the second word line layer is lower than the upper surface of the first word line layer located in the first partition.

[0037] In some embodiments, the work function of the second word line layer is less than the work function of the first word line layer.

[0038] This disclosure provides a method for manufacturing a semiconductor structure, including providing a substrate, the substrate including a first partition and a second partition; forming a first trench in the substrate, the first trench passing through the first partition and the second partition; forming a gate dielectric layer covering the inner surface of the first trench; forming a first word line material layer, the first word line material layer covering the gate dielectric layer and filling the first trench; performing an etching process to etch the first word line material layer, such that the upper surface of the first word line material layer located in the second partition drops by a predetermined distance, while forming a first hole in the first word line material layer located in the first partition. In this disclosure, a first trench is first formed within a substrate, penetrating a first partition and a second partition. Next, a gate dielectric layer and a first word line material layer covering the gate dielectric layer and filling the first trench are formed on the inner surface of the first trench. Then, the first word line material layer is etched, causing the upper surface of the first word line material layer in the second partition to drop by a predetermined distance. This facilitates the subsequent deposition of other conductive layers above the first word line material layer in the second partition to form a hybrid gate, mitigating gate-induced drain leakage (GIDL) effects, increasing saturation current, and improving the reliability of the semiconductor device. Simultaneously, a first via is formed on the first word line material layer in the first partition, allowing the contact structure subsequently formed in the first partition to fill the via. This enables direct contact between the contact structure and the first word line layer, effectively increasing the contact area, reducing contact resistance, enhancing the stability of the connection, and ultimately improving the performance of the semiconductor device. In this disclosure, a single etching process simultaneously completes etching for different purposes in the first and second partitions of the substrate, simplifying the process and resulting in a semiconductor device with high overall performance.

[0039] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description

[0040] Figure 1 This is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

[0041] Figures 2a to 2h This is a schematic diagram of the semiconductor structure during the manufacturing process provided in the embodiments of this disclosure;

[0042] Figure 3 This is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure;

[0043] Figure 4 This is a cross-sectional schematic diagram of a semiconductor structure according to another embodiment of the present disclosure.

[0044] Figure label:

[0045] 10-Substrate; 101-First partition; 102-Second partition; 103-Active region; 11-First trench; 12-Gate dielectric layer; 13-First word line material layer; 131-First word line layer; 14-First hole; 15-Mask layer; 151-First opening; 152-Second opening; 16-Second word line material layer; 161-Second word line layer; 17-Isolation layer; 18-Second hole; 19-Contact structure; 191-Contact sub-part; 20-Metal layer. Detailed Implementation

[0046] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0047] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0048] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0049] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0050] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0051] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0052] Dynamic Random Access Memory (DRAM) cells typically include capacitors and transistors. Word lines are connected to word line drivers via local interconnect contacts (LICONs) located on the periphery of the cell, facilitating the input of voltage signals to the word lines to control the switching on and off of the transistors. As DRAM feature sizes continue to shrink, word line widths become increasingly narrow, resulting in a smaller contact area between the contact structures and the word lines. This leads to higher contact resistance and increased manufacturing complexity. Furthermore, with decreasing feature sizes, gate-induced drain leakage (GIDL) is more likely to occur between the gate and drain of the transistors, thus affecting memory reliability.

[0053] Based on this, this disclosure provides a method for manufacturing a semiconductor structure, as detailed in the appendix. Figure 1 As shown in the figure, the method includes:

[0054] Step 101: Provide a base, which includes a first partition and a second partition;

[0055] Step 102: Form a first trench in the substrate, the first trench passing through the first partition and the second partition;

[0056] Step 103: Form a gate dielectric layer covering the inner surface of the first trench;

[0057] Step 104: Form a first word line material layer, which covers the gate dielectric layer and fills the first trench;

[0058] Step 105: Perform an etching process to etch the first character line material layer, causing the upper surface of the first character line material layer in the second partition to drop by a preset distance, while simultaneously forming a first hole in the first character line material layer in the first partition.

[0059] The method for manufacturing the semiconductor structure provided in this disclosure will be further described in detail below with reference to specific embodiments.

[0060] First, perform step 101, see appendix. Figure 2a A base 10 is provided, which includes a first partition 101 and a second partition 102.

[0061] Here, the substrate 10 may include, but is not limited to, a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. In some specific embodiments, the substrate 10 includes a doped or undoped silicon substrate, wherein the second partition 102 of the substrate 10 may include a plurality of arrayed active regions 103, adjacent active regions 103 are isolated by an isolation structure (not shown), serving as an array region of memory cells; the first partition 101 may serve as the peripheral region of the memory cells, used to connect external control circuits and other components. The first partition 101 and the second partition 102 may be arranged adjacent to each other, or the first partition 101 may surround the outer periphery of the second partition 102, without specific limitations here.

[0062] Next, proceed to step 102, see appendix. Figure 2a A first trench 11 is formed in the substrate 10, and the first trench 11 passes through the first partition 101 and the second partition 102.

[0063] A buried gate can be formed in the first trench 11. As the size of semiconductor devices decreases, a recessed channel array transistor is formed, which makes the channel length longer and can suppress the short-channel effect.

[0064] In practice, anisotropic etching processes can be used to form the first trench 11. For example, a mask pattern for the first trench 11 can first be formed using self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP). Then, using the mask pattern as a mask, plasma etching processes are employed to etch the substrate 10 to form the first trench 11. Ideally, the bottom of the first trench 11 should be flush. However, in reality, since the active region 103 typically comprises monocrystalline silicon and the isolation structure between adjacent active regions 103 typically comprises oxide, the etching rates of the two differ in the same etching step. This results in a greater depth of etching of the isolation structure, thus giving the active region 103 a convex morphology.

[0065] Next, proceed to step 103, see appendix. Figure 2b This forms a gate dielectric layer 12 covering the inner surface of the first trench 11.

[0066] The gate dielectric layer 12 can be used to isolate the word line from the substrate 10 and suppress gate tunneling leakage current.

[0067] In practice, one or more of the following processes can be used to form the gate dielectric layer 12: physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or thermal oxidation. The material of the gate dielectric layer 12 can include, but is not limited to, silicon dioxide, silicon monoxide, hafnium oxide, or titanium oxide.

[0068] Next, proceed to step 104, see appendix. Figure 2b A first word line material layer 13 is formed, which covers the gate dielectric layer 12 and fills the first trench 11.

[0069] In practice, the first word line material layer 13 can be formed using one or more of the following processes: physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or electroplating. The material of the first word line material layer 13 can be, but is not limited to, metallic materials, such as tungsten, copper, aluminum, titanium, tantalum, silver, tantalum nitride, and titanium nitride, or any combination thereof. In some specific embodiments, the material of the first word line material layer 13 includes tungsten.

[0070] In some embodiments, before forming the first word line material layer 13, the method further includes forming a metal barrier layer on the surface of the gate dielectric layer 12.

[0071] The metal barrier layer has good diffusion blocking properties, good stability at high temperatures, and is resistant to corrosion and oxidation. It has good contact with both semiconductors and metals, high electrical conductivity and low ohmic contact resistance, and can prevent the metal material in the first word line material layer 13 from diffusing into the gate dielectric layer 12, so as to avoid affecting the performance of the semiconductor device.

[0072] In practice, one or more of the following processes can be used to form a metal barrier layer: physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or electroplating. The material of the metal barrier layer can include any combination of one or more of titanium, titanium nitride, tantalum, silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), or silicon carbonitride oxycarbonate (SiOCN). In some specific embodiments, the first word line material layer 13 is made of tungsten, and the material of the metal barrier layer can include one or a combination of titanium or titanium nitride.

[0073] Next, proceed to step 105, see appendix. Figure 2c and attached Figure 2d An etching process is performed to etch the first character line material layer 13, causing the upper surface of the first character line material layer 13 located in the second partition 102 to drop by a predetermined distance, while forming a first hole 14 on the first character line material layer 13 located in the first partition 101.

[0074] By employing a one-step etching process, the upper surface of the first word line material layer 13 located in the second partition 102 is lowered by a predetermined distance. This facilitates the subsequent deposition of other conductive layers above the first word line material layer 13 in the second partition 102 to form a hybrid gate, thereby mitigating the gate-induced drain leakage (GIDL) effect, increasing saturation current, and improving the reliability of the semiconductor device. Simultaneously, a first via 14 is formed on the first word line material layer 13 located in the first partition 101, allowing the contact structure 19 subsequently formed in the first partition 101 to fill within the first via 14. This enables direct contact between the contact structure 19 and the first word line layer 131, effectively increasing the contact area and significantly reducing contact resistance, thus improving the performance of the semiconductor device. The process is simplified and highly practical.

[0075] In some embodiments, see Appendix Figure 2c and attached Figure 2d The etching process includes: forming a mask layer 15 on the first letter line material layer 13; patterning the mask layer 15 to form a first opening 151 on the first partition 101 and a second opening 152 on the second partition 102, wherein the area of ​​the second opening 152 is larger than the area of ​​the first opening 151 (see Appendix). Figure 2c Using the mask layer 15 as a barrier, the first character line material layer 13 is etched to form the first hole 14, and the upper surface of the first character line material layer 13 located in the second partition 102 is lowered by a predetermined distance (see Appendix). Figure 2d The etching rate of the first word line material layer 13 exposed to the first opening 151 is less than the etching rate of the first word line material layer 14 exposed to the second opening 152.

[0076] Since the area of ​​the second opening 152 on the mask layer 15 is larger than the area of ​​the first opening 151, the etching load effect related to the aspect ratio during etching is utilized to make the etching rate of the first word line material layer 13 exposed by different openings different. As a result, the distance the upper surface of the first word line material layer 13 located in the second partition 102 descends is greater than the depth of the first hole 14. The larger distance the upper surface of the first word line material layer 13 located in the second partition 102 descends can reserve sufficient space for subsequent processes to deposit other conductive layers above the first word line material layer 13 to form a hybrid gate, thereby mitigating the GIDL effect. The depth of the formed first hole 14 is moderate, which can effectively increase the contact area between the contact structure 19 formed in the first hole 14 and the first word line material layer 13 in subsequent processes, while avoiding problems such as poor contact between the contact structure 19 and the first word line material layer 13 caused by the isolation layer 17 in the hole not being completely removed in subsequent processes due to the excessive depth of the first hole 14.

[0077] In practice, one or more of the following processes can be used to form the mask layer 15: physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). The material of the mask layer 15 can include oxides, nitrides, or carbon. The first opening 151 and the second opening 152 can be formed by patterning the mask layer 15 using photolithography and etching processes. The first word line material layer 13 can be etched using dry etching or wet etching, such as plasma etching, laser etching, or chemical etching. The etching causes the upper surface of the first word line material layer 13 located in the second partition 102 to drop by a predetermined distance. Here, the predetermined distance can be in the range of 50nm-100nm, including endpoint values, such as 60nm, 75nm, 85nm, or 90nm. Within this range, on the one hand, there is enough space to form a hybrid gate to alleviate the GIDL effect, and on the other hand, the thickness of the remaining first word line material layer 13 can be guaranteed, thereby ensuring the performance of the semiconductor structure.

[0078] In some embodiments, see Appendix Figure 2d The etching process also includes controlling the etching parameters to make the bottom contour of the first hole 14 curved.

[0079] Since the bottom of the subsequently formed contact structure 19 is filled in the first hole 14, when the outline of the bottom of the first hole 14 is curved, compared with the flat outline, the transition of the contact surface between the contact structure 19 and the first letter line material layer 13 from the side of the contact structure 19 to the bottom of the contact structure 19 is relatively gentle, so as to avoid the problem of device performance degradation caused by sharp corners of the contact surface leading to tip discharge and breakdown.

[0080] In practice, the etching rate can be controlled by adjusting etching parameters such as the type of etching gas, gas flow rate and velocity, etching time, temperature, and pressure. This improves the controllability of the etching process and makes the bottom contour of the first hole 14 curved. In some specific embodiments, the radius of curvature of the bottom surface of the first hole 14 can be in the range of 10nm-20nm, including endpoint values, such as 12nm, 15nm, 17nm, or 19mm. Within this range, on the one hand, the transition of the contact surface between the contact structure 19 and the first word line material layer 13 in the first hole 14 from the side to the bottom is relatively smooth to avoid the problem of sharp corners causing tip discharge and breakdown, which leads to device performance degradation. On the other hand, it can avoid the problem of voids and other defects that may easily appear at the bottom when depositing material of the contact structure 19 due to excessive curvature of the bottom surface of the first hole 14. This ensures the stability of the electrical connection between the contact structure 19 and the first word line material layer 13.

[0081] In some specific embodiments, see the appendix. Figure 2d After etching the first letter line material layer 13, the mask layer 15 is removed. Specifically, the mask layer 15 can be removed using ashing, etching, or chemical mechanical polishing processes.

[0082] In some embodiments, see Appendix Figure 2e and attached Figure 2f After the etching process, the process further includes: forming a second word line material layer 16, which fills the first hole 14 and covers the first word line layer 131 (the remaining first word line material layer 13 after the etching process is defined as the first word line layer 131) (see Appendix). Figure 2e The second character line material layer 16 is etched to remove the second character line material layer 16 located in the first partition 101. The remaining second character line material layer 16 located in the second partition 102 is defined as the second character line layer 161. The upper surface of the second character line layer 161 is lower than the upper surface of the first character line layer 131 located in the first partition 101 (see Appendix). Figure 2f ).

[0083] The first word line layer 131 is typically a low-resistance metal layer. A second word line layer 161, such as a semiconductor layer, is then formed on top of it, together constituting the word line. This keeps the metal layer as far away as possible from areas prone to the GIDL effect, thereby reducing the GIDL effect and improving the reliability of the semiconductor device. Furthermore, the second word line layer 161 is only present in the second partition 102, while the first word line layer 131 in the first partition 101 is thicker. Because the first word line layer 131 includes a low-resistance metal material, the overall resistance of the word line is reduced, resulting in higher semiconductor device performance.

[0084] In practice, one or more of the following processes can be used to form the second word line material layer 16: physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). The second word line material layer 16 can be, but is not limited to, semiconductors or compounds containing semiconductors. The second word line material layer 16 can be etched using dry etching or wet etching.

[0085] In some specific embodiments, the first word line layer 131 may include tungsten metal, because tungsten metal has low resistance. The work function of the second word line layer 161 is less than that of the first word line layer 131. Here, the second word line layer 161 may include germanium silicon, monocrystalline silicon, or polycrystalline silicon, etc. Preferably, the second word line layer 161 may include polycrystalline silicon, because polycrystalline silicon can be easily modified by doping with impurities of different polarities.

[0086] The work function of the second word line layer 161 is less than that of the first word line layer 131. For example, the word line is composed of a tungsten metal layer and a polysilicon layer with a work function lower than that of tungsten metal. As a hybrid gate of the transistor, it can improve the electric field distribution in the overlapping region of the gate and the source / drain region. Therefore, it can combine the advantages of metal gate and polysilicon gate. While ensuring that the gate has a low resistance value, it can also reduce the leakage current in the overlapping region of the gate and the source / drain region, better alleviate the GIDL effect, and further improve the performance and reliability of the semiconductor device.

[0087] In some embodiments, see Appendix Figure 2g After forming the second letter line layer 161, the method further includes: forming an isolation layer 17, the isolation layer 17 filling the first trench 11 and covering the first letter line layer 131 and the second letter line layer 161; the upper surface of the isolation layer 17 is flush with the upper surface of the substrate 10.

[0088] The isolation layer 17 is used to isolate the embedded letter lines. Its upper surface is flush with the upper surface of the substrate 10, which facilitates the subsequent manufacturing process. Since the upper surface of the second letter line layer 161 is lower than the upper surface of the first letter line layer 131 located in the first partition 101, the isolation layer thickness of the first partition 101 is smaller, which reduces the difficulty of the subsequent process of forming the second hole 18.

[0089] In practice, the isolation layer 17 can be formed by one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) processes. The material of the isolation layer 17 may include one or more of silicon nitride, silicon oxide, or silicon oxynitride.

[0090] In some embodiments, see Appendix Figure 2h and attached Figure 3After forming the isolation layer 17, the process further includes: etching the isolation layer 17 to form a second hole 18, the second hole 18 being connected to the first hole 14, and then removing the isolation layer 17 located within the first hole 14 (see appendix). Figure 2h Contact structure 19 is formed within the second hole 18 and the first hole 14 (see appendix). Figure 3 ).

[0091] Because the isolation layer 17 located in the first partition 101 has a small thickness, problems such as poor fabrication caused by the difficulty in forming the second hole 18 with a high aspect ratio can be avoided. In addition, the bottom of the contact structure 19 is located inside the first hole 14, directly contacting the first word line layer 131, and has a large contact area, resulting in low contact resistance and good connection stability between the two, which is beneficial to the improvement of semiconductor device performance.

[0092] In practice, the etching of the isolation layer 17 can be performed using dry etching, such as plasma etching. The contact structure 19 can be formed using one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) processes. The material of the contact structure 19 can include any combination of one or more of the following metallic materials: tungsten, copper, aluminum, titanium, tantalum, silver, tantalum nitride, and titanium nitride.

[0093] In some embodiments, see Appendix Figure 3 After forming the contact structure 19, the process also includes forming a metal layer 20, which is connected to the upper end of the contact structure 19.

[0094] The upper end of the contact structure 19 is connected to the word line driver through the metal layer 20, and the lower end of the contact structure 19 is connected to the word line, thereby facilitating the word line driver to input voltage signals into the word line to control the transistor to turn on or off.

[0095] In practice, firstly, one or more of the physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) processes can be used to form a metal material layer. Then, the metal material layer is etched to form a metal layer 20. The material of the metal layer 20 includes, but is not limited to, metallic materials, such as tungsten, copper, aluminum, titanium, tantalum, silver, tantalum nitride, and titanium nitride, or any combination of one or more of these.

[0096] This disclosure also provides a semiconductor structure; please refer to the appendix for details. Figure 3 As shown in the figure, the semiconductor structure includes:

[0097] Base 10, which includes a first partition 101 and a second partition 102;

[0098] A first trench 11 is located within the base 10, and the first trench 11 passes through the first partition 101 and the second partition 102;

[0099] A gate dielectric layer 12 covering the inner surface of the first trench 11;

[0100] A first word line layer 131 covering the gate dielectric layer 12 and filling the first trench 11, wherein the upper surface of the first word line layer 131 located above the first partition 101 is higher than the upper surface of the first word line layer 131 located in the second partition 102.

[0101] The contact structure 19 is located in the first partition 101, and the bottom of the contact structure 19 extends into the first word line layer 131.

[0102] The upper surface of the first word line layer 131 located in the second partition 102 is lower to reserve space above it for forming a hybrid gate, thereby mitigating the gate-induced drain leakage (GIDL) effect, increasing saturation current, and improving the reliability of the semiconductor device. The bottom of the contact structure 19 extends into the first word line layer 131, allowing the contact structure 19 and the first word line layer 131 to make direct contact and effectively increasing the contact area, which can better reduce contact resistance and improve the connection stability between the two.

[0103] In practice, the substrate 10 can be, but is not limited to, a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. In some specific embodiments, the substrate 10 includes a doped or undoped silicon substrate, wherein the second partition 102 of the substrate 10 may include a plurality of arrayed active regions 103, adjacent active regions 103 are isolated by an isolation structure (not shown), serving as an array region of memory cells; the first partition 101 can serve as the peripheral region of the memory cells, used to connect external control circuits and other components. The first partition 101 and the second partition 102 can be arranged adjacently side by side, or the first partition 101 can surround the outer periphery of the second partition 102, without specific limitations. The material of the gate dielectric layer 12 can be, but is not limited to, silicon dioxide, silicon monoxide, hafnium oxide, or titanium oxide, etc. The materials of the first word line layer 131 and the contact structure 19 may include, but are not limited to, metallic materials, such as one or more of tungsten, copper, aluminum, titanium, tantalum, silver, tantalum nitride, and titanium nitride, or any combination thereof.

[0104] In some other embodiments, a metal barrier layer may also be included between the first word line layer 131 and the gate dielectric layer 12, wherein the material of the metal barrier layer may include, but is not limited to, one or a combination of titanium or titanium nitride.

[0105] The metal barrier layer has good diffusion blocking properties, good stability at high temperatures, resistance to corrosion and oxidation, good contact with both semiconductors and metals, high electrical conductivity and low ohmic contact resistance. When the material of the first word line layer 131 includes a metal material, such as tungsten, the metal barrier layer can prevent the tungsten in the first word line layer 131 from diffusing into the gate dielectric layer 12, so as to avoid affecting the performance of the semiconductor device.

[0106] In some embodiments, see Appendix Figure 3 The bottom surface of contact structure 19 is curved.

[0107] In practice, the radius of curvature of the bottom surface of the contact structure 19 can range from 10nm to 20nm, including endpoint values, such as 12nm, 15nm, 17nm, or 19mm. Within this range, on the one hand, the transition of the contact surface between the contact structure 19 and the first word line layer 131 from the side to the bottom of the contact structure 19 can be relatively smooth, so as to avoid the problem of sharp corners of the contact surface causing tip discharge and breakdown, which would lead to device performance degradation. On the other hand, in the actual process, it can avoid the problem of defects such as voids in the bottom material that may occur when the bottom curvature of the contact structure 19 is too large, thereby ensuring the stability of the electrical connection between the contact structure 19 and the first word line layer 131.

[0108] In some embodiments, along a direction perpendicular to the upper surface of the substrate 10, the ratio of the thickness of the first word line layer 131 in the first partition 101 to the thickness of the first word line layer 131 in the second partition 102 is greater than 1.5, for example, it can be 1.8, 2, 2.5, or 3. This ensures sufficient space above the first word line layer 131 in the second partition 102, facilitating the subsequent formation of a hybrid gate comprising multiple layers of material with different work functions to better mitigate the GIDL effect; on the other hand, it ensures that the first word line layer 131 in the first partition 101 has sufficient thickness, allowing for a wider range of choices in the size of the contact structure 19 formed subsequently within the first word line layer 131.

[0109] In some embodiments, see Appendix Figure 3The contact structure 19 includes a contact portion 191 located within the first word line layer 131. The contact portion 191 has a depth H perpendicular to the upper surface of the substrate 10 and a width W parallel to the upper surface of the substrate 10. Here, the aspect ratio of the contact portion 191 can be defined as the ratio of its depth H to its width W. When the aspect ratio of the contact portion 191 is small, the depth H of the contact portion 191 is relatively small, thus its effect on reducing the contact resistance between the contact structure 19 and the first word line layer 131 and increasing the stability of their connection is relatively limited. When the aspect ratio of the contact portion 191 is large, in actual manufacturing processes, the high aspect ratio may easily lead to manufacturing defects. For example, when etching away the insulating layer material in the first hole with a high aspect ratio, some residue may remain, and when depositing conductive material in the first hole with a high aspect ratio to form the contact portion 191, voids and other defects may easily appear inside, thus affecting the stability of the electrical connection between the contact structure 19 and the first word line layer 131. Therefore, in actual operation, the aspect ratio of the contact sub-section 191 can be controlled within the range of 0.7-1.65, including endpoint values, such as 0.8, 1.0, 1.2, or 1.5. This effectively reduces the contact resistance between the contact structure 19 and the first word line layer 131 while ensuring the stability of the electrical connection between them.

[0110] In some embodiments, see Appendix Figure 4 There are at least two contact sub-parts 191.

[0111] In actual process, at least two first holes can be formed on the first word line layer 131 of the first partition 101 in one etching step. The final contact structure 19, which is filled in the first holes, includes at least two contact sub-parts 191. This can increase the contact area between the contact structure 19 and the first word line layer 131 by a factor of two, which can more effectively reduce the contact resistance and further increase the connection stability between the two, so as to better improve the performance of the semiconductor device.

[0112] The number of contact sub-parts 191 shown in the above embodiment is two. In some other embodiments, the contact structure 19 may include three or more contact sub-parts 191, which can be set according to actual needs to further reduce the contact resistance between the first word line layer 131 and the contact structure 19 and further increase the connection stability between the two.

[0113] In some embodiments, see Appendix Figure 3 The bottom of the contact structure 19 is higher than the upper surface of the first word line layer 131 located in the second partition 102.

[0114] The higher bottom of the contact structure 19 is a result of the etching load effect during the actual formation of the first word line layer 131. Specifically, in the actual process, through a one-step etching process, the upper surface of the first word line layer 131 located in the second partition 102 is lowered by a predetermined distance, and a first hole is formed on the upper surface of the first word line layer 131 in the first partition 101, with the bottom of the contact structure 19 located within the first hole. In some specific embodiments, the ratio of the area of ​​the upper surface of the first word line layer 131 in the second partition 102 to the area of ​​the cross-section of the contact structure 19 at the upper surface of the first word line layer 131 is 2 × 10⁻⁶. 6 Up to 5×10 6 This includes endpoint values, for example, 2.5 × 10⁻⁶. 6 3×10 6 3.5×10 6 Or 4.5×10 6 Within this range, on the one hand, the current distribution in the actual etching process is more uniform, which helps to reduce heat generation and improve the controllability of etching; on the other hand, the etching rate of the first word line layer 131 exposed in the second partition 102 and the etching rate of the first word line layer 131 exposed in the first partition 101 are within a suitable range, so that the upper surface of the first word line material layer 13 in the second partition 102 drops a large distance, which can reserve enough space for subsequent processes to form a hybrid gate, thereby mitigating the GIDL effect. At the same time, the depth of the first hole is moderate, which can effectively increase the contact area between the contact structure 19 filled in the first hole and the first word line layer 131 in the subsequent process, while avoiding problems such as poor contact between the contact structure 19 and the first word line layer 131 caused by the isolation layer in the hole not being completely removed in the actual process due to the excessive depth of the first hole.

[0115] In some embodiments, see Appendix Figure 3 The semiconductor structure also includes a second word line layer 161, which covers the first word line layer 131 located in the second partition 102, wherein the upper surface of the second word line layer 161 is lower than the upper surface of the first word line layer 131 located in the first partition 101.

[0116] The first word line layer 131 can generally be a low-resistance metal layer. The second word line layer 161 above it, such as a semiconductor layer, can together form the word line, keeping the metal layer as far away as possible from the region prone to GIDL effect, thereby reducing the GIDL effect and improving the reliability of the semiconductor device. In addition, the second word line layer 161 is only in the second partition 102, and the first word line layer 131 in the first partition 101 is thicker. Because the first word line layer 131 includes a low-resistance metal material, the overall resistance of the word line can be reduced, resulting in higher performance of the semiconductor device.

[0117] In practice, the second word line material layer 16 may include, but is not limited to, semiconductors or compounds containing semiconductors. In some specific embodiments, the first word line layer 131 may include tungsten metal, as tungsten metal has low resistance, wherein the work function of the second word line layer 161 is less than that of the first word line layer 131. Here, the second word line layer 161 may include, for example, germanium silicon, monocrystalline silicon, or polycrystalline silicon. Preferably, the second word line layer 161 may include polycrystalline silicon, because polycrystalline silicon can be easily modified by doping with impurities of different polarities.

[0118] The work function of the second word line layer 161 is less than that of the first word line layer 131. For example, the word line is composed of a tungsten metal layer and a polysilicon layer with a work function lower than that of tungsten metal. As a hybrid gate of the transistor, it can improve the electric field distribution in the overlapping region of the gate and the source / drain region. Therefore, it can combine the advantages of metal gate and polysilicon gate. While ensuring that the gate has a low resistance value, it can also reduce the leakage current in the overlapping region of the gate and the source / drain region, better alleviate the GIDL effect, and further improve the performance and reliability of the semiconductor device.

[0119] In some embodiments, see Appendix Figure 3 The semiconductor structure also includes an isolation layer 17, which covers the second word line layer 161 and the first word line layer 131, and the upper surface of the isolation layer 17 is flush with the upper surface of the substrate 10.

[0120] The isolation layer 17 is used to isolate the embedded letter lines. Its upper surface is flush with the upper surface of the base 10, which facilitates the continued fabrication of other components on top in the actual process.

[0121] In practice, the material of the isolation layer 17 may include one or more of silicon nitride, silicon oxide, or silicon oxynitride.

[0122] In some embodiments, see Appendix Figure 3 The semiconductor structure also includes a metal layer 20, which is connected to the upper end of the contact structure 19.

[0123] The upper end of the contact structure 19 is connected to the word line driver through the metal layer 20, and the lower end of the contact structure 19 is connected to the word line, thereby facilitating the word line driver to input voltage signals into the word line to control the transistor to turn on or off.

[0124] In practice, the material of the metal layer 20 includes, but is not limited to, metallic materials, such as one or more of tungsten, copper, aluminum, titanium, tantalum, silver, tantalum nitride, and titanium nitride, or any combination thereof.

[0125] In summary, this disclosure first forms a first trench 11 passing through the first partition 101 and the second partition 102 within the substrate 10. Then, a gate dielectric layer 12 and a first word line material layer 13 covering the gate dielectric layer 12 and filling the first trench 11 are formed on the inner surface of the first trench 11. Next, the first word line material layer 13 is etched to lower the upper surface of the first word line material layer 13 in the second partition 102 by a predetermined distance. This facilitates the subsequent deposition of other conductive layers above the first word line material layer 13 in the second partition 102 to form a hybrid gate, thereby mitigating the gate-induced drain leakage (GIDL) effect, increasing the saturation current, and improving the reliability of the semiconductor device. Simultaneously, a first via 14 is formed on the first word line material layer 13 in the first partition 101, allowing the contact structure 19 subsequently formed on the first partition 101 to fill the first via 14. This enables direct contact between the contact structure 19 and the first word line layer 131, effectively increasing the contact area, which can better reduce contact resistance, enhance the connection stability between the two, and thus improve the performance of the semiconductor device. In this disclosure, different etching purposes are simultaneously completed in the first partition 101 and the second partition 102 of the substrate 10 through a one-step etching process, which simplifies the process and results in a semiconductor device with higher overall performance.

[0126] It should be noted that the semiconductor structure manufacturing method and semiconductor structure provided in this disclosure can be applied to any integrated circuit including such a structure, such as dynamic random access memory (DRAM). The technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0127] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first partition and a second partition; A first trench is formed within the substrate, the first trench passing through the first partition and the second partition; A gate dielectric layer is formed covering the inner surface of the first trench; A first word line material layer is formed, which covers the gate dielectric layer and fills the first trench; An etching process is performed to etch the first character line material layer, causing the upper surface of the first character line material layer located in the second partition to drop by a predetermined distance, while simultaneously forming a first hole in the first character line material layer located in the first partition; After the etching process is performed, the remaining first word line material layer is defined as the first word line layer, and the method further includes: A second word line material layer is formed, which fills the first hole and covers the first word line layer; The second word line material layer is etched to remove the second word line material layer located in the first partition. The remaining second word line material layer located in the second partition is defined as the second word line layer. The upper surface of the second word line layer is lower than the upper surface of the first word line layer located in the first partition. The upper surface of the first word line layer located above the first partition is higher than the upper surface of the first word line layer located in the second partition.

2. The method according to claim 1, characterized in that, Performing the etching process includes: A mask layer is formed on the first word line material layer; The mask layer is patterned to form a first opening in the first partition and a second opening in the second partition, wherein the area of ​​the second opening is larger than the area of ​​the first opening; Using the mask layer as a barrier, the first word line material layer is etched to form the first hole and cause the upper surface of the first word line material layer located in the second partition to drop by a predetermined distance, wherein the etching rate of the first word line material layer exposed to the first opening is less than the etching rate of the first word line material layer exposed to the second opening.

3. The method according to claim 1, characterized in that, Performing the etching process also includes: By controlling the etching parameters, the contour of the bottom of the first hole is made into a curved shape.

4. The method according to claim 1, characterized in that, After forming the second word line layer, the method further includes: An isolation layer is formed, which fills the first trench and covers the first letter line layer and the second letter line layer; the upper surface of the isolation layer is flush with the upper surface of the substrate.

5. The method according to claim 4, characterized in that, After forming the isolation layer, the method further includes: The isolation layer is etched to form a second hole, which is connected to the first hole, and the isolation layer located in the first hole is removed. A contact structure is formed in the second hole and the first hole.

6. A semiconductor structure, characterized in that, include: The substrate includes a first partition and a second partition; A first trench located within the substrate, the first trench passing through the first partition and the second partition; A gate dielectric layer covering the inner surface of the first trench; A first word line layer covering the gate dielectric layer and filling the first trench, wherein the upper surface of the first word line layer located above the first partition is higher than the upper surface of the first word line layer located in the second partition; A contact structure located in the first partition, the bottom of which extends into the first word line layer; The bottom surface of the contact structure is curved.

7. The semiconductor structure according to claim 6, characterized in that, Along a direction perpendicular to the upper surface of the substrate, the ratio of the thickness of the first word line layer in the first partition to the thickness of the first word line layer in the second partition is greater than 1.5; and / or, The contact structure includes a contact sub-part located within the first letter line layer; the aspect ratio of the contact sub-part ranges from 0.7 to 1.65; and / or, The bottom of the contact structure is higher than the upper surface of the first word line layer located in the second partition; And / or, The ratio of the area of ​​the upper surface of the first word line layer located in the second partition to the area of ​​the cross-section of the contact structure at the upper surface of the first word line layer is 2×106 to 5×106.

8. The semiconductor structure according to claim 6, characterized in that, The semiconductor structure also includes: A second word line layer covers the first word line layer located in the second partition, wherein the upper surface of the second word line layer is lower than the upper surface of the first word line layer located in the first partition.

9. The semiconductor structure according to claim 8, characterized in that, The work function of the second word line layer is less than the work function of the first word line layer.

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