A method of forming a semiconductor structure

Abstract

The application discloses a forming method of a semiconductor structure. Based on the effect of load, the larger the opening size in a patterned layer is, the larger the opening depth formed in an interlayer dielectric layer is, so that a first opening and a second opening with different depths can be formed in the interlayer dielectric layer. Since the capacitance of a capacitor is related to the area of an electrode plate, the distance between electrode plates and the dielectric constant of a dielectric material between the electrode plates, the capacitor with different capacitance values can be obtained by obtaining the first opening and the second opening with different sizes and selecting the dielectric constant of the dielectric material filled in the first opening and the second opening. Since the first opening and the second opening adopt the same patterned layer as a mask and the patterned layer is formed by using a photoetching process only once, the capacitor with different capacitance values can be obtained without multiple photoetching, which is beneficial to saving production cost and promoting the development of capacitor production technology.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] Metal-Insulator-Metal (MIM) capacitors are widely used in integrated circuit chips for charge storage, voltage control, and radio frequency control. MIM capacitors can be integrated into back-end metal interconnect processes and are highly compatible with downstream semiconductor manufacturing processes.

[0003] With the development of integrated circuits, the demand for capacitors has become more diversified. In existing manufacturing technologies, to produce MIM capacitors with different capacitance values, each capacitor requires photolithography and etching steps, resulting in high manufacturing costs.

[0004] Figures 1-3 The paper presents a method for fabricating MIM capacitors with different capacitance values ​​in the prior art. In this method of forming a semiconductor structure, the two capacitors are processed sequentially step by step.

[0005] Please refer to Figure 1 A substrate (not shown) is provided, the substrate having a first conductive layer 101 and exposing the top surface of the first conductive layer 101; an interlayer dielectric layer 102 is formed on the substrate; a first mask layer 103 is formed on the surface of the interlayer dielectric layer 102, the first mask layer 103 exposing a portion of the interlayer dielectric layer 102; the interlayer dielectric layer 102 is etched using the first mask layer 103 as a mask to form a first opening 104 in the interlayer dielectric layer 102; the first mask layer 103 is removed.

[0006] Please refer to Figure 2 A second mask layer 105 is formed on the surface of the first opening 104 and the interlayer dielectric layer 102, the second mask layer 105 exposing a portion of the interlayer dielectric layer 102; using the second mask layer 105 as a mask, the interlayer dielectric layer 102 is etched until the substrate surface is exposed, forming a second opening 106 in the interlayer dielectric layer 102, the first opening 104 and the second opening 106 having different sizes; the second mask layer 105 is removed, exposing the sidewalls and bottom surface of the first opening 104.

[0007] Please refer to Figure 3Dielectric material is deposited in the first opening 104 and the second opening 106 to form a first capacitor dielectric layer 107 with the dielectric material in the first opening 104 and a second capacitor dielectric layer 108 with the dielectric material in the second opening 106; a second conductive layer 109 is formed on the surface of the interlayer dielectric layer 102, the first capacitor dielectric layer 107 and the second capacitor dielectric layer 108.

[0008] The above method is used to form capacitor devices with different capacitance values. Specifically, capacitor devices with different capacitance values ​​are obtained by forming a first opening 104 and a second opening 106 of different sizes, and by filling the first opening 104 and the second opening 106 with a dielectric material having a different dielectric constant value than the interlayer dielectric layer.

[0009] However, in the above method, since the first opening 104 and the second opening 106 have different sizes, two different photolithography and etching processes are required to obtain them, which increases the production cost and is not conducive to the development of semiconductor technology.

[0010] Therefore, the existing manufacturing technology for metal-insulator-metal capacitors needs further improvement. Summary of the Invention

[0011] To address the aforementioned problems, this invention provides a method for forming a semiconductor structure. Since the sizes of the first and second patterned openings are different, during plasma etching, due to the loading effect, the larger the opening size within the patterned layer, the greater the opening depth formed within the interlayer dielectric layer. Therefore, first and second openings of different depths can be formed within the interlayer dielectric layer. Because the capacitance of a capacitor is related to the plate area, plate spacing, and dielectric constant of the interlayer dielectric material, capacitors with different capacitance values ​​can be obtained by acquiring first and second openings of different sizes and by selecting the dielectric constant of the dielectric material filling the first and second openings. Since the first and second openings use the same patterned layer as a mask, and the patterned layer is formed using only a single photolithography etching process, capacitors with different capacitance values ​​can be obtained without multiple photolithography steps, which helps save production costs and promotes the development of capacitor manufacturing technology.

[0012] A method for forming a semiconductor structure includes the following steps:

[0013] (1) A substrate is provided having a first conductive layer therein, the substrate exposing a top surface of the first conductive layer;

[0014] (2) An interlayer dielectric layer and a patterned layer located on the surface of the interlayer dielectric layer are formed on the substrate, wherein the material of the interlayer dielectric layer and the material of the patterned layer are different; the patterned layer has a first patterned opening and a second patterned opening of different sizes, and the surface of the interlayer dielectric layer is exposed at the first patterned opening and the second patterned opening.

[0015] (3) The interlayer dielectric layer is etched using the patterned layer as a mask, a first opening is formed in the interlayer dielectric layer at the opening corresponding to the first pattern, and a second opening is formed in the interlayer dielectric layer at the opening corresponding to the second pattern, wherein the depths of the first opening and the second opening are different.

[0016] (4) Remove the graphical layer;

[0017] (5) A first capacitor dielectric layer is formed in the first opening, and a second capacitor dielectric layer is formed in the second opening. The materials of the first capacitor dielectric layer and the second capacitor dielectric layer are different from those of the interlayer dielectric layer.

[0018] (6) A second conductive layer is formed on the surface of the interlayer dielectric layer, the first capacitor dielectric layer and the second capacitor dielectric layer.

[0019] Preferably, the method for forming the semiconductor structure further includes patterning the second conductive layer after step (6) to form a first electrode plate and a second electrode plate that are isolated from each other, wherein the first electrode plate and the second electrode plate are respectively located on the first capacitor dielectric layer and the second capacitor dielectric layer.

[0020] Preferably, the width ratio of the first graphic opening and the second graphic opening is 1:4 to 6, and the depth ratio of the first opening and the second opening is the same as the width ratio of the first graphic opening and the second graphic opening.

[0021] Preferably, in step (3), the etching process is plasma etching, wet etching, or ion milling. More preferably, the etching gas used in the plasma etching process is at least one of chlorine-based gas and fluorine-based gas. The chlorine-based gas can be carbon tetrachloride or chlorine, and the fluorine-based gas can be carbon tetrafluoride or trifluoromethane. More preferably, the process parameters of the plasma etching process are: the etching gas includes fluorine-based gas and argon, the volume percentage of argon in the etching gas is in the range of 2% to 5%, the radio frequency power is in the range of 2 to 9 kW, the plasma electron temperature is in the range of 1 to 10 eV, and the plasma density is in the range of 10 eV. 15 ~10 18 pcs / m 3 The ionization rate ranges from 10. -7 ~10 -4 .

[0022] Preferably, in step (2), the method for forming the patterned layer includes: forming a patterned material layer on the surface of the interlayer dielectric layer, forming a mask layer on a portion of the surface of the patterned material layer, and using the mask layer as a mask to etch the patterned material layer to form the patterned layer.

[0023] Preferably, the method for forming the first capacitor dielectric layer and the second capacitor dielectric layer includes: forming a capacitor dielectric material layer on the surface of the first opening, the second opening, and the interlayer dielectric layer; planarizing the capacitor dielectric material layer until the surface of the interlayer dielectric layer is exposed. Optionally, the material of the capacitor dielectric material layer includes a high-k dielectric material.

[0024] Preferably, the material of the interlayer dielectric layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, and silicon carbonitride; the material of the patterning layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, and silicon carbonitride.

[0025] Preferably, the projection of the first patterned opening onto the substrate surface is a rectangle or a circle; the projection of the second patterned opening onto the substrate surface is a rectangle or a circle.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] In the semiconductor structure formation method provided by this invention, since the sizes of the first and second patterned openings are different, during plasma etching, due to the loading effect, the larger the opening size in the patterned layer, the greater the opening depth formed in the interlayer dielectric layer. Therefore, first and second openings of different depths can be formed in the interlayer dielectric layer. Since the capacitance of a capacitor is related to the plate area, plate spacing, and dielectric constant of the interlayer dielectric material, capacitors with different capacitance values ​​can be obtained by acquiring first and second openings of different sizes and by selecting the dielectric constant of the dielectric material filling the first and second openings. Since the first and second openings use the same patterned layer as a mask, the patterned layer is formed using only one photolithography etching process. Therefore, capacitors with different capacitance values ​​can be obtained without multiple photolithography steps, which helps save production costs and promotes the development of capacitor manufacturing technology. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the structure for forming the first opening in a conventional semiconductor structure formation method.

[0029] Figure 2 This is a schematic diagram of the structure for forming a second opening in a conventional semiconductor structure formation method.

[0030] Figure 3 This is a schematic diagram of the deposition of dielectric material and the formation of the second conductive layer in the existing semiconductor structure formation method.

[0031] Figure 4 This is a schematic diagram of the structure of the first conductive layer in the semiconductor structure formation method of the present invention.

[0032] Figure 5 This is a schematic diagram of the semiconductor structure formation method of the present invention, which involves forming an interlayer dielectric layer and a patterned layer on a substrate.

[0033] Figure 6 This is a schematic diagram of the structure for forming the first opening and the second opening in the semiconductor structure formation method of the present invention.

[0034] Figure 7 This is a schematic diagram of the semiconductor structure after the patterning layer is removed in the semiconductor structure formation method of the present invention.

[0035] Figure 8 This is a schematic diagram of the structure of the semiconductor structure formed in the method of forming the first capacitor dielectric layer, the second capacitor dielectric layer, and the second conductive layer of the present invention.

[0036] Figure 9 This is a schematic diagram of the patterned second conductive layer in the semiconductor structure formation method of the present invention. Detailed Implementation

[0037] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0038] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Figures 4 to 9 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0040] Please refer to Figure 4 A substrate (not shown) is provided, wherein the substrate has a first conductive layer 201 and the top surface of the first conductive layer 201 is exposed.

[0041] In this embodiment, the substrate further includes a substrate (not shown in the figure), a device layer (not shown in the figure) located on the substrate, and a dielectric layer (not shown in the figure) located on the surface of the substrate and the device layer. The device layer includes an isolation structure (not shown in the figure) and a device structure (not shown in the figure) located within the isolation structure. The device structure includes transistors, diodes, triodes, capacitors, inductors, or conductive structures, etc.

[0042] Please refer to Figure 5 An interlayer dielectric layer 202 and a patterned layer 203 located on the surface of the interlayer dielectric layer 202 are formed on the substrate. The patterned layer 203 has a first patterned opening 204 and a second patterned opening 205. The first patterned opening 204 and the second patterned opening 205 expose the surface of the interlayer dielectric layer 203, and the first patterned opening 204 and the second patterned opening 205 have different sizes.

[0043] In this embodiment, the first patterned opening 204 has a first width, and the second patterned opening 205 has a second width. The ratio of the first width to the second width ranges from 1:4 to 1:6. The width refers to the dimension in the direction parallel to the substrate surface.

[0044] The projection of the first patterned opening 204 onto the substrate surface is rectangular or circular; the projection of the second patterned opening 205 onto the substrate surface is also rectangular or circular. In this embodiment, the projection of both the first patterned opening 204 and the second patterned opening 205 onto the substrate surface is rectangular.

[0045] Please refer to Figure 6 Using the patterned layer 203 as a mask, the interlayer dielectric layer 202 is etched to form a first opening 206 and a second opening 207 within the interlayer dielectric layer 202. The first opening 206 is located at the bottom of the first patterned opening 204, and the second opening 207 is located at the bottom of the second patterned opening 205. The depths of the first opening 206 and the second opening 207 are different.

[0046] Because the first patterned opening 204 and the second patterned opening 205 have different sizes, during plasma etching, due to the loading effect, the larger the opening size in the patterned layer 203, the greater the opening depth formed in the interlayer dielectric layer 202. Therefore, first openings 206 and second openings 207 of different depths can be formed in the interlayer dielectric layer 202. Since the capacitance of a capacitor is related to the plate area, plate spacing, and dielectric constant of the interlayer dielectric material, capacitors with different capacitance values ​​can be obtained by obtaining first openings 206 and second openings 207 of different sizes and by selecting the dielectric constant of the dielectric material filling the first openings 206 and second openings 207. Since the first openings 206 and second openings 207 use the same patterned layer as a mask, the patterned layer is formed in only one photolithography etching process. Therefore, capacitors with different capacitance values ​​can be obtained without multiple photolithography processes, which helps to save production costs and promotes the development of capacitor manufacturing technology.

[0047] In this embodiment, the first opening 206 has a first depth, the second opening 207 has a second depth, and the ratio of the first depth to the second depth is in the range of 1:4 to 1:6.

[0048] In this embodiment, the bottom of the second opening 207 exposes the top surface of the interlayer dielectric layer 201.

[0049] In this embodiment, the process of etching the interlayer dielectric layer 202 using the patterned layer 203 as a mask includes a plasma etching process.

[0050] In this embodiment, the etching gas used in the plasma etching process includes chlorine-based gas or fluorine-based gas.

[0051] In this embodiment, the process parameters of the plasma etching process include: the etching gas includes fluorine-based gas and argon, the proportion of argon in the etching gas ranges from 2% to 5%, the radio frequency power ranges from 2kW to 9kW, the plasma electron temperature ranges from 1eV to 10eV, and the plasma density ranges from 10... 15 ~10 18 pcs / m 3 (atom / m 3 ), with an ionization rate range of 10. -7 Up to 10 -4 Specifically, the fluorine-based gas can be SF6 or CF4.

[0052] The patterned layer 203 and the interlayer dielectric layer 202 are made of different materials.

[0053] The material of the interlayer dielectric layer 202 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, and silicon carbonitride; the material of the patterning layer 203 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, and silicon carbonitride.

[0054] In this embodiment, the patterning layer 203 is made of silicon oxide; the interlayer dielectric layer 202 is made of nitrogen oxycarbonate (NDC).

[0055] In this embodiment, the material of the interlayer dielectric layer 202 is a low-k dielectric material. The low-k dielectric material refers to a dielectric material with a dielectric constant value less than 3.9.

[0056] The method for forming the patterned layer 203 includes: forming a patterned material layer (not shown in the figure) on the surface of the interlayer dielectric layer 202; forming a mask layer (not shown in the figure) on a portion of the surface of the patterned material layer; and etching the patterned material layer using the mask layer as a mask to form the patterned layer 203.

[0057] In this embodiment, the material of the mask layer includes photoresist. In the etching process of the patterned material layer, selecting an etching process with a large etching selectivity between the patterned material layer and the interlayer dielectric layer 202 helps to reduce etching damage to the interlayer dielectric layer 202 during the etching process.

[0058] In this embodiment, before forming the first capacitor dielectric layer and the second capacitor dielectric layer, please refer to... Figure 7 .

[0059] Please refer to Figure 7 Remove the graphical layer 203.

[0060] The process for removing the patterned layer 203 includes one or both of dry etching and wet etching processes.

[0061] In this embodiment, the process for removing the patterned layer 203 is a wet etching process.

[0062] Please refer to Figure 8 A first capacitor dielectric layer 208 is formed in the first opening 206, and the first capacitor dielectric layer 208 is made of a different material than the interlayer dielectric layer 202; a second capacitor dielectric layer 209 is formed in the second opening 207, and the second capacitor dielectric layer 209 is made of a different material than the interlayer dielectric layer 202.

[0063] In this embodiment, the method for forming the first capacitor dielectric layer 208 and the second capacitor dielectric layer 209 includes: forming a capacitor dielectric material layer (not shown in the figure) on the surface of the first opening 206, the second opening 207 and the interlayer dielectric layer 202; planarizing the capacitor dielectric material layer until the surface of the interlayer dielectric layer 202 is exposed.

[0064] In this embodiment, the capacitor dielectric material layer is made of a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a dielectric constant greater than 3.9.

[0065] Please refer to Figure 8 A second conductive layer 210 is formed on the surface of the interlayer dielectric layer 202, the first capacitor dielectric layer 208 and the second capacitor dielectric layer 209.

[0066] The material of the second conductive layer 210 includes metal. The first conductive layer 201 and the second conductive layer 210 respectively form the two electrode plates of the capacitor.

[0067] Please refer to Figure 9 The second conductive layer 210 is patterned to form a first electrode plate 211 and a second electrode plate 212 that are isolated from each other. The first electrode plate 211 is located on the first capacitor dielectric layer 208, and the second electrode plate 212 is located on the second capacitor dielectric layer 209.

[0068] Since the capacitance of a capacitor is related to the plate area, the plate spacing, and the dielectric constant of the dielectric material between the plates, capacitors with different capacitance values ​​can be obtained by acquiring first openings 206 and second openings 207 of different sizes, and by selecting the dielectric constant of the dielectric material layer filling the first and second openings. Since the first and second openings use the same patterned layer as a mask, and the patterned layer is formed by only one photolithography etching process, capacitors with different capacitance values ​​can be obtained without multiple photolithography processes, which helps to save production costs and promotes the development of capacitor manufacturing technology.

[0069] In this embodiment, the first electrode plate 211 and the first conductive layer 201 form a first capacitor, and the second electrode plate 212 and the first conductive layer 201 form a second capacitor.

[0070] In this embodiment, since the first electrode plate 211 and the second electrode plate 212 are the same size, the capacitance difference between the first capacitor and the second capacitor lies in the difference in the dielectric constant of the dielectric material between the plates. Because the second opening 207 is larger than the first opening 206, the capacitance of the second capacitor is greater than that of the first capacitor. In other embodiments, first and second capacitors with different capacitance differences can be obtained by adjusting the plate size, the material of the capacitor dielectric layer, etc.

[0071] In this embodiment, the first capacitor and the second capacitor share a first conductive layer 201 as the lower electrode plate. In another embodiment, the first conductive layer may include a third electrode plate and a fourth electrode plate, the third electrode plate being located below the first capacitor dielectric layer and the fourth electrode plate being located below the second capacitor dielectric layer. The first electrode plate and the second electrode plate constitute the first capacitor, and the third electrode plate and the fourth electrode plate constitute the second capacitor.

[0072] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Includes the following steps: (1) A substrate is provided having a first conductive layer therein, the substrate exposing the top surface of the first conductive layer; (2) An interlayer dielectric layer and a patterned layer located on the surface of the interlayer dielectric layer are formed on the substrate, wherein the materials of the interlayer dielectric layer and the patterned layer are different; the patterned layer has a first patterned opening and a second patterned opening of different sizes, wherein the surface of the interlayer dielectric layer is exposed at the first patterned opening and the second patterned opening. (3) The interlayer dielectric layer is etched using the patterned layer as a mask, a first opening is formed in the interlayer dielectric layer at the opening corresponding to the first pattern, and a second opening is formed in the interlayer dielectric layer at the opening corresponding to the second pattern, wherein the depths of the first opening and the second opening are different. (4) Remove the graphical layer; (5) A first capacitor dielectric layer is formed in the first opening and a second capacitor dielectric layer is formed in the second opening. The materials of the first capacitor dielectric layer and the second capacitor dielectric layer are different from those of the interlayer dielectric layer. (6) A second conductive layer is formed on the surface of the interlayer dielectric layer, the first capacitor dielectric layer, and the second capacitor dielectric layer; The width ratio of the first graphic opening to the second graphic opening is 1:4 to 6, and the depth ratio of the first opening to the second opening is the same as the width ratio of the first graphic opening to the second graphic opening.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, It also includes patterning the second conductive layer after step (6) to form a first electrode plate and a second electrode plate that are isolated from each other, with the first electrode plate and the second electrode plate located on the first capacitor dielectric layer and the second capacitor dielectric layer, respectively.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, In step (3), the etching process is plasma etching, wet etching, or ion milling.

4. The method for forming a semiconductor structure according to claim 3, characterized in that, The etching gas used in the plasma etching process is at least one of chlorine-based gas and fluorine-based gas.

5. The method for forming a semiconductor structure according to claim 3, characterized in that, The process parameters for plasma etching are as follows: the etching gas includes fluorine-based gas and argon, with the volume percentage of argon in the etching gas ranging from 2% to 5%; the radio frequency power ranges from 2 to 9 kW; the plasma electron temperature ranges from 1 to 10 eV; and the plasma density ranges from 10... 15 ~10 18 pcs / m 3 The ionization rate ranges from 10. -7 ~10 -4 .

6. The method for forming a semiconductor structure according to claim 1, characterized in that, In step (2), the method for forming the patterned layer includes: forming a patterned material layer on the surface of the interlayer dielectric layer, forming a mask layer on a portion of the surface of the patterned material layer, and using the mask layer as a mask to etch the patterned material layer to form the patterned layer.

7. The method for forming a semiconductor structure according to claim 1, characterized in that, The method for forming the first capacitor dielectric layer and the second capacitor dielectric layer includes: forming a capacitor dielectric material layer on the surface of the first opening, the second opening and the interlayer dielectric layer; planarizing the capacitor dielectric material layer until the surface of the interlayer dielectric layer is exposed.

8. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the interlayer dielectric layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, and silicon carbonitride; the material of the patterning layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbonitride.

9. The method for forming a semiconductor structure according to claim 1, characterized in that, The projection of the first patterned opening onto the substrate surface is a rectangle or a circle; the projection of the second patterned opening onto the substrate surface is a rectangle or a circle.

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