Register renaming for power saving

Abstract

Systems and methods for register renaming are disclosed. For example, an integrated circuit is described comprising: a first cluster including a first set of physical registers and a first execution resource circuit, wherein the input to an operation of the first execution resource circuit is a first data type; a second cluster including a second set of physical registers and a second execution resource circuit, wherein the input to an operation of the second execution resource circuit is a second data type different from the first data type; and a register renaming circuit configured to: determine a data type prediction of the result of a first instruction to be stored in a first logical register; and, based on the data type prediction matching the first data type, rename the first logical register so that it is stored in a physical register of the first set of physical registers.

Description

Technical Field

[0001] This disclosure relates to register renaming for power saving purposes. Background Technology

[0002] Modern processors frequently use out-of-order execution with physical register renaming. Previous systems had used physical register renaming to eliminate the dangers of write-after-write and read-after-write by allocating a new destination register for each produced result.

[0003] In some processors (e.g., Motorola 88000 and RISC-V Zfinx options), architectural registers are capable of holding different types of data at different times. For example, a single register can hold integer or floating-point values. In some traditional processors, where the instruction set architecture allows multiple data types to be stored in the same architectural registers, a unified physical register file is used to store different data types and routes them to various functional units that process different data types.

[0004] Two-dimensional structures (e.g., systolic arrays) are highly efficient for matrix computations because operands reside in the array and require only minimal data movement to process. However, these two-dimensional structures for matrix computations are hardwired and typically used in fixed-function machines. Because operands are distributed, it is highly specialized and requires writing microcode to do things correctly. These advantages are lost in the different contexts of a general-purpose central processing unit (CPU), and there are very different timings for accessing registers versus accessing cache versus accessing main memory. Attached Figure Description

[0005] This disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, by convention, the various features in the drawings are not drawn to scale. Instead, for clarity, the dimensions of the various features have been arbitrarily enlarged or reduced.

[0006] Figure 1 This is a block diagram of an example system that uses register renaming based on data type prediction to execute instructions.

[0007] Figure 2 This is a block diagram of an example system that executes instructions using data type prediction register renaming and alternative data paths between clusters that can be used to recover from error prediction.

[0008] Figure 3 This is a flowchart illustrating an example of a register renaming process based on data type prediction.

[0009] Figure 4This is a flowchart illustrating an example of the process of recovering from data type misprediction by inserting micro-operations to move data to the correct cluster.

[0010] Figure 5 This is a flowchart illustrating an example of the process of recovering from data type error prediction by using alternative data paths between clusters.

[0011] Figure 6 This is a block diagram of an example system that executes instructions from an instruction set that uses register renaming.

[0012] Figure 7 This is a block diagram of an example system that executes instructions from an instruction set that uses register renaming. Detailed Implementation

[0013] Overview

[0014] This article discloses an implementation method for register renaming for power saving.

[0015] In a first aspect, the subject matter described herein can be embodied in an integrated circuit for executing instructions, the integrated circuit comprising: a first cluster including a first set of physical registers and a first execution resource circuit configured to perform an operation taking the contents of one or more registers of the first set of physical registers as input, wherein the input for the operation of the first execution resource circuit is a first data type; a second cluster including a second set of physical registers and a second execution resource circuit configured to perform an operation taking the contents of one or more registers of the second set of physical registers as input, wherein the input for the operation of the second execution resource circuit is a second data type different from the first data type; and a register renaming circuit configured to: determine a data type prediction of the result of a first instruction to be stored in a first logical register; and, based on the data type prediction matching the first data type, rename the first logical register to be stored in a physical register of the first set of physical registers.

[0016] In a second aspect, the subject matter described in this specification can be embodied in a method comprising: determining a data type prediction of the result of a first instruction to be stored in a first logical register; and, based on the data type prediction matching a first data type, renaming the first logical register to be stored in a physical register of a first cluster selected from a plurality of clusters, wherein the plurality of clusters includes: a first cluster comprising a first set of physical registers and a first execution resource circuit, the first execution resource circuit being configured to perform an operation taking the contents of one or more registers of the first set of physical registers as input, wherein the input for the operation of the first execution resource circuit is a first data type; and a second cluster comprising a second set of physical registers and a second execution resource circuit, the second execution resource circuit being configured to perform an operation taking the contents of one or more registers of the second set of physical registers as input, wherein the input for the operation of the second execution resource circuit is a second data type different from the first data type.

[0017] In a third aspect, the subject matter described herein can be embodied in an integrated circuit for executing instructions, the integrated circuit including execution resource circuitry configured to execute instructions on operands stored in physical registers; a set of physical registers including a first subset of physical registers located near the execution resource circuitry and a second subset of physical registers located further away from the execution resource circuitry than registers in the first subset of physical registers; and register renaming circuitry configured to: detect an instruction sequence stored in an instruction decoding buffer, the instruction sequence including multiple sequential references to a first logical register having real dependencies; and, based on the detection of the instruction sequence, rename the first logical register to be stored in a physical register of the first subset of physical registers, and rename another logical register referenced in the instruction sequence to be stored in a physical register of the second subset of physical registers.

[0018] These and other aspects of this disclosure are made clear in the following detailed description, the appended claims and the accompanying drawings.

[0019] Specialized physical architectures can be used to improve the storage and processing of different data types. For example, one such architecture is a cluster comprising a combination of physical register files and functional units tightly coupled using local data paths. One advantage of this approach is the ability to optimize the representation of data values ​​in each register file for dynamic data types currently residing in each architecture register. A second advantage might be that sequences of computations involving the same data type are localized to the same cluster, thereby improving energy efficiency and reducing circuit latency.

[0020] Some implementations described herein can provide the benefit of providing separate, localized processing of different data types within an optimized cluster, even when the instruction set architecture requires all data types to be stored and processed from a unified set of architecture registers. For example, a scalar processor with a unified architecture register file can provide two clusters, one for integers and one for floating-point data types. The methods described herein dynamically assign values ​​to clusters and perform computations in the appropriate cluster based on the data type.

[0021] For example, some implementations determine which cluster to execute the instruction in based on the instruction opcode. If space is available, the destination is allocated in that cluster and the mapping table is updated (otherwise decoding stops). The mapping table is checked to see if the source is in the correct cluster. If so, the instruction is dispatched to the correct cluster. If the source is in the wrong cluster (e.g., loaded into an integer register file but now being treated as a floating-point number), additional micro-operations are inserted to move the data from one cluster to another, possibly reformatting the data as part of a transformation.

[0022] Prediction is possible when the target format is unclear from the opcode (e.g., loaded from memory). Some prediction options include: 1) Using the same type as the last type of a register with the same architecture. It has been observed that in many codes, especially loops, the same architecture register is used repeatedly to hold the same type. If the software understands this prediction strategy, it can improve the performance of this approach. 2) Carrying ahead in the instruction buffer to see if the subsequent opcode indicates the use of this source. 3) Generating data type predictions randomly. 4) Based on the program counter (PC) plus instruction encoding. The program counter is ignored if the encoding is sufficient to determine the result type; otherwise, a portion of the program counter is used to index into the prediction table. For example, the same architecture register can be used twice in the same loop to hold data of different types.

[0023]

[0024] 5) The above combination can be used to predict the data type of the result of the instruction to be stored in the destination register.

[0025] For example, some extensions include: 1) Processors typically provide operations on Boolean values. For example, comparison instructions that might return 1 or 0. These are often used as input to branch instructions or other logical operations. Dedicated predicate value clusters can be provided to improve the performance of these instructions. These unit values ​​require significantly less physical storage than full-width physical registers, and the energy required to process them is also significantly less. In the case of logical operations (e.g., AND, OR, XOR), the instruction encoding plus the source data type is used to determine which cluster to use. Branch execution typically resides on the processor's critical path, and isolating Boolean values ​​into separate clusters can reduce circuit latency for branch resolution. 2) Half-width scalars (e.g., 32-bit width in a 64-bit scalar) can be used to gain more capacity by reusing physical registers. 3) Separate clusters in scalar registers can be provided for packing SIMD values ​​to reduce the critical path for unpacked SIMD values. This can improve the energy efficiency of packed SIMD clusters with longer circuit latency. 4) Vector register files.

[0026] Systems and methods for register renaming are disclosed. Integrated circuits (e.g., processors or microcontrollers) can decode and execute instructions of an instruction set architecture (ISA) (e.g., RISC V instruction set). This method for integrated circuit design uses register renaming to gain some of the benefits of fixed-function machines with two-dimensional structures used for matrix computations (e.g., systolic arrays) in general-purpose CPUs. For example, consider multiply-add, multiply-add, and add matrices. If the source and destination are the same (c <- c*a+b), then matrix c can remain "immobile" in one of the arrays and the others (e.g., a, then b is the only thing that could flow in).

[0027] Register renaming has already been done with different objectives. The previous objective was to remove erroneous dependencies, such as read-after-write and write-after-write (WAR and WAW). However, here we've allocated a new physical register for each result being written. So, compare: rc2 = rc1 + ra1 * rb1. Now rc2 resides in a different physical register than rc1. But what we want to do is keep c1 in place by overwriting it, for example, rc1 = rc1 + ra1 * rb1.

[0028] Another difference is that renaming is performed based on physical location within the chip (e.g., proximity to the Arithmetic Logic Unit (ALU)). Previous techniques typically used registers all located in a central registry file, but here renaming can be performed to force one of the inputs to the ALU to be physically close to the ALU, which reduces the power required to transfer values ​​to the ALU to execute subsequent instructions. These power savings can be particularly important for vector or matrix operations. For example, consider the instruction C = A + B, where A, B, and C are vectors. In this example, C could be reassigned to a standard one-dimensional vector. Similarly, consider the instruction F = D + E, where D, E, and F are matrices. In this example, F would be a two-dimensional structure next to the ALU. The shape / size of the assigned register can vary based on the type of data and operation.

[0029] As used herein, the term "circuit" refers to an arrangement of electronic components (e.g., transistors, resistors, capacitors, and / or inductors) configured to perform one or more functions. For example, a circuit may include one or more transistors interconnected to form logic gates that collectively perform a logic function.

[0030] detail

[0031] Figure 1 This is a block diagram of an example of a system 100 that executes instructions using register renaming based on data type prediction. System 100 includes an integrated circuit 110 for executing instructions (e.g., RISC-V instructions or x86 instructions). Integrated circuit 110 includes: a first cluster 120 configured to perform operations on one or more inputs of a first data type; a second cluster 130 configured to perform operations on one or more inputs of a second data type; and register renaming circuitry 140 configured to rename logical registers to map to physical registers in a cluster selected from a set of clusters based on data type prediction of the instruction result (e.g., load instructions, add instructions, or XOR instructions). Integrated circuit 110 may include additional clusters ( Figure 1 (Not shown in the diagram), which executes instructions by taking additional input of different data types. In some embodiments, integrated circuit 110 may include additional clusters ( Figure 1 (Not shown in the diagram), which executes instructions by taking input of a first data type or a second data type, and when selecting among multiple clusters using the same data type for register renaming, register renaming can be based on additional considerations, such as the actual dependencies between instruction sequences. Integrated circuit 110 includes instruction buffer 170, which stores instructions expected to be executed in the near future. For example, integrated circuit 110 may be a microprocessor or a microcontroller.

[0032] Integrated circuit 110 includes a first cluster 120 and a first execution resource circuit 122. The first cluster 120 includes a first set of physical registers 124, 126, and 128. The first execution resource circuit 122 is configured to perform operations that take the contents of one or more registers of the first set of physical registers 124, 126, and 128 as input. The input to the operation of the first execution resource circuit 122 is a first data type (e.g., integer, floating-point, Boolean, scalar, vector, or matrix). For example, the execution resource circuit 122 may include an arithmetic logic unit (ALU). For example, the execution resource circuit 122 may include a floating-point unit (FPU). The cluster may include data paths to the registers of the first set of physical registers 124, 126, and 128 that enable the execution resource circuit 122 to access source registers that store input arguments and / or destination registers that store results. For example, the first cluster 120 may be used to execute an instruction (e.g., an addition instruction) that takes a value stored in physical register 124 and a value stored in physical register 126 as input parameters and outputs the result to physical register 126. For example, the first set of physical registers 124, 126 and 128 can be located adjacent to the first execution resource circuit 122.

[0033] Integrated circuit 110 includes a second cluster 130 and a second execution resource circuit 132. The second cluster 130 includes a second set of physical registers 134, 136, and 138. The second execution resource circuit 132 is configured to perform operations that take the contents of one or more registers of the second set of physical registers as input. The input to the operation of the second execution resource circuit 132 is a second data type different from the first data type. For example, the first data type may be floating-point while the second data type may be integer. In some embodiments, the first data type is a Boolean value and the registers in the first set of physical registers are single-bit in size. For example, the first execution resource circuit 122 may be configured to execute branch instructions. Branch execution is typically on the critical path of the processor, and isolating Boolean values ​​in a separate cluster can reduce circuit latency for branch resolution. In some embodiments, the first data type is a scalar (e.g., a 64-bit scalar) and the second data type is a half-width scalar (e.g., a 32-bit scalar). In some embodiments, the first data type is packed SIMD (Single Instruction, Multiple Data) and the second data type is unpacked SIMD. Providing a separate cluster may reduce the critical path of unpacked SIMD values. For example, a packed SIMD cluster can be tailored for power savings with longer circuit delays. For example, execution resource circuit 132 may include an arithmetic logic unit (ALU). For example, execution resource circuit 132 may include a floating-point unit (FPU). The cluster may include data paths of registers in a first set of physical registers 134, 326, and 138 that enable execution resource circuit 132 to access source registers as storage input arguments and / or destination registers as storage results. For example, a second cluster 130 may be used to execute instructions (e.g., multiplication instructions) that take values ​​stored in physical register 136 and values ​​stored in physical register 138 as input parameters and output the result to physical register 134. For example, the second set of physical registers 134, 136, and 138 is adjacent to the second execution resource circuit 132.

[0034] Integrated circuit 110 includes register renaming circuitry 140. Register renaming circuitry 140 maintains a renaming table 150 that associates logical registers of the instruction set (e.g., RISC-V registers) with one or more corresponding physical registers that store or will store the values ​​of those logical registers. Register renaming circuitry 140 includes data type predictor circuitry 160 configured to generate data type predictions for the results of instructions to be stored in destination registers.

[0035] Register renaming circuitry 140 is configured to determine a data type prediction for the result of a first instruction to be stored in a first logical register. The first logical register may be allowed to store data of different data types (e.g., integer or floating-point) under applicable instruction sets. For example, data type predictor circuitry 160 may be used to determine the data type prediction. For example, the first logical register may be a vector with at least two elements, and the vector is stored in a physical register of a first set of physical registers. For example, the first logical register may be a matrix with multiple rows and columns of elements, and the matrix may be stored in a physical register of a first set of physical registers. In some implementations, the data type prediction is determined based on the opcode of the first instruction. For example, if the first instruction is a floating-point addition, the data type prediction may be biased towards floating-point. Nevertheless, other factors may be considered to predict subsequent instructions that reinterpret or type-convert the result depending on the outcome. In some implementations, the first instruction is an untyped transfer instruction (e.g., a load instruction), so the opcode of the first instruction may lack information about the data type of the result.

[0036] For example, register renaming circuitry 140 can carry-forward in instruction buffer 170 to detect a second instruction that will access the result of a first instruction in the first logical register and use information about the consumed instruction to determine a data type prediction. For example, the data type prediction can be determined based on the opcode of a queued instruction that will access the result of the first instruction. The queued instructions can be stored in instruction buffer 170. For example, the first instruction can be stored in the instruction buffer as the next instruction 172 to be issued, and register renaming circuitry 140 can scan the instruction buffer to detect a second instruction 174 that will next access the first logical register, which is the source register. The data type prediction can then be determined based on the opcode of the second instruction 174.

[0037] For example, data type prediction can be determined based on the current data type of the data currently stored in the first logical register. It has been observed that in many parts of code, especially within loops, the same schema registers are used repeatedly to hold the same type. If software developers understand this prediction strategy, the software can improve the performance of this approach. For instance, the first instruction might be a load instruction, which may not provide inherent information about the data type of its result (i.e., the value retrieved from the memory system), but consistent use of schema registers by the software can provide the necessary cues to accurately predict the data type of the data loaded from memory.

[0038] For example, data type prediction can be determined based on the value of the program counter (e.g., the program counter value associated with the first instruction). In some implementations, the data type predictor circuit 160 can maintain a prediction table of prediction counters indexed by the program counter value.

[0039] For example, data type predictions can be determined based on a combination of the factors mentioned above.

[0040] Register renaming circuitry 140 is configured to rename a first logical register to be stored in a physical register of a first set of physical registers 124, 126, or 128 based on a data type prediction matching a first data type. For example, renaming the first logical register may include updating entries in renaming table 150 to associate the first logical register with a physical register of the first set of physical registers 124, 126, or 128. Renaming the first logical register allows the result of a first instruction to be stored in a physical register of the first set of physical registers 124, 126, or 128. If the data type prediction is accurate, the second instruction can be efficiently executed using the first cluster 120 when a second, subsequent instruction accesses the first logical register to access its result.

[0041] If the data type prediction proves inaccurate, a misprediction has occurred. For example, a misprediction can be addressed by inserting an additional micro-operation before the second instruction to move the result of the first instruction into a physical register in the appropriate cluster of the second instruction. In some embodiments, register renaming circuitry 140 is configured to detect misprediction, wherein a second instruction to be executed after the first instruction will access a first logical register as input to a second data type; and, in response to the misprediction, a micro-operation is issued before the second instruction. The micro-operation copies the value of the first logical register, stored in a physical register of a first set of physical registers, to a physical register of a second set of physical registers. For example, the micro-operation could be a microarchitecture move instruction. In some embodiments, the micro-operation can also cause an update to rename table 150 to reflect the move of the result of the first instruction.

[0042] The integrated circuit includes an instruction buffer 170. For example, the instruction buffer 170 may be a decode buffer of the integrated circuit 110. For example, the instruction buffer 170 may be a publish buffer of the integrated circuit 110. For example, the instruction buffer 170 may be a cache line of the instruction cache of the integrated circuit 110.

[0043] Figure 2This is a block diagram of an example of a system 200 for executing instructions using register-rename-based data type prediction and an alternative data path between clusters capable of recovering from error prediction. System 200 includes an integrated circuit 210 for executing instructions (e.g., RISC-V instructions or x86 instructions). Integrated circuit 210 includes: a first cluster 120 configured to perform operations on one or more inputs of a first data type; a second cluster 130 configured to perform operations on one or more inputs of a second data type; and register renaming circuitry 240 configured to rename logical registers to map to physical registers in a cluster selected from a set of clusters based on data type prediction of the instruction result (e.g., load instruction, add instruction, or XOR instruction). Integrated circuit 210 may include additional clusters ( Figure 2 (Not shown in the diagram), which executes instructions by taking additional input of different data types. In some embodiments, integrated circuit 210 may include additional clusters ( Figure 2 (Not shown in the diagram), which executes instructions by taking input of a first data type or a second data type, and when selecting among multiple clusters using the same data type for register renaming, register renaming can be based on additional considerations, such as the actual dependencies between instruction sequences. Integrated circuit 210 includes instruction buffer 170, which stores instructions expected to be executed in the near future. For example, integrated circuit 210 may be a microprocessor or a microcontroller.

[0044] Integrated Circuit 210 and Figure 1 The difference between integrated circuits 110 and 210 is that integrated circuit 210 includes an alternative data path 280 from physical register 128 of the first set of physical registers 124, 126, and 128 to the second execution resource circuit 132. The alternative data path 280 allows the second execution resource circuit 132 to directly access the value stored in physical register 128, instead of having to wait for other resources of integrated circuit 210 to move the result stored in physical register 128 to the physical registers of the second set of physical registers 134, 136, and 138. For example, register renaming circuit 240 can be configured to: detect error predictions, where a second instruction to be executed after the first instruction will access the first logical register as input of a second data type; and, in response to the error prediction, cause the second execution resource circuit 132 to access the value of the first logical register using the alternative data path 280. Using the alternative data path 280 may consume more power to access data from a greater distance, but it can save time compared to inserting micro-operations to copy data between clusters.

[0045] Figure 3This is a flowchart illustrating an example of a register renaming process 300 based on data type prediction. Process 300 includes: determining a data type prediction 310 for the result of a first instruction to be stored in a first logical register; and renaming the first logical register 320 to be stored in a physical register of a first cluster selected from multiple clusters, based on the data type prediction matching a first data type. For example, process 300 can use... Figure 1 This is implemented using integrated circuit 110. For example, process 300 can be implemented using... Figure 2 It is implemented using the integrated circuit 210.

[0046] Process 300 includes determining 310 a data type prediction for the result of a first instruction to be stored in a first logic register. The first logic register may be allowed to store data of different data types (e.g., integer, floating-point, boolean, scalar, vector, or matrix) under an applicable instruction set (e.g., RISC-V or x86 instruction set).

[0047] In some implementations, the data type prediction for 310 is determined based on the opcode of the first instruction. For example, the destination register of a logical AND instruction may be predicted as a Boolean data type based on the opcode of the instruction that produces the result to be stored in the destination register. For example, in the case where the first instruction is a floating-point addition, the data type prediction may be biased towards floating-point. However, other factors can be considered to predict subsequent instructions that depend on the result for reinterpretation or type conversion of the result.

[0048] For example, the first instruction could be an untyped transfer instruction (e.g., a load instruction). In this case, the opcode of the first instruction may lack information about how the result will be used, so other techniques can be used to determine the data type prediction of the result of the first instruction.

[0049] For example, the look-ahead carry in the instruction buffer can be used to identify future instructions that may access the result in the first logic register, and thus provide useful information about what data type the result should be. In some implementations, the data type prediction is determined based on the opcode of the queued instruction that will access the result of the first instruction. The queued instructions can be stored in the instruction buffer. For example, the instruction buffer can be a decode buffer. For example, the instruction buffer can be a cache line of the instruction cache. For example, the instruction buffer can be a issue buffer.

[0050] For example, the data type prediction for 310 can be determined based on the current data type of the data currently stored in the first logical register. Observations show that in many code segments, especially loops, the same schema registers are used repeatedly to hold the same type. If software developers understand this prediction strategy, the software can improve the performance of this approach. For example, the first instruction might be a load instruction, which may not provide inherent information about the data type of its result (i.e., the value retrieved from the memory system), but consistent use of schema registers by the software can provide the necessary clues to determine the accurate data type prediction of the data loaded from memory by 310.

[0051] For example, the 310 data type prediction can be determined based on the value of the program counter (e.g., the program counter value associated with the first instruction). In some implementations, a prediction table of prediction counters indexed by the program counter values ​​can be maintained. In some implementations, the 310 data type prediction can be determined randomly.

[0052] For example, the 310 data type prediction can be determined based on a combination of the above factors, such as the opcode of the first instruction, the carry-ahead of the opcode of the subsequent consumed instruction, the current data type of the first logic register, and / or the program counter value.

[0053] Process 300 includes predicting and matching a first data type based on data type, and renaming 320 a first logical register to be stored in a physical register of a first cluster selected from multiple clusters. The first cluster may include a first set of physical registers and a first execution resource circuit, the first execution resource circuit being configured to perform operations that take the contents of one or more registers of the first set of physical registers as input. The operation input of the first execution resource circuit may be of the first data type. The multiple clusters may include a second cluster, the second cluster including a second set of physical registers and a second execution resource circuit, the second execution resource circuit being configured to perform operations that take the contents of one or more registers of the second set of physical registers as input. The operation input of the second execution resource circuit may be of a second data type different from the first data type. For example, the first data type may be floating-point while the second data type may be integer. In some embodiments, the first data type is a Boolean value and the registers of the first set of physical registers are single-bit in size. For example, the first execution resource circuit may be configured to execute branch instructions. In some embodiments, the first logical register is a vector with at least two elements and the physical registers of the first set of physical registers store the vector. In some implementations, the first logical register is a matrix with multiple rows and columns of elements, and the matrix is ​​stored in the physical registers of the first set of physical registers. In some implementations, the first data type is a scalar (e.g., a 64-bit scalar), and the second data type is a half-width scalar (e.g., a 32-bit scalar). In some implementations, the first data type is packed SIMD (Single Instruction, Multiple Data), and the second data type is unpacked SIMD. Providing a separate cluster may reduce the critical path for unpacked SIMD values.

[0054] If the data type prediction proves inaccurate, a misprediction has occurred. In some implementations, the prediction error can be mitigated by inserting an additional micro-operation before the second instruction to move the result of the first instruction into a physical register in the appropriate cluster of the second instruction. For example, this can be implemented... Figure 4 The process 400 addresses erroneous predictions regarding the data type of the results. In some implementations, prediction errors can be resolved by using alternative data paths within the integrated circuit to access results from one of the clusters associated with different data types. For example, this can be achieved... Figure 5 The process 500 is used to handle the error prediction of the data type of the result.

[0055] Figure 4This is a flowchart illustrating an example of process 400 for recovering from a data type misprediction by inserting a micro-operation to move data to the correct cluster. Process 400 includes detecting a misprediction at 410, where a second instruction, to be executed after a first instruction, will access a first logical register as input of a second data type; and, in response to the misprediction, issuing a micro-operation at 420 before the second instruction to copy the value of the first logical register stored in the physical register of the second cluster to the physical register of the second cluster. For example, process 400 can use... Figure 1 This is implemented using integrated circuit 110. For example, process 400 can be implemented using... Figure 2 It is implemented using the integrated circuit 210.

[0056] Process 400 includes detecting 410 error prediction, wherein a second instruction to be executed after the first instruction will access the first logical register as input of a second data type. For example, 410 error prediction can be detected by scanning the release buffer for instructions with the first logical register as a source register when the second instruction is in the release buffer. Detecting 410 error prediction may also include checking for intervention rewriting of the result of the first instruction in the logical register. Detecting 410 error prediction may include, when a second instruction accessing the result in the first logical register is detected, checking whether the data type of the first logical register, as the source register of the second instruction, matches the data type prediction for the result of the first instruction, and / or whether the result is currently stored in the appropriate cluster for executing the second instruction.

[0057] Process 400 includes issuing a 420 micro-operation in response to an error prediction, prior to the second instruction. The micro-operation copies the value of a first logical register stored in the physical registers of a first set of physical registers (i.e., the first cluster) to the physical registers of a second set of physical registers (i.e., the second cluster). For example, the micro-operation could be a microarchitecture move instruction. In some implementations, the micro-operation may also cause an update to a rename table (e.g., rename table 150) to reflect the move of the result of the first instruction. After the result of the first instruction has been copied to the second cluster, the second cluster can be used to execute the second instruction, effectively accessing the result of the first instruction and treating it as data of a second data type associated with the second cluster.

[0058] Figure 5This is a flowchart illustrating an example of a process 500 for recovering from a data type error prediction by using an alternative data path between clusters. Process 500 includes detecting an error prediction 510, where a second instruction to be executed after a first instruction will access a first logical register as input of a second data type; and, in response to the error prediction, causing a second execution resource circuit 520 (e.g., second execution resource circuit 132) to access the value of the first logical register using an alternative data path (e.g., alternative data path 280) from the physical registers of a first set of physical registers (e.g., the first cluster 120) to the second execution resource circuit. For example, it can be used... Figure 2 The process 500 is implemented using integrated circuit 210.

[0059] Process 500 includes detecting 510 error prediction, wherein a second instruction to be executed after the first instruction will access the first logical register as input of a second data type. For example, when the second instruction is in the release buffer, 510 error prediction can be detected by scanning the release buffer for instructions that have the first logical register as a source register. Detecting 510 error prediction may also include checking for intervention rewriting of the result of the first instruction in the logical register. Detecting 510 error prediction may include, when a second instruction accessing the result in the first logical register is detected, checking whether the data type of the first logical register, as the source register of the second instruction, matches the data type prediction for the result of the first instruction and / or whether the result is currently stored in the appropriate cluster for executing the second instruction.

[0060] Process 500 includes, in response to an error prediction, causing 520 of the second execution resource circuitry to access the value of the first logic register using an alternative data path from the physical registers of the first set of physical registers (i.e., the first cluster) to the second execution resource circuitry. The integrated circuit (e.g., integrated circuit 210) includes an alternative data path from the physical registers of the first set of physical registers to the second execution resource circuitry. This alternative data path allows the second execution resource circuitry to directly access the value stored in the physical registers of the first set of physical registers without waiting for other resources of the integrated circuitry to move the result stored in the physical registers to the physical registers of the second set of physical registers. Using an alternative data path may consume more power to access data from a greater distance, but it saves time compared to inserting micro-operations to copy data between clusters.

[0061] Figure 6This is a block diagram of an example of a system 600 that uses register renaming to execute instructions from an instruction set. System 600 includes an integrated circuit 610 configured to execute instructions. For example, integrated circuit 610 may be a processor or a microcontroller. Integrated circuit 610 includes a renaming table 620, a central register file 630, and an execution resource unit 640. Renaming table 620 includes entries (e.g., entries 622, 624, and 626) that map logical registers supported by an assembly instruction set (e.g., RISC V, x86, or ARM instruction sets) to physical registers of integrated circuit 610. Central register file 630 includes physical registers such as physical register 632 and physical register 634. Execution resource unit 640 includes execution resource circuitry 642 and physical registers 644, 646, and 648 adjacent to execution resource circuitry 642.

[0062] Integrated circuit 610 is characterized by including a renaming table 620 that maps to physical registers located at different locations on integrated circuit 610. In some implementations, the physical registers can be of different types. For example, physical registers 644, 646, and 648 can be vectors, while scalars can be stored in physical register 632. Physical registers 644, 646, and 648 are located very close to the arithmetic logic unit (ALU) 642, which can result in higher speed, power savings, and / or a smaller area.

[0063] In some implementations, renaming table 620 can enable the use of a heterogeneous set of physical registers near the execution resource circuitry. For example, an instruction set architecture (ISA) can encode the shape (e.g., scalar, vector, or matrix) of logical registers. In some implementations, each logical register name in the ISA can encode the shape of the logical register. The shapes of operands (e.g., source and destination) may be known during fetch, decode, and execution. This allows different types of registers (e.g., scalar, vector, and matrix) to be used for different parts of equations implemented using instructions from the ISA. In some implementations, two types of vectors can be supported, one for row vectors and another for column vectors, to better handle two-dimensional matrix operations. See also Figure 7 To see an example of the potential physical register types near the matrix function unit.

[0064] Figure 7This is a block diagram of an example system 700 for executing instructions from an instruction set using register renaming. System 700 includes an integrated circuit 710 configured to execute instructions. For example, integrated circuit 710 may be a processor or a microcontroller. Integrated circuit 710 includes a renaming table 720, a measure, a matrix execution unit 730, a scalar execution unit 740, a vector execution unit 750, and physical registers 760, 762, 764, and 766. Renaming table 720 includes entries (e.g., 722, 724, and 726) that map logical registers supported by an assembly instruction set (e.g., RISC-V, x86, or ARM) to the physical registers of integrated circuit 710. Matrix execution unit 730 includes execution resource circuit 732 and a physical register 734 containing a storage matrix adjacent to execution resource circuit 732. Scalar execution unit 740 includes execution resource circuit 742 and physical registers 744, 746, and 748 containing storage scalars adjacent to execution resource circuit 742. The vector execution unit 750 includes an execution resource circuit 752 and physical registers 754, 756 and 758 adjacent to the execution resource circuit 752 for storing vectors.

[0065] Integrated circuit 710 includes four types of physical registers. Note that some physical registers for one-dimensional vectors (760, 762, 764, and 766) have no functional units because they are fed to matrix functional units. For example, physical registers 760, 762, 764, and 766 can store column vectors. In contrast, theorem, scalar, and matrix registers have similar functional units for operations. In some implementations ( Figure 7 (Not shown in the diagram), integrated circuit 710 may include one or more execution resource circuits adjacent to physical registers 760, 762, 764 and 766 for one-dimensional vectors (e.g., column vectors). Figure 7 The example architecture might be more efficient for ISAs, where vectors are specified to be used for matrix transformations or element-wise operations. Although not shown... Figure 7 However, multiple physical matrix registers can exist.

[0066] For example, a simple path is: input all type1, output all type1 → allocate type1 registers (e.g., all scalars or all one-dimensional vectors (e.g., row vectors) or load matrices). If no physical registers are available, instructions can be deferred to schedule execution when a suitable physical register becomes available.

[0067] For example, a slightly more complex path is to select the best type of physical register for each input / output based on hints in the ISA or register name.

[0068] For example, a more advanced / complex implementation involves applying branch prediction type heuristics to track how the result is used and selecting the correct type of register for the output. For example, in... Figure 7 In a matrix, we might have two types of one-dimensional vectors: rows and columns. Inefficiency can arise if the result is frequently stored in a row vector but needs to be used in a column vector for later matrix operations. Conversely, inefficiency can occur if the result is typically stored in a column vector register but is needed to directly perform shift operations. Therefore, tracking the most recent use of an operand along this path can inform future arrangements. Most loops support this using a simple predictor consisting of buffers that track the register types used previously. So, something like this would be tracked for rename tables:

[0069] Rename table Using prediction v0 1D row vector v1 scalar v2 2D matrix v3 1D column vector v...

[0070] In this case, the prediction used is precisely what happened at the end of the previous example. Therefore, the prediction generated by the predictor may depend on the final path.

[0071] Another issue besides physical geolocation is what happens if there's an integer ALU and another ALU performing floating-point calculations. Therefore, the types of available physical registers can also vary depending on the precision format of one or more elements of the register. For example, a rename table can be extended to track or predict the element types of logical registers, which could lead to a rename table:

[0072] Rename table Using prediction Element type v0 1D row vector Single-precision floating point v1 scalar Double-precision floating point v2 2D matrix Plastic Surgery v3 1D column vector custom made v...

[0073] Register renaming can be associated with out-of-order execution in the processor. This approach can be used for both.

[0074] For example, the integrated circuit 610 for executing instructions includes execution resource circuitry 642 configured to execute instructions on operands stored in physical registers; a set of physical registers including a first subset of physical registers 644, 646, and 648 located close to the execution resource circuitry and a second subset of physical registers (e.g., central register file 630), the second subset of physical registers being further away from the execution resource circuitry 642 than the registers in the first subset of physical registers 644, 646, and 648; and register renaming circuitry configured to: detect an instruction sequence stored in an instruction decoding buffer, the instruction sequence including multiple sequential references to a first logical register having real dependencies; and, based on the detection of the instruction sequence, rename the first logical register to be stored in the physical registers of the first subset of physical registers 644, 646, and 648, and rename another logical register referenced in the instruction sequence to be stored in the physical registers of the second subset of physical registers 644, 646, and 648. For example, the first logical register may be a vector having at least two elements, and the physical registers of the first subset of physical registers store the vector. For example, the first logical register may be a matrix with multiple rows and columns of elements, and the matrix is ​​stored in the physical registers of a subset of the first physical registers. In some implementations, the instruction sequence is accumulated in the first logical register.

[0075] While this disclosure has been described in conjunction with certain embodiments, it should be understood that this disclosure is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims, which should be interpreted in the broadest possible sense to cover all such modifications and equivalent structures permitted by law.

Claims

1. An integrated circuit for executing instructions, comprising: A first cluster, the first cluster including a first set of physical registers and a first execution resource circuit, the first execution resource circuit being configured to perform an operation taking the contents of one or more registers of the first set of physical registers as input, wherein the input for the operation of the first execution resource circuit is a first data type; A second cluster, comprising a second set of physical registers and a second execution resource circuit, the second execution resource circuit being configured to perform operations taking the contents of one or more registers of the second set of physical registers as input, wherein the input for the operation of the second execution resource circuit is a second data type different from the first data type; and Register renaming circuit, the register renaming circuit being configured as follows: Determine the data type prediction of the result of the first instruction to be stored in the first logical register; and Based on the data type prediction, the first data type is matched, and the first logical register is renamed so that it is stored in the physical register of the first group of physical registers.

2. The integrated circuit according to claim 1, wherein, The first instruction is an untyped transfer instruction.

3. The integrated circuit according to claim 1, wherein, The first instruction is a load instruction.

4. The integrated circuit according to any one of claims 1 to 3, wherein, The data type prediction is determined based on the opcode of the first instruction.

5. The integrated circuit according to any one of claims 1 to 3, wherein, The data type prediction is determined based on the opcode of a queued instruction that will access the result of the first instruction, wherein the queued instruction is stored in an instruction buffer.

6. The integrated circuit according to claim 5, wherein, The instruction buffer is the decoding buffer of the integrated circuit.

7. The integrated circuit according to claim 5, wherein, The instruction buffer is a cache line of the instruction cache of the integrated circuit.

8. The integrated circuit according to any one of claims 1 to 3, wherein, The data type prediction is determined based on the current data type of the data currently stored in the first logical register.

9. The integrated circuit according to any one of claims 1 to 3, wherein, The data type prediction is determined based on the value of the program counter.

10. The integrated circuit according to any one of claims 1 to 3, wherein, The register renaming circuit is configured as follows: Error prediction is detected, wherein a second instruction to be executed after the first instruction will access the first logical register as input to the second data type; and In response to the error prediction, a micro-operation is issued before the second instruction, wherein the micro-operation copies the value of the first logical register stored in the physical register of the first set of physical registers to the physical register of the second set of physical registers.

11. The integrated circuit according to any one of claims 1 to 3, comprising an alternative data path from the physical registers of the first set of physical registers to the second execution resource circuit, wherein, The register renaming circuit is configured as follows: Error prediction is detected, wherein a second instruction to be executed after the first instruction will access the first logical register as input to the second data type; and In response to the error prediction, the second execution resource circuitry accesses the value of the first logic register using the alternative data path.

12. The integrated circuit according to claim 11, wherein, The first logical register is a vector with at least two elements, and the physical registers of the first set of physical registers store the vector.

13. The integrated circuit according to claim 11, wherein, The first logical register is a matrix with multiple rows and columns of elements, and the physical registers of the first group of physical registers store the matrix.

14. The integrated circuit according to any one of claims 1 to 3, wherein, The first data type is floating-point and the second data type is integer.

15. The integrated circuit according to any one of claims 1 to 3, wherein, The first data type is integer and the second data type is floating-point.

16. The integrated circuit according to any one of claims 1 to 3, wherein, The first data type is Boolean and the registers of the first group of physical registers are single-bit in size.

17. The integrated circuit according to claim 16, wherein, The first execution resource circuit is configured to execute branch instructions.

18. The integrated circuit according to any one of claims 1 to 3, wherein, The first data type is a scalar and the second data type is a half-width scalar.

19. The integrated circuit according to any one of claims 1 to 3, wherein, The first data type is packed SIMD and the second data type is unpacked SIMD.

20. A method for executing instructions, comprising: Determine the data type prediction of the result of the first instruction to be stored in the first logical register; as well as Based on the predicted data type, a first data type is matched, and the first logical register is renamed so that it is stored in the physical register of a first cluster selected from a plurality of clusters, wherein the plurality of clusters includes: A first cluster, comprising a first set of physical registers and a first execution resource circuit, the first execution resource circuit being configured to perform operations taking the contents of one or more registers of the first set of physical registers as input, wherein the input for the operation of the first execution resource circuit is the first data type; and The second cluster includes a second set of physical registers and a second execution resource circuit, the second execution resource circuit being configured to perform operations that take the contents of one or more registers of the second set of physical registers as input, wherein the input for the operation of the second execution resource circuit is a second data type different from the first data type.

21. The method according to claim 20, wherein, The first instruction is an untyped transfer instruction.

22. The method according to claim 20, wherein, The first instruction is a load instruction.

23. The method according to any one of claims 20 to 22, wherein, The data type prediction is determined based on the opcode of the first instruction.

24. The method according to any one of claims 20 to 22, wherein, The data type prediction is determined based on the opcode of a queued instruction that will access the result of the first instruction, wherein the queued instruction is stored in an instruction buffer.

25. The method according to claim 24, wherein, The instruction buffer is a decoding buffer.

26. The method of claim 24, wherein, The instruction buffer is a cache line of the instruction cache.

27. The method according to any one of claims 20 to 22, wherein, The data type prediction is determined based on the current data type of the data currently stored in the first logical register.

28. The method according to any one of claims 20 to 22, wherein, The data type prediction is determined based on the value of the program counter.

29. The method according to any one of claims 20 to 22, comprising: Error prediction is detected, wherein a second instruction to be executed after the first instruction will access the first logical register as input to the second data type; and In response to the error prediction, a micro-operation is issued before the second instruction, wherein the micro-operation copies the value of the first logical register stored in the physical register of the first set of physical registers to the physical register of the second set of physical registers.

30. The method according to any one of claims 20 to 22, comprising: Error prediction is detected, wherein a second instruction to be executed after the first instruction will access the first logical register as input to the second data type; and In response to the error prediction, the second execution resource circuitry uses an alternative data path from the physical registers of the first set of physical registers to the second execution resource circuitry to access the value of the first logical register.

31. The method according to claim 30, wherein, The first logical register is a vector with at least two elements, and the physical registers of the first set of physical registers store the vector.

32. The method according to claim 30, wherein, The first logical register is a matrix with multiple rows and columns of elements, and the physical registers of the first group of physical registers store the matrix.

33. The method according to any one of claims 20 to 22, wherein, The first data type is floating-point and the second data type is integer.

34. The method according to any one of claims 20 to 22, wherein, The first data type is integer and the second data type is floating-point.

35. The method according to any one of claims 20 to 22, wherein, The first data type is a Boolean value and the registers of the first group of physical registers are single-bit in size.

36. The method according to any one of claims 20 to 22, wherein, The first execution resource circuit is configured to execute branch instructions.

37. The method according to any one of claims 20 to 22, wherein, The first data type is a scalar and the second data type is a half-width scalar.

38. The method according to any one of claims 20 to 22, wherein, The first data type is packed SIMD and the second data type is unpacked SIMD.

39. An integrated circuit for executing instructions, comprising: An execution resource circuit, configured to execute instructions on operands stored in physical registers. A set of physical registers, the set of physical registers including a first subset of physical registers located near the execution resource circuitry and a second subset of physical registers located further away from the execution resource circuitry than the registers in the first subset of physical registers, and Register renaming circuit, the register renaming circuit being configured as follows: Detect an instruction sequence stored in an instruction decoding buffer, the instruction sequence comprising multiple sequential references to a first logical register having real dependencies; and Based on the detection of the instruction sequence, the first logical register is renamed to be stored in the physical registers of the first physical register subset, and another logical register referenced in the instruction sequence is renamed to be stored in the physical registers of the second physical register subset.

40. The integrated circuit according to claim 39, wherein, The first logical register is a vector with at least two elements, and the physical registers of the first subset of physical registers store the vector.

41. The integrated circuit according to claim 39, wherein, The first logical register is a matrix with multiple rows and columns of elements, and the physical registers of the first subset of physical registers store the matrix.

42. The integrated circuit according to any one of claims 39 to 41, wherein, The instruction sequence is accumulated in the first logic register.

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