Enhanced semiconductor structure and method of making the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises, from bottom to top, a semiconductor substrate, a heterojunction structure, a cap layer, a first passivation layer, and a second passivation layer; a groove penetrating through the first passivation layer and the second passivation layer; and a P-type semiconductor layer at least on the inner wall of the groove. After the groove is formed by dry etching the second passivation layer, the first passivation layer can be used for etching endpoint detection to avoid over-etching. The first passivation layer exposed at the groove of the second passivation layer can be removed by wet etching. When the first passivation layer is removed by wet etching, the cap layer has very high stability, so that the cap layer is not damaged after the first passivation layer is removed by wet etching. The undamaged cap layer can effectively reduce the surface defects of the heterojunction structure, so as to reduce the probability of electron capture by defects, achieve weakening of the current collapse effect, and reduce the dynamic on-resistance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to an enhancement-mode semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] III-nitride semiconductor is the third generation of semiconductor material after the first and second generation of Si and GaAs. III-nitride semiconductor has high saturated electron mobility, high breakdown voltage and wide band gap. Due to these characteristics, the GaN-based high electron mobility transistor (HEMT) device has broad application prospects.

[0003] The existing III-nitride semiconductor HEMT device has a current collapse phenomenon when used as a high-frequency device or a high-voltage and high-power switching device. That is, when the device works in a direct current pulse mode or a high-frequency mode, the drain output current cannot follow the change of the gate control signal, and the drain current instantaneously decreases and the dynamic on-resistance increases, which seriously affects the application of the device. This phenomenon is ultimately caused by the polarization effect, which brings the two-dimensional electron gas (2DEG) in the heterojunction interface channel, and at the same time, forms a positively charged ionized donor on the surface of the barrier layer in the heterojunction with a charge density comparable to the 2DEG concentration. The principle lies in that when the HEMT device works in the off state, the electric field strength on the gate side of the drain reaches the maximum, and the electrons on the gate are transferred to the surface of the barrier layer under the action of the electric field force, and migrate laterally to the drain direction between the surface donor energy levels, neutralizing the surface ionized donor and depleting the electrons in the channel, forming a "virtual gate". When the working state of the HEMT device changes from off to on, the electrons on the surface of the barrier layer that migrate from the gate will migrate back to the gate at a slow rate. However, when the HEMT device is switched at a certain frequency, the electrons on the surface of the barrier layer cannot migrate back to the gate in time, causing the resistance in the on state to increase, which may be several times the static on-resistance, i.e. current collapse.

[0004] Therefore, it is necessary to provide a new enhancement-mode semiconductor structure and a manufacturing method thereof to solve the above problems. SUMMARY

[0005] The purpose of the present application is to provide an enhancement-mode semiconductor structure and a manufacturing method thereof to solve the problem of current collapse.

[0006] To achieve the above purpose, the first aspect of the present application provides a manufacturing method of an enhancement-mode semiconductor structure, comprising:

[0007] forming a heterojunction structure, a cap layer, a first passivation layer and a second passivation layer on a semiconductor substrate in sequence;

[0008] forming a groove through the first passivation layer and the second passivation layer; the second passivation layer is removed by dry etching, the first passivation layer is used as the etching stop layer during the dry etching; the first passivation layer is removed by wet etching, and the cap layer is used to protect the heterojunction structure during the wet etching;

[0009] forming a P-type semiconductor layer on at least the inner wall of the groove.

[0010] Optionally, the P-type semiconductor layer is a p-GaN layer, a p-AlGaN layer, a stack structure of a p-AlGaN layer and a p-GaN layer, or a stack structure of an AlGaN layer and a p-GaN layer.

[0011] Optionally:

[0012] when the P-type semiconductor layer is a p-GaN layer, the P-type semiconductor layer is formed by a selective growth method, and the P-type semiconductor layer is located only in the groove;

[0013] or when the P-type semiconductor layer is a p-AlGaN layer, the P-type semiconductor layer is formed by a full-area epitaxial growth method and selective etching, and the p-AlGaN layer is also located on the second passivation layer in the gate region;

[0014] or when the P-type semiconductor layer is a stack structure of a p-AlGaN layer and a p-GaN layer distributed from bottom to top, the P-type semiconductor layer is formed by a full-area epitaxial growth method and selective etching, and the stack structure of the p-AlGaN layer and the p-GaN layer is also located on the second passivation layer in the gate region;

[0015] or when the P-type semiconductor layer is a stack structure of an AlGaN layer and a p-GaN layer distributed from bottom to top, the P-type semiconductor layer is formed by a full-area epitaxial growth method and selective etching, and the stack structure of the AlGaN layer and the p-GaN layer is also located on the second passivation layer in the gate region.

[0016] Optionally, the material combination of the second passivation layer and the first passivation layer includes SiNx / amorphous AlN, SiNx / SiO2, or SiO2 / SiNx.

[0017] Optionally, the material of the cap layer is GaN.

[0018] Optionally, a gate is formed on the P-type semiconductor layer, and a source and a drain are formed on both sides of the gate.

[0019] Optionally, the heterojunction structure includes a channel layer and a barrier layer from bottom to top, and the source and the drain contact the channel layer or the barrier layer.

[0020] A second aspect of the present application provides an enhanced semiconductor structure, comprising:

[0021] a semiconductor substrate distributed from bottom to top, a heterojunction structure, a cap layer, a first passivation layer, and a second passivation layer;

[0022] a groove penetrating through the first passivation layer and the second passivation layer;

[0023] and a P-type semiconductor layer at least located on an inner wall of the groove.

[0024] Optionally:

[0025] the P-type semiconductor layer is a p-GaN layer;

[0026] or the P-type semiconductor layer is a p-AlGaN layer, which is also located on the second passivation layer of a gate region;

[0027] or the P-type semiconductor layer is a stacked structure of a p-AlGaN layer and a p-GaN layer distributed from bottom to top, which is also located on the second passivation layer of a gate region;

[0028] or the P-type semiconductor layer is a p-GaN layer, which has an AlGaN layer between the p-GaN layer and the cap layer, and the stacked structure of the AlGaN layer and the p-GaN layer is also located on the second passivation layer of a gate region.

[0029] Optionally, a material combination of the second passivation layer and the first passivation layer comprises: SiNx / amorphous AlN, SiNx / SiO2, or SiO2 / SiNx.

[0030] Optionally, a material of the cap layer is GaN.

[0031] Optionally, the heterojunction structure comprises a group III nitride material.

[0032] Optionally, the semiconductor structure further comprises: a gate located on the P-type semiconductor layer; and a source and a drain located on two sides of the gate.

[0033] Optionally, the heterojunction structure comprises a channel layer and a barrier layer from bottom to top, and the source and the drain contact the channel layer or the barrier layer.

[0034] Optionally, the heterojunction structure comprises a group III nitride material.

[0035] Optionally, the enhanced semiconductor structure further comprises: an N-type ion heavily doped layer on the P-type semiconductor layer of the gate region, and / or on the heterojunction structure of the source region, and / or on the heterojunction structure of the drain region.

[0036] Optionally, the enhanced semiconductor structure further comprises: a gate on the N-type ion heavily doped layer of the gate region, a source on the N-type ion heavily doped layer of the source region, and a drain on the N-type ion heavily doped layer of the drain region.

[0037] Compared with the prior art, the present application has the following beneficial effects:

[0038] 1) After the dry etching of the second passivation layer to form the groove, the first passivation layer can be used for etching endpoint detection when the second passivation layer is dry etched to form the groove, avoiding over-etching. The first passivation layer exposed at the groove of the second passivation layer can be removed by wet etching. When the first passivation layer is removed by wet etching, the cap layer has very high stability, so the wet etching can completely remove the first passivation layer without damaging the cap layer. The undamaged cap layer can effectively reduce the surface defects of the heterojunction structure, thereby reducing the probability of electron capture by defects, increasing the rate of electron release back to the gate, and achieving the effects of weakening the current collapse effect and reducing the dynamic on-resistance.

[0039] 2) In the optional solution, the material of the cap layer is GaN. The negative polarization charge between the GaN cap layer and the heterojunction structure enhances the electric field in the heterojunction structure, which can increase the rate of electron release back to the gate, thereby further weakening the current collapse effect and reducing the dynamic on-resistance.

[0040] 3) In the optional solution, a) the material of the second passivation layer is SiNx, and the material of the first passivation layer is amorphous AlN. SiNx can be removed by dry etching with F-containing gas, and the F-containing gas has a high etching selectivity for SiNx and amorphous AlN, i.e., it has a faster etching rate for SiNx and a slower etching rate for amorphous AlN, so that the dry etching endpoint can be effectively detected and the dry etching can be stopped in time. The amorphous AlN exposed by the second passivation layer can be removed by KOH, NaOH or other alkaline solutions, and KOH, NaOH or other alkaline solutions are non-corrosive on the Ga surface of the GaN cap layer, so that the amorphous AlN can be removed without damaging the GaN cap layer.

[0041] or b) the material of the second passivation layer is SiNx and the material of the first passivation layer is SiO2; or c) the material of the second passivation layer is SiO2 and the material of the first passivation layer is SiNx. SiNx or SiO2 can be removed by dry etching with a mixed gas of CF-based gas and oxygen. By adjusting the mixing ratio of the CF-based gas and oxygen, the etching selectivity of SiNx and SiO2 can be improved or reduced. For example, in the b) scheme, increasing the content of oxygen can significantly improve the etching rate of SiNx, so that the dry etching endpoint of SiO2 can be effectively detected, and the dry etching is stopped in time; in the c) scheme, reducing the content of oxygen can significantly improve the etching rate of SiO2, so that the dry etching endpoint of SiNx can be effectively detected, and the dry etching is stopped in time. The exposed SiO2 of the second passivation layer can be removed by HF acid solution, and SiNx can be removed by hot phosphoric acid solution. HF acid and hot phosphoric acid have no corrosive effect on the GaN cap layer, so that the GaN cap layer is not damaged when the first passivation layer is removed. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 is a flowchart of the manufacturing method of the enhanced semiconductor structure of the first embodiment of the present application;

[0043] Figures 2 to 4 is a schematic diagram of the intermediate structure corresponding to the flowchart in Figure 1

[0044] Figure 5 is a schematic diagram of the cross-sectional structure of the enhanced semiconductor structure of the first embodiment of the present application;

[0045] Figure 5-1 is another schematic diagram of the cross-sectional structure of the enhanced semiconductor structure of the first embodiment of the present application;

[0046] Figure 6 is a schematic diagram of the cross-sectional structure of the enhanced semiconductor structure of the second embodiment of the present application;

[0047] Figure 7 is a flowchart of the manufacturing method of the enhanced semiconductor structure in Figure 6

[0048] Figure 8 is a schematic diagram of the cross-sectional structure of the enhanced semiconductor structure of the third embodiment of the present application;

[0049] Figure 9 is a schematic diagram of the cross-sectional structure of the enhanced semiconductor structure of the fourth embodiment of the present application;

[0050] Figure 10 is a schematic diagram of the cross-sectional structure of the enhanced semiconductor structure of the fifth embodiment of the present application.

[0051] ​​For the convenience of understanding the present application, all the reference signs appearing in the present application are listed as follows:

[0052] Enhanced semiconductor structure 1, 2, 3, 4, 5 Semiconductor substrate 10

[0053] Heterojunction structure 11 Cap layer 12

[0054] First passivation layer 13 Second passivation layer 14

[0055] Recess 15 Patterned mask layer 16

[0056] P-type semiconductor layer 17 N-type ion heavily doped layer 18

[0057] Channel layer 11a Barrier layer 11b

[0058] Gate 19a Source 19b

[0059] Drain 19c Gate region 1a

[0060] Drain region 1c Source region 1b DETAILED DESCRIPTION

[0061] In order to make the above objectives, characteristics and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0062] Figure 1 is a flow chart of the manufacturing method of the enhanced semiconductor structure of the first embodiment of the present application; Figures 2 to 4 is the corresponding intermediate structure schematic diagram of the flow in Figure 1 ; Figure 5 is a cross-sectional structure schematic diagram of the enhanced semiconductor structure of the first embodiment of the present application.

[0063] Firstly, referring to step S1 in Figure 1 and shown in Figure 2 , the heterojunction structure 11, the cap layer 12, the first passivation layer 13 and the second passivation layer 14 are sequentially formed on the semiconductor substrate 10.

[0064] The material of the semiconductor substrate 10 can be a group III nitride material. The group III nitride material can be at least one of GaN, AlGaN, InGaN and AlInGaN.

[0065] It should be noted that in the present embodiment, a chemical element represents a certain material, but the molar proportion of each chemical element in the material is not limited. For example, in the GaN material, Ga element and N element are contained, but the molar proportion of Ga element and N element is not limited; in the AlGaN material, Al, Ga and N elements are contained, but the molar proportions of each are not limited.

[0066] The semiconductor substrate 10 can also include at least one of sapphire, silicon carbide, and silicon, or at least one of sapphire, silicon carbide, and silicon and a group III nitride material thereon, and the embodiments are not limited thereto.

[0067] The heterojunction structure 11 can include, from bottom to top, a channel layer 11a and a barrier layer 11b. A two-dimensional electron gas can be formed at the interface of the channel layer 11a and the barrier layer 11b. Specifically, a) the channel layer 11a and the barrier layer 11b can each have one layer; or b) the channel layer 11a and the barrier layer 11b can each have multiple layers, and are alternately distributed; or c) one channel layer 11a and two or more barrier layers 11b, to meet different functional requirements.

[0068] The material combination of the channel layer 11a and the barrier layer 11b can include GaN / AlN, GaN / InN, GaN / AlGaN, GaAs / AlGaAs, GaN / InAlN, or InN / InAlN.

[0069] When the material of the barrier layer 11b is AlGaN, the mole percentage range of Al can include 5% to 25%, and the thickness range can include 1 nm to 20 nm.

[0070] The forming process of the channel layer 11a and / or the barrier layer 11b can include atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), or a combination thereof.

[0071] The heterojunction structure 11 and the semiconductor substrate 10 may also have a nucleation layer and a buffer layer (not shown) from bottom to top. The nucleation layer can be made of materials such as AlN or AlGaN, and the buffer layer can be made of at least one of AlN, GaN, AlGaN, and AlInGaN. The nucleation layer can alleviate the problems of lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layer, such as the channel layer 11a in the heterojunction structure 11, and the semiconductor substrate 10. The buffer layer can reduce the dislocation density and defect density of the epitaxially grown semiconductor layer, thereby improving the crystal quality.

[0072] The cap layer 12 can be made of GaN. The upper surface of the GaN cap layer can be a Ga surface. The GaN crystal has a wurtzite structure, in which the Ga and N atomic layers are stacked in an ABABAB hexagonal layer, and each Ga(N) atom is bonded to the surrounding 4 N(Ga) atoms in a diamond-like tetrahedral structure. It should be noted that, taking the Ga-N bond parallel to the C-axis (

[0001] crystal direction) as a reference, if the Ga atom in each Ga-N bond is further away from the lower surface, then the upper surface is a Ga surface; if the N atom in each Ga-N bond is further away from the lower surface, then the upper surface is an N surface.

[0073] The formation method of the cap layer 12 can refer to the formation process of the channel layer 11a or the barrier layer 11b.

[0074] The material of the first passivation layer 13 can be amorphous AlN; the material of the second passivation layer 14 can be SiNx. Other alternatives include a material combination of SiNx / SiO2 or SiO2 / SiNx for the second passivation layer 14 and the first passivation layer 13. The formation process of amorphous AlN can include: metal-organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The formation process of SiNx or SiO2 can include: chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0075] In addition, the second passivation layer 14 can also be SiNx formed by low-pressure chemical vapor deposition (LPCVD), and the first passivation layer 13 can be SiNx formed by plasma-enhanced chemical vapor deposition (PECVD).

[0076] The structure includes a gate region 1a, and a source region 1b and a drain region 1c located on both sides of the gate region 1a.

[0077] Next, refer to Figure 1 Step S2 in Figures 2 to 4As shown, the groove 15 is formed through the first passivation layer 13 and the second passivation layer 14; the second passivation layer 14 is removed by dry etching, and the first passivation layer 13 is used as the etching stop layer during dry etching; the first passivation layer 13 is removed by wet etching, and the cap layer 12 is used to protect the heterojunction structure 11 during wet etching.

[0078] Referring to Figure 2 As shown, the dry etching can use a patterned mask layer 16 as the mask. The material of the patterned mask layer 16 can be photoresist.

[0079] Referring to Figure 3 As shown, in this embodiment, the wet etching is maskless etching. In other embodiments, the wet etching can also use a mask layer as the mask, and the mask layer has a window exposing the first passivation layer 13.

[0080] When the material of the second passivation layer 14 is SiNx and the material of the first passivation layer 13 is amorphous AlN: SiNx can be removed by dry etching using F-containing gas (CF4, or C3F8, etc.), and the F-containing gas has a high etching selectivity ratio for SiNx and amorphous AlN, that is, it has a faster etching rate for SiN and a slower etching rate for amorphous AlN, so that the dry etching endpoint can be effectively detected, and the dry etching is stopped in time. The amorphous AlN exposed by the second passivation layer 14 can be removed by using KOH, NaOH, or other alkaline solutions, and KOH, NaOH, or other alkaline solutions are non-corrosive on the Ga surface of the GaN cap layer, so that the amorphous AlN is removed without damaging the GaN cap layer.

[0081] When the material of the second passivation layer 14 is SiNx and the material of the first passivation layer 13 is SiO2: SiNx can be removed by dry etching using a mixed gas of CF-based gas and oxygen, and the etching rate of SiN can be significantly increased by adjusting the mixing ratio of CF-based gas and oxygen, for example, by increasing the content of oxygen, so that the dry etching endpoint of SiO2 can be effectively detected, and the dry etching is stopped in time. The SiO2 exposed by the second passivation layer 14 can be removed by using HF acid solution, and HF acid is non-corrosive to the GaN cap layer, so that the first passivation layer 13 is removed without damaging the GaN cap layer.

[0082] When the material of the second passivation layer 14 is SiO2 and the material of the first passivation layer 13 is SiNx, the SiO2 can be removed by dry etching using a mixed gas of CF-based gas and oxygen. By adjusting the mixing ratio of the CF-based gas and oxygen, for example, by reducing the content of oxygen, the etching rate of SiO2 can be significantly improved, so that the dry etching endpoint can be effectively detected, and the dry etching is stopped in time. The exposed SiNx of the second passivation layer 14 can be removed by a hot phosphoric acid solution, and the hot phosphoric acid has no corrosive effect on the GaN cap layer. Therefore, while the first passivation layer 13 is removed, the GaN cap layer is not damaged.

[0083] Thereafter, referring to steps S3 and S4 in FIG. 3, at least a P-type semiconductor layer 17 is formed on the inner wall of the groove 15. Figure 1 Figure 5

[0084] In this embodiment, the P-type semiconductor layer 17 can deplete the two-dimensional electron gas in the heterojunction structure 11 and turn off the conduction of the channel. That is, the P-type semiconductor layer 17 forms an always-off state, i.e., forms an enhancement mode structure.

[0085] The material of the P-type semiconductor layer 17 can be a group III nitride material, and the corresponding formation method can refer to the formation process of the channel layer 11a or the barrier layer 11b. The P-type doping ions can be at least one of Mg ions, Zn ions, Ca ions, Sr ions, or Ba ions. In-situ doping can be used, i.e., doping while growing.

[0086] More specifically, Figure 5 In the embodiment shown in FIG. 4, the material of the P-type semiconductor layer 17 formed is p-AlGaN. The p-AlGaN layer can be epitaxially grown on the inner wall of the groove 15 and the second passivation layer 14. Then, by dry etching or wet etching, the p-AlGaN layer outside the gate region 1a is removed, and the p-AlGaN layer on the second passivation layer 14 of the gate region 1a is retained.

[0087] The dry etching can be inductively coupled plasma etching (ICP). The etching gas can include Cl2 and BCl3. The wet etching can use an alkaline solution such as KOH or NaOH.

[0088] In some embodiments, the P-type semiconductor layer 17 formed can also be a stacked structure of a p-AlGaN layer and a p-GaN layer distributed from bottom to top. At this time, the stacked structure of the p-AlGaN layer and the p-GaN layer is not only located on the inner wall of the groove 15, but also located on the second passivation layer 14 of the gate region 1a.

[0089] ​​In some embodiments, the material of the formed P-type semiconductor layer 17 is an AlGaN and p-GaN stacked structure distributed from bottom to top. In this case, before forming the P-type semiconductor layer 17, an AlGaN layer is first formed on the inner wall of the groove 15 and on the second passivation layer 14; then, the stacked structure of the AlGaN layer and p-GaN layer outside the gate region 1a is removed by dry etching or wet etching, while retaining the stacked structure of the AlGaN layer and p-GaN layer on the second passivation layer 14 of the gate region 1a.

[0090] In some embodiments, such as Figure 5-1 As shown, the material of the formed P-type semiconductor layer 17 is p-GaN, and the p-GaN layer can only be selectively epitaxially grown in the groove 15.

[0091] Reference Figure 5 and Figure 5-1 As shown, the enhanced semiconductor structure 1 of this embodiment includes:

[0092] The semiconductor substrate 10, heterojunction structure 11, cap layer 12, first passivation layer 13 and second passivation layer 14 are distributed from bottom to top.

[0093] The groove 15 penetrating the first passivation layer 13 and the second passivation layer 14 (see reference) Figure 4 (as shown);

[0094] And at least a P-type semiconductor layer 17 located on the inner wall of the groove 15.

[0095] The semiconductor substrate 10 can be a group III nitride material. The group III nitride material can be at least one of GaN, AlGaN, InGaN, and AlInGaN.

[0096] The semiconductor substrate 10 may also include at least one of sapphire, silicon carbide and silicon, or at least one of sapphire, silicon carbide and silicon and a group III nitride material thereon, which is not limited in this embodiment.

[0097] The heterojunction structure 11 may include a channel layer 11a and a barrier layer 11b from bottom to top. A two-dimensional electron gas may be formed at the interface between the channel layer 11a and the barrier layer 11b. Specifically, a) the channel layer 11a and the barrier layer 11b may each have one layer; or b) the channel layer 11a and the barrier layer 11b may each have multiple layers, which are alternately distributed; or c) one channel layer 11a and two or more barrier layers 11b to meet different functional requirements.

[0098] The material combination of the channel layer 11a and the barrier layer 11b may include: GaN / AlN, GaN / InN, GaN / AlGaN, GaAs / AlGaAs, GaN / InAlN, or InN / InAlN.

[0099] When the material of the barrier layer 11b is AlGaN, the molar percentage of Al can range from 5% to 25%, and the thickness can range from 1 nm to 20 nm.

[0100] The heterojunction structure 11 and the semiconductor substrate 10 can further have a nucleation layer and a buffer layer (not shown) from bottom to top. The material of the nucleation layer can be, for example, AlN, AlGaN, etc., and the material of the buffer layer can include at least one of AlN, GaN, AlGaN, and AlInGaN. The nucleation layer can alleviate the problems of lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layer, such as the channel layer 11a in the heterojunction structure 11, and the semiconductor substrate 10, and the buffer layer can reduce the dislocation density and defect density of the epitaxially grown semiconductor layer, thereby improving the crystal quality.

[0101] The material of the cap layer 12 can be GaN. The upper surface of the GaN cap layer can be a Ga face. The GaN crystal has a wurtzite structure, in which the Ga and N atomic layers are stacked in an ABABAB hexagonal layer, and each Ga(N) atom is bonded to the surrounding 4 N(Ga) atoms in a diamondoid tetrahedral structure. It should be noted that, with reference to the Ga-N bond parallel to the C axis (

[0001] direction), if the Ga atom in each Ga-N bond is further away from the lower surface, the upper surface is a Ga face; if the N atom in each Ga-N bond is further away from the lower surface, the upper surface is an N face.

[0102] The material of the first passivation layer 13 can be amorphous AlN, and the material of the second passivation layer 14 can be SiNx. In other optional solutions, the material combination of the second passivation layer 14 and the first passivation layer 13 can also be SiNx / SiO2 or SiO2 / SiNx. In addition, the second passivation layer 14 can be SiNx formed by low-pressure chemical vapor deposition (LPCVD), and the first passivation layer 13 can be SiNx formed by plasma-enhanced chemical vapor deposition (PECVD).

[0103] Figure 5 In the illustrated embodiment, the P-type semiconductor layer 17 is a p-AlGaN layer. The p-AlGaN layer is not only located on the inner wall of the groove 15, but also on the second passivation layer 14 of the gate region 1a.

[0104] In some embodiments, the P-type semiconductor layer 17 can also be a stacked structure of a p-AlGaN layer and a p-GaN layer distributed from bottom to top. At this time, the stacked structure of the p-AlGaN layer and the p-GaN layer is not only located on the inner wall of the groove 15, but also on the second passivation layer 14 of the gate region 1a.

[0105] In some embodiments, the P-type semiconductor layer 17 is a p-GaN layer. In this case, an AlGaN layer is further provided between the p-GaN layer and the cap layer 12. The stack of the AlGaN layer and the p-GaN layer is not only provided on the inner wall of the trench 15, but also on the second passivation layer 14 of the gate region la.

[0106] In some embodiments, the P-type semiconductor layer 17 is a p-GaN layer, and the p-GaN layer is only provided in the trench 15.

[0107] The second passivation layer 14 can reduce the channel leakage to the gate 19a (see Figure 6 ) formed by the gate leakage current.

[0108] By providing the first passivation layer 13, the cap layer 12 can be formed without damage in the etching process of the trench 15. The cap layer 12 without damage can effectively reduce the surface defects of the heterojunction structure 11, so as to reduce the probability of the electrons being captured by the defects, thereby increasing the rate of the electrons being released back to the gate 19a (see Figure 6 ) to weaken the current collapse effect and reduce the dynamic on-resistance. On the other hand, when the material of the cap layer 12 is GaN, the negative polarization charge between the GaN cap layer and the heterojunction structure 11 can further increase the rate of the electrons being released back to the gate 19a (see Figure 6 ) to further weaken the current collapse effect and reduce the dynamic on-resistance.

[0109] The enhancement-mode semiconductor structure 1 can be produced and sold as a semi-finished product of a semiconductor device.

[0110] Figure 6 is a cross-sectional structure diagram of an enhancement-mode semiconductor structure according to a second embodiment of the present application, Figure 7 is a flowchart of a manufacturing method of the enhancement-mode semiconductor structure in Figure 6 .

[0111] Referring to Figure 6 and Figure 7 , the enhancement-mode semiconductor structure 2 and the manufacturing method thereof according to the second embodiment are substantially the same as the enhancement-mode semiconductor structure 1 and the manufacturing method thereof according to the first embodiment, and the difference is that the enhancement-mode semiconductor structure 2 further includes: a gate 19a provided on the P-type semiconductor layer 17; and a source 19b and a drain 19c provided on both sides of the gate 19a.

[0112] Correspondingly, referring to Figure 7 , the manufacturing method further includes: in step S4, forming the gate 19a on the P-type semiconductor layer 17, and forming the source 19b and the drain 19c on both sides of the gate 19a.

[0113] Specifically, the second passivation layer 14, the first passivation layer 13 and the cap layer 12 of the source region 1b and the drain region 1c are removed.

[0114] In this embodiment two, the source 19b and the drain 19c contact the barrier layer 11b and form an ohmic contact therebetween. The gate 19a also forms an ohmic contact with the P-type semiconductor layer 17. The source 19b, the drain 19c and the gate 19a can be made of metal, such as Ti / Al / Ni / Au, Ni / Au and other existing conductive materials.

[0115] The ohmic contact between the source 19b and the barrier layer 11b, the ohmic contact between the drain 19c and the barrier layer 11b, and the ohmic contact between the gate 19a and the P-type semiconductor layer 17 can be formed by high-temperature annealing.

[0116] Figure 8 is a schematic diagram of the cross-sectional structure of the enhanced semiconductor structure of the third embodiment of the present application.

[0117] Referring to Figure 8 The enhanced semiconductor structure 3 of this embodiment three and the method of manufacturing the same are substantially the same as the enhanced semiconductor structure 2 of embodiment two and the method of manufacturing the same, except that the source 19b and the drain 19c contact the channel layer 11a and form an ohmic contact therebetween.

[0118] Correspondingly, in step S4 of the method of manufacturing, the second passivation layer 14, the first passivation layer 13, the cap layer 12 of the source region 1b and the drain region 1c are removed, and the barrier layer 11b is also removed.

[0119] The ohmic contact between the source 19b and the channel layer 11a, and the ohmic contact between the drain 19c and the channel layer 11a can be formed by high-temperature annealing.

[0120] Figure 9 is a schematic diagram of the cross-sectional structure of the enhanced semiconductor structure of the fourth embodiment of the present application.

[0121] Referring to Figure 9 The enhanced semiconductor structure 4 of this embodiment four is substantially the same as the enhanced semiconductor structures 2, 3 of embodiment two and embodiment three, except that the enhanced semiconductor structure 4 further comprises an N-type ion heavily doped layer 18 between the heterojunction structure 11 of the source region 1b and the source 19b, and between the heterojunction structure 11 of the drain region 1c and the drain 19c.

[0122] The P-type semiconductor layer 17 of the gate region 1a also has an N-type ion heavily doped layer 18 between the gate 19a.

[0123] The material of the N-type ion heavily doped layer 18 can be a group III nitride material, such as at least one of GaN, AlGaN, and AlInGaN, wherein the N-type dopant ion can be at least one of Si ions, Ge ions, Sn ions, Se ions, or Te ions; the corresponding formation method can refer to the formation process of the channel layer 11a or the barrier layer 11b. For different N-type ions, the doping concentration can be greater than 1E19 / cm3.

[0124] The N-type ion-doped layer 18 enables the source 19b to directly form an ohmic contact with the heterojunction structure 11, the drain 19c to the heterojunction structure 11, and the gate 19a to the P-type semiconductor layer 17 without high-temperature annealing, and avoids the performance degradation and electron migration rate reduction of the heterojunction structure 11 caused by the high temperature during the annealing process.

[0125] In some embodiments, at least one of the P-type semiconductor layer 17, the heterojunction structure 11 of the source region 1b, and the heterojunction structure 11 of the drain region 1c may have an N-type ion heavily doped layer 18. The P-type semiconductor layer 17 without the N-type ion heavily doped layer 18 and the gate 19a, the heterojunction structure 11 of the source region 1b without the N-type ion heavily doped layer 18 and the source 19b, or the heterojunction structure 11 of the drain region 1c without the N-type ion heavily doped layer 18 and the drain 19c may form an ohmic contact through high-temperature annealing.

[0126] Figure 10 This is a cross-sectional schematic diagram of the enhanced semiconductor structure according to the fifth embodiment of the present invention.

[0127] Reference Figure 10 As shown, the enhanced semiconductor structure 5 and its fabrication method in this embodiment are largely the same as the enhanced semiconductor structure 4 and its fabrication method in embodiment four, except that the enhanced semiconductor structure 5 is an intermediate semiconductor structure and does not have a gate 19a, a source 19b, and a drain 19c fabricated.

[0128] Correspondingly, step S4 is omitted from the manufacturing method.

[0129] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for fabricating an enhanced semiconductor structure, characterized in that, include: A heterojunction structure (11), a cap layer (12), a first passivation layer (13), and a second passivation layer (14) are sequentially formed on a semiconductor substrate (10); A groove (15) is formed that penetrates the first passivation layer (13) and the second passivation layer (14); the second passivation layer (14) is removed by dry etching, and the first passivation layer (13) is used as the etching termination layer during the dry etching; the first passivation layer (13) is removed by wet etching, and the cap layer (12) is used to protect the heterojunction structure (11) during the wet etching. A P-type semiconductor layer (17) is formed at least on the inner wall of the groove (15), penetrating the first passivation layer (13) and the second passivation layer (14), wherein the thickness of the P-type semiconductor layer (17) is less than the thickness of the first passivation layer (13); and An N-type ion heavily doped layer (18) is formed on the P-type semiconductor layer (17), wherein the N-type ion heavily doped layer (18) penetrates the second passivation layer (14) and a portion of the first passivation layer (13).

2. The method for fabricating an enhanced semiconductor structure according to claim 1, characterized in that, The P-type semiconductor layer (17) is a stacked structure of p-GaN, p-AlGaN, p-AlGaN and p-GaN layers, or an AlGaN and p-GaN layer.

3. The method for fabricating an enhanced semiconductor structure according to claim 2, characterized in that: When the P-type semiconductor layer (17) is a p-GaN layer, the P-type semiconductor layer (17) is fabricated by a selective growth method, and the P-type semiconductor layer (17) is located only in the groove (15); Or when the P-type semiconductor layer (17) is a p-AlGaN layer, the P-type semiconductor layer (17) is fabricated by a full-surface epitaxial growth method and selective etching, and the p-AlGaN layer is also located on the second passivation layer (14) in the gate region; Or, when the P-type semiconductor layer (17) is a stacked structure of p-AlGaN layer and p-GaN layer distributed from bottom to top, the P-type semiconductor layer (17) is fabricated by full-surface epitaxial growth and selective etching, and the stacked structure of p-AlGaN layer and p-GaN layer is also located on the second passivation layer (14) in the gate region. Or, when the P-type semiconductor layer (17) is a stacked structure of AlGaN layer and p-GaN layer distributed from bottom to top, the P-type semiconductor layer (17) is fabricated by full-surface epitaxial growth and selective etching, and the stacked structure of AlGaN layer and p-GaN layer is also located on the second passivation layer (14) in the gate region.

4. The method for fabricating an enhanced semiconductor structure according to claim 1, characterized in that, The material combination of the second passivation layer (14) and the first passivation layer (13) includes: SiNx / amorphous AlN, SiNx / SiO2, or SiO2 / SiNx.

5. The method for fabricating an enhanced semiconductor structure according to claim 1, characterized in that, The material of the cap layer (12) is GaN.

6. The method for fabricating an enhanced semiconductor structure according to claim 1, characterized in that, A gate (19a) is formed on the P-type semiconductor layer (17), and a source (19b) and a drain (19c) are formed on both sides of the gate (19a).

7. The method for fabricating an enhanced semiconductor structure according to claim 6, characterized in that, The heterojunction structure (11) includes a channel layer (11a) and a barrier layer (11b) from bottom to top, and the source (19b) and drain (19c) are in contact with the channel layer (11a) or the barrier layer (11b).

8. An enhanced semiconductor structure, characterized in that, include: The semiconductor substrate (10), heterojunction structure (11), cap layer (12), first passivation layer (13) and second passivation layer (14) are distributed from bottom to top; A groove (15) penetrating the first passivation layer (13) and the second passivation layer (14); and a P-type semiconductor layer (17) located at least on the inner wall of the groove (15) and penetrating the first passivation layer (13) and the second passivation layer (14), wherein the thickness of the P-type semiconductor layer (17) is less than the thickness of the first passivation layer (13); and An N-type ion heavily doped layer (18) is formed on the P-type semiconductor layer (17), wherein the N-type ion heavily doped layer (18) penetrates the second passivation layer (14) and a portion of the first passivation layer (13).

9. The enhanced semiconductor structure according to claim 8, characterized in that: The P-type semiconductor layer (17) is a p-GaN layer; Alternatively, the P-type semiconductor layer (17) may be a p-AlGaN layer, and the p-AlGaN layer may also be located on the second passivation layer (14) in the gate region; Alternatively, the P-type semiconductor layer (17) may be a stacked structure of p-AlGaN layers and p-GaN layers distributed from bottom to top, and the stacked structure of p-AlGaN layers and p-GaN layers may also be located on the second passivation layer (14) in the gate region; Alternatively, the P-type semiconductor layer (17) may be a p-GaN layer, and an AlGaN layer may be present between the p-GaN layer and the cap layer (12). The stacked structure of the AlGaN layer and the p-GaN layer may also be located on the second passivation layer (14) in the gate region.

10. The enhanced semiconductor structure according to claim 8, characterized in that, The material combination of the second passivation layer (14) and the first passivation layer (13) includes: SiNx / amorphous AlN, SiNx / SiO2, or SiO2 / SiNx.

11. The enhanced semiconductor structure according to claim 8, characterized in that, The material of the cap layer (12) is GaN.

12. The enhanced semiconductor structure according to claim 8, characterized in that, The heterojunction structure (11) includes group III nitride materials.

13. The enhanced semiconductor structure according to claim 8, characterized in that, The semiconductor structure further includes: a gate (19a) located on the P-type semiconductor layer (17); and a source (19b) and a drain (19c) located on both sides of the gate (19a).

14. The enhanced semiconductor structure according to claim 13, characterized in that, The heterojunction structure (11) includes a channel layer (11a) and a barrier layer (11b) from bottom to top, and the source (19b) and drain (19c) are in contact with the channel layer (11a) or the barrier layer (11b).

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