Chips, chip voltage regulation systems and related products

Abstract

The present disclosure relates to a chip voltage regulation system, which can be implemented in a circuit board, the circuit board includes a chip and other supporting components, the supporting components include but are not limited to: a memory device, an interface device and a control device. The memory device is connected to the chip in the chip packaging structure through a bus, and is used to store data. The memory device may include multiple groups of storage units.

Description

Technical Field

[0001] The present disclosure relates to the field of circuits, and more specifically, to the field of voltage regulation of chips. Background Art

[0002] With the advancement of chip process scale, the size of chips is becoming smaller and smaller, while the integration is getting higher and higher, which also leads to higher and higher power consumption of chips. Therefore, reducing the power consumption of chips has become an issue that needs to be considered. Generally, the power consumption of a chip is related to its operating voltage and operating frequency. Therefore, dynamically adjusting the operating voltage of the chip according to the operating frequency is a commonly used way to save power, namely DVFS (Dynamic Voltage Frequency Scaling). In this technology, the operating voltage of the chip can be dynamically adjusted according to the operating frequency of the chip, that is, the operating voltage of the chip is reduced when the operating frequency is low, and the operating voltage of the chip is raised when the operating frequency is high. Through this dynamic power supply method, chip energy saving can be effectively achieved.

[0003] There are many ways to achieve DVFS. For example, the required voltage can be converted into a series of digital codes, and the digital codes are transmitted to the VRM (Voltage Regulating Module) through a dedicated digital signal interface. The VRM then converts the digital code into the voltage value that needs to be adjusted and outputs the voltage value. However, the timing of the existing digital signal interface is relatively complex and uses more signal lines. As chip functions become more and more complex, the integration of functional modules becomes higher and higher, and pin resources become more and more limited, how to use fewer signal lines and simpler logic to achieve DVFS has become a problem that needs to be solved. Summary of the invention

[0004] The purpose of the present disclosure is to achieve dynamic voltage and frequency regulation through fewer connections and simpler logic, thereby solving the problems of complex logic and high resource usage in the prior art.

[0005] According to a first aspect of the present disclosure, a chip 1 is provided, comprising: a frequency voltage adaptive adjustment FVAS module 11, a voltage frequency conversion VFC module 12, a notification signal generating module 13, a notification signal sending terminal 14 and a voltage input terminal 15, wherein the FVAS module 11 is used to determine the operating frequency and the corresponding target voltage of the chip according to the load of the chip; the VFC module 12 is connected to the FVAS module 11, and is used to determine the notification frequency of the notification signal according to the target voltage; the notification signal generating module 13 is connected to the VFC module 12, and is used to generate a notification signal with the notification frequency according to the determined notification frequency; the notification signal sending terminal 14 is connected to the notification signal generating module 13, and is used to send the notification signal; and the voltage input terminal 15 is used to receive a power supply with the target voltage, so that the chip works at the operating frequency, wherein the power supply is generated according to the notification signal.

[0006] According to a second aspect of the present disclosure, a chip voltage regulation system is provided, comprising the chip 1 and a voltage regulation device 2 as described above, wherein the voltage regulation device 2 comprises: a notification signal detection module 21, a frequency-to-voltage conversion FVC module 22, a voltage regulation VR module 23, a notification signal receiving terminal 24 and a voltage output terminal 25, wherein the notification signal receiving terminal 24 is connected to the notification signal sending terminal 14 for receiving the notification signal; the notification signal detection module 21 is connected to the notification signal receiving terminal 24 for detecting the notification frequency of the notification signal; the FVC module 22 is connected to the notification signal detection module 21 for determining the target voltage according to the notification frequency of the notification signal; the VR module 23 is connected to the FVC module 22 for adjusting the reference voltage according to the determined target voltage to generate the target voltage; and the voltage output terminal 25 is connected to the VR module 23 for outputting the generated target voltage to the voltage input terminal 15 in the chip.

[0007] According to a third aspect of the present disclosure, a chip voltage regulation system is provided, comprising the chip 1 as described above, a voltage regulation device 2 and a control device 3, wherein the voltage regulation device 2 comprises: a voltage regulation VR module 23, a voltage signal receiving terminal 26 and a voltage output terminal 25, the control device 3 comprises a notification signal receiving terminal 34, a notification signal detection module 31, a frequency voltage conversion FVC module 32 and a voltage signal sending terminal 36, wherein the notification signal receiving terminal 34 is connected to the notification signal sending terminal 14 for receiving the notification signal; the notification signal detection module 31 is connected to the notification signal receiving terminal 34 for detecting the notification frequency of the notification signal; the FVC module 32 is connected to the notification signal detection module 31 for detecting the notification frequency of the notification signal; The detection module 31 is connected to determine the target voltage according to the notification frequency of the notification signal; the voltage signal sending terminal 36 is connected to the FVC module 32, and is used to receive the voltage value of the target voltage from the FVC module 32; the voltage signal receiving terminal 26 is connected to the voltage signal sending terminal 36, and is used to receive the voltage value of the target voltage from the voltage signal sending terminal 36; the VR module 23 is connected to the voltage signal receiving terminal 26, and is used to adjust the reference voltage according to the determined voltage value of the target voltage to generate the target voltage; and the voltage output terminal 25 is connected to the VR module 23, and is used to output the generated target voltage to the voltage input terminal 15 in the chip.

[0008] According to a fourth aspect of the present disclosure, a circuit board is provided, comprising the chip as described above, or the system as described above.

[0009] According to a fifth aspect of the present disclosure, there is provided an electronic device, comprising the circuit board as described above.

[0010] Some beneficial effects of the technical solution disclosed in the present invention include that only one signal line and simple communication logic are needed to realize dynamic voltage regulation of the chip. With more and more chip functional modules and increasingly limited pin resources and logic resources, precious pin resources and logic resources are greatly saved. At the same time, chip power consumption can be saved and energy utilization efficiency can be improved.

[0011] The technical solution of the present disclosure also involves other beneficial effects, which will be described in detail in the subsequent description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] By reading the detailed description below with reference to the accompanying drawings, the above and other purposes, features and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0013] Figure 1 A schematic diagram of a chip according to a first embodiment of the present disclosure is shown;

[0014] Figure 2 shows a schematic diagram of a FVAS module 11 according to one embodiment of the present disclosure;

[0015] Figure 3 A schematic diagram of a chip voltage regulation system according to a second embodiment of the present disclosure is shown;

[0016] Figure 4 FIG. 2 shows a schematic diagram of a VR module 23 for generating a target voltage according to an embodiment of the present disclosure;

[0017] Figure 5 A schematic diagram of a chip voltage regulation system according to a third embodiment of the present disclosure is shown;

[0018] Figure 6a A schematic diagram of a chip voltage regulation system according to a fourth embodiment of the present disclosure is shown;

[0019] Figure 6b A schematic diagram of a chip voltage regulation system according to a fifth embodiment of the present disclosure is shown;

[0020] Figure 6c A schematic diagram showing a chip voltage regulation system according to a sixth embodiment of the present disclosure; and

[0021] Figure 7 A schematic diagram of a circuit board is shown. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0023] The specific embodiments of the present disclosure will be explained in detail below with reference to the accompanying drawings.

[0024] Implementation Method 1

[0025] Figure 1 A schematic diagram of a chip according to a first embodiment of the present disclosure is shown.

[0026] like Figure 1As shown, the chip 1 of the present disclosure includes: a frequency voltage adaptive adjustment (Frequency Voltage Adaptive Scaling) FVAS module 11, a voltage frequency conversion (Voltage Frequency Converter) VFC module 12, a notification signal generating module 13, a notification signal sending terminal 14 and a voltage input terminal 15.

[0027] The above-mentioned components 11 to 15 can be implemented by using inherent software, hardware, firmware, terminals, interfaces, pins, etc. in the chip, or can be implemented as separate hardware circuits, sub-chips, etc. For example, they can be implemented as FVAS circuits, VFC circuits, notification signal generating circuits, etc. Therefore, the "module" referred to in this article includes pure hardware implementation, pure software implementation, and implementation of a combination of hardware and software. It should also be understood that the "pin" referred to in this article is usually a pin included in an interface. When a digital signal pin is used in this article, it refers to the corresponding pin in the digital signal interface, and when an analog signal pin is used in this article, it refers to the corresponding pin in the analog signal interface.

[0028] More specifically, the FVAS module 11 may be used to determine the operating frequency of the chip and the corresponding target voltage according to the load of the chip 1 .

[0029] The load of the chip can be the amount of data involved in the calculation, the amount of data involved in the communication, the complexity of the calculation, etc. As these factors change, the load of the chip may also change. It can be understood that if the processing load of the chip increases, the operating frequency of the chip can be increased to improve the processing efficiency; and if the processing load of the chip decreases, the operating frequency of the chip can be reduced to reduce power consumption. Accordingly, if the operating frequency of the chip increases, it is necessary to increase the target voltage corresponding to the operating frequency; or, if the operating frequency of the chip decreases, the target voltage corresponding to the operating frequency can be reduced. The correspondence between the operating frequency and the target voltage will be described in detail below.

[0030] Figure 2 FIG. 1 is a schematic diagram of a FVAS module 11 according to an embodiment of the present disclosure. Figure 2 As shown, the FVAS module 11 may include: a task detection unit 110 and a frequency-voltage mapping unit 112, wherein the task detection unit 110 is used to determine the operating frequency required by the load according to the load of the chip; and the frequency-voltage mapping unit 112 is used to determine the corresponding target voltage according to the operating frequency.

[0031] like Figure 2As shown, the task detection unit 110 first detects the load of the chip, and determines the required operating frequency of the chip according to the size or change (such as increase or decrease) of the load. As mentioned above, the greater the load, the higher the required operating frequency, and the smaller the load, the lower the required operating frequency.

[0032] After the task detection unit 110 determines the corresponding operating frequency according to the load size, the frequency-voltage mapping unit 112 may determine the corresponding target voltage according to the determined operating frequency, so that the chip can stably operate at the corresponding operating frequency.

[0033] The corresponding target voltage can be determined according to the operating frequency in a variety of ways, which may include determining the corresponding target voltage according to the operating frequency in a linear relationship; or may include discretely determining the corresponding target voltage according to the operating frequency in a segmented relationship (such as a lookup table).

[0034] According to one embodiment of the present disclosure, the frequency-voltage mapping unit 112 may be used to determine the corresponding target voltage Vt according to the operating frequency in the following linear relationship:

[0035] Vt=Vmin+k*F0 Equation (1)

[0036] Among them, Vmin represents the minimum operating voltage of the chip, k represents the adjustment coefficient, and F0 represents the operating frequency of the chip.

[0037] In the above, Vmin is the minimum voltage to ensure that the chip maintains normal operation when in an idle state. If the voltage is lower than the minimum operating voltage Vmin, the chip cannot operate normally. The adjustment coefficient k can be set in advance to set the corresponding k value according to the different requirements of each chip.

[0038] According to another embodiment of the present disclosure, the frequency-voltage mapping unit 112 may be configured to determine a corresponding target voltage according to an operating frequency in a segmented manner.

[0039] The following equation group (2) shows an example of determining the corresponding target voltage in a piecewise relationship.

[0040]

[0041] As shown in equation group (2), when the operating frequency is between 0 and f 0 When the target voltage is between V 0 ; When the operating frequency is f 0 and f 1 When the target voltage is between V 1 ; and when the operating frequency is f 1 and f2 When the target voltage is between V 2 In this embodiment, a lookup table can be formed, and the target voltage corresponding to each operating frequency can be determined by the lookup table. It should be understood that the equation group (2) is only an example, and the target voltage can be divided into more or fewer segments, and is not limited to the segmentation method shown in the equation group (2).

[0042] The functions and implementation methods of the FVAS module 11 are described above, and the VFC module 12 is described next. According to one embodiment of the present disclosure, the VFC module 12 is connected to the FVAS module 11, and is used to determine the notification frequency of the notification signal according to the target voltage. The notification signal can be a pulse frequency modulation (Pulse Frequency Modulation) PFM signal. PFM signals of different frequencies represent different voltages. When the voltage changes, the frequency of the PFM signal also changes. The use of the PFM signal does not require complex digital communication interface logic.

[0043] After the target voltage Vt is determined, the target voltage Vt needs to be notified to the voltage regulator outside the chip so that the voltage regulator can generate the required target voltage. In the prior art, notifications about the target voltage are sent in the form of digital signals, which requires more pins and more complex control logic, which is not conducive to the efficient use of the limited number of pins in the chip. In the present disclosure, corresponding notification signals can be generated according to the required target voltage, and each notification signal has a notification frequency corresponding to the target voltage.

[0044] It should be understood that the notification frequency of the notification signal may be completely different from the operating frequency of the chip. Generally speaking, the operating frequency of the chip is several GHz, while the frequency of the notification signal may be several KHz to several MHz or even higher or lower.

[0045] According to one embodiment of the present disclosure, the VFC module 12 may be used to determine the notification frequency Fn of the notification signal according to the target voltage in a linear relationship as follows:

[0046]

[0047] Among them, Vt represents the target voltage, Vd represents the default operating voltage of the chip, and Fd represents the default notification frequency of the chip under the default operating voltage.

[0048] The default operating voltage Vd mentioned here refers to the voltage at which the chip usually works, such as the operating voltage set when the chip leaves the factory; Fd refers to the default notification frequency corresponding to the default operating voltage. Both Vd and Fd can be set in advance to determine the corresponding relationship between the two.

[0049] Therefore, it can be seen from equation (3) that the notification frequency Fn is proportional to the target voltage Vt, but this is only one implementation method and is not a must. As long as a corresponding relationship can be established between the notification frequency and the target voltage, the technical solution of the present disclosure can be adopted and implemented. For example, the notification frequency Fn and the target voltage Vt can be inversely proportional or have other nonlinear relationships.

[0050] The notification frequency Fn is not applicable in the entire frequency range, but has a certain range. According to one embodiment of the present disclosure, the notification frequency Fn has an upper limit notification frequency and a lower limit notification frequency. When the target voltage exceeds the upper limit voltage, the notification frequency Fn is set to the upper limit notification frequency, and when the target voltage is lower than the lower limit voltage, the notification frequency Fn is set to the lower limit notification frequency.

[0051] In this embodiment, the notification frequency Fn can be set to have an upper notification frequency and a lower notification frequency to correspond to the upper and lower voltage limits of the chip, respectively. The upper voltage limit here can be the highest voltage allowed by the chip, and the lower voltage limit can be the lowest voltage allowed by the chip; but the upper and lower voltage limits can also be freely set (for example, by software drive), and are not limited to the physically allowed maximum and minimum voltages. The setting of the maximum and minimum voltages is conducive to protecting the chip from damage by ultra-high or ultra-low voltages.

[0052] Further as described above, when the target voltage Vt exceeds the upper limit voltage, the notification frequency Fn may have an upper limit notification frequency, so that the actual voltage of the chip will not exceed the upper limit voltage; when the target voltage is lower than the lower limit voltage, the notification frequency Fn may have a lower limit notification frequency, so that the actual voltage of the chip will not be lower than the lower limit voltage.

[0053] After the notification frequency Fn of the notification signal is determined, a corresponding notification signal may be generated according to the notification frequency Fn.

[0054] like Figure 1 As shown, the notification signal generating module 13 can be connected to the VFC module 12 to generate a notification signal with the notification frequency according to the determined notification frequency. The notification signal with the required notification frequency can be generated by a crystal oscillator, a phase-locked loop (PLL), a frequency divider, etc. in the chip.

[0055] Next, if Figure 1 As shown, the notification signal sending end 14 is connected to the notification signal generating module 13 and can be used to send a notification signal.

[0056] In the prior art, the notification signal sending end needs to use multiple pins and send the notification signal in the form of a digital signal. According to the technical solution of the present disclosure, the notification signal sending end 14 is a single pin of the chip, and the notification signal sending end 14 is an analog signal pin.

[0057] In the present disclosure, the notification signal transmitting terminal 14 may transmit a square wave signal having the above notification frequency, and may use only a single pin.

[0058] The voltage regulator outside the chip generates a corresponding target voltage according to the received notification signal, and transmits the power supply with the target voltage to the chip. The voltage input terminal 15 in the chip is used to receive the power supply with the target voltage so that the chip operates at the corresponding operating frequency, wherein the power supply is generated according to the notification signal (this will be explained in detail later).

[0059] In the present disclosure, a notification signal can be sent through only one pin, and the notification signal can be received through one pin to obtain the target power supply voltage according to the notification signal, thereby greatly saving the pins for the chip to communicate with the outside and improving the chip utilization.

[0060] Implementation Method 2

[0061] Figure 3 FIG. 2 shows a schematic diagram of a chip voltage regulation system according to a second embodiment of the present disclosure. Figure 3 As shown, a chip voltage regulation system is provided, including Figure 1 The chip 1 and the voltage regulating device 2 shown, wherein the voltage regulating device 2 includes: a notification signal detection module 21, a frequency voltage conversion FVC (Frequency Voltage Converter) module 22, a voltage regulating VR (Voltage Regulating) module 23, a notification signal receiving terminal 24 and a voltage output terminal 25.

[0062] like Figure 3 As shown, chip 1 in the chip voltage regulation system has been combined Figure 1 and Figure 2 The description has been made, which will not be repeated here. Next, the voltage regulating module 2 (Voltage Regulating Module, VRM) will be described in detail.

[0063] like Figure 3 As shown, the notification signal receiving terminal 24 in the voltage regulating device 2 is connected to the notification signal sending terminal 14 for receiving the notification signal. Figure 1Corresponding to the notification signal sending end 14, the notification signal receiving end 24 is also an analog signal pin, which can receive the analog notification signal sent from the notification signal sending end 14. The notification signal receiving end 24 can be a pin of the VRM.

[0064] The notification signal detection module 21 in the voltage regulating device 2 is connected to the notification signal receiving terminal 24 and is used to detect the notification frequency of the notification signal.

[0065] Furthermore, the FVC module 22 is connected to the notification signal detection module 21. The FVC module 22 and the VFC module 12 belong to opposite processes, and their function is to determine the target voltage according to the notification frequency of the notification signal, so as to provide the corresponding target voltage for the chip later.

[0066] According to one embodiment of the present disclosure, the FVC module 22 is used to determine the target voltage Vt according to the notification frequency of the notification signal in the following linear relationship:

[0067]

[0068] Wherein, Fn is the notification frequency of the notification signal, Vd represents the default operating voltage of the chip, and Fd represents the default notification frequency of the chip under the default operating voltage.

[0069] As mentioned above, the default operating voltage Vd mentioned here refers to the voltage at which the chip usually works, such as the operating voltage set when the chip leaves the factory; Fd refers to the default notification frequency corresponding to the default operating voltage. Both Vd and Fd can be set in advance to determine the corresponding relationship between the two.

[0070] Therefore, equation (4) corresponds to equation (3). If equation (3) adopts other formulas, equation (4) can also be adjusted accordingly, thereby becoming the inverse process of equation (3). Therefore, the above equation (4) is only an example, and is not necessarily as shown in equation (4).

[0071] Next, the VR module 23 is connected to the FVC module 22 and is used to adjust the reference voltage according to the determined target voltage to generate the target voltage.

[0072] Figure 4 FIG. 2 is a schematic diagram showing a VR module 23 for generating a target voltage according to an embodiment of the present disclosure.

[0073] like Figure 4As shown, the target voltage value Vt is input into the reference voltage Vref generator 230, the reference voltage Vref generator 230 is connected to the comparator 232, the comparator 232 is connected to the control module 234, the control module 234 is connected to the voltage output terminal 25, and the voltage output terminal 25 is connected to the comparator 232 through a feedback loop. The reference voltage Vref generator 230 adjusts the reference voltage Vref according to the target voltage Vt, and then the comparator 232 adjusts the control module 234 according to the difference between the output voltage of the voltage output terminal 25 and the reference voltage Vref, so that the output voltage of the voltage output terminal 25 is equal to the target voltage Vt.

[0074] The VR module 23 may adopt any existing or future voltage regulator, such as a PWM voltage regulator and the like.

[0075] Finally, the voltage output terminal 25 is connected to the VR module 23 to output the generated target voltage to the voltage input terminal 15 in the chip, so that the voltage in the chip reaches the target voltage, and the chip can run at the corresponding operating frequency.

[0076] Implementation 3

[0077] Figure 5 FIG. 2 shows a schematic diagram of a chip voltage regulation system according to a third embodiment of the present disclosure. Figure 5 As shown, a chip voltage regulation system is provided, including Figure 1 The chip 1, voltage regulating device 2 and control device 3 shown in the figure, wherein the voltage regulating device 2 includes: a voltage regulating VR module 23, a voltage signal receiving terminal 26 and a voltage output terminal 25, and the control device 3 includes a notification signal receiving terminal 34, a notification signal detection module 31, a frequency-voltage conversion FVC module 32 and a voltage signal sending terminal 36.

[0078] like Figure 5 As shown, chip 1 in the chip voltage regulation system has been combined Figure 1 and Figure 2 The description has been made above and will not be repeated here. Next, the voltage regulating device 2 (Voltage Regulating Module, VRM) and the control device 3 will be described in detail.

[0079] like Figure 5 As shown, the notification signal receiving terminal 34 is connected to the notification signal sending terminal 14 for receiving the notification signal. Figure 1 Corresponding to the notification signal sending end 14 in the figure, the notification signal receiving end 34 is also an analog signal pin, which can receive the analog notification signal sent from the notification signal sending end 14. The notification signal receiving end 34 can be a pin of the control device 3.

[0080] The notification signal detection module 31 is connected to the notification signal receiving terminal 34 and is used to detect the notification frequency of the notification signal.

[0081] Furthermore, the FVC module 32 is connected to the notification signal detection module 31. The FVC module 32 and the VFC module 12 belong to opposite processes, and their function is to determine the target voltage according to the notification frequency of the notification signal, so as to provide the corresponding target voltage for the chip later.

[0082] According to one embodiment of the present disclosure, the FVC module 32 is used to determine the target voltage Vt according to the notification frequency of the notification signal in the following linear relationship:

[0083]

[0084] Wherein, Fn is the notification frequency of the notification signal, Vd represents the default operating voltage of the chip, and Fd represents the default notification frequency of the chip under the default operating voltage.

[0085] As mentioned above, the default operating voltage Vd mentioned here refers to the voltage at which the chip usually works, such as the operating voltage set when the chip leaves the factory; Fd refers to the default notification frequency corresponding to the default operating voltage. Both Vd and Fd can be set in advance to determine the corresponding relationship between the two.

[0086] Therefore, equation (5) corresponds to equation (3). If equation (3) adopts other formulas, equation (5) can also be adjusted accordingly, thereby becoming the inverse process of equation (3). Therefore, the above equation (5) is only an example and is not a necessity.

[0087] Furthermore, the voltage signal sending terminal 36 is connected to the FVC module 32 and is used to receive the voltage value of the target voltage from the FVC module 32 .

[0088] In the third embodiment, the voltage value of the target voltage may be a digital signal, and thus the voltage signal receiving terminal 26 and the voltage signal sending terminal 36 are digital signal pins.

[0089] The control device 3 can be implemented by a microprocessor MCU or a complex programmable logic device CPLD, so the voltage signal sending terminal 36 can be a digital signal interface of the MCU or CPLD.

[0090] The VR module 23 is connected to the voltage signal receiving terminal 26 and is used to adjust the reference voltage according to the determined voltage value of the target voltage to generate the target voltage.

[0091] The process of generating the target voltage can be referred to Figure 4 As shown, no further description will be given here.

[0092] The voltage output terminal 25 is connected to the VR module 23 and is used to output the generated target voltage to the voltage input terminal 15 in the chip, so that the voltage in the chip reaches the target voltage, and further enables the chip to operate at the corresponding operating frequency.

[0093] Figure 5 The difference between the described embodiment 3 and the embodiment 2 is that the detection of the notification signal and the determination of the target voltage can be realized by the existing MCU or CPLD on the board, so that the function of the control device 3 does not need to be realized by hardware as in the embodiment 2; and the purpose of the present disclosure can also be achieved by the existing voltage regulator 2 without redesigning the voltage regulator 2. This is conducive to the flexible realization of the voltage control of the chip and the reduction of hardware costs.

[0094] Implementation 4

[0095] Figure 6a FIG. 4 is a schematic diagram of a chip voltage regulation system according to a fourth embodiment of the present disclosure. Figure 6a As shown, a chip voltage regulation system is provided, including a chip 1, a voltage regulation device 2 and a control device 3, wherein the chip 1 includes: a load signal sending terminal 17, an operating frequency receiving terminal 18 and a voltage input terminal 15; the control device 3 includes: a load signal receiving terminal 37, an operating frequency sending terminal 38, a frequency voltage adaptive adjustment (Frequency Voltage Adaptive Scaling) FVAS module 1-31, a voltage frequency conversion (Voltage Frequency Converter) VFC module 1-32, a notification signal generating module 1-33, a notification signal detection module 31, a frequency voltage conversion FVC module 32 and a voltage signal sending terminal 36; the voltage regulation device 2 includes: a voltage regulation VR module 23, a voltage signal receiving terminal 26 and a voltage output terminal 25.

[0096] According to the fourth embodiment of the present disclosure, the chip 1 is an existing chip, and its existing pins can be used as the load signal sending terminal 17 to send the load signal of the chip 1, and the existing pins (digital or analog) can be used as the working frequency receiving terminal 18. More specifically, the load signal sending terminal 17 and the working frequency receiving terminal 18 can share the same existing pins on the chip 1.

[0097] The load signal receiving terminal 37 of the control device 3 receives the load signal from the load signal sending terminal 17 of the chip 1 and transmits the load signal to the FVAS module 1 - 31 .

[0098] The FVAS module 1 - 31 is connected to the load signal receiving terminal 37 and is used to determine the operating frequency and the corresponding target voltage of the chip 1 according to the load of the chip 1 .

[0099] The operating frequency transmitting terminal 38 is connected to the FVAS module 1 - 31 and is used to transmit the determined operating frequency to the operating frequency receiving terminal 18 of the chip 1 , so that the chip 1 can know the required operating frequency.

[0100] The VFC module 1 - 32 is connected to the FVAS module 1 - 31 and is used to determine the notification frequency of the notification signal according to the target voltage.

[0101] The notification signal generating module 1 - 33 is connected to the VFC module 1 - 32 and is used to generate a notification signal having the notification frequency according to the determined notification frequency.

[0102] The notification signal detection module 31 is connected to the notification signal generation module 1 - 33 and is used to detect the notification frequency of the notification signal.

[0103] The FVC module 32 is connected to the notification signal detection module 31 and is used to determine the target voltage according to the notification frequency of the notification signal.

[0104] The voltage signal sending terminal 36 is connected to the FVC module 32 and is used to receive the voltage value of the target voltage from the FVC module 32 .

[0105] The voltage signal receiving terminal 26 is connected to the voltage signal sending terminal 36 and is used to receive the voltage value of the target voltage from the voltage signal sending terminal 36 .

[0106] The VR module 23 is connected to the voltage signal receiving terminal 26 and is used to adjust the reference voltage according to the determined voltage value of the target voltage to generate the target voltage.

[0107] The voltage output terminal 25 is connected to the VR module 23 and is used to output the generated target voltage to the voltage input terminal 15 in the chip, so that the voltage in the chip reaches the target voltage, and further enables the chip to operate at the corresponding operating frequency.

[0108] In the fourth embodiment, the FVAS module 1-31, the VFC module 1-32 and the notification signal generating module 1-33 correspond to the FVAS module 11, the VFC module 12 and the notification signal generating module 13 in the first three embodiments, respectively, except that the modules in which they are located are different during implementation, so they will not be described here. In the fourth embodiment, the existing pins of the chip can be used to adjust the voltage of any existing chip without redesigning the existing chip; and the existing voltage regulating device can also be used without redesigning a new voltage regulating device, which significantly saves costs. In addition, the control device 3 can be implemented by MCU and CPLD, so that the voltage regulation of the chip can be controlled by programming.

[0109] Implementation method 5

[0110] Figure 6b FIG. 4 is a schematic diagram of a chip voltage regulation system according to a fifth embodiment of the present disclosure. Figure 6b As shown, a chip voltage regulation system is provided, including a chip 1, a voltage regulation device 2 and a control device 3, wherein the chip 1 includes: a load signal sending terminal 17, an operating frequency receiving terminal 18 and a voltage input terminal 15; the control device 3 includes: a load signal receiving terminal 37, an operating frequency sending terminal 38, an FVAS module 1-31, a VFC module 1-32, a notification signal generating module 1-33 and a notification signal sending terminal 1-34; the voltage regulation device 2 includes: a notification signal detection module 21, an FVC module 22, a VR module 23, a notification signal receiving terminal 24 and a voltage output terminal 25.

[0111] According to the fifth embodiment of the present disclosure, the chip 1 is an existing chip, and its existing pins can be used as the load signal transmitting end 17 to transmit the load signal of the chip 1, and the existing pins can be used as the operating frequency receiving end 18. More specifically, the load signal transmitting end 17 and the operating frequency receiving end 18 can share the same existing pins on the chip 1.

[0112] The load signal receiving terminal 37 of the control device 3 receives the load signal from the load signal sending terminal 17 of the chip 1 and transmits the load signal to the FVAS module 1 - 31 .

[0113] The FVAS module 1 - 31 is connected to the load signal receiving terminal 37 and is used to determine the operating frequency and the corresponding target voltage of the chip 1 according to the load of the chip 1 .

[0114] The operating frequency transmitting terminal 38 is connected to the FVAS module 1 - 31 and is used to transmit the determined operating frequency to the operating frequency receiving terminal 18 of the chip 1 , so that the chip 1 can know the required operating frequency.

[0115] The VFC module 1 - 32 is connected to the FVAS module 1 - 31 and is used to determine the notification frequency of the notification signal according to the target voltage.

[0116] The notification signal generating module 1 - 33 is connected to the VFC module 1 - 32 and is used to generate a notification signal having the notification frequency according to the determined notification frequency.

[0117] The notification signal sending end 1-34 is connected to the notification signal generating module 1-33 and is used to send the notification signal.

[0118] The notification signal receiving end 24 is connected to the notification signal sending end 1-34 and is used to receive the notification signal.

[0119] The notification signal detection module 21 is connected to the notification signal receiving terminal 24 and is used to detect the notification frequency of the notification signal.

[0120] The FVC module 22 is connected to the notification signal detection module 21 and is used to determine the target voltage according to the notification frequency of the notification signal.

[0121] The VR module 23 is connected to the FVC module 22 and is used to adjust the reference voltage according to the determined target voltage to generate the target voltage.

[0122] The voltage output terminal 25 is connected to the VR module 23 and is used to output the generated target voltage to the voltage input terminal 15 in the chip 1, so that the voltage in the chip 1 reaches the target voltage, and further enables the chip 1 to operate at the corresponding operating frequency.

[0123] In the fifth embodiment, the existing pins of the chip can be used to adjust the voltage of any existing chip without redesigning the existing chip. In addition, the control device 3 can also be implemented by MCU and CPLD, so that the voltage adjustment of the chip can be controlled by programming.

[0124] Implementation 6

[0125] Figure 6c FIG. 4 is a schematic diagram of a chip voltage regulation system according to a sixth embodiment of the present disclosure. Figure 6cAs shown, a chip voltage regulation system is provided, including a chip 1, a voltage regulation device 2 and a control device 3, wherein the chip 1 includes: a load signal sending terminal 17, an operating frequency receiving terminal 18 and a voltage input terminal 15; the control device 3 includes: a load signal receiving terminal 37, an operating frequency sending terminal 38, an FVAS module 1-31 and a voltage signal sending terminal 36; the voltage regulation device 2 includes a voltage regulation VR module 23, a voltage signal receiving terminal 26 and a voltage output terminal 25.

[0126] According to the sixth embodiment of the present disclosure, the chip 1 is an existing chip, and its existing pins can be used as the load signal transmitting end 17 to transmit the load signal of the chip 1, and the existing pins can be used as the operating frequency receiving end 18. More specifically, the load signal transmitting end 17 and the operating frequency receiving end 18 can share the same existing pins on the chip 1.

[0127] The load signal receiving terminal 37 of the control device 3 receives the load signal from the load signal sending terminal 17 of the chip 1 and transmits the load signal to the FVAS module 1 - 31 .

[0128] The FVAS module 1 - 31 is connected to the load signal receiving terminal 37 and is used to determine the operating frequency and the corresponding target voltage of the chip 1 according to the load of the chip 1 .

[0129] The operating frequency transmitting terminal 38 is connected to the FVAS module 1 - 31 and is used to transmit the determined operating frequency to the operating frequency receiving terminal 18 of the chip 1 , so that the chip 1 can know the required operating frequency.

[0130] The voltage signal sending terminal 36 is connected to the FVAS module 1 - 31 and is used to receive the voltage value of the target voltage from the FVAS module 1 - 31 .

[0131] The voltage signal receiving terminal 26 is connected to the voltage signal sending terminal 36 and is used to receive the voltage value of the target voltage from the voltage signal sending terminal 36 .

[0132] The VR module 23 is connected to the voltage signal receiving terminal 26 and is used to adjust the reference voltage according to the determined voltage value of the target voltage to generate the target voltage.

[0133] The voltage output terminal 25 is connected to the VR module 23 and is used to output the generated target voltage to the voltage input terminal 15 in the chip, so that the voltage in the chip reaches the target voltage, and further enables the chip to operate at the corresponding operating frequency.

[0134] In the fifth embodiment, the existing pins of the chip can be used to adjust the voltage of any existing chip without redesigning the existing chip. In addition, the existing voltage regulator can be used without redesigning a new voltage regulator, which significantly saves costs.

[0135] In summary, the beneficial effect of some technical solutions disclosed in the present invention is that only one signal line and simple logic are needed to realize dynamic voltage regulation of the chip. With more and more chip functional modules and increasingly limited pin resources and logic resources, precious pin resources and logic resources are greatly saved. At the same time, chip power consumption can be saved and energy utilization efficiency can be improved.

[0136] In addition, some embodiments of the present disclosure can also adjust the chip voltage without modifying the existing chip, so that the chip can operate at the corresponding operating frequency under the target voltage, thereby improving processing efficiency when the load is higher and reducing power consumption when the load is lower.

[0137] The present disclosure also provides a circuit board, including the chip as described above, or the system as described above. The chip 1 described above in the present disclosure can be arranged on the circuit board, and the chip 1 can be connected to other devices or components in addition to being connected to the voltage regulating device 2 and the control device 3 described above. Alternatively, the chip voltage regulating system formed by the chip 1, the voltage regulating device 2 and the control device 3 can be integrated into an independent device. Therefore, the chip device 702 described below may refer to the chip 1 described above, or may refer to a chip voltage control system formed by the chip 1, the voltage regulating device 2 and the control device 3.

[0138] Figure 7 An exemplary circuit board or card is shown, which includes a chip device 702 and other supporting components, including but not limited to: a storage device 704, an interface device 706 and a control device 708.

[0139] The memory device is connected to the chip via a bus for storing data. The memory device may include multiple groups of memory cells 710. Each group of memory cells is connected to the chip device 702 via a bus. It is understood that each group of memory cells may be DDR SDRAM (English: Double Data Rate SDRAM, double rate synchronous dynamic random access memory).

[0140] DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on the rising and falling edges of the clock pulse. The speed of DDR is twice that of standard SDRAM. In one embodiment, the storage device may include 4 groups of storage units. Each group of storage units may include multiple DDR4 particles (chips). In one embodiment, the chip may include 4 72-bit DDR4 controllers, 64 bits of the above 72-bit DDR4 controllers are used for data transmission, and 8 bits are used for ECC verification. In one embodiment, each group of storage units includes multiple double-rate synchronous dynamic random access memories arranged in parallel. DDR can transmit data twice in one clock cycle. A controller for controlling DDR is set in the chip to control the data transmission and data storage of each storage unit.

[0141] The interface device is electrically connected to the chip. The interface device is used to realize data transmission between the chip and an external device 712 (such as a server or a computer). For example, in one embodiment, the interface device can be a standard PCIE interface. For example, the data to be processed is transmitted to the chip by the server through the standard PCIE interface to realize data transfer. In another embodiment, the interface device can also be other interfaces. This disclosure does not limit the specific manifestations of the above-mentioned other interfaces. The interface unit can realize the switching function. In addition, the calculation results of the chip are still transmitted back to the external device (such as a server) by the interface device.

[0142] The control device is electrically connected to the chip. The control device is used to monitor the state of the chip. Specifically, the chip and the control device can be electrically connected via an SPI interface. The control device may include a single-chip microcomputer (Micro Controller Unit, MCU). For example, the chip may include multiple processing chips, multiple processing cores or multiple processing circuits, which can drive multiple loads. Therefore, the chip can be in different working states such as multi-load and light load. The control device can realize the regulation of the working states of multiple processing chips, multiple processing and / or multiple processing circuits in the chip.

[0143] The present disclosure also provides an electronic device, comprising the circuit board as described above.

[0144] Electronic devices or apparatuses include data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, mobile phones, driving recorders, navigators, sensors, cameras, servers, cloud servers, cameras, camcorders, projectors, watches, headphones, mobile storage, wearable devices, vehicles, household appliances, and / or medical equipment.

[0145] The transportation means include airplanes, ships and / or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical equipment includes magnetic resonance imaging, ultrasound machines and / or electrocardiographs.

[0146] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should know that the present disclosure is not limited by the order of the actions described, because according to the present disclosure, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present disclosure.

[0147] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0148] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some pins, and the indirect coupling or communication connection of the device or unit can be electrical, optical, acoustic, magnetic or other forms.

[0149] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0150] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of a software program module.

[0151] If the integrated unit is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, when the technical solution of the present disclosure can be embodied in the form of a software product, the computer software product is stored in a memory, including a number of instructions for a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

[0152] The embodiments of the present disclosure are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method of the present disclosure and its core idea. At the same time, for those skilled in the art, according to the ideas of the present disclosure, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

Claims

1. A chip (1), comprising: A frequency voltage adaptive adjustment FVAS module (11), a voltage frequency conversion VFC module (12), a notification signal generation module (13), a notification signal sending terminal (14) and a voltage input terminal (15), wherein: The FVAS module (11) is used to determine the operating frequency and the corresponding target voltage of the chip according to the load of the chip, wherein the FVAS module (11) comprises: a task detection unit (110) and a frequency-voltage mapping unit (112), wherein the task detection unit (110) is used to determine the operating frequency required by the load according to the load of the chip; and the frequency-voltage mapping unit (112) is used to determine the corresponding target voltage according to the operating frequency; The VFC module (12) is connected to the FVAS module (11) and is used to determine the notification frequency of the notification signal according to the target voltage; The notification signal generating module (13) is connected to the VFC module (12) and is used to generate a notification signal having the notification frequency according to the determined notification frequency; The notification signal sending end (14) is connected to the notification signal generating module (13) and is used to send the notification signal; and The voltage input terminal (15) is used to receive a power supply having the target voltage so that the chip operates at the operating frequency, wherein the power supply is generated according to the notification signal.

2. The chip (1) according to claim 1, wherein: The frequency-voltage mapping unit (112) is used to determine the corresponding target voltage Vt according to the operating frequency in the following linear relationship: Vt=Vmin+k*F0 Wherein, Vmin represents the minimum operating voltage of the chip, k represents the adjustment coefficient, and F0 represents the operating frequency of the chip.

3. The chip (1) according to claim 1, wherein: The frequency-voltage mapping unit (112) is used to determine the corresponding target voltage according to the operating frequency in a segmented manner.

4. The chip (1) according to any one of claims 1 to 3, wherein: The VFC module (12) is used to determine the notification frequency Fn of the notification signal according to the target voltage in a linear relationship as follows: Wherein, Vt represents the target voltage, Vd represents the default operating voltage of the chip, and Fd represents the default notification frequency of the chip under the default operating voltage.

5. The chip (1) according to claim 4, wherein: The notification frequency Fn has an upper limit notification frequency and a lower limit notification frequency. When the target voltage exceeds the upper limit voltage, the notification frequency Fn is set to the upper limit notification frequency. When the target voltage is lower than the lower limit voltage, the notification frequency Fn is set to the lower limit notification frequency.

6. The chip (1) according to any one of claims 1 to 5, wherein: The notification signal sending end (14) is a single pin of the chip; and the notification signal sending end (14) is an analog signal pin.

7. A chip voltage regulation system, comprising a chip (1) and a voltage regulation device (2) as claimed in any one of claims 1 to 6, wherein: The voltage regulating device (2) comprises: a notification signal detection module (21), a frequency voltage conversion FVC module (22), a voltage regulation VR module (23), a notification signal receiving terminal (24) and a voltage output terminal (25), wherein: The notification signal receiving end (24) is connected to the notification signal sending end (14) and is used to receive the notification signal; The notification signal detection module (21) is connected to the notification signal receiving end (24) and is used to detect the notification frequency of the notification signal; The FVC module (22) is connected to the notification signal detection module (21) and is used to determine the target voltage according to the notification frequency of the notification signal; The VR module (23) is connected to the FVC module (22) and is used to adjust the reference voltage according to the determined target voltage to generate the target voltage; and The voltage output terminal (25) is connected to the VR module (23) and is used to output the generated target voltage to the voltage input terminal (15) in the chip.

8. The system according to claim 7, wherein: The notification signal receiving end (24) is an analog signal pin.

9. The system according to claim 7 or 8, wherein: The FVC module (22) is used to determine the target voltage Vt according to the notification frequency of the notification signal in a linear relationship as follows: Wherein, Fn is the notification frequency of the notification signal, Vd represents the default operating voltage of the chip, and Fd represents the default notification frequency of the chip under the default operating voltage.

10. A chip voltage regulation system, comprising a chip (1) as claimed in any one of claims 1 to 6, a voltage regulation device (2) and a control device (3), wherein: The voltage regulating device (2) comprises: a voltage regulating VR module (23), a voltage signal receiving terminal (26) and a voltage output terminal (25); the control device (3) comprises a notification signal receiving terminal (34), a notification signal detection module (31), a frequency voltage conversion FVC module (32) and a voltage signal sending terminal (36); wherein: The notification signal receiving end (34) is connected to the notification signal sending end (14) and is used to receive the notification signal; The notification signal detection module (31) is connected to the notification signal receiving end (34) and is used to detect the notification frequency of the notification signal; The FVC module (32) is connected to the notification signal detection module (31) and is used to determine the target voltage according to the notification frequency of the notification signal; The voltage signal sending end (36) is connected to the FVC module (32) and is used to receive the voltage value of the target voltage from the FVC module (32); The voltage signal receiving end (26) is connected to the voltage signal sending end (36) and is used to receive the voltage value of the target voltage from the voltage signal sending end (36); The VR module (23) is connected to the voltage signal receiving terminal (26) and is used to adjust the reference voltage according to the determined voltage value of the target voltage to generate the target voltage; and The voltage output terminal (25) is connected to the VR module (23) and is used to output the generated target voltage to the voltage input terminal (15) in the chip.

11. The system according to claim 10, wherein: The notification signal receiving end (34) is an analog signal pin.

12. The system according to claim 10 or 11, wherein: The voltage signal receiving end (26) and the voltage signal sending end (36) are digital signal pins.

13. The system according to any one of claims 10 to 12, wherein: The control device (3) is implemented by a microprocessor MCU or a complex programmable logic device CPLD.

14. The system according to any one of claims 10 to 13, wherein: The FVC module (32) is used to determine the target voltage Vt according to the notification frequency of the notification signal in a linear relationship as follows: Wherein, Fn is the notification frequency of the notification signal, Vd represents the default operating voltage of the chip, and Fd represents the default notification frequency of the chip under the default operating voltage.

15. A circuit board, comprising the chip according to any one of claims 1 to 6, or the system according to any one of claims 7 to 14.

16. An electronic device comprising the circuit board according to claim 15.

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