Display device, drive circuit, and display driving method

Abstract

Embodiments of the present disclosure relate to a display device, including a display panel including a light emitting element, a driving transistor for providing a driving current to the light emitting element using a driving voltage, and a plurality of switching transistors for controlling the operation of the driving transistor, a gate driving circuit for providing a plurality of scan signals to the display panel through a plurality of gate lines, a light emitting driving circuit for providing a plurality of light emitting signals to the display panel through a plurality of light emitting signal lines, a data driving circuit for providing a data voltage to the display panel, and a timing controller for, in a low speed mode in which the display panel is driven at a lower driving frequency, controlling to provide a leakage current suppression voltage to the driving transistor for a leakage current suppression period after providing a bias voltage to the driving transistor.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0157176, filed on November 16, 2021, which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] Embodiments of this disclosure relate to a display device, driving circuit, and display driving method that can reduce image quality defects by reducing leakage current generated during operation at lower driving frequencies. Background Technology

[0004] With the development of the information society, the demand for various types of image display devices is increasing. In this regard, a range of display devices, such as liquid crystal displays, electroluminescent displays, and quantum dot displays, have recently been widely used.

[0005] Among these display devices, organic light-emitting display devices have superior performance characteristics such as fast response speed, high contrast, high luminous efficiency, high brightness and wide viewing angle due to the use of self-emissive light-emitting diodes.

[0006] This organic light-emitting display device may include organic light-emitting diodes disposed in a plurality of sub-pixels arranged in a display panel, and the light emission of the organic light-emitting diodes can be controlled by controlling the voltage flowing through the organic light-emitting diodes, so as to display images while controlling the brightness of the sub-pixels.

[0007] In this case, the image data provided to the display device can be a still image or a moving image with a variable speed, and even in the case of a moving image, it can correspond to various types of images such as sports images, movie images, and game images.

[0008] In addition, the display device can switch its operating status to various driving modes based on user input.

[0009] On the other hand, the display device can change the driving frequency according to the type of image data or the driving mode, but due to the leakage current flowing during operation at a lower driving frequency, image quality degradation such as black glare may occur. Summary of the Invention

[0010] Therefore, the inventors of this disclosure have invented a display device, driving circuit, and display driving method that can reduce image quality defects that occur during operation at lower driving frequencies.

[0011] Embodiments of this disclosure can provide a display device, driving circuit, and display driving method capable of reducing image quality defects such as flicker by stably maintaining the driving transistor during operating periods at lower driving frequencies.

[0012] Embodiments of this disclosure can provide a display device, driving circuit, and display driving method capable of reducing image quality defects by controlling the levels of the initialization voltage, bias voltage, and leakage suppression voltage supplied to the driving transistor during operating periods at lower driving frequencies.

[0013] Embodiments of this disclosure can provide a display device, driving circuit, and display driving method capable of improving image quality due to leakage current by providing a leakage current suppression voltage to the driving transistor during the light-emitting period in operation at a lower driving frequency, which is different from the bias voltage level.

[0014] Embodiments of this disclosure can provide a display device, driving circuit, and display driving method that can effectively improve image quality caused by leakage current by controlling the level of leakage current suppression voltage supplied to the driving transistor during the light-emitting period based on the grayscale of the data voltage during operation at a lower driving frequency.

[0015] The problems to be solved according to the embodiments of this disclosure described below are not limited to the problems described above, and those skilled in the art will clearly understand other problems not mentioned from the following description.

[0016] A display device according to an embodiment of the present disclosure includes: a display panel, including a light-emitting element, a driving transistor for providing a driving current to the light-emitting element using a driving voltage, and a plurality of switching transistors for controlling the operation of the driving transistor; a gate driving circuit for providing a plurality of scan signals to the display panel through a plurality of gate lines; a light-emitting driving circuit for providing a plurality of light-emitting signals to the display panel through a plurality of light-emitting signal lines; a data driving circuit for providing a data voltage to the display panel; and a timing controller for controlling a leakage current suppression voltage to provide the leakage current suppression voltage to the driving transistor during a leakage current suppression period after providing a bias voltage to the driving transistor in a low-speed mode of driving the display panel at a lower driving frequency.

[0017] In a display device according to an embodiment of the present disclosure, a low-speed mode includes a refresh frame that provides a data voltage for driving a light-emitting element, and a skip frame that does not provide a data voltage.

[0018] In a display device according to an embodiment of the present disclosure, a plurality of switching transistors include: a first switching transistor, wherein a first scan signal is provided to a gate, a drain is connected to the gate of a driving transistor and a storage capacitor, and a source is connected to the source of the driving transistor; a second switching transistor, wherein a second scan signal is provided to a gate, a data voltage is provided to a drain, and a source is connected to the drain of the driving transistor; a third switching transistor, wherein a light emission signal is provided to a gate, a driving voltage is provided to a drain, and a source is connected to the drain of the driving transistor; a fourth switching transistor, wherein a light emission signal is provided to a gate, a driving voltage is provided to a drain, and a source is connected to the anode of a light-emitting element; a fifth switching transistor, wherein a third scan signal is provided to a gate, a stabilizing voltage is provided to a drain, and a source is connected to the source of the driving transistor; and a sixth switching transistor, wherein a fourth scan signal is provided to a gate, a reset voltage is provided to a drain, and a source is connected to the anode of a light-emitting element.

[0019] In a display device according to an embodiment of the present disclosure, the stabilizing voltage includes an initialization voltage for initializing the driving transistor; a bias voltage; and a leakage current suppression voltage.

[0020] In the display device according to an embodiment of the present disclosure, an initialization voltage is provided within a refresh frame, a bias voltage is provided within a refresh frame or a skip frame, and a leakage suppression voltage is provided during a leakage suppression period that includes a light emission period in which the light-emitting element emits light.

[0021] In a display device according to an embodiment of the present disclosure, the initialization voltage has a negative level, the bias voltage has a first positive level, and the leakage suppression voltage has a second positive level lower than the first positive level.

[0022] The display device according to an embodiment of the present disclosure further includes: a memory for storing image data provided to a display panel, wherein a timing controller controls the levels of leakage current suppression voltage and bias voltage based on the grayscale of the image data provided from the memory within a refresh frame.

[0023] A driving circuit for a display panel according to embodiments of the present disclosure includes a light-emitting element, a driving transistor for providing a driving current to the light-emitting element using a driving voltage, and a plurality of switching transistors for controlling the operation of the driving transistor. The circuit comprises: a shift register for generating a first output signal through a first node and a second output signal through a second node based on a stable start pulse; a buffer circuit for transmitting an initialization voltage to a first output terminal and a bias voltage and a leakage suppression voltage to a second output terminal based on the first and second output signals; and a switching circuit for providing a bias voltage or a leakage suppression voltage to the source of the driving transistor based on a selection signal.

[0024] In a driving circuit according to an embodiment of the present disclosure, the switching circuit includes: a first control transistor and a second control transistor, each of the first control transistor and the second control transistor having a drain connected to a second output terminal; and an inverter that receives a selection signal, has an output terminal connected to the gate of the first control transistor, and an input terminal connected to the gate of the second control transistor.

[0025] In the driving circuit according to an embodiment of the present disclosure, in a low-speed mode driven at a lower driving frequency, an initialization voltage is provided within a refresh frame in which a data voltage for driving the light-emitting element is applied; in a low-speed mode driven at a lower driving frequency, a bias voltage is provided within a refresh frame or a skip frame in which no data voltage is provided; and a leakage suppression voltage is provided during a leakage suppression period that includes the light-emitting period in which the light-emitting element emits light.

[0026] In the driving circuit according to an embodiment of the present disclosure, the levels of leakage current suppression voltage and bias voltage are determined based on the grayscale of the image data provided within the refresh frame.

[0027] In the driving circuit according to an embodiment of the present disclosure, the initialization voltage has a negative level, the bias voltage has a first positive level, and the leakage suppression voltage has a second positive level lower than the first positive level.

[0028] A display driving method according to embodiments of the present disclosure includes a display panel comprising a light-emitting element, a driving transistor for providing a driving current to the light-emitting element using a driving voltage, and a plurality of switching transistors for controlling the operation of the driving transistor. The method includes: switching from a first mode driven at a higher driving frequency to a second mode driven at a lower driving frequency; providing an initialization voltage having a negative level to the driving transistor during an initialization period; providing a bias voltage having a first positive level to the driving transistor during a bias period; and providing a leakage suppression voltage having a second positive level different from the first positive level to the driving transistor during a leakage suppression period including the light-emitting period.

[0029] In a display driving method according to an embodiment of the present disclosure, a low-speed mode includes a refresh frame that provides a data voltage for driving a light-emitting element, and a skip frame that does not provide a data voltage.

[0030] In the display driving method according to embodiments of the present disclosure, an initialization voltage is provided within a refresh frame, a bias voltage is provided within a refresh frame or a skip frame, and a leakage suppression voltage is provided during a leakage suppression period that includes a light emission period in which the light-emitting element emits light.

[0031] In the display driving method according to an embodiment of the present disclosure, the levels of leakage suppression voltage and bias voltage are determined based on the grayscale of image data provided within a refresh frame.

[0032] In the display driving method according to an embodiment of the present disclosure, the second positive level is lower than the first positive level.

[0033] According to embodiments of this disclosure, a display device, driving circuit, and display driving method can be provided that can reduce image quality defects occurring during operation at lower driving frequencies.

[0034] According to embodiments of the present disclosure, a display device, driving circuit, and display driving method can be provided that can reduce image quality defects such as flicker by stably maintaining the driving transistor during operating periods at lower driving frequencies.

[0035] According to embodiments of the present disclosure, a display device, driving circuit, and display driving method can be provided that can reduce image quality defects by controlling the levels of the initialization voltage, bias voltage, and leakage suppression voltage supplied to the driving transistor during operating periods at lower driving frequencies.

[0036] According to embodiments of this disclosure, a display device, driving circuit, and display driving method can be provided that can improve image quality caused by leakage current by providing a leakage current suppression voltage to the driving transistor during the light-emitting period in operation at a lower driving frequency, which is different from the bias voltage level.

[0037] According to embodiments of this disclosure, a display device, driving circuit, and display driving method can be provided that can effectively improve image quality caused by leakage current by controlling the level of leakage current suppression voltage supplied to the driving transistor during the light-emitting period based on the grayscale of the data voltage during operation at a lower driving frequency.

[0038] The effects of the embodiments disclosed in this disclosure are not limited to those described above. Furthermore, the embodiments disclosed in this disclosure may cause other effects not mentioned above, which will be clearly understood by those skilled in the art through the following description. Attached Figure Description

[0039] In the attached diagram:

[0040] Figure 1 A schematic diagram of a display device according to an embodiment of the present disclosure is shown.

[0041] Figure 2 A system diagram of a display device according to an embodiment of the present disclosure is shown.

[0042] Figure 3 A view of a display panel of a display device according to an embodiment of the present disclosure, showing a gate drive circuit and a light emission drive circuit implemented in a GIP type.

[0043] Figure 4 A schematic diagram of a frequency-varying driving mode of a display device according to an embodiment of the present disclosure is shown.

[0044] Figure 5 A view of a sub-pixel circuit of a display device according to an embodiment of the present disclosure is shown.

[0045] Figure 6 A schematic block diagram of a stable voltage generation circuit for a display device according to an embodiment of the present disclosure is shown.

[0046] Figure 7 An exemplary view of the relationship of a stable voltage generation circuit of a display device according to an embodiment of the present disclosure is shown.

[0047] Figure 8 A view of a switching circuit for controlling the output timing of bias voltage and leakage suppression voltage of a display device according to an embodiment of the present disclosure is shown.

[0048] Figure 9 This is a signal waveform showing the levels of the initialization voltage, bias voltage, and leakage suppression voltage constituting the stable voltage of a display device according to an embodiment of the present disclosure.

[0049] Figure 10 The driving timing of a second mode of a display device driven at a lower driving frequency according to an embodiment of the present disclosure is shown.

[0050] Figure 11 An exemplary view of the driving timing of a display device according to an embodiment of the present disclosure for determining the levels of bias voltage and leakage suppression voltage based on image data transmitted within a refresh frame is shown.

[0051] Figure 12 An example is shown of a display device according to an embodiment of the present disclosure in which image data provided within a refresh frame is divided into multiple gray levels and leakage suppression voltage and bias voltage are determined according to the different gray levels of the image data.

[0052] Figure 13 A flowchart of a display driving method according to an embodiment of the present disclosure is shown. Detailed Implementation

[0053] The advantages and features of this disclosure, as well as its implementation methods, will become apparent from the accompanying drawings and detailed description of the embodiments. This disclosure should not be construed as limiting itself to the embodiments set forth herein, and may be implemented in various different forms. Rather, these embodiments are provided to this disclosure in a complete and thorough manner, fully conveying the scope of this disclosure to those skilled in the art. The scope of this disclosure should be defined by the appended claims.

[0054] The shapes, dimensions, scales, angles, quantities, etc., shown in the accompanying drawings to illustrate exemplary embodiments are merely illustrative, and this disclosure is not limited to the embodiments shown in the drawings. In this document, the same reference numerals will be used to designate the same or similar components. In the following description of this disclosure, detailed descriptions of the subject matter will be omitted where such descriptions may become unclear due to the incorporation of detailed descriptions of known functions and components of this disclosure. It should be understood that the terms "comprising," "including," "having," and any variations thereof as used herein are intended to cover non-exclusive inclusion unless explicitly stated otherwise. The singular forms of component descriptions used herein are intended to include the plural forms of component descriptions unless explicitly stated otherwise.

[0055] When analyzing components, it should be understood that this includes error ranges, even if they are not explicitly described.

[0056] When spatially related terms such as “on top of,” “above,” “below,” “under,” and “on one side of” are used in this document to describe the relationship between one element or component and another element or component, one or more intermediate elements or components may exist between one element or component and other elements or components, unless a term such as “directly” is used.

[0057] When using time-related terms such as “after,” “following,” “next,” and “before” to define time relationships, discontinuous situations may be included unless the terms “immediately” or “directly” are used.

[0058] In descriptions of signal transmission such as “a signal is sent from node A to node B”, a signal can be sent from node A to node B via another node, unless the terms “immediately” or “directly” are used.

[0059] Furthermore, this document may use terms such as “first” and “second” to describe various components. However, it should be understood that these components are not limited by these terms. These terms are used only to distinguish one element or component from other elements or components. Therefore, a first component referred to below as “first” may be a second component within the spirit of this disclosure.

[0060] The features of the exemplary embodiments disclosed herein may be partially or wholly coupled or combined with each other, and may work synergistically with each other, or may work in various technical ways. Furthermore, each exemplary embodiment may be performed independently, or may be associated with and synergistically with other embodiments.

[0061] Various embodiments will be described in detail below with reference to the accompanying drawings.

[0062] Figure 1A schematic diagram of a display device according to an embodiment of the present disclosure is shown.

[0063] refer to Figure 1 The display device 100 according to an embodiment of the present disclosure may include: a display panel 110 connected to a plurality of gate lines GL and a plurality of data lines DL, wherein a plurality of sub-pixels SP are arranged in rows and columns; a gate driving circuit 120 for providing scan signals to the plurality of gate lines GL; a light-emitting driving circuit 122 for driving a plurality of light-emitting signal lines EL; a data driving circuit 130 for providing data voltages to the plurality of data lines DL; a timing controller 140 for controlling the gate driving circuit 120 and the data driving circuit 130; and a power management circuit 150.

[0064] The display panel 110 displays images based on scan signals provided from the gate drive circuit 120 via multiple gate lines GL and data voltages provided from the data drive circuit 130 via multiple data lines DL.

[0065] In the case of a liquid crystal display, the display panel 110 includes a liquid crystal layer formed between two substrates and can operate in TN (twisted nematic) mode, VA (vertical alignment) mode, IPS (in-plane switching) mode, FFS (edge ​​field switching) mode, or any known mode. In the case of an organic light-emitting display device, the display panel 110 can be implemented using a top-emitting method, a bottom-emitting method, or a double-sided emitting method.

[0066] In the display panel 110, multiple pixels can be arranged in a matrix. Each pixel can be composed of sub-pixels SP of different colors, such as white sub-pixels, red sub-pixels, green sub-pixels, and blue sub-pixels. Each sub-pixel SP can be defined by multiple data lines DL and multiple gate lines GL.

[0067] The sub-pixel SP may include a thin-film transistor (TFT) disposed in the region where the data line DL and the gate line GL intersect, a light-emitting element such as a light-emitting diode that emits light according to the data voltage, and a storage capacitor for maintaining the data voltage by being electrically connected to the light-emitting element.

[0068] For example, when a display device 100 with a resolution of 2160×3840 includes four sub-pixels SP: white sub-pixel W, red sub-pixel R, green sub-pixel G, and blue sub-pixel B, 3840×4=15360 data lines DL can be set by connecting 2160 gate lines GL and 3840 data lines DL to the four sub-pixels WRGB respectively. Each of the multiple sub-pixels SP can be located in the area where multiple gate lines GL and multiple data lines DL overlap.

[0069] The gate drive circuit 120 is controlled by the timing controller 140, and controls the driving timing of multiple sub-pixels SP by sequentially providing scan signals to multiple gate lines GL disposed in the display panel 110.

[0070] In a display device 100 with a resolution of 2160×3840, the operation of sequentially providing scan signals to 2160 gate lines GL from the first gate line GL1 to the 2160th gate line GL2 can be called a 2160-phase drive operation. Otherwise, the operation of sequentially providing scan signals to every four gate lines GL, for example, providing scan signals sequentially to the first gate line GL1 to the fourth gate line GL4, and then sequentially to the fifth gate line GL5 to the eighth gate line GL8, can be called a four-phase drive operation. As described above, the operation of sequentially providing scan signals to every N gate lines can be called an N-phase drive operation.

[0071] The gate driving circuit 120 may include one or more gate driving integrated circuits (GDICs), which may be disposed on one or both sides of the display panel 110 depending on the driving method. Alternatively, the gate driving circuit 120 may be implemented as a gate in panel (GIP) structure embedded in the bezel area of ​​the display panel 110.

[0072] Here, the gate driving circuit 120 is shown located on the left side of the display panel 110 and the light-emitting driving circuit 122 is located on the right side of the display panel 110. The gate driving circuit 120 and the light-emitting driving circuit 122 can be located in the same position.

[0073] The light-emitting driving circuit 122 generates a light-emitting signal EM under the control of the timing controller 140, and provides it to the display panel 110 through the light-emitting signal line EL.

[0074] By shifting the light emission signal EM using a shift register, the light emission driving circuit 122 can sequentially provide the light emission signal EM via the light emission signal line EL. At this time, the light emission driving circuit 122 can drive the display panel 110 with a specific duty cycle (e.g., 50%) by repeatedly switching the light emission signal EM during the image driving period, according to the control of the timing controller 140.

[0075] In this configuration, the light-emitting driving circuit 122 may include one or more light-emitting control circuits (ECCs), and may be located on one side of the display panel 110 or on both sides of the display panel 110, depending on the driving mode. The light-emitting driving circuit 122 may be directly formed on the substrate of the display panel 110 together with the gate driving circuit 120 via a GIP (gate in panel) process.

[0076] A frame time period can include a write period in which data voltage is supplied to and written to each sub-pixel SP, and a light-emitting period in which the sub-pixel SP emits light at a predetermined duty cycle according to the light-emitting signal EM after the write period. Typically, the light-emitting signal EM causes the sub-pixel SP to emit light at a duty cycle of less than 50% during the light-emitting period. Since the write period is only about one horizontal time period (1H), most of a frame time period corresponds to the light-emitting period.

[0077] During the write period, the subpixel SP charges the storage capacitor with the data voltage, and the subpixel SP repeatedly turns on and off according to the emission signal EM. That is, the subpixel SP repeatedly turns on and off within a frame period to emit light with a duty cycle of less than 50%.

[0078] As described above, by emitting light after being turned off due to the voltage charged in the storage capacitor, the subpixel can display data with the same brightness at a duty cycle of less than 50% during the light emission period after the write period without receiving additional data voltage.

[0079] The data driving circuit 130 receives digital image data DATA from the timing controller 140 and converts the received digital image data DATA into an analog data voltage. Then, the data driving circuit 130 provides the analog data voltage to each data line DL when the scan signal is provided through the gate line GL, so that each sub-pixel SP connected to the data line DL emits light with a corresponding brightness in response to the timing of the provision of the light emission signal EM.

[0080] Similarly, the data driver circuit 130 may include one or more source driver integrated circuits (SDICs). Each source driver integrated circuit (SDIC) may be connected to the bonding pads of the display panel 110 via tape auto-bonding (TAB) or chip-on-glass (COG), or may be directly mounted on the display panel 110.

[0081] In some cases, each source driver integrated circuit (SDIC) can be integrated with the display panel 110. Furthermore, each source driver integrated circuit (SDIC) can be implemented using a chip-on-film (COF) structure. In this case, the source driver integrated circuit (SDIC) can be mounted on a circuit film to be electrically connected to the data lines DL in the display panel 110 via the circuit film.

[0082] The timing controller 140 provides various control signals to the gate driving circuit 120, the light-emitting driving circuit 122, and the data driving circuit 130, and controls the operation of the gate driving circuit 120, the light-emitting driving circuit 122, and the data driving circuit 130. That is, the timing controller 140 outputs a time control scan signal from the gate driving circuit 120 in response to each frame, outputs a light-emitting signal EM from the light-emitting driving circuit 122, and on the other hand, transmits image data DATA from an external source to the data driving circuit 130.

[0083] Here, the timing controller 140 receives various timing signals from the external host system 200, including the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the master clock MCLK.

[0084] The host system 200 can be any one of a TV system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, and wearable device.

[0085] Therefore, the timing controller 140 uses various timing signals received from external sources to generate control signals and provides the control signals to the gate drive circuit 120, the light-emitting drive circuit 122, and the data drive circuit 130.

[0086] For example, timing controller 140 generates various gate control signals, including a gate start pulse (GSP), a gate clock (GCLK), and a gate output enable signal (GOE), to control gate drive circuit 120. Here, the gate start pulse (GSP) is used to control the start timing of one or more gate driver integrated circuits (GDICs) of gate drive circuit 120. Furthermore, the gate clock (GCLK) is a clock signal typically provided to one or more gate driver integrated circuits (GDICs) to control the shift timing of scan signals. The gate output enable signal (GOE) specifies the timing information of one or more gate driver integrated circuits (GDICs).

[0087] Furthermore, the timing controller 140 generates various light-emitting signals, including a light-emitting start pulse ESP, a light-emitting clock ECLK, and a light-emitting output enable signal EOE, to control the light-emitting drive circuit 122. Here, the light-emitting start pulse ESP controls the starting timing of the operation of one or more light-emitting control circuits ECC that constitute the light-emitting drive circuit 122. Furthermore, the light-emitting clock ECLK is a clock signal typically provided to one or more light-emitting control circuits ECC and controls the shift timing of the light-emitting signal EM. Additionally, the light-emitting output enable signal EOE specifies the timing information of one or more light-emitting control circuits ECC.

[0088] Furthermore, the timing controller 140 generates various data control signals, including a source start pulse SSP, a source sampling clock SSC, and a source output enable signal SOE, to control the data drive circuit 130. Here, the source start pulse SSP controls the start timing of data sampling for one or more source driver integrated circuits (SDICs) of the data drive circuit 130. The source sampling clock SSC is a clock signal used to control the timing of data sampling in each source driver integrated circuit (SDIC). The source output enable signal SOE controls the output timing of the data drive circuit 130.

[0089] The display device 100 may further include a power management circuit 150, which is used to provide or control various voltages or currents to the display panel 110, the gate driving circuit 120, the light-emitting driving circuit 122, and the data driving circuit 130.

[0090] The power management circuit 150 generates the power required to drive the display panel 110, the gate drive circuit 120, the light-emitting drive circuit 122, and the data drive circuit 130 by controlling the DC input voltage Vin provided from the host system 200.

[0091] Subpixels SP are located at the intersection of gate line GL and data line DL, and light-emitting elements can be disposed in each subpixel SP. For example, an organic light-emitting display device can include light-emitting elements such as light-emitting diodes in each subpixel SP, and can display images in response to data voltage by controlling the current flowing through the light-emitting elements.

[0092] The display device 100 can be various types of devices such as liquid crystal displays, organic light-emitting displays, and plasma display panels.

[0093] Figure 2 A system diagram of a display device according to an embodiment of the present disclosure is shown.

[0094] As an example, Figure 2 Each source driver integrated circuit (SDIC) of the data driver circuit 130 of the display device 100 according to an embodiment of the present disclosure is shown in a COF type among various structures (e.g., TAB, COG, and COF), and the gate driver circuit 120 and the light-emitting driver circuit 122 are implemented in a GIP type among various structures such as TAB, COG, COF, and GIP.

[0095] When the gate drive circuit 120 is implemented in GIP type, a plurality of gate drive integrated circuits (GDICs) of the gate drive circuit 120 can be directly formed in the bezel area of ​​the display panel 110. At this time, the gate drive integrated circuits (GDICs) can receive various signals (e.g., clock signals, gate high signals, gate low signals, etc.) required to generate scan signals through signal lines related to gate drive operation provided in the bezel area.

[0096] Furthermore, when the light-emitting drive circuit 122 is implemented in a GIP (Glass In-Place) configuration, the multiple light-emitting control circuits (ECCs) included in the light-emitting drive circuit 122 can be directly formed in the bezel area of ​​the display panel 110. In this case, the light-emitting control circuits (ECCs) can receive various signals (e.g., clock signals, light-emitting drive signals) required to generate the light-emitting signal EM through signal lines related to light-emitting operation provided in the bezel area.

[0097] Similarly, the data driving circuit 130 may include one or more source driver integrated circuits (SDICs), which may be mounted on the source film SF. A portion of the source film SF may be electrically connected to the display panel 110. Furthermore, electronic circuitry may be disposed on the source film SF to electrically connect the source driver integrated circuits (SDICs) and the display panel 110.

[0098] The display device 100 may include: at least one source printed circuit board (SPCB) for connecting multiple source driver integrated circuits (SDICs) to other devices via electronic circuitry; and a control printed circuit board (CPCB) for mounting various control components and electronic elements.

[0099] Other parts of the source film SF, which houses the active driver integrated circuit SDIC, can be connected to at least one source printed circuit board SPCB. That is, a portion of the source film SF, which houses the active driver integrated circuit SDIC, can be electrically connected to the display panel 110, and other parts of the source film SF can be electrically connected to the source printed circuit board SPCB.

[0100] The timing controller 140 and power management circuit 150 can be mounted on the control printed circuit board (CPCB). The timing controller 140 can control the operation of the data drive circuit 130 and the gate drive circuit 120. The power management integrated circuit 150 can provide drive voltage and drive current, or control voltage and current, for the display panel 110, the data drive circuit 130, the gate drive circuit 120, and the light-emitting drive circuit 122.

[0101] At least one of the source printed circuit board (SPCB) and the control printed circuit board (CPCB) can be electrically connected via at least one connecting member. For example, the connecting member can be a flexible printed circuit board (FPC), a flexible flat cable (FFC), etc. At least one of the source printed circuit board (SPCB) and the control printed circuit board (CPCB) can be integrated into a single printed circuit board.

[0102] The display device 100 may further include a setup board 170 electrically connected to a control printed circuit board (CPCB). The setup board 170 may also be referred to as a power board. A main power management circuit (M-PMC) 160 that manages the total power of the display device 100 may be located on the setup board 170. The main power management circuit 160 may be coupled to a power management integrated circuit 150.

[0103] In the display device 100 with the above configuration, a drive voltage is generated by a setting plate 170 and supplied to a power management integrated circuit 150. The power management integrated circuit 150 provides the drive voltage required for display driving operation or feature value sensing operation to a source printed circuit board (SPCB) via a flexible printed circuit (FPC) or a flexible flat cable (FFC). The drive voltage supplied to the source printed circuit board (SPCB) is transmitted to cause specific sub-pixels SP in the display panel 110 to emit light or sense specific sub-pixels SP in the display panel 110 via a source driver integrated circuit (SDIC).

[0104] Each sub-pixel SP disposed in the display panel 110 of the display device 100 may include a light-emitting element and circuit elements such as driving transistors for driving the light-emitting element.

[0105] The type and number of circuit elements constituting each sub-pixel SP can be determined according to different functions, designs, etc.

[0106] Figure 3 A view of a display panel of a display device according to an embodiment of the present disclosure, showing a gate drive circuit and a light emission drive circuit implemented in a GIP type.

[0107] refer to Figure 3 According to embodiments of the present disclosure, the display device 100 may include n gate lines GL1 to GLn (n is a natural number) and n light-emitting signal lines EL1 to ELn (n is a natural number) in an active region A / A on the display panel 110 for displaying images.

[0108] Here, the active region A / A is an area equipped with multiple sub-pixels SP (e.g., white sub-pixels, red sub-pixels, green sub-pixels, and blue sub-pixels) for emitting light of corresponding colors and displaying images. Additionally, multiple dummy pixels may be provided at some locations within the active region A / A that do not emit light due to the absence of a scan signal SCAN or data voltage Vdata, but have a similar load to the sub-pixels SP.

[0109] In embodiments of this disclosure, the active region A / A may include multiple sub-pixel regions that emit light of a corresponding color, and a region with non-emitting dummy pixels. Alternatively, the multiple sub-pixel regions that emit light of a corresponding color and the region with non-emitting dummy pixels may be referred to as a pixel array.

[0110] The gate drive circuit 120 can be disposed in the bezel region (Bezel) on the active region A / A side, where no pixels are formed, and can include n gate drive integrated circuits (GDIC1 to GDICn) corresponding to n gate lines GL1 to GLn.

[0111] Therefore, n gate driver integrated circuits GDIC1 to GDICn can provide scan signals SCAN to n gate lines GL1 to GLn.

[0112] Furthermore, the light-emitting driving circuit 122 can be disposed in the border area Bezel on the other side of the active area A / A where no pixels are formed, and can include n light-emitting control circuits ECC1 to ECCn corresponding to n light-emitting signal lines EL1 to ELn.

[0113] Therefore, n light-emitting control circuits ECC1 to ECCn can provide light-emitting signals EM to n light-emitting signal lines EL1 to ELn.

[0114] As described above, when the gate drive circuit 120 and the light-emitting drive circuit 122 are implemented in GIP type, it is not necessary to manufacture a separate integrated circuit with gate drive function and bond it to the display panel 110. Therefore, the number of integrated circuits can be reduced, and the connection process from the integrated circuits to the display panel 110 can be omitted. In addition, the size of the bezel area used to bond the integrated circuits in the display panel 110 can be reduced.

[0115] Alternatively, n gate driver integrated circuits GDIC1 to GDICn and n light emission control circuits ECC1 to ECCn can be set together only on one side of the bezel area.

[0116] Multiple clock lines CL, used to provide the gate clock GCLK required to generate the scan signal SCAN and supply the scan signal SCAN to the gate drive circuit 120, can be set in the bezel area (Bezel) on the active region A / A side, where no pixels are formed.

[0117] In addition, multiple light-emitting clock lines ECL, which are used to provide the light-emitting clock ECLK required to generate the light-emitting signal EM and provide the light-emitting signal EM to the light-emitting driving circuit 122, can be set in the border area Bezel on the other side of the active area A / A, where no pixels are formed.

[0118] Figure 4 A schematic diagram of a frequency-varying driving mode of a display device according to an embodiment of the present disclosure is shown.

[0119] refer to Figure 4 The display device 100 according to embodiments of the present disclosure may include a first mode Mode1 that displays moving image data at a higher first frequency, and a second mode Mode2 that displays static image data or low-speed image data at a lower second frequency.

[0120] For example, in the first mode (Mode1), motion image data can be displayed on the display panel 110 at a frequency of 120Hz, corresponding to the first frequency. When the display device 100 operates in the first mode (Mode1), the sub-pixels SP of the display panel 110 display motion image data transmitted from the timing controller 140 every 120 frames.

[0121] As described above, the period during which image data is continuously displayed on the display panel 110 at a higher driving frequency can be called a refresh frame. For example, when the driving frequency is 120Hz, all 120 frames per second in the first mode (Mode1) will be refresh frames for displaying image data.

[0122] Meanwhile, when the display device 100 operates in the second mode Mode2, which displays static image data or low-speed image data, the display device 100 may display specified image data on the display panel 110 during the initial period of the second mode Mode2, and may not display image data on the display panel 110 during the remaining periods.

[0123] For example, when entering the second mode (Mode2), the display device 100 can change the driving frequency from a first frequency of 120Hz to a second frequency of 1Hz. At this time, the image data displayed in the last period of the first mode (Mode1) can be displayed on the display panel 110 in the second mode (Mode2) with the frequency changed to 1Hz.

[0124] For example, in the second mode Mode2 driven at 1Hz, the display device 100 can display the image data displayed in the last frame of the first mode Mode1 once on the display panel 110, and can not display the image data for the rest of the time.

[0125] In this case, the subpixel SP can display image data once in the second mode (Mode2), but can retain the voltage stored in the storage capacitor Cst for the rest of the time.

[0126] As described above, the period during which the voltage stored in the storage capacitor Cst is maintained without transmitting image data to the display panel 110 can be called a skip frame. For example, when the drive frequency is 120Hz, the first frame of the second mode Mode2 will be a refresh frame for displaying image data, and the remaining frames will be skip frames without transmitting image data.

[0127] As mentioned above, power consumption can be reduced by not transmitting image data (DATA) during specific periods (skipped frames) in the second mode (Mode2) driven at a lower frequency.

[0128] Figure 5 A view of a sub-pixel circuit of a display device according to an embodiment of the present disclosure is shown.

[0129] refer to Figure 5 According to an embodiment of the present disclosure, the sub-pixel SP of the display device 100 includes a first switching transistor T1 to a sixth switching transistor T6, a driving transistor DRT, a storage capacitor Cst, and a light-emitting element ED.

[0130] In this paper, it is assumed that the light-emitting element ED emits light through the nth light-emitting signal EM, just like the nth sub-pixel SP.

[0131] Here, for example, the light-emitting element ED can be a self-emissive element, such as an organic light-emitting diode (OLED), capable of emitting its own light.

[0132] In the sub-pixel SP according to embodiments of the present disclosure, the second switching transistor T2 to the sixth switching transistor T6 and the driving transistor DRT can be P-type transistors. Furthermore, the first switching transistor T1 can be an N-type transistor.

[0133] P-type transistors are more reliable than N-type transistors. The advantage of P-type transistors is that, because the drain is electrically connected to the high-potential drive voltage VDDEL, the current flowing through the light-emitting element ED does not fluctuate due to the storage capacitor Cst. Therefore, it is easier to provide a stable current.

[0134] For example, the fourth switching transistor T4 and the sixth switching transistor T6 can be connected to the anode of the light-emitting element (ED). In this case, when the switching transistors T4 and T6 connected to the ED operate in the saturation region, a constant current can flow regardless of changes in the current and threshold voltage of the ED. Therefore, the reliability is relatively high.

[0135] In this sub-pixel SP structure, the N-type transistor T1 can be an oxide transistor formed using semiconductor oxides (e.g., a transistor with a channel formed by semiconductor oxides such as indium oxide, gallium oxide, zinc oxide, or IGZO), and the other P-type transistors DRT, T2 to T6 can be silicon transistors formed by semiconductors such as silicon (e.g., transistors with polysilicon channels formed by low-temperature processes such as LTPS or low-temperature polysilicon).

[0136] Oxide transistors have lower leakage current than silicon transistors. Therefore, when implemented using oxide transistors, the leakage current from the gate of the driving transistor DRT is reduced, and there is an effect that can reduce image quality defects such as flicker.

[0137] Meanwhile, except for the first switching transistor T1 corresponding to the N-type transistor, the remaining P-type transistors DRT, T2 to T6 can be made of low-temperature polycrystalline silicon.

[0138] A first scan signal SCAN1 is provided to the gate of the first switching transistor T1. The drain of the first switching transistor T1 is connected to the gate of the driving transistor DRT. The source of the first switching transistor T1 is connected to the source of the driving transistor DRT.

[0139] The first switching transistor T1 is turned on by the first scan signal SCAN1, and the operation of the driving transistor DRT is controlled by the high-potential driving voltage VDDEL stored in the storage capacitor Cst. The value of the high-potential driving voltage VDDEL can be from 2V to 3V.

[0140] The first switching transistor T1 can be formed from an N-type MOS transistor to constitute an oxide transistor. Since N-type MOS transistors use electrons as charge carriers, they have higher mobility and faster switching speeds than P-type MOS transistors.

[0141] The second scan signal SCAN2 is provided to the gate of the second switching transistor T2. The data voltage Vdata can be provided to the drain of the second switching transistor T2. The source of the second switching transistor T2 is connected to the drain of the driving transistor DRT through the first node N1.

[0142] The second switching transistor T2 is turned on by the second scan signal SCAN2 to provide a data voltage Vdata to the drain of the driving transistor DRT.

[0143] The emitted signal EM is supplied to the gate of the third switching transistor T3. The high-potential drive voltage VDDEL is supplied to the drain of the third switching transistor T3. The source of the third switching transistor T3 is connected to the drain of the driving transistor DRT through the first node N1.

[0144] The third switching transistor T3 is turned on by the light-emitting signal EM to provide a high-potential driving voltage VDD to the drain of the driving transistor DRT.

[0145] The light-emitting signal EM is supplied to the gate of the fourth switching transistor T4. The drain of the fourth switching transistor T4 is connected to the source of the driving transistor DRT through the third node N3. The source of the fourth switching transistor T4 is connected to the anode of the light-emitting element ED through the fourth node N4.

[0146] Therefore, the fourth switching transistor T4 is turned on simultaneously with the third switching transistor T3 through the light-emitting signal EM, and provides driving current to the anode of the light-emitting element ED.

[0147] The third scan signal SCAN3 is provided to the gate of the fifth switching transistor T5.

[0148] A stabilizing voltage VST is provided to the drain of the fifth switching transistor T5. The stabilizing voltage VST can be provided to the source of the driving transistor DRT in a driving mode with a lower driving frequency, and can be divided into an initialization voltage VINI for initializing the driving transistor DRT, a bias voltage VOBS for reducing the hysteresis of the driving transistor DRT, and a leakage current suppression voltage VLS for reducing leakage current according to the provision time.

[0149] The initialization voltage VINI can be between -6V and -4V, and the bias voltage VOBS can be between 5.5V and 7V. Additionally, the leakage current suppression voltage VLS can be between 2V and 5V.

[0150] The source of the fifth switching transistor T5 is connected to the source of the driving transistor DRT through the third node N3. The fifth switching transistor T5 is turned on by the third scan signal SCAN3 to provide a stable voltage VST to the source of the driving transistor DRT.

[0151] The fourth scan signal SCAN4 is provided to the gate of the sixth switching transistor T6.

[0152] Here, the fourth scan signal SCAN4 can be the third scan signal SCAN3 provided to a sub-pixel SP at another location. For example, when the third scan signal SCAN3 is provided to the nth gate line, the fourth scan signal SCAN4 can be the third scan signal SCAN3 provided to the (n+1)th gate line. That is, depending on the driving phase of the display panel 110, the fourth scan signal SCAN4 can be used as the third scan signal SCAN3 at another gate line GL.

[0153] The reset voltage VAR is supplied to the drain of the sixth switching transistor T6. The source of the sixth switching transistor T6 is connected to the anode of the light-emitting element ED through the fourth node N4.

[0154] The sixth switching transistor T6 is turned on by the fourth scan signal SCAN4 to provide a reset voltage VAR to the anode of the light-emitting element ED.

[0155] The gate of the driving transistor DRT is connected to the drain of the first switching transistor T1. The drain of the driving transistor DRT is connected to the source of the second switching transistor T2. The source of the driving transistor DRT is connected to the source of the first switching transistor T1.

[0156] The driving transistor DRT is turned on by the voltage difference between the source and drain of the first switching transistor T1 to provide driving current to the light-emitting element ED.

[0157] A high-potential drive voltage VDDEL is provided to one side of the storage capacitor Cst, and the other side of the storage capacitor Cst is connected to the gate of the drive transistor DRT. The storage capacitor Cst stores the voltage at the gate of the drive transistor DRT.

[0158] The anode of the light-emitting element ED is connected to the source of the fourth switching transistor T4 and the source of the sixth switching transistor T6. A low-potential drive voltage VSSEL is provided to the cathode of the light-emitting element ED.

[0159] Because the driving transistor DRT controls the driving current, the light-emitting element ED emits light at a predetermined brightness.

[0160] At this time, a reset voltage VAR is provided to reset the anode of the light-emitting element ED.

[0161] When the reset voltage VAR is supplied to the anode of the light-emitting element ED in the off state of the fourth switching transistor T4 located between the anode of the light-emitting element ED and the driving transistor DRT, the anode of the light-emitting element ED can be reset.

[0162] In order to perform the driving operation of the driving transistor DRT and the reset operation of the anode of the light-emitting element ED respectively, the third scan signal SCAN3, which provides the stable voltage VST, and the fourth scan signal SCAN4, which controls the supply of the reset voltage VAR to the anode of the light-emitting element ED, can have different phases.

[0163] When switching transistors T5 and T6, which provide the stabilizing voltage VINI and the reset voltage VAR, are turned on, the fourth switching transistor T4, which connects the source of the driving transistor DRT to the anode of the light-emitting element ED, can be turned off. Therefore, the drive current of the driving transistor DRT is blocked from flowing to the anode of the light-emitting element ED, thus preventing the anode from being affected by voltages other than the reset voltage VAR.

[0164] As described above, a sub-pixel SP comprising seven transistors DRT, T1, T2, T3, T4, T5, T6 and one capacitor Cst can be referred to as a 7T1C structure.

[0165] Here, a 7T1C structure is shown as an example of various types of subpixel SP circuits. The structure and number of transistors and capacitors constituting the subpixel SP can be varied. Furthermore, each of the multiple subpixel SPs can have the same structure, or some of the multiple subpixel SPs can have different structures.

[0166] At this time, because the bias voltage VOBS supplied to the source of the driving transistor DRT during the bias period has a relatively high level, leakage current may occur even if the third switching transistor T3 is turned off.

[0167] Even when the third switching transistor T3 is off, leakage current through the operation of the light-emitting element ED can cause luminous errors, such as black glare.

[0168] Therefore, the display device 100 of this disclosure can reduce image quality degradation due to leakage current by providing a leakage suppression voltage VLS with a level lower than the bias voltage VOBS after the bias period, so that no light emission error occurs in the light emission period after the bias period.

[0169] Figure 6 A schematic block diagram of a stable voltage generation circuit for a display device according to an embodiment of the present disclosure is shown.

[0170] refer to Figure 6 In the display device 100 according to an embodiment of the present disclosure, the stable voltage generation circuit 155 may include a shift register 152 and a buffer circuit 154.

[0171] The stable voltage generation circuit 155 operates according to the stable start pulse VSP and generates a stable voltage VST according to the stable clock VCLK. The stable voltage VST generated by the stable voltage generation circuit 155 is sequentially shifted and provided sequentially through the fifth switching transistor T5.

[0172] The buffer circuit 154 may have two nodes, Q and QB, which are important for the drive state, and may include a pull-up transistor TU and a pull-down transistor TD. Here, the gate of the pull-up transistor TU may correspond to the Q node, and the gate of the pull-down transistor TD may correspond to the QB node.

[0173] The shift register 152 can be referred to as a shift logic circuit and can be used to generate a stable voltage VST in sync with a stable clock VCLK.

[0174] The shift register 152 may include multiple transistors and control the gates of the pull-up transistor TU and the pull-down transistor TD that constitute the buffer circuit 154, so that the buffer circuit 124 can generate a stable voltage VST.

[0175] The shift register 152 sequentially enables its outputs according to the stable gate clock VCLK. In other words, by controlling the output time of the shift register 152 using the stable gate clock VCLK, a stable voltage VST with a predetermined level can be sequentially provided to the buffer circuit 154.

[0176] Each voltage state of the gate of the pull-up transistor TU and the gate of the pull-down transistor TD constituting the buffer circuit 154 can be changed by the shift register 152. Therefore, the buffer circuit 154 can provide an initialization voltage VINI for initializing the drive transistor DRT, a bias voltage VOBS for reducing the hysteresis of the drive transistor DRT, and a leakage current suppression voltage VLS for reducing leakage current.

[0177] In addition to the shift register 152 and the buffer circuit 154, the stable voltage generation circuit 155 may further include a level shifter.

[0178] In this case, the shift register 152 and the buffer circuit 154 that constitute the stable voltage generation circuit 155 can be connected in various structures.

[0179] Figure 7 An exemplary view of the relationship of a stable voltage generation circuit of a display device according to an embodiment of the present disclosure is shown.

[0180] refer to Figure 7The shift register 152 constituting the stable voltage generation circuit 155 in the display device 100 according to an embodiment of the present disclosure can be configured to correspond to a plurality of buffer circuits 154. Conversely, the plurality of buffer circuits 154 can be configured to correspond to a single shift register 152.

[0181] Here, an example is shown in which multiple shift registers 152[1] to 152[4] constituting the stable voltage generation circuit 155 are connected to multiple buffer circuits 154[1] to 154[4] in a 1:1 ratio.

[0182] The first shift register 152[1] of the stable voltage generation circuit 155 starts working by a stable start pulse VSP, and the second shift register 152[2] to the fourth shift register 152[4] can use the carry signal transmitted from the previous shift register as the stable start pulse VSP.

[0183] At this time, the carry signal used as the stable start pulse VSP can be the signal of the gate of the pull-up transistor TU or the gate of the pull-down transistor TD in the previous stage. Alternatively, it can be the stable voltage VST generated from the buffer circuit 154. Here, the case where the stable voltage VST of the previous stage is used as the stable start pulse VSP is shown.

[0184] For example, the first shift register 152[1] starts working by the first stable start pulse VSP, and the second shift register 152[2] to the fourth shift register 152[4] can be cascaded by using the stable voltages VST1 to VST3 of the previous stage as carry signals to generate stable voltages VST2 to VST4.

[0185] Meanwhile, in the display device 100 of this disclosure, the initialization voltage VINI can have a negative voltage level, while the bias voltage VOBS and the leakage suppression voltage VLS can have positive voltage levels.

[0186] Therefore, the stable voltage generation circuit 155 can transmit an initialization voltage VINI with a negative voltage level through the first output terminal, and can transmit a bias voltage VOBS and a leakage current suppression voltage VLS with a positive voltage level through the second output terminal.

[0187] In this case, the output timing of the bias voltage VOBS and the leakage suppression voltage VLS can be controlled by a switching circuit connected to the second output terminal of the bias voltage VOBS and the leakage suppression voltage VLS.

[0188] Figure 8 A view of a switching circuit for controlling the output timing of bias voltage and leakage suppression voltage of a display device according to an embodiment of the present disclosure is shown.

[0189] refer to Figure 8 The stable voltage generation circuit 155 in the display device 100 according to an embodiment of the present disclosure may include a first output terminal for generating an initialization voltage VINI, and a second output terminal for generating a bias voltage VOBS and a leakage current suppression voltage VLS.

[0190] The second output terminal can be connected to the switching circuit 156 to transmit the bias voltage VOBS or leakage suppression voltage VLS to the sub-pixel SP via the selection signal SEL.

[0191] The switching circuit 156 may include a first control transistor CT1, a second control transistor CT2, and an inverter INV. The first control transistor CT1 and the second control transistor CT2 each have a drain connected to the second output terminal of the stable voltage generation circuit 155. The inverter INV receives a selection signal SEL and has an output terminal connected to the gate of the first control transistor CT1 and an input terminal connected to the gate of the second control transistor CT2.

[0192] Therefore, the phase of the signal supplied to the gate of the first control transistor CT1 is opposite to the phase of the signal supplied to the gate of the second control transistor CT2. That is, the first control transistor CT1 and the second control transistor CT2 are driven alternately, wherein, by providing the selection signal SEL to the inverter INV, one of the first control transistor CT1 and the second control transistor CT2 is turned on, while the other is turned off.

[0193] Therefore, only one of the bias voltage VOB or the leakage current suppression voltage VLS generated from the second output terminal of the stabilizing voltage generation circuit 155 is provided to the sub-pixel SP via the selection signal SEL. The selection signal SEL can be provided from the timing controller 140.

[0194] Therefore, the display device 100 of this disclosure can determine the time when the stable voltage generation circuit 155 provides the initialization voltage VINI to the sub-pixel SP, and the time when the timing controller 140 provides the bias voltage VOBS or leakage suppression voltage VLS to the sub-pixel SP.

[0195] The voltage stabilization generation circuit 155 may be included in the power management circuit 150. Alternatively, the voltage stabilization generation circuit 155 may be included in a drive circuit such as the gate drive circuit 120 or the data drive circuit 130.

[0196] Figure 9 This is a signal waveform showing the levels of the initialization voltage, bias voltage, and leakage suppression voltage constituting the stable voltage of a display device according to an embodiment of the present disclosure.

[0197] refer to Figure 9 According to an embodiment of the present disclosure, the display device 100 can provide a stable voltage VST of different levels to the driving transistor DRT constituting the sub-pixel SP over time in a second mode Mode2 driven at a lower driving frequency.

[0198] For example, an initialization voltage VINI with a negative level can be provided during the initialization period INIT, which is used to initialize the driving transistor DRT, and a bias voltage VOBS with a first positive level can be provided during the bias period OBS, which is used to reduce the hysteresis of the driving transistor DRT. Furthermore, a leakage suppression voltage VLS with a second positive level can be provided during the leakage suppression period LS, which includes the emission period EMISSION, which includes the emission of the light-emitting element ED.

[0199] The leakage suppression period LS that provides the leakage suppression voltage VLS can be located between the second bias period OBS2 of the refresh frame and the third bias period OBS3 of the skip frame to reduce the leakage current caused by the bias voltage VOBS.

[0200] In this case, the initialization period INIT, which provides the initialization voltage VINI to the driving transistor DRT, can be included in the refresh frame that provides the data voltage Vdata to the sub-pixel SP.

[0201] Furthermore, the bias period OBS, which provides the bias voltage VOBS to the driving transistor DRT, can be included only in skip frames where image data DATA is not provided to the sub-pixel SP. Conversely, it can be included in both refresh frame periods where image data DATA is provided to the sub-pixel SP and skip frames where image data DATA is not provided to the sub-pixel SP.

[0202] The bias voltage VOBS used to reduce the hysteresis of the drive transistor DRT can have a relatively high level, and the leakage current suppression voltage VLS can have a lower level than the bias voltage VOBS, because the leakage current suppression voltage VLS is the voltage used to suppress leakage current.

[0203] Figure 10 The driving timing of a second mode of a display device driven at a lower driving frequency according to an embodiment of the present disclosure is shown.

[0204] refer to Figure 10 In the display device 100 according to an embodiment of the present disclosure, the second mode Mode2 driven at a lower driving frequency may include a first frame period and a second frame period divided from a frame period based on the synchronization signal SYNC.

[0205] The first frame period can be a refresh frame that displays image data DATA, and the second frame period can be a skip frame that does not transmit image data DATA.

[0206] The refresh frame can provide the data voltage Vdata, initialization voltage VINI, and reset voltage VAR for driving the subpixel SP.

[0207] A refresh frame is a period used to initialize the storage capacitor Cst and the voltage charged or remaining in the drive transistor DRT. In Mode 2, which is driven at a lower speed, the refresh frame can be partially set at the beginning of each frame. The effects of the data voltage Vdata and drive voltage stored in the sub-pixel SP in Mode 1, which is driven at a higher speed, can be eliminated during the refresh frame.

[0208] After the refresh operation is completed within the refresh frame, the light-emitting element ED can emit light according to the data voltage Vdata provided to the sub-pixel SP.

[0209] Simultaneously, a sampling process for compensating the characteristic values ​​(threshold voltage or mobility) of the driving transistor DRT can be performed within the refresh frame.

[0210] For example, when the first switching transistor T1 is turned on by the first scan signal SCAN1 to electrically connect the gate and source of the driving transistor DRT, the gate and source of the driving transistor DRT have substantially equal potentials.

[0211] At this time, when the second switching transistor T2 is turned on by the second scan signal SCAN2 to provide the data voltage Vdata, it forms a current path until the voltage difference Vgs between the gate and source of the driving transistor DRT reaches the threshold voltage of the driving transistor DRT. Therefore, the voltage difference between the gate and source of the driving transistor DRT increases.

[0212] In other words, when the data voltage Vdata is supplied to the drain of the driving transistor DRT, the voltage difference between the gate and source of the driving transistor DRT rises to the voltage difference between the data voltage and the threshold voltage. Therefore, the threshold voltage of the driving transistor DRT can be compensated.

[0213] As described above, the process of compensating for the characteristic values ​​of the driving transistor DRT through the sampling process can correspond to internal compensation.

[0214] Meanwhile, in order to reduce the hysteresis effect that may occur in the driving transistor DRT and improve the response characteristics, a bias voltage VOBS can be provided during the refresh frame.

[0215] For example, by providing a peak white grayscale voltage to the gate of the driving transistor DRT, the driving transistor DRT can be in an on-bias state where a large current flows between the drain and source of the driving transistor DRT.

[0216] On the other hand, by providing a peak black grayscale voltage to the gate of the driving transistor DRT, the driving transistor DRT can be in an off-bias state where no current flows between the drain and source of the driving transistor DRT.

[0217] Peak white grayscale voltage refers to the voltage supplied to the gate of the driving transistor DRT to make the light-emitting element ED emit light at peak white grayscale, and peak black grayscale voltage refers to the voltage supplied to the gate of the driving transistor DRT to make the light-emitting element ED emit light at peak black grayscale. For example, when the grayscale value is represented as an 8-bit digital value, peak black grayscale can refer to the minimum value "0", and peak white grayscale can refer to the maximum value "255".

[0218] At this time, because the sweep curves of the on-bias state and the off-bias state in the P-type driving transistor DRT are different, the current flowing between the drain and source of the driving transistor DRT may be different under the same gray level.

[0219] At this point, in grayscale representation, due to the voltage deviation between the gate and source of the driving transistor DRT, the current characteristics flowing between the drain and source of the driving transistor DRT change between the on-bias state and the off-bias state. This phenomenon is called hysteresis and may cause image retention.

[0220] Furthermore, the difference between the drive current flowing through the drain and source of the driving transistor DRT can cause instability in the driving characteristics of the light-emitting element ED, and may lead to brightness deviation.

[0221] In particular, when the operating mode of the display device 100 changes from the first mode Mode1 driven at a higher driving frequency to the second mode Mode2 driven at a lower driving frequency, image retention due to hysteresis may easily occur.

[0222] Therefore, when the display device 100 operates in the second mode Mode2 driven at a lower driving frequency, before the start of the emission period EMISSION of the light-emitting signal EM due to the low logic level L, a first bias period OBS1 and a second bias period OBS2 for setting the driving transistor DRT to the on-bias state can be executed to minimize image retention caused by hysteresis.

[0223] The bias periods OBS1 and OBS2 can be performed only once within a refresh frame, or they can be performed more than twice.

[0224] For the purposes described above, the driving transistor DRT can be set to an on-bias state by providing a bias voltage VOBS with a first positive level to the source of the driving transistor DRT before the start of the emission period EMISSION.

[0225] For example, in the refresh frame of Mode 2, which operates at a lower drive frequency, a bias voltage VOBS can be provided to the source of the drive transistor DRT before the start of the emission period EMISSION.

[0226] At this time, when the light-emitting signal EM is converted to a low logic level at the same time that the bias voltage VOBS is provided to the source of the driving transistor DRT, the bias voltage VOBS with a first positive level may cause leakage current to flow in the light-emitting element ED.

[0227] Therefore, the voltage level of the anode of the light-emitting element (ED) is higher than the conduction level of the ED, resulting in black glare or brightness deviation.

[0228] To improve this problem, the time period of the bias period OBS, including the two ends of the emission period EMISSION, can be set as the leakage suppression period LS, and a leakage suppression voltage VLS with a second positive level can be provided to the driving transistor DRT during the leakage suppression period LS to reduce leakage current.

[0229] The leakage suppression period LS can include the time from the end of the bias period OBS2 before the emission period EMISSION in the refresh frame to the end of the emission period EMISSION in the skip frame.

[0230] The second positive level of the leakage current suppression voltage VLS is used to reduce the leakage current flowing through the light-emitting element ED during the emission period EMISSION, and can have a value lower than the first positive level of the bias voltage VOBS.

[0231] A skip frame is a period of time during which the data voltage Vdata and drive voltage are charged or set in each frame. The skip frame continues from the completion of the refresh frame in each frame until the start of the next refresh frame.

[0232] During the skip frame, the anode of the light-emitting element (ED) can be reset to the reset voltage VAR. In this case, the anode of the ED can be reset to a predetermined voltage to improve flickering caused by the extended drive time of the skip frame due to driving the skip frame at a lower drive frequency.

[0233] Specifically, the data voltage Vdata within the skip frame remains at a low logic level L.

[0234] In addition, a third bias period OBS3, which provides the bias voltage VOBS, can be executed during the skip frame to reduce the hysteresis effect that may occur in the drive transistor DRT and improve the response characteristics.

[0235] In other words, when the display device 100 operates in the second mode Mode2, which operates at a lower driving frequency, the third bias period OBS3, which sets the driving transistor DRT to the on-bias state, can be executed in the skip frame to minimize the recognition of afterimages caused by hysteresis.

[0236] As described above, the display device 100 of this disclosure can reduce image quality degradation due to leakage current by providing a leakage suppression voltage VLS with a level lower than the bias voltage VOBS during the leakage suppression period LS, which includes the emission period EMISSION, so as to suppress the emission error due to leakage current during the emission period EMISSION after the bias period OBS2 of the refresh frame.

[0237] Meanwhile, the display device 100 of this disclosure can determine the first positive level of the bias voltage VOBS and the second positive level of the leakage suppression voltage VLS by reflecting the grayscale of the image data DATA provided during the refresh frame.

[0238] Figure 11 An exemplary view of the driving timing of a display device according to an embodiment of the present disclosure for determining the levels of bias voltage and leakage suppression voltage based on image data transmitted within a refresh frame is shown.

[0239] refer to Figure 11 When the first mode Mode1 driven at a higher driving frequency is changed to the second mode Mode2 driven at a lower driving frequency, the display device 100 according to the embodiment of the present disclosure can control the levels of the leakage suppression voltage VLS provided during the leakage suppression period LS and the bias voltage VOBS provided during the bias period OBS3 of the skip frame based on the image data DATA provided to the display panel 110 in the refresh frame or the data voltage Vdata provided to the display panel 110 through the data line DL.

[0240] For the purposes described above, the image data DATA provided to the display panel 110 during the refresh frame can be temporarily stored in the memory 142. In this case, the memory 142 storing the image data DATA can be located on the control printed circuit board (CPCB) together with the timing controller 140, or it can be located outside the control printed circuit board (CPCB).

[0241] Therefore, the timing controller 140 can predetermine the grayscale of the image data DATA to be provided from the memory 142 within the refresh frame. Furthermore, it can control the levels of the leakage suppression voltage VLS provided during the leakage suppression period LS and the bias voltage VOBS provided during the bias period OBS3 of the skip frame, based on the grayscale of the image data DATA provided within the refresh frame.

[0242] The power management circuit 150 can provide the source of the driving transistor DRT with a leakage current suppression voltage VLS and a bias voltage VOBS corresponding to the grayscale of the image data DATA provided in the refresh frame, according to the control of the timing controller 140.

[0243] For example, when the image data DATA provided within a refresh frame has a low grayscale level, the user is unlikely to detect image defects because the display panel 110 displays an image that is close to black. On the other hand, when the image data DATA provided within a refresh frame has a high grayscale level, the user is more likely to detect image defects, even minor ones, because the display panel 110 displays an image that is close to white.

[0244] Considering these characteristics, when the image data DATA provided within the refresh frame has a low gray level, the leakage current suppression voltage VLS and the bias voltage VOBS can be determined to be high, and when the image data DATA provided within the refresh frame has a high gray level, the leakage current suppression voltage VLS and the bias voltage VOBS can be determined to be low, thereby reducing image defects identified by the user.

[0245] Figure 12 An example is shown of a display device according to an embodiment of the present disclosure in which image data provided within a refresh frame is divided into multiple gray levels and leakage suppression voltage and bias voltage are determined according to the different gray levels of the image data.

[0246] refer to Figure 12 According to an embodiment of the present disclosure, the display device 100 can determine the leakage current suppression voltage VLS and the bias voltage VOB that can reduce image defects based on the different gray levels of the image data DATA.

[0247] In this case, the leakage suppression voltage VLS provided during the leakage suppression period LS and the bias voltage VOBS provided during the bias period OBS can determine the voltage that minimizes image defects for each grayscale of the image data DATA as the optimal level.

[0248] For example, when the image data DATA provided within the refresh frame has 9 gray levels G9, the leakage current suppression voltage VLS and bias voltage VOBS that can minimize image defects can be determined as levels VLS / VOBS (G0 to G9) within the range between 0 gray levels G0 and 9 gray levels G9. Furthermore, when the image data DATA provided within the refresh frame has 18 gray levels G18, the leakage current suppression voltage VLS and bias voltage VOBS that can minimize image defects can be determined as levels VLS / VOBS (G10 to G18) within the range between 10 gray levels G10 and 18 gray levels G18.

[0249] Furthermore, when the image data DATA provided within the refresh frame has 50 gray levels G50, the leakage current suppression voltage VLS and bias voltage VOBS that minimize image defects can be determined to be levels VLS / VOBS (G19 to G50) within the range of 19 gray levels G19 and 50 gray levels G50. Furthermore, when the image data DATA provided within the refresh frame has 144 gray levels G144, the leakage current suppression voltage VLS and bias voltage VOBS that minimize image defects can be determined to be levels VLS / VOBS (G51 to G144) within the range of 51 gray levels G51 and 144 gray levels G144.

[0250] Furthermore, when the image data DATA provided within the refresh frame has 255 gray levels G255, the leakage suppression voltage VLS and bias voltage VOBS that can minimize image defects can be determined as the level VLS / VOBS (G145 to G255) within the range between 145 gray levels G145 and 255 gray levels G255.

[0251] As an example, the leakage current suppression voltage VLS and bias voltage VOBS corresponding to the gray levels of the image data DATA described above are illustrated, and the gray levels of the image data DATA used to determine the levels of leakage current suppression voltage VLS and bias voltage VOBS can be changed differently.

[0252] As described above, by dividing the grayscale of the image data DATA provided within the refresh frame into multiple ranges, and determining the leakage current suppression voltage VLS and bias voltage VOBS as the optimal levels based on the range of each grayscale with the least image defect, the phenomenon of image defects that can be identified by the user can be effectively reduced.

[0253] Figure 13 A flowchart of a display driving method according to an embodiment of the present disclosure is shown.

[0254] refer to Figure 13The display driving method according to embodiments of the present disclosure may include: step S100, switching from a first mode driven at a higher driving frequency to a second mode driven at a lower driving frequency; step S200, providing an initialization voltage VINI with a negative level to the source of the driving transistor DRT during the initialization period INIT; step S300, providing a bias voltage VOBS with a first positive level to the source of the driving transistor DRT during the bias period OBS; and step S400, providing a leakage suppression voltage VLS with a second positive level different from the first positive level during the leakage suppression period LS including the emission period EMISSION.

[0255] The step S100, which switches from the first mode driven by a higher driving frequency to the second mode driven by a lower driving frequency, is a period for displaying static or low-speed images. A predetermined image may be displayed on the display panel 110 during the refresh frame of the second mode, and no image may be displayed on the display panel 110 during the remaining skip frames.

[0256] The step S200, which provides an initialization voltage VINI with a negative level to the source of the driving transistor DRT during the initialization period INIT, is the process of providing an initialization voltage VINI for initializing the driving transistor DRT during the refresh frame in which the data voltage Vdata is provided to the sub-pixel SP.

[0257] The step S300, which provides a bias voltage VOBS with a first positive level to the source of the driving transistor DRT during the bias period OBS, is a process of setting the driving transistor DRT to an on-bias state before the light-emitting element ED emits light, so as to minimize the image retention caused by hysteresis when the display device 100 operates in the second mode driven at a lower driving frequency.

[0258] The process of setting the driving transistor DRT to the on-bias state can be performed within a refresh frame or a skip frame, and can be performed only once or more than twice, respectively.

[0259] Step S400, which provides a leakage suppression voltage VLS having a second positive level different from the first positive level during the leakage suppression period LS including the EMISSION, is a process of providing a leakage suppression voltage VLS with a level lower than the bias voltage VOBS to the source of the driving transistor DRT, so as to reduce the leakage current flowing through the light-emitting element ED during the EMISSION.

[0260] By using the display driving method, the display device 100 of this disclosure can reduce image quality degradation due to leakage current by providing a leakage suppression voltage VLS with a level lower than the bias voltage VOBS during the leakage suppression period LS, which includes the emission period EMISSION, thereby reducing the emission error caused by leakage current during the emission period EMISSION after the bias period OBS of the refresh frame.

[0261] The foregoing description and accompanying drawings are for illustrative purposes only and provide examples of the technical concepts of this disclosure. Those skilled in the art to which this disclosure pertains will understand that various modifications and changes in form can be made, such as changes in combination, separation, substitution, and configuration, without departing from the essential characteristics of this disclosure. Therefore, the embodiments disclosed herein are intended to illustrate the scope of the technical concepts of this disclosure, and the scope of this disclosure is not limited to the embodiments. The scope of this disclosure should be interpreted based on the appended claims, so that all technical concepts included within the same scope as the claims fall within this disclosure.

Claims

1. A display device comprising: a display panel including a light emitting element, a drive transistor for supplying a drive current to the light emitting element using a drive voltage, and a plurality of switching transistors for controlling operation of the drive transistor; a gate driver circuit for supplying a plurality of scan signals to the display panel through a plurality of gate lines; a light emission driver circuit for supplying a plurality of light emission signals to the display panel through a plurality of light emission signal lines; a data driver circuit for supplying a data voltage to the display panel; and a timing controller for, in a low speed mode in which the display panel is driven at a low drive frequency, controlling to supply a leakage current suppression voltage to the drive transistor for a leakage current suppression period after a bias period in which a bias voltage is supplied to the drive transistor, wherein the low speed mode includes: a refresh frame in which the data voltage for driving the light emitting element is supplied; and a skip frame in which the data voltage is not supplied, wherein the bias voltage has a first positive level, and wherein the leakage current suppression voltage has a second positive level lower than the first positive level. the plurality of switching transistors include:

2. The display device according to claim 1, wherein a first switching transistor in which a first scan signal is supplied to a gate, a drain is connected to a gate and a storage capacitor of the drive transistor, and a source is connected to a source of the drive transistor; a second switching transistor in which a second scan signal is supplied to a gate, the data voltage is supplied to a drain, and a source is connected to a drain of the drive transistor; a third switching transistor in which the light emission signal is supplied to a gate, the drive voltage is supplied to a drain, and a source is connected to the drain of the drive transistor; a fourth switching transistor in which the light emission signal is supplied to a gate, the drive voltage is supplied to a drain, and a source is connected to an anode of the light emitting element; a fifth switching transistor in which a third scan signal is supplied to a gate, a stabilization voltage is supplied to a drain, and a source is connected to the source of the drive transistor; and a sixth switching transistor in which a fourth scan signal is supplied to a gate, a reset voltage is supplied to a drain, and a source is connected to the anode of the light emitting element. the stabilization voltage includes:

3. The display device of claim 2, wherein, an initialization voltage for initializing the drive transistor; the bias voltage; and the leakage current suppression voltage. the initialization voltage is supplied within the refresh frame, 4. The display device according to claim 3, wherein the bias voltage is supplied within the refresh frame or the skip frame, and the leakage current suppression voltage is supplied during the leakage current suppression period, and a light emission period in which the light emitting element emits light is included in the leakage current suppression period. the initialization voltage has a negative level.

5. The display device of claim 4, wherein, 6.The display device of claim 1, further comprising: a memory for storing image data supplied to the display panel, wherein the timing controller controls levels of the leakage current suppression voltage and the bias voltage according to a gray scale of the image data supplied from the memory within the refresh frame. ​ 7. A drive circuit of a display panel, wherein, The display panel includes a light emitting element, a drive transistor for supplying a drive current to the light emitting element using a drive voltage, and a plurality of switching transistors for controlling operation of the drive transistor, and the drive circuit includes: a shift register for generating a first output signal through a first node and a second output signal through a second node from a stable start pulse; a buffer circuit for transmitting an initialization voltage to a first output terminal and a bias voltage and a leakage suppression voltage to a second output terminal from the first output signal and the second output signal; and a switching circuit for supplying the bias voltage or the leakage suppression voltage to a source of the drive transistor according to a selection signal.

8. The drive circuit of claim 7, wherein, The switching circuit includes: a first control transistor and a second control transistor each having a drain connected to the second output terminal; and an inverter receiving the selection signal, an output terminal connected to a gate of the first control transistor, and an input terminal connected to a gate of the second control transistor.

9. The drive circuit of claim 7, wherein, The initialization voltage is supplied within a refresh frame in which a data voltage for driving the light emitting element is applied in a low-speed mode driven at a lower drive frequency; The bias voltage is supplied within the refresh frame or a skip frame in which the data voltage is not supplied in the low-speed mode driven at the lower drive frequency; and The leakage suppression voltage is supplied within a leakage suppression period including a light emission period in which the light emitting element emits light.

10. The drive circuit of claim 9, wherein, Levels of the leakage suppression voltage and the bias voltage are determined according to a gray scale of image data supplied within the refresh frame.

11. The drive circuit of claim 7, wherein, The initialization voltage has a negative level, The bias voltage has a first positive level, and The leakage suppression voltage has a second positive level lower than the first positive level.

12. A display driving method of a display panel, wherein, The display panel includes a light emitting element, a drive transistor for supplying a drive current to the light emitting element using a drive voltage, and a plurality of switching transistors for controlling operation of the drive transistor, and the display drive method includes: switching from a first mode driven at a higher drive frequency to a second mode driven at a lower drive frequency; supplying an initialization voltage having a negative level to a drive transistor within an initialization period; supplying a bias voltage having a first positive level to the drive transistor within a bias period; and supplying a leakage suppression voltage having a second positive level lower than the first positive level to the drive transistor within a leakage suppression period including a light emission period.

13. The display driving method according to claim 12, wherein The second mode includes: a refresh frame in which a data voltage for driving the light emitting element is supplied; and a skip frame in which the data voltage is not supplied.

14. The display driving method according to claim 13, wherein The initialization voltage is supplied within the refresh frame, The bias voltage is supplied within the refresh frame or the skip frame, and The leakage suppression voltage is supplied within the leakage suppression period including the light emission period in which the light emitting element emits light.

15. The display driving method according to claim 14, wherein Levels of the leakage suppression voltage and the bias voltage are determined according to a gray scale of image data supplied within the refresh frame.

Images