Method of fabricating integrated mos devices

Abstract

The application provides a manufacturing method of integrated MOS devices. First and second gate structures are respectively formed on first and second MOS device regions of a substrate. The first gate structure has a first gate dielectric layer with a thickness smaller than that of a second gate dielectric layer of the second gate structure. A first doping treatment is performed based on a first mask layer to form a first doping region with a first conductivity type in the substrate on both sides of the first gate structure and a second doping region with the first conductivity type in the substrate on both sides of the second gate structure. A second doping treatment is continuously performed based on the first mask layer to form a third doping region with a second conductivity type in the substrate on both sides of the first gate structure. The third doping region is located on an upper layer of the first doping region and extends to below the first gate conductive layer. Thus, the first, second and third doping regions are formed by using only one mask layer, which helps to save mask plates and reduce manufacturing costs.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and particularly relates to a manufacturing method of integrated MOS devices. BACKGROUND

[0002] BCD is a monolithic integrated technology, which can manufacture bipolar junction transistor (BJT), complementary metal oxide semiconductor (CMOS) devices and diffused metal oxide semiconductor (DMOS) devices on the same chip. The BCD technology not only integrates the high transconductance, strong load driving capability of bipolar devices and the high integration, low power consumption of CMOS, but also integrates the fast switching speed of DMOS power devices.

[0003] The integrated MOS device formed by the BCD technology can include MOS devices of multiple voltage grades. In order to form the LDD injection regions of the first voltage grade NMOS device, the first voltage grade PMOS device, the second voltage grade NMOS device and the second voltage grade PMOS device, and form the halo (HALO) injection regions in the first voltage grade NMOS device and the first voltage grade PMOS device, four different mask processes are required to respectively complete the (LDD+HALO) injection of the first voltage grade NMOS device, the (LDD+HALO) injection of the first voltage grade PMOS device, the LDD injection of the second voltage grade NMOS device and the LDD injection of the second voltage grade PMOS device in one flow process, which results in high manufacturing cost of the integrated MOS device. SUMMARY

[0004] The present application provides a manufacturing method of integrated MOS devices, which can save masks and reduce manufacturing cost.

[0005] In order to achieve the above purpose, the present application provides a manufacturing method of integrated MOS devices. The manufacturing method comprises:

[0006] A substrate is provided, which comprises a first MOS device region and a second MOS device region isolated from each other, and a first gate structure and a second gate structure are respectively formed on the first MOS device region and the second MOS device region, the first gate structure comprises a first gate dielectric layer and a first gate conductive layer which are sequentially stacked on the substrate, the second gate structure comprises a second gate dielectric layer and a second gate conductive layer which are sequentially stacked on the substrate, and the thickness of the first gate dielectric layer is less than the thickness of the second gate dielectric layer.

[0007] forming a patterned first mask layer on the substrate, the first mask layer exposing the substrate of the first MOS device region and the substrate of the second MOS device region;

[0008] performing a first doping process based on the patterned first mask layer, forming a first doped region having a first conductivity type in the substrate on both sides of the first gate structure, and forming a second doped region having the first conductivity type in the substrate on both sides of the second gate structure; and

[0009] continuing to perform a second doping process based on the patterned first mask layer, forming a third doped region having a second conductivity type in the substrate on both sides of the first gate structure, the third doped region being located in an upper layer of the first doped region and extending to below the first gate conductive layer, the first conductivity type being opposite to the second conductivity type, and the doping concentration of the third doped region being greater than the doping concentration of the first doped region.

[0010] Optionally, the substrate of the first MOS device region and the substrate of the second MOS device region are respectively formed with a first gate structure and a second gate structure, which includes:

[0011] forming a first dielectric layer covering an upper surface of the substrate;

[0012] removing the first dielectric layer on the first MOS device region and retaining the first dielectric layer on the second MOS device region;

[0013] forming a second dielectric layer covering an upper surface of the substrate and the first dielectric layer;

[0014] forming a gate material layer covering an upper surface of the second dielectric layer;

[0015] performing a patterning process on the gate material layer, the first dielectric layer, and the second dielectric layer, the remaining second dielectric layer in the first MOS device region becoming the first gate dielectric layer, and the remaining gate material layer in the first MOS device region becoming the first gate conductive layer; the remaining first dielectric layer and the remaining second dielectric layer in the second MOS device region becoming the second gate dielectric layer, and the remaining gate material layer in the second MOS device region becoming the second gate conductive layer.

[0016] Optionally, the substrate of the first MOS device region and the substrate of the second MOS device region are respectively formed with a first gate structure and a second gate structure, which includes:

[0017] the substrate surface of the second MOS device region on both sides of the second gate structure is further formed with a residual dielectric layer having a thickness of 80 angstroms to 100 angstroms,

[0018] The first doping treatment is performed by using a dopant with the first conductivity type.

[0019] Optionally, the second doping treatment has an implantation angle of 30 degrees to 60 degrees.

[0020] Optionally, the second doping treatment has an implantation energy of 20K to 30K and an implantation dose of 1e14 / cm 2 to 1e15 / cm 2 .

[0021] Optionally, the first gate dielectric layer has a thickness of 18 angstroms to 38 angstroms, and the second gate dielectric layer has a thickness of 118 angstroms to 158 angstroms.

[0022] Optionally, the substrate has the second conductivity type.

[0023] Optionally, the substrate further comprises a third MOS device region and a fourth MOS device region which are isolated from each other, and after the second doping treatment, the substrate further comprises:

[0024] The third MOS device region and the fourth MOS device region each have a well region with the first conductivity type,

[0025] The third MOS device region has a third gate structure formed on the well region, the third gate structure comprises a third gate dielectric layer and a third gate conductive layer which are stacked in sequence, and a fourth doping region with the second conductivity type is formed in an upper layer of the well region on both sides of the third gate structure,

[0026] The fourth MOS device region has a fourth gate structure formed on the well region, the fourth gate structure comprises a fourth gate dielectric layer and a fourth gate conductive layer which are stacked in sequence, the fourth gate dielectric layer has a thickness greater than that of the third gate dielectric layer, and a fifth doping region with the second conductivity type is formed in an upper layer of the well region on both sides of the fourth gate structure, the fifth doping region and the fourth doping region are formed simultaneously in the same process step;

[0027] An upper layer of the fourth doping region of the third MOS device region on both sides of the third gate structure has a sixth doping region with the first conductivity type, the sixth doping region further extends below the third gate conductive layer, and the sixth doping region has a doping concentration greater than that of the fourth doping region.

[0028] Optionally, the first MOS device region and the third MOS device region form devices with the same withstand voltage capability, the second MOS device region and the fourth MOS device region form devices with the same withstand voltage capability, and the device formed by the first MOS device region has a smaller withstand voltage capability than the device formed by the second MOS device region.

[0029] Optionally, before the first gate structure and the second gate structure are respectively formed on the first MOS device region and the second MOS device region, the substrate has a first conductivity type, and the substrate includes a well region with a second conductivity type in the first MOS device region and the second MOS device region.

[0030] In the first doping process, the first doping region with the first conductivity type is formed on the upper surface layer of the well region of the first MOS device region, and the second doping region with the first conductivity type is formed on the upper surface layer of the well region of the second MOS device region.

[0031] In the method for manufacturing the integrated MOS device, the substrate includes a first MOS device region and a second MOS device region which are isolated from each other, the first MOS device region and the second MOS device region respectively have a first gate structure and a second gate structure formed thereon, and the first gate dielectric layer of the first gate structure has a smaller thickness than the second gate dielectric layer of the second gate structure. Then, a patterned first mask layer is formed, and based on the patterned first mask layer, a first doping region with a first conductivity type is formed in the substrate on both sides of the first gate structure, and a second doping region with the first conductivity type is formed in the substrate on both sides of the second gate structure. Subsequently, based on the patterned first mask layer, a second doping region with a second conductivity type is formed in the substrate on both sides of the first gate structure, and the second doping region is located on the upper surface layer of the first doping region and extends to below the first gate conductive layer. In this way, by using one mask layer (i.e., the first mask layer) as a mask, the first doping region and the second doping region can be formed in the first MOS device region and the second MOS device region, respectively, and the third doping region can be formed on the upper surface layer of the first doping region, which helps to save mask plates and reduce the manufacturing cost of the integrated MOS device. Moreover, since the thickness of the second gate dielectric layer is greater than the thickness of the first gate dielectric layer, the dopant of the second doping process is less likely to pass through the second gate dielectric layer and enter the channel region below the second gate conductive layer, that is, the second doping process has a smaller impact on the device formed by the second MOS device region. In other words, by using the method for manufacturing the integrated MOS device, the manufacturing cost can be saved without affecting the performance of the devices formed by the MOS device regions. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 Flow chart of the method for manufacturing the integrated MOS device according to an embodiment of the present application.

[0033] Figures 2 to 9 Process cross-sectional view of the integrated MOS device manufactured by the method for manufacturing the integrated MOS device according to an embodiment of the present application.

[0034] Figure 10 Cross-sectional view of the integrated MOS device according to another embodiment of the present application.

[0035] Explanation of reference numerals:

[0036] 10 - substrate; 10a - first MOS device region; 10b - second MOS device region; 10c - third MOS device region; 10d - fourth MOS device region; 101 - well region of first conductivity type; 102 - channel isolation structure; 103 - first dielectric layer; 104 - second dielectric layer; 105 - gate material layer; 105a - first gate conductive layer; 105b - second gate conductive layer; 105c - third gate conductive layer; 105d - fourth gate conductive layer; 106a - first gate dielectric layer; 106b - second gate dielectric layer; 106c - third gate dielectric layer; 106d - fourth gate dielectric layer; 107a - first gate structure; 107b - second gate structure; 107c - third gate structure; 107d - fourth gate structure; 108 - first mask layer; 109 - first doped region; 110 - second doped region; 111 - third doped region; 112 - second mask layer; 113 - fourth doped region; 114 - fifth doped region; 115 - sixth doped region; 116 - well region of second conductivity type; 117 - second P-type halo doped region; 118 - second N-type halo doped region. DETAILED DESCRIPTION

[0037] The method for manufacturing the integrated MOS device according to the present application will be described in further detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent from the following description. It should be noted that the accompanying drawings are very simplified and use non-precise proportions only for the purpose of conveniently and clearly illustrating the embodiments of the present application.

[0038] In order to save mask plates and reduce the manufacturing cost of the integrated MOS device without affecting the performance of the devices formed in the individual MOS device regions, the present embodiment provides a method for manufacturing the integrated MOS device. Figure 1 Flow chart of the method for manufacturing the integrated MOS device according to an embodiment of the present application. As shown in Figure 1 the method for manufacturing the integrated MOS device comprises the following steps.

[0039] S1, providing a substrate, the substrate comprising a first MOS device region and a second MOS device region isolated from each other, a first gate structure and a second gate structure being formed on the first MOS device region and the second MOS device region respectively, the first gate structure comprising a first gate dielectric layer and a first gate conductive layer stacked on a top surface of the substrate in sequence, the second gate structure comprising a second gate dielectric layer and a second gate conductive layer stacked on the top surface of the substrate in sequence, a thickness of the first gate dielectric layer being less than a thickness of the second gate dielectric layer;

[0040] S2, forming a patterned first mask layer on the substrate, the first mask layer exposing the substrate of the first MOS device region and the substrate of the second MOS device region;

[0041] S3, based on the patterned first mask layer, performing a first doping treatment to form a first doped region having a first conductivity type in the substrate on both sides of the first gate structure, and to form a second doped region having the first conductivity type in the substrate on both sides of the second gate structure;

[0042] S4, continuing to perform a second doping treatment based on the patterned first mask layer to form a third doped region having a second conductivity type in the substrate on both sides of the first gate structure, the third doped region being located in an upper layer of the first doped region and extending below the first gate conductive layer, the first conductivity type being opposite to the second conductivity type, and a doping concentration of the third doped region being greater than a doping concentration of the first doped region.

[0043] Figures 2 to 10 A process cross-sectional view of an integrated MOS device fabricated by the method of fabricating an integrated MOS device according to an embodiment of the present application is shown in FIG. 1. The method of fabricating an integrated MOS device according to the embodiment will be described below with reference to FIG. 1. Figures 2 to 10 The method of fabricating an integrated MOS device according to the embodiment will be described below with reference to FIG. 1.

[0044] In the embodiment, the substrate 10 can be a silicon substrate. The substrate 10 can also be a germanium substrate, a silicon-germanium substrate, a silicon on insulator (SOI) or a germanium on insulator (GOT), etc. The substrate 10 can also be doped with certain doping particles to change electrical parameters according to design requirements. In an embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type can be P-type and the second conductivity type can be N-type.

[0045] In this embodiment, the first conductivity type is N-type, the second conductivity type is P-type, and the conductivity type of the substrate 10 can be the second conductivity type (P-type). In other embodiments, the first conductivity type is N-type, the second conductivity type is P-type, and the conductivity type of the substrate 10 can be the first conductivity type (N-type). In other embodiments, the first conductivity type is P-type, the second conductivity type is N-type, and the conductivity type of the substrate 10 can be the second conductivity type (N-type). In other embodiments, the first conductivity type is P-type, the second conductivity type is N-type, and the conductivity type of the substrate 10 can be the first conductivity type (P-type).

[0046] The following example illustrates the situation where the first conductivity type is N-type, the second conductivity type is P-type, and the substrate 10 is a substrate of the second conductivity type.

[0047] like Figure 2 As shown, the substrate 10 includes a first MOS device region 10a and a second MOS device region 10b that are isolated from each other. In one embodiment, as... Figure 2 As shown, the first MOS device region 10a and the second MOS device region 10b are isolated by a channel isolation structure 102. In another embodiment, the isolation method between the first MOS device region 10a and the second MOS device region 10b can also be junction isolation or local silicon oxide isolation (LOCOS), etc. The first MOS device region 10a can be used to form a first MOS device, and the second MOS device region 10b can be used to form a second MOS device. The first MOS device and the second MOS device have the same channel conductivity type; for example, both the first MOS device and the second MOS device are MOS devices of the first conductivity type (N-type).

[0048] like Figures 2 to 6 As shown, the substrate 10 may also have mutually isolated third MOS device region 10c and fourth MOS device region 10d. The third MOS device region 10c can be used to form a third MOS device, and the fourth MOS device region 10d can be used to form a fourth MOS device. The third MOS device and the fourth MOS device have the same channel conductivity type, for example, both are second conductivity type (P-type) MOS devices.

[0049] When the conductivity type of the substrate 10 is the second conductivity type, in order to form MOS devices of the second conductivity type in the third MOS device region 10c and the fourth MOS device region 10d, well regions 101 of the first conductivity type are formed in the substrates of both the third MOS device region 10c and the fourth MOS device region 10d.

[0050] like Figure 6As shown, a first gate structure 107a and a second gate structure 107b are respectively formed on the base of the first MOS device region 10a and the second MOS device region 10b, the first gate structure 107a includes a first gate dielectric layer 106a and a first gate conductive layer 105a which are sequentially stacked on the base 10, the second gate structure 107b includes a second gate dielectric layer 106b and a second gate conductive layer 105b which are sequentially stacked on the base 10, and the thickness of the first gate dielectric layer 106a is less than the thickness of the second gate dielectric layer 106b.

[0051] A third gate structure 107c is formed on the well region of the third MOS device region 10c, and the third gate structure 107c can include a third gate dielectric layer 106c and a third gate conductive layer 105c which are sequentially stacked on the base 10. A fourth gate structure 107d is formed on the well region of the fourth MOS device region 10d, and the fourth gate structure 107d can include a fourth gate dielectric layer 106d and a fourth gate conductive layer 105d which are sequentially stacked on the base 10, and the thickness of the fourth gate dielectric layer 106d is greater than the thickness of the third gate dielectric layer 106c.

[0052] In the embodiment, the first gate dielectric layer 106a and the third gate dielectric layer 106c can belong to the same deposition layer, and the thicknesses of the two can be equal. The second gate dielectric layer 106b and the fourth gate dielectric layer 106d can be formed by the same process, and the thicknesses of the two can be equal. However, it is not limited thereto, and in other embodiments, the first gate dielectric layer 106a, the second gate dielectric layer 106b, the third gate dielectric layer 106c and the fourth gate dielectric layer 106d can also be formed separately.

[0053] As an example, the method of forming the first gate structure 107a, the second gate structure 107b, the third gate structure 107c and the fourth gate structure 107d on the first MOS device region 10a, the second MOS device region 10b, the third MOS device region 10c and the fourth MOS device region 10d respectively can include: as shown, Figure 2 As shown, a first dielectric layer 103 is formed on the upper surface of the base 10, and the first dielectric layer 103 covers the upper surface of the base 10; as shown, Figure 3 As shown, the first dielectric layer 103 on the first MOS device region 10a and the third MOS device region 10c is removed, and the first dielectric layer 103 on the second MOS device region 10b and the fourth MOS device region 10d is retained; as shown, Figure 4 As shown, a second dielectric layer 104 is formed which covers the base 10 and the upper surface of the first dielectric layer 103; as shown, Figure 5 As shown, a gate material layer 105 is formed which covers the upper surface of the second dielectric layer 104; as shown, Figure 6As shown, the gate material layer 105, the first dielectric layer 103 and the second dielectric layer 104 are subjected to a patterning process, the remaining second dielectric layer 104 in the first MOS device region 10a becomes the first gate dielectric layer 106a, and the remaining gate material layer 105 in the first MOS device region 10a becomes the first gate conductive layer 105a; the remaining first dielectric layer 103 and the remaining second dielectric layer 104 in the second MOS device region 10b become the second gate dielectric layer 106b, and the remaining gate material layer 105 in the second MOS device region 10b becomes the second gate conductive layer 105b; the remaining second dielectric layer 104 in the third MOS device region 10c becomes the third gate dielectric layer 106c, and the remaining gate material layer 105 in the third MOS device region 10c becomes the third gate conductive layer 105c; the remaining first dielectric layer 103 and the remaining second dielectric layer 104 in the fourth MOS device region 10d become the fourth gate dielectric layer 106d, and the remaining gate material layer 105 in the fourth MOS device region 10d becomes the fourth gate conductive layer 105d.

[0054] In an embodiment, the material of the first dielectric layer 103 and the second dielectric layer 104 can include silicon oxide. In other embodiments, the material of the first dielectric layer 103 and the second dielectric layer 104 can include silicon nitride or silicon oxynitride or other dielectric material (or insulating material).

[0055] In the embodiment, in order to make the dopant of the second doping process pass through the first gate dielectric layer 106a into the channel under the first gate conductive layer 105a smoothly and not easily pass through the second gate dielectric layer 106b into the channel under the second gate conductive layer 105b, the thickness of the first gate dielectric layer 106a can range from 18 angstroms to 38 angstroms (for example, 28 angstroms), and the thickness of the second gate dielectric layer 106b can range from 118 angstroms to 158 angstroms (for example, 127 angstroms or 140 angstroms). The thickness of the third gate dielectric layer 106c can range from 18 angstroms to 38 angstroms (for example, 28 angstroms). The thickness of the fourth gate dielectric layer 106d can range from 118 angstroms to 158 angstroms (for example, 127 angstroms or 140 angstroms).

[0056] The gate material layer 105 may be made of doped polysilicon. The gate material layer 105 may be formed using techniques known in the art. A method for patterning the gate material layer 105 may include: forming a patterned photoresist layer on the upper surface of the gate material layer 105; using the patterned photoresist layer as a mask, etching the gate material layer 105 and stopping it in the underlying dielectric layers (including a first dielectric layer 103 and a second dielectric layer 104) to form a first gate conductive layer 105a, a second gate conductive layer 105b, a third gate conductive layer 105c, and a fourth gate conductive layer 105d.

[0057] During the process of patterning the gate material layer 105, the first dielectric layer 103, and the second dielectric layer 104 to form each gate structure, the dielectric layers (including the first dielectric layer 103 and the second dielectric layer 104) on both sides of the gate structure on each MOS device region are all or partially removed. In the case of partial removal, the dielectric layers on both sides of each gate structure are thinner than the dielectric layer directly below the gate conductive layer. Figure 6 As shown, on the first MOS device region 10a and the second MOS device region 10b, the dielectric layers on both sides of the first gate structure 107a and the third gate structure 107c are removed or are so thin as to be negligible; on the second MOS device region 10b and the fourth MOS device region 10d, residual dielectric layers are also formed on the substrate surfaces on both sides of the second gate structure 107b and the fourth gate structure 107d (i.e., the remaining first and second dielectric layers on the substrate surfaces of the second MOS device region 10b on both sides of the second gate conductive layer 105b and the fourth MOS device region 10d on both sides of the fourth gate conductive layer 105d).

[0058] In this embodiment, the thickness of the residual dielectric layer formed on the substrate surface of the second MOS device region 10b on both sides of the second gate structure 107b and the substrate surface of the fourth MOS device region 10d on both sides of the fourth gate structure 107d (e.g., Figure 6 The value of H in the figure can be 80 angstroms to 100 angstroms. The residual dielectric layer protects the substrate surface it covers and allows for shallower penetration of the dopant in the second MOS device region 10b and the fourth MOS device region 10d during subsequent doping processes, thus improving the performance of the integrated MOS device. In other embodiments, after forming the second gate structure 107b and the fourth gate structure 107d, there is no residual dielectric layer on the substrate surfaces of the second MOS device region 10b on both sides of the second gate conductive layer 105b and the fourth MOS device region on both sides of the fourth gate conductive layer 105d.

[0059] After the first gate conductive layer 105a, the second gate conductive layer 105b, the third gate conductive layer 105c and the fourth gate conductive layer 105d are formed, step S2 is performed, as shown in Figure 7 A patterned first mask layer 108 is formed on the substrate 10, as shown in the figure, the first mask layer 108 exposes the substrate of the first MOS device region 10a and the substrate of the second MOS device region 10b. It should be noted that when the upper surface of the substrate is also formed with a residual dielectric layer, the first mask layer 108 exposes the upper surface of the residual dielectric layer. The first mask layer 108 can cover the upper surfaces of the first gate conductive layer 105a and the second gate conductive layer 105b, so as to avoid the dopant entering the gate conductive layer and affecting the performance of the gate structure.

[0060] The method for forming the patterned first mask layer 108 on the substrate 10 can include: coating a photoresist layer on the substrate 10, exposing and developing the photoresist layer to form the patterned first mask layer 108.

[0061] After step S2 is completed, step S3 is performed, as shown in Figure 8 The first doping process is performed to form a first doped region 109 with the first conductivity type (N type) in the substrate on both sides of the first gate structure 107a, and a second doped region 110 with the first conductivity type in the substrate on both sides of the second gate structure 107b.

[0062] The side edge of the first doped region 109 can slightly extend below the first gate structure 107a; the side edge of the second doped region 110 can slightly extend below the second gate structure 107b. In this embodiment, the doping process can be realized by ion implantation. In other embodiments, the doping process can be realized by heat diffusion and high-temperature push-out.

[0063] In this embodiment, during the first doping process, the dopant with the first conductivity type needs to pass through the residual dielectric layer on both sides of the second gate structure 107b to form the second doped region 110, so the depth of the second doped region 110 is less than the depth of the first doped region 109. As shown in Figure 8As shown, in the embodiment, the substrate 10 has the second conductivity type, the first doped region 109 and the second doped region 110 are both of the first conductivity type, i.e. the conductivity type of the substrate 10 is different from that of the first doped region 109 and the second doped region 110, then the deep well region can not be provided in the first MOS device region 10a and the second MOS device region 10b, i.e. the first doped region 109 and the second doped region 110 of the first conductivity type can be directly formed in the substrate of the first MOS device region 10a and the second MOS device region 10b, which helps to simplify the process of forming the first MOS device and the second MOS device in the first MOS device region 10a and the second MOS device region 10b, and helps to save the manufacturing cost of the integrated MOS device. In other embodiments, the substrate 10 has the first conductivity type, the first doped region 109 and the second doped region 110 are both of the first conductivity type, i.e. the conductivity type of the substrate 10 is the same as that of the first doped region 109 and the second doped region 110, then the deep well region of the second conductivity type is provided in the first MOS device region 10a and the second MOS device region 10b, i.e. the first doped region 109 and the second doped region 110 of the first conductivity type need to be provided in the deep well region in the substrate.

[0064] The first-time doping process can be a tilt implantation. The first-time doping process can include at least two N-type ion implantations, each of which employs at least one of different dopants, implantation energies and implantation doses. Specifically, the first-time doping process can include a first N-type ion implantation and a second N-type ion implantation, the first N-type ion implantation having a higher implantation energy than the second N-type ion implantation.

[0065] As an example, the first N-type ion implantation and the second N-type ion implantation can employ the same implantation angle, for example, both within a range of 30 degrees to 60 degrees. The first N-type ion implantation can employ phosphorus as the dopant, 50K to 70K as the implantation energy, and 5e12 / cm 2 to 2e13 / cm 2 ; the second N-type ion implantation can employ arsenic as the dopant, 1K to 5K as the implantation energy, and 5e13 / cm 2 to 1e14 / cm 2 .

[0066] After the first-time doping process is completed, a second-time doping process is performed on the substrate 10, for example, by using a mask to cover the first MOS device region 10a and the second MOS device region 10b, and then performing ion implantation on the substrate 10. Figure 8As shown, based on the patterned first mask layer 108, a second doping process is performed to form a third doped region 111 with a second conductivity type (P-type) in the substrate on both sides of the first gate structure 107a. The third doped region 111 is located on the upper surface of the first doped region 109 and extends below the first gate conductive layer 105a. The doping concentration of the third doped region 111 is greater than that of the first doped region 109. The third doped region 111 can be referred to as the first P-type halo (HALO) doped region.

[0067] It should be noted that, as Figure 8 As shown, after the second doping treatment, a second P-type halo doped region 117 can be formed on the upper surface of the second doped region 110. Due to the obstruction of the residual dielectric layers on both sides of the second gate conductive layer 105b, the depth of the second P-type halo doped region 117 is less than the depth of the third doped region 111 (the first P-type halo doped region). Furthermore, since the thickness of the second gate dielectric layer 106b is greater than that of the first gate dielectric layer 106a, the dopant from the second doping treatment is less likely to penetrate the second gate dielectric layer 106b and enter the channel region under the second gate conductive layer 105b. In other words, the second P-type halo doped region 117 is less likely to extend below the second gate conductive layer 105b, or the amount of dopant from the second doping treatment that laterally enters below the second gate conductive layer 105b is relatively small, and will not significantly increase the doping concentration of the channel region of the second MOS device region 10b, thus not affecting the performance of the second MOS device formed in the second MOS device region 10b.

[0068] The second doping treatment can be performed by tilted implantation, for example, at an implantation angle of 30 to 60 degrees. The second doping treatment can be performed by ion implantation, with the implanted dopant (e.g., indium) being p-type, the implantation energy being 20 K to 30 K, and the implantation dose being 1e14 / cm². 2 ~1e15 / cm 2 .

[0069] like Figure 8 As shown, during the first and second doping processes, the patterned first mask layer 108 covers the third MOS device region 10c and the fourth MOS device region 10d. After the first and second doping processes are completed, the patterned first mask layer 108 is removed. Compared to using two mask layers to form the implantation regions of the respective devices in the first MOS device region 10a and the second MOS device region 10b, this embodiment requires only one mask layer to form the first doped region 109 and the third doped region 111 in the first MOS device region 10a, and the second doped region 110 and the second P-type halo doped region 117 in the second MOS device region 10b, effectively reducing the number of masks and significantly lowering manufacturing costs.

[0070] After removing the first mask layer 108, the method for manufacturing the integrated MOS device further comprises: Figure 9 As shown, the base of the third MOS device region 10c and the fourth MOS device region 10d are pre-formed with a well region 101 of the first conductivity type. A fourth doped region 113 of the second conductivity type is formed in the upper surface layer of the well region 101 of the third MOS device region 10c on both sides of the third gate structure 107c; a fifth doped region 114 of the second conductivity type is formed in the upper surface layer of the well region 101 of the fourth MOS device region 10d on both sides of the fourth gate structure 107d, the fifth doped region 114 is formed simultaneously with the fourth doped region 113 in the same process step; a sixth doped region 115 of the first conductivity type is formed in the upper surface layer of the fourth doped region 113 of the third MOS device region 10c on both sides of the third gate structure 107c, the sixth doped region 115 also extends below the third gate conductive layer 105c, and the doping concentration of the sixth doped region 115 is greater than that of the fourth doped region 113.

[0071] The specific steps for forming the fourth doped region 113 and the fifth doped region 114 can comprise: forming a patterned second mask layer 112 on the base 10, the second mask layer 112 exposes the base of the third MOS device region 10c and the base of the fourth MOS device region 10d (or the residual dielectric layer on the fourth MOS device region 10d); based on the patterned second mask layer 112, performing a third doping process to form the fourth doped region 113 in the upper surface layer of the well region 101 of the third MOS device region 10c on both sides of the third gate structure 107c, and to form the fifth doped region 114 in the upper surface layer of the well region 101 of the fourth MOS device region 10d on both sides of the fourth gate structure 107d. The side of the fourth doped region 113 can slightly extend below the third gate conductive layer 105c; the side of the fifth doped region 114 can slightly extend below the fourth gate conductive layer 105d.

[0072] It should be noted that due to the blockage of the residual dielectric layer on the fourth MOS device region 10d on both sides of the fourth gate conductive layer 105d, the depth of the fourth doped region 113 is greater than that of the fifth doped region 114.

[0073] The third doping treatment can be performed by ion implantation. The third doping treatment can include a first P-type ion implantation and a second P-type ion implantation, the first P-type ion implantation having a higher implantation energy than the second P-type ion implantation. The first P-type ion implantation and the second P-type ion implantation can have the same implantation angle, and at least one of implantation substance, implantation energy and implantation dose can be different.

[0074] For example, the first P-type ion implantation and the second P-type ion implantation can have an implantation angle of 30-60 degrees; the first P-type ion implantation can use boron as dopant, have an implantation energy of 50-70 K and an implantation dose of 5e12 / cm2-2e13 / cm2; and the second P-type ion implantation can use indium as dopant, have an implantation energy of 1-5 K and an implantation dose of 5e13 / cm2-1e14 / cm2. 2 2 2 2 .

[0075] Referring to Figure 9 , the step of forming the sixth doping region 115 on the upper surface layer of the fourth doping region 113 of the third MOS device region 10c on both sides of the third gate structure 107c includes: continuing to perform the fourth doping treatment based on the patterned second mask layer 112 to form the sixth doping region 115 on the upper surface layer of the fourth doping region 113 of the third MOS device region 10c on both sides of the third gate structure 107c. The sixth doping region 115 can be referred to as a first N-type halo doping region.

[0076] It should be noted that, as Figure 9 shown, after the fourth doping treatment, the upper surface layer of the fifth doping region 114 can form a second N-type halo doping region 118, and due to the blocking of the residual dielectric layer on both sides of the fourth gate conductive layer 105d, the depth of the second N-type halo doping region 118 is less than that of the sixth doping region 115 (first N-type halo doping region). In addition, due to the greater thickness of the fourth gate dielectric layer 106d than the third gate dielectric layer 106c, the dopant of the fourth doping treatment is not easy to penetrate through the fourth gate dielectric layer 106d into the channel region below the fourth gate conductive layer 105d, that is, the second N-type halo doping region 118 is not easy to extend below the fourth gate conductive layer 105d, or in other words, the amount of dopant of the fourth doping treatment laterally entering below the fourth gate conductive layer 105b is less, which is not enough to affect the performance of the fourth MOS device formed by the fourth MOS device region 10d.

[0077] ​​​The fourth doping treatment is an oblique implantation with an implantation angle of 30-60 degrees. The fourth doping treatment can be realized by ion implantation. The dopant used in the fourth doping treatment can be N-type (for example, arsenic), the implantation energy is 20-30 K, and the implantation dose is 1e14 / cm 2 ~1e15 / cm 2 .

[0078] It should be noted that in this embodiment, the first doping treatment and the second doping treatment are first performed in the first MOS device region 10a and the second MOS device region 10b, and then the third doping treatment and the fourth doping treatment are performed in the third MOS device region 10c and the fourth MOS device region 10d. However, it is not limited thereto. In other embodiments, the third doping treatment and the fourth doping treatment can be first performed in the third MOS device region 10c and the fourth MOS device region 10d, and then the first doping treatment and the second doping treatment are performed in the first MOS device region 10a and the second MOS device region 10b.

[0079] Figure 10 is a cross-sectional view of an integrated MOS device according to another embodiment of the present application. Referring to Figure 10 , the first conductivity type is N-type, and the second conductivity type is P-type. The conductivity type of the substrate 10 can be the first conductivity type (N-type). In order to form the MOS device of the first conductivity type, before the first gate structure 107a and the second gate structure 107b are formed on the first MOS device region 10a and the second MOS device region 10b, respectively, the manufacturing method can further include: forming a well region 116 (also referred to as a deep P-well) having the second conductivity type in the substrate of the first MOS device region 10a and the second MOS device region 10b. In the first doping treatment, the first doped region 109 having the first conductivity type is formed in the upper surface layer of the well region of the first MOS device region 10a, and the second doped region 110 having the first conductivity type is formed in the upper surface layer of the well region 116 of the second MOS device region 10b. The substrate of the third MOS device region 10c and the fourth MOS device region 10d can not be provided with a deep well, and the fourth doped region 113 and the fifth doped region 114 can be directly formed in the substrate 10. The method of forming the first doped region 109, the second doped region 110, the fourth doped region 113, and the fifth doped region 114 in the substrate 10 is similar to when the substrate 10 is of the second conductivity type, and is not repeated here.

[0080] In this embodiment, the first MOS device region 10a and the third MOS device region 10c form devices with the same withstand voltage capability, the second MOS device region 10b and the fourth MOS device region 10d form devices with the same withstand voltage capability, and the withstand voltage capability of the device formed by the first MOS device region 10a is less than that of the device formed by the second MOS device region 10b.

[0081] For example, NMOS devices are formed in the first MOS device region 10a and the second MOS device region 10b, and PMOS devices are formed in the third MOS device region 10c and the fourth MOS device region 10d. The working voltage of the MOS devices formed in the first MOS device region 10a and the third MOS device region 10c can be in the range of 1.5V to 1.8V. The working voltage of the MOS devices formed in the second MOS device region 10b and the fourth MOS device region 10d can be in the range of 5V to 6V.

[0082] The first gate dielectric layer 106a and the first gate conductive layer 105a of the first MOS device region 10a can be used to form a 1.8V NMOS device. The second gate dielectric layer 106b and the second gate conductive layer 105b of the second MOS device region 10b can be used to form a 5V NMOS device. The third gate dielectric layer 106c and the third gate conductive layer 105c of the third MOS device region 10c can be used to form a 1.8V PMOS device. The fourth gate dielectric layer 106d and the fourth gate conductive layer 105d of the fourth MOS device region 10d can be used to form a 5V PMOS device.

[0083] The manufacturing method of the integrated MOS device includes the following steps: the substrate 10 includes a first MOS device region 10a and a second MOS device region 10b which are isolated from each other; the first gate structure 107a and the second gate structure 107b are respectively formed on the substrate of the first MOS device region 10a and the second MOS device region 10b, and the thickness of the first gate dielectric layer 106a of the first gate structure 107a is less than the thickness of the second gate dielectric layer 106b of the second gate structure 107b; then, the first mask layer 108 is formed, and based on the first mask layer 108, the first doping region 109 with the first conductivity type is formed in the substrate on both sides of the first gate structure 107a by performing the first doping treatment, and the second doping region 110 with the first conductivity type is formed in the substrate on both sides of the second gate structure 107b; then, based on the first mask layer 108, the third doping region 111 with the second conductivity type is formed in the substrate on both sides of the first gate structure 107a by performing the second doping treatment, and the third doping region 111 is located in the upper layer of the first doping region 109 and extends to the lower side of the first gate conductive layer 105a. In this way, by using one mask layer (i.e. the first mask layer 108) as a mask, the first doping region 109 and the second doping region 110 can be respectively formed in the first MOS device region 10a and the second MOS device region 10b, and the third doping region 111 can be formed in the upper layer of the first doping region 109, which helps to save mask plates and reduce the manufacturing cost of the integrated MOS device. Moreover, since the thickness of the second gate dielectric layer 106b is greater than the thickness of the first gate dielectric layer 106a, the dopant of the second doping treatment is not easy to pass through the second gate dielectric layer 106b to the channel region below the second gate conductive layer 105b under the block of the second gate dielectric layer 106b, that is, the influence of the second doping treatment on the device formed in the second MOS device region 10b is small. That is, by using the manufacturing method of the integrated MOS device, the manufacturing cost can be saved without affecting the performance of the device formed in each MOS device region.

[0084] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present application without departing from the spirit and scope of the present application by using the disclosed methods and technical contents. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, which does not deviate from the technical solutions of the present application, is within the protection scope of the present application.

Claims

1. A method of fabricating an integrated MOS device, comprising: The method comprises the following steps: providing a substrate, the substrate comprising a first MOS device region and a second MOS device region isolated from each other, a first gate structure and a second gate structure being formed on the first MOS device region and the second MOS device region respectively, the first gate structure comprising a first gate dielectric layer and a first gate conductive layer which are sequentially stacked on the substrate, the second gate structure comprising a second gate dielectric layer and a second gate conductive layer which are sequentially stacked on the substrate, the thickness of the first gate dielectric layer being less than the thickness of the second gate dielectric layer; forming a patterned first mask layer on the substrate, the first mask layer exposing the substrate of the first MOS device region and the substrate of the second MOS device region; based on the patterned first mask layer, performing a first doping treatment to form a first doped region with a first conductivity type in the substrate on both sides of the first gate structure and a second doped region with the first conductivity type in the substrate on both sides of the second gate structure; and continuing to perform a second doping treatment based on the patterned first mask layer, the second doping treatment being inclined implantation to form a third doped region with a second conductivity type in the substrate on both sides of the first gate structure, the third doped region being located in an upper layer of the first doped region and extending laterally from the side of the first gate conductive layer to below the first gate conductive layer as a halo doped region, the first conductivity type being opposite to the second conductivity type, the doping concentration of the third doped region being greater than the doping concentration of the first doped region.

2. The method of claim 1, wherein The first gate structure and the second gate structure are respectively formed on the substrate of the first MOS device region and the substrate of the second MOS device region, comprising: forming a first dielectric layer covering the upper surface of the substrate; removing the first dielectric layer on the first MOS device region and retaining the first dielectric layer on the second MOS device region; forming a second dielectric layer covering the upper surface of the substrate and the first dielectric layer; forming a gate material layer covering the upper surface of the second dielectric layer; performing a patterning process on the gate material layer, the first dielectric layer and the second dielectric layer, the remaining second dielectric layer in the first MOS device region becoming the first gate dielectric layer, and the remaining gate material layer in the first MOS device region becoming the first gate conductive layer; the remaining first dielectric layer and the remaining second dielectric layer in the second MOS device region becoming the second gate dielectric layer, and the remaining gate material layer in the second MOS device region becoming the second gate conductive layer.

3. The production method according to claim 1 or 2, wherein The first gate structure and the second gate structure are respectively formed on the substrate of the first MOS device region and the substrate of the second MOS device region, comprising: the substrate surface of the second MOS device region on both sides of the second gate structure further forms a residual dielectric layer with a thickness of 80 angstroms to 100 angstroms, in the first doping treatment, the dopant with the first conductivity type forms the second doped region after passing through the residual dielectric layer.

4. The method of claim 1, wherein The injection angle of the second doping treatment is 30 degrees to 60 degrees.

5. The method of claim 1, wherein The second doping treatment has an injection energy of 20K-30K and an injection dose of 1e14 / cm 2 ~1e15 / cm 2 .

6. The method of claim 1, wherein The first gate dielectric layer has a thickness ranging from 18 angstroms to 38 angstroms, and the second gate dielectric layer has a thickness ranging from 118 angstroms to 158 angstroms.

7. The method of claim 1, wherein The substrate has the second conductivity type.

8. The manufacturing method as described in claim 7, characterized in that, The substrate further comprises a third MOS device region and a fourth MOS device region which are isolated from each other, and after the second doping process is performed, the substrate further comprises: The substrate of the third MOS device region and the fourth MOS device region each has a well region with the first conductivity type, The third gate structure is formed on the well region of the third MOS device region, and the third gate structure comprises a third gate dielectric layer and a third gate conductive layer which are sequentially stacked, and a fourth doped region with the second conductivity type is formed in the upper surface layer of the well region of the third MOS device region on both sides of the third gate structure, The fourth gate structure is formed on the well region of the fourth MOS device region, and the fourth gate structure comprises a fourth gate dielectric layer and a fourth gate conductive layer which are sequentially stacked, the fourth gate dielectric layer has a thickness greater than that of the third gate dielectric layer, and a fifth doped region with the second conductivity type is formed in the upper surface layer of the well region of the fourth MOS device region on both sides of the fourth gate structure, and the fifth doped region is formed simultaneously with the fourth doped region in the same process step; The upper surface layer of the fourth doped region of the third MOS device region on both sides of the third gate structure has a sixth doped region with the first conductivity type, and the sixth doped region further extends below the third gate conductive layer, and the sixth doped region has a doping concentration greater than that of the fourth doped region.

9. The manufacturing method as described in claim 8, characterized in that, The first MOS device region and the third MOS device region form devices with the same withstand voltage capability, the second MOS device region and the fourth MOS device region form devices with the same withstand voltage capability, and the device formed by the first MOS device region has a withstand voltage capability less than that of the device formed by the second MOS device region.

10. The method of claim 1, wherein The substrate has the first conductivity type, and before the first gate structure and the second gate structure are respectively formed on the first MOS device region and the second MOS device region, the substrate of the first MOS device region and the second MOS device region each has a well region with the second conductivity type, In the first doping process, a first doped region with the first conductivity type is formed in the upper surface layer of the well region of the first MOS device region, and a second doped region with the first conductivity type is formed in the upper surface layer of the well region of the second MOS device region.

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