Dynamic amplifier with large output swing

Abstract

The present application relates to a dynamic amplifier with large output swing. The dynamic amplifier includes a common-source amplifier configured to receive a gate voltage of a gate node and output a drain current to a drain node; a current mirror configured to mirror the drain current as an output current of an output node; a source capacitor connected to the source node; a load capacitor connected to the output node; a first switch configured to conditionally connect the gate node to an input voltage; a second switch configured to conditionally connect the gate node to a gate reset voltage; a third switch configured to conditionally connect the source node to a source reset voltage; a fourth switch configured to conditionally connect the drain node to a drain reset voltage; and a fifth switch configured to conditionally connect the output node to an output reset voltage.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to dynamic amplifiers, and more particularly to dynamic amplifiers with large output swing. BACKGROUND

[0002] Without using static bias current, a dynamic amplifier can amplify an input voltage signal into an output voltage signal according to a logic signal. Figure 1 is a schematic diagram of a prior art dynamic amplifier 100. The dynamic amplifier 100 comprises an n-channel metal oxide semiconductor (NMOS) transistor MN0 for receiving a gate voltage V a of a gate node 101 and outputting an output voltage V out of a drain node 102 according to a source voltage V b of a source node 103; a source capacitor C src connected to the source node 103; a drain capacitor C drn connected to the drain node 102; a first switch 131 for conditionally connecting the gate node 101 to an input voltage V in according to a first logic signal CK1; a second switch 132 for conditionally connecting the gate node 101 to a reference ground according to a second logic signal CK2; a third switch 133 for conditionally connecting the source node 103 to the reference ground according to a third logic signal CK3; and a fourth switch 134 for conditionally connecting the drain node 102 to a power supply node V DD . The dynamic amplifier 100 operates in a two-phase manner, which comprises a reset phase and an amplification phase. In the reset phase, the first logic signal CK1 is de-asserted, while the second logic signal CK2, the third logic signal CK3 and the fourth logic signal CK4 are asserted, so that the first switch 131 is closed (i.e. open) and the second switch 132, the third switch 133 and the fourth switch 134 are open (i.e. conductive). As such, the gate voltage V a and the source voltage V b are pulled down to the reference ground, and the output voltage V out is pulled up to the power supply node V DDIn the amplification phase, the first logic signal CK1 is positive, while the second logic signal CK2, the third logic signal CK3, and the fourth logic signal CK4 are negative, thus the first switch 131 is open, and the second switch 132, the third switch 133, and the fourth switch 134 are closed. As a result, the gate voltage V a is approximately the same as the input voltage V in . The NMOS transistor MN0 inputs a first current I1 to the source node 103, and draws a second current I2 from the drain node, causing the source voltage V b to rise and the output voltage V out to fall, until the gate-to source voltage of the NMOS transistor MN0 reaches its threshold voltage (hereinafter referred to as threshold voltage V th0 ). In the amplification phase, the amount of charge added to the source capacitance C src is approximately the same as the amount of charge removed from the drain capacitance C drn , and is determined by the difference between the input voltage V in and the threshold voltage V th0 of the NMOS transistor MN0. At the end of the amplification phase, the source-to-drain voltage of the NMOS transistor MN0 reaches its threshold voltage V th0 , and can be represented by Equations 1 and 2.

[0003] V b = V in -V th0 … (Equation 1)

[0004]

[0005] Equation 2 is based on charge conservation, i.e., the amount of charge added to the source capacitance C src is the same as the amount of charge removed from the drain capacitance C drn .

[0006] The gain (hereinafter referred to as gain G 100 ) of the dynamic amplifier 100 is defined as the incremental change of the output voltage V out divided by the incremental change of the input voltage V in , and can be represented by Equation 3.

[0007]

[0008] Thus, the gain of the dynamic amplifier 100 is determined by the source capacitance C src and the drain capacitance C drnthe ratio between them determines.

[0009] Since the drop of the output voltage V out is always accompanied by a proportional rise of the source voltage V b , the output voltage V out of the dynamic amplifier 100 is difficult to have a large swing. Since the output voltage V out cannot be lower than the source voltage V b , the drop of the output voltage V out is hindered by the rise of the source voltage V b .

[0010] It is desirable for one skilled in the art to have a dynamic amplifier that can allow a large output swing. SUMMARY

[0011] In one embodiment, the dynamic amplifier comprises: a common-source amplifier, receiving a gate voltage of a gate node, and outputting a drain current to a drain node according to a source voltage of a source node; a current mirror, mirroring the drain current as an output current of an output node; a source capacitor, connected to the source node; a load capacitor, connected to the output node; a first switch, conditionally connecting the gate node to an input voltage according to a first logic signal; a second switch, conditionally connecting the gate node to a gate reset voltage according to a second logic signal; a third switch, conditionally connecting the source node to a source reset voltage according to a third logic signal; a fourth switch, conditionally connecting the drain node to a drain reset voltage according to a fourth logic signal; and a fifth switch, conditionally connecting the output node to an output reset voltage according to a fifth logic signal; wherein in a reset phase, the first logic signal is negative, and the second logic signal, the third logic signal, the fourth logic signal, and the fifth logic signal are positive; in an amplification phase, the first logic signal is positive, and the second logic signal, the third logic signal, the fourth logic signal, and the fifth logic signal are negative. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a schematic diagram of a prior art dynamic amplifier.

[0013] Figure 2 is a schematic diagram of a dynamic amplifier according to one embodiment of the present disclosure.

[0014] LIST OF SYMBOLS

[0015] 100: dynamic amplifier

[0016] 131: first switch

[0017] 132: second switch

[0018] 133: third switch

[0019] 134: fourth switch

[0020] MN0: NMOS transistor

[0021] 101: gate node

[0022] 102: drain node

[0023] 103: source node

[0024] C drn : drain capacitance

[0025] C src : source capacitance

[0026] CK1: first logic signal

[0027] CK2: second logic signal

[0028] CK3: third logic signal

[0029] CK4: fourth logic signal

[0030] V DD : power supply node

[0031] V in : input voltage

[0032] V a : gate voltage

[0033] V b : source voltage

[0034] V out : output voltage

[0035] I1: first current

[0036] I2: second current

[0037] 200: dynamic amplifier

[0038] SW1: first switch

[0039] SW2: second switch

[0040] SW3: third switch

[0041] SW4: fourth switch

[0042] SW5: fifth switch

[0043] 210: common-source amplifier

[0044] MN1: NMOS transistor

[0045] 220: current mirror

[0046] MP1: first PMOS transistor

[0047] MP2: second PMOS transistor

[0048] NG: gate node

[0049] NS: source node

[0050] ND: drain node

[0051] NO: output node

[0052] C S : source capacitance

[0053] C L : load capacitance

[0054] C F : feedback capacitance

[0055] C1: first logic signal

[0056] C2: second logic signal

[0057] C3: third logic signal

[0058] C4: fourth logic signal

[0059] C5: fifth logic signal

[0060] V d0 : drain reset voltage

[0061] V i : input voltage

[0062] V g0 : gate reset voltage

[0063] V g : gate voltage

[0064] V s0 : source reset voltage

[0065] V s : source voltage

[0066] V SS1 : first reference ground node

[0067] V d : drain voltage

[0068] V o0 : output reset voltage

[0069] V o : output voltage

[0070] V SS2 : second reference ground node

[0071] I s : source current

[0072] I d : drain current

[0073] I o : output current DETAILED DESCRIPTION

[0074] The present disclosure relates to dynamic amplifiers. While the specification describes particular embodiments of the present disclosure, and what is described is presently preferred, it is to be understood that the disclosure is not limited to the particular embodiments described and / or shown, and that modifications can be made in various aspects, consisting in particular of the various features and combinations of features illustrated and / or described, without departing from the scope of the disclosure.

[0075] Those skilled in the art will appreciate the use of terminology and underlying concepts related to microelectronics technology used herein, such as "voltage", "current", "signal", "amplifier", "gain", "bias", "capacitance", "common-source amplifier", "current mirror", "load", "parallel connection", "circuit node", "reference ground", "direct current", "power supply", "metal oxide semiconductor (MOS) transistor", "complementary metal oxide semiconductor (CMOS) technology", "n-channel metal oxide semiconductor (NMOS) transistor", and "p-channel metal oxide semiconductor (PMOS) transistor". Such terminology is used in the context of microelectronics, and the relevant concepts will be apparent to those skilled in the art, and are therefore not explained in detail herein.

[0076] Units of measure such as femto-Farad (fF), nano-meter (nm), micrometer (μm), and the like, are understood by those skilled in the art without further explanation.

[0077] Without delving into a tedious description of how one element in a circuit schematic is connected to another, those skilled in the art can read a schematic of a circuit containing electronic elements (e.g., inductors, capacitors, resistors, NMOS transistors, PMOS transistors, etc.). Those skilled in the art can also recognize the symbols for a reference ground, a capacitor, an inductor, a resistor, and a PMOS transistor versus an NMOS transistor, and can recognize the "source terminal," the "gate terminal," and the "drain terminal" of a PMOS transistor versus an NMOS transistor. For brevity in the description, the "source terminal" is referred to simply as the "source," the "gate terminal" is referred to simply as the "gate," and the "drain terminal" is referred to simply as the "drain" for MOS transistors.

[0078] A circuit is a collection of transistors, capacitors, resistors, and / or other electronic devices that are connected to one another in a certain manner to achieve a certain function.

[0079] A power supply node is a circuit node that is nearly at a constant voltage, and so is a reference ground node. Both power supply nodes and reference ground nodes are DC nodes, but have different voltage levels; that is, the voltage level of a power supply node is greater than the voltage level of a reference ground node. In accordance with a convention widely used in the literature, in the circuits herein, "V DD " is denoted as a power supply node, and "V SS " is denoted as a reference ground node. If there are multiple power supply nodes in a single circuit, "V DD1 " is denoted as the first power supply node, and "V DD2 " is denoted as the second power supply node. If there are multiple reference ground nodes in a single circuit, "V SS1 " is denoted as the first reference ground node, and "V SS2 " is denoted as the second reference ground node.

[0080] A MOS transistor (either a PMOS transistor or an NMOS transistor) has a threshold voltage. When the gate-to-source voltage of an NMOS transistor is greater than the threshold voltage of the NMOS transistor, the NMOS transistor turns on; otherwise, the NMOS transistor turns off (i.e., when the gate-to-source voltage of the NMOS transistor is not greater than the threshold voltage of the NMOS transistor, the NMOS transistor turns off). In some literature, a PMOS transistor turns on when the gate-to-source voltage of the PMOS transistor is less than the threshold voltage of the PMOS transistor; otherwise, the PMOS transistor turns off (i.e., when the gate-to-source voltage of the PMOS transistor is not less than the threshold voltage of the PMOS transistor, the PMOS transistor turns off). This is based on the convention that the threshold voltage of a PMOS transistor is negative. In this document, the convention that the threshold voltage of a PMOS transistor is positive is used, and thus in this document, a PMOS transistor turns on when the source-to-gate voltage of the PMOS transistor is greater than the threshold voltage of the PMOS transistor; otherwise, the PMOS transistor turns off (i.e., when the source-to-gate voltage of the PMOS transistor is not greater than the threshold voltage of the PMOS transistor, the PMOS transistor turns off).

[0081] In this document, a "circuit node" is often simply referred to as a "node" when it is clear from the context that the "node" means a "circuit node".

[0082] A signal is a voltage with variable levels that carries some information and can change over time. The level of a signal at a point in time represents the state of the signal at that point in time. In this document, "signal" and "voltage signal" refer to the same thing and thus are interchangeable.

[0083] A logic signal is a voltage signal that has two states: a low state and a high state. A logic signal is in the high state when the voltage level of the logic signal is above a trip point; otherwise, the logic signal is in the low state (i.e., the logic signal is in the low state when the voltage level of the logic signal is not above the trip point). The low state is also referred to as a "0" state, and the high state is also referred to as a "1" state. With respect to a logic signal Q, when it is stated that the logic signal Q is "high" ("high level") or "low" ("low level"), it means that the logic signal Q is in the high state or the logic signal Q is in the low state. Similarly, when it is stated that the logic signal Q is "1" or "0", it means that the logic signal Q is in the "1" state or the logic signal Q is in the "0" state.

[0084] The first logic signal does not necessarily have the same trip point as the second logic signal.

[0085] If the first logic signal and the second logic signal are always in opposite states, the first logic signal is said to be the logical inversion of the second logic signal. That is, when the first logic signal is "low", the second logic signal is "high"; when the first logic signal is "high", the second logic signal is "low". When the first logic signal is the logical inversion of the second logic signal, the first logic signal is said to be the complement of the second logic signal.

[0086] A logic signal is often used as a control signal to enable or disable the function of a circuit. When a logic signal is in a logic state that enables the function of a circuit, the logic signal is said to be "positive"; otherwise, the logic signal is said to be "negative" (i.e., when a logic signal is in a logic state that disables the function of a circuit, the logic signal is said to be "negative"). When a logic signal is positive at a high level, it is said to be "active high". When a logic signal is positive at a low level, it is said to be "active low".

[0087] A switch is used extensively in this document. A switch is a device that conditionally connects a first node to a second node according to the control of a logic signal. When the logic signal is positive, the switch is open and equivalent to a short circuit; when the logic signal is negative, the switch is closed and equivalent to an open circuit.

[0088] A switch can be implemented by an NMOS transistor whose gate voltage is controlled by a high-level active logic signal, and whose source and drain are connected to the first node and the second node, respectively. In this case, the transition point of the high-level active logic signal is the same as the source voltage of the first node plus the threshold voltage of the NMOS transistor.

[0089] Alternatively, a switch can be implemented by a PMOS transistor whose gate voltage is controlled by a low-level active logic signal, and whose source and drain are connected to the first node and the second node, respectively. In this case, the transition point of the low-level active logic signal is the same as the source voltage of the first node minus the threshold voltage of the PMOS transistor (which is a positive voltage according to the convention used in this document).

[0090] Alternatively, the switch can be implemented using an NMOS transistor and a PMOS transistor connected in parallel. The gate voltage of the NMOS transistor is controlled by a high-level start-up logic signal, and the gate voltage of the PMOS transistor is controlled by a low-level start-up logic signal. The high-level and low-level start-up logic signals are complementary. This is called a "transmission gate" and is well known to those skilled in the art, therefore it will not be explained in detail here.

[0091] like Figure 2 As shown, according to one embodiment of this disclosure, the dynamic amplifier 200 includes a common-source amplifier 210 and a source capacitor C. S A current mirror 220, a load capacitor C L A first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, and a fifth switch SW5. A common-source amplifier 210 is used to receive a gate voltage V at a gate node NG. g And based on the source voltage V of the source node NS s Output a drain current I d The common-source amplifier 210 includes an NMOS transistor MN1, connected to a drain node ND. The source capacitance C... S Connect the source node NS to maintain the source voltage V. s The current mirror 220 is used to reflect the drain current I. d Mirroring is an output current I at an output node NO. o The current mirror 220 includes a first PMOS transistor MP1 and a second PMOS transistor MP2. The load capacitance C... L Connect the output node NO and use it to maintain an output voltage V. o The first switch SW1 is used to conditionally connect the gate node NG to an input voltage V according to a first logic signal C1. i The second switch SW2 is used to conditionally connect the gate node NG to a gate reset voltage V according to a second logic signal C2. g0 The third switch SW3 is used to conditionally connect the source node NS to a source reset voltage V based on a third logic signal C3. s0 The fourth switch SW4 is used to conditionally connect the drain node ND to a drain reset voltage V based on a fourth logic signal C4. d0 The fifth switch SW5 is used to conditionally connect the output node NO to an output reset voltage V based on a fifth logic signal C5. o0The dynamic amplifier 200 operates in a two-phase manner, which includes a reset phase and an amplify phase. In the reset phase, the second logic signal C2, the third logic signal C3, the fourth logic signal C4, and the fifth logic signal C5 are positive (thus, the second switch SW2, the third switch SW3, the fourth switch SW4, and the fifth switch SW5 are on and equivalent to short circuit), while the first logic signal C1 is negative (thus, the first switch SW1 is off and equivalent to open circuit). As such, the NMOS transistor MN1 is shut off, the gate voltage V g is tied to the gate reset voltage V g0 , the source voltage V s is tied to the source reset voltage V s0 , the drain voltage V d is tied to the drain reset voltage V d0 , and the output voltage V o is tied to the output reset voltage V o0 .

[0092] In the amplify phase, the second logic signal C2, the third logic signal C3, the fourth logic signal C4, and the fifth logic signal C5 are negative (thus, the second switch SW2, the third switch SW3, the fourth switch SW4, and the fifth switch SW5 are off and equivalent to open circuit), while the first logic signal C1 is positive (thus, the first switch SW1 is on and equivalent to short circuit). The gate voltage V g is tied to the input voltage V i . The source current I s of the NMOS transistor MN1 charges the source capacitance C S and pulls up the source voltage V s . The drain current I d is mirrored as the output current I o to charge the load capacitance C L and pull up the output voltage V o . A higher input voltage V i will cause the NMOS transistor MN1 to have a larger gate-source voltage, causing the drain current I d to be larger, causing the output current I o to be larger, and causing the output voltage V o to be larger.

[0093] In an embodiment, the gate reset voltage V g0 , the source reset voltage V s0 , the drain reset voltage V d0 , and the output reset voltage V o0 are chosen to satisfy the constraints of Equations 4-7.

[0094] Vd0 ≤ V DD … (Formula 4)

[0095] V g0 ≤ V d0 + V th1 … (Formula 5)

[0096] V g0 ≤ V s0 + V th1 … (Formula 6)

[0097] V o0 ≤ V DD … (Formula 7)

[0098] wherein V th1 is the threshold voltage of the NMOS transistor MN1.

[0099] The constraints of Formula 4, Formula 5 and Formula 6 ensure that the NMOS transistor MN1 is turned off during the reset phase, and the constraint of Formula 7 ensures that the current mirror can perform the current-mirroring function during the amplification phase.

[0100] At the end of the amplification phase, the gate-source voltage of the NMOS transistor MN1 reaches the threshold voltage V th1 of the NMOS transistor, and can be represented by Formula 8 and Formula 9.

[0101] V s = V i - V th1 … (Formula 8)

[0102]

[0103] wherein β is the current-mirroring factor of the current mirror 220, and can be represented by Formula 10.

[0104]

[0105] wherein W1 and L1 are the width and length of the first PMOS transistor MP1, and W2 and L2 are the width and length of the second PMOS transistor MP2.

[0106] Formula 9 is based on charge conservation and current mirroring, i.e., the increase in the charge of the load capacitor C L is equal to the increase in the charge of the source capacitor C S multiplied by the current-mirroring factor β of the current mirror 220.

[0107] The gain (hereinafter referred to as gain G 200 ) of the dynamic amplifier 200 is defined as the infinitesimal change of the output voltage V o divided by the infinitesimal change of the input voltage V i , and can be represented by equation 11.

[0108]

[0109] The dynamic amplifier 200 has some advantages. First, by using the current mirror 220, the dynamic amplifier 200 can have a large output swing, effectively avoiding the output voltage V o being limited by the source voltage V s . The output swing is only limited by the second PMOS transistor MP2, which can charge the output voltage V o to be close to the power supply node V DD , thus making the output voltage V o have a large swing. Second, the gain of the dynamic amplifier is determined by the ratio between the source capacitance C S and the load capacitance C L multiplied by the current mirror parameter β. Thus, a large gain can be achieved, and the circuit designer has more freedom in optimizing the design.

[0110] For example, but not limited to, in one embodiment: the dynamic amplifier 200 is fabricated on a silicon substrate using a 12 nm CMOS process technology; the power supply node V DD is 0.8 V (volt); the first reference ground node V SS1 is 0 V; the second reference ground node V SS2 is 0 V; the gate reset voltage V g0 is 0 V; the source reset voltage V s0 is 0 V; the drain reset voltage V d0 is 0.8 V; the output reset voltage V o0 is 0 V; the source capacitance C S is 200 fF; the load capacitance C L is 200 fF; the "W / L" (which stands for width / length) of the NMOS transistor MN1 is 2 μm / 16 nm; the "W / L" of the first PMOS transistor MP1 is 2 μm / 16 nm; and the "W / L" of the second PMOS transistor MP2 is 6 μm / 16 nm.

[0111] In a further embodiment, the dynamic amplifier 200 further comprises a feedback capacitance C F . The feedback capacitance C F is located between the drain node ND and the output node NO. The feedback capacitance C FThe purpose is to reduce the nonlinearity of the dynamic amplifier 200 through negative feedback. The nonlinear error of the output voltage V o out can be fed back to the drain node ND so that the second PMOS transistor MP2 adjusts the output current I o out, and in turn corrects the nonlinear error. For example, but not limited to, in an embodiment, the feedback capacitance C F is 25 fF.

[0112] It is well known that for a given first circuit, if each NMOS transistor is replaced by a PMOS transistor, if each PMOS transistor is replaced by an NMOS transistor, if each power node is replaced by a reference ground node, and if each reference ground node is replaced by a power node, then the second circuit formed after the replacement will be functionally identical to the original given first circuit. That is, in alternative embodiments not shown but clear to those skilled in the art, the dynamic amplifier 200 can be modified by using the following changes: the NMOS transistor MN1 is replaced by a PMOS transistor MP1' having an absolute value of threshold voltage V ’ th1 ; the first PMOS transistor MP1 is replaced by a first NMOS transistor MN1'; the second PMOS transistor MP2 is replaced by a second NMOS transistor MN2'; the power node V DD is replaced by a reference ground node V SS ; the first reference ground node V SS1 is replaced by a first power node V DD1 ; the second reference ground node V SS2 is replaced by a second power node V DD2 ; and the gate reset voltage V g0 , the source reset voltage V s0 , the drain reset voltage V d0 , and the output reset voltage V o0 are chosen to satisfy the constraints of equations 12-15.

[0113] V d0 ≥ V SS ………………………………………………(equation 12)

[0114] V g0 ≥ V d0 -V' th1 ………………………………………(equation 13)

[0115] V g0 ≥ V s0 -V' th1… … … … (Formula 14)

[0116] V o0 ≥V SS … … … … (Formula 15)

[0117] Formulae 12-14 can ensure that PMOS transistor MP1' is turned off in the reset phase. Formula 15 can ensure that the current mirror implemented by first NMOS transistor MN1' and second NMOS transistor MN2' can perform the current mirror function in the amplification phase.

[0118] This alternative embodiment is a flipped version of dynamic amplifier 200 and is functionally equivalent. In the appended claims, one of the NMOS and PMOS transistors is referred to as a first type of MOS transistor, while the other is referred to as a second type of MOS transistor. In dynamic amplifier 200, the first type of MOS transistor is an NMOS transistor, and the second type of MOS transistor is a PMOS transistor. In the alternative embodiment, the first type of MOS transistor is a PMOS transistor, and the second type of MOS transistor is an NMOS transistor.

[0119] Those skilled in the art will readily observe that numerous modifications and changes can be made to the devices and methods without departing from the scope of the disclosure. Accordingly, the above should not be construed as limiting the disclosure, but merely as exemplifications of the preferred embodiments thereof.

Claims

1. A dynamic amplifier operating in a two-phase mode including a reset phase and an amplify phase, the dynamic amplifier comprising: a common-source amplifier configured to receive a gate voltage of a gate node and output a drain current to a drain node according to a source voltage of a source node; a current mirror configured to mirror the drain current as an output current of an output node; a source capacitor connected to the source node; a load capacitor connected to the output node; a first switch configured to conditionally connect the gate node to an input voltage according to a first logic signal; a second switch configured to conditionally connect the gate node to a gate reset voltage according to a second logic signal; a third switch configured to conditionally connect the source node to a source reset voltage according to a third logic signal; a fourth switch configured to conditionally connect the drain node to a drain reset voltage according to a fourth logic signal; and a fifth switch configured to conditionally connect the output node to an output reset voltage according to a fifth logic signal; wherein, in the reset phase, the first logic signal is negative and the second, third, fourth, and fifth logic signals are positive, and in the amplify phase, the first logic signal is positive and the second, third, fourth, and fifth logic signals are negative. the common-source amplifier comprises a first metal-oxide-semiconductor transistor of a first type, a gate of the first metal-oxide-semiconductor transistor being connected to the gate node, a source of the first metal-oxide-semiconductor transistor being connected to the source node, and a drain of the first metal-oxide-semiconductor transistor being connected to the drain node.

2. The dynamic amplifier of claim 1, wherein, the current mirror comprises:

3. The dynamic amplifier of claim 2, wherein, a first metal-oxide-semiconductor transistor of a second type, a drain and a gate of the first metal-oxide-semiconductor transistor of the second type being connected to the drain node, and a source of the first metal-oxide-semiconductor transistor of the second type being connected to a direct current node; and a second metal-oxide-semiconductor transistor of the second type, a gate of the second metal-oxide-semiconductor transistor of the second type being connected to the drain node, a drain of the second metal-oxide-semiconductor transistor of the second type being connected to the output node, and a source of the second metal-oxide-semiconductor transistor of the second type being connected to the direct current node. the first metal-oxide-semiconductor transistor of the first type is an N-type metal-oxide-semiconductor transistor, the first metal-oxide-semiconductor transistor of the second type is a first P-type metal-oxide-semiconductor transistor, and the second metal-oxide-semiconductor transistor of the second type is a second P-type metal-oxide-semiconductor transistor. the direct current node is a power node, the drain reset voltage is not greater than a voltage of the power node, and the output reset voltage is not greater than the voltage of the power node.

4. The dynamic amplifier of claim 3, wherein, the gate reset voltage is not greater than a result between the drain reset voltage and a threshold voltage of the N-type metal-oxide-semiconductor transistor, and the gate reset voltage is not greater than a result between the source reset voltage and the threshold voltage of the N-type metal-oxide-semiconductor transistor.

5. The dynamic amplifier of claim 4, wherein, ​ 6. The dynamic amplifier of claim 5, wherein, ​ 7. The dynamic amplifier of claim 3, wherein, The first metal oxide semiconductor transistor is a P-type metal oxide semiconductor transistor, the first metal oxide semiconductor transistor of the second type is a first N-type metal oxide semiconductor transistor, and the second metal oxide semiconductor transistor of the second type is a second N-type metal oxide semiconductor transistor.

8. The dynamic amplifier of claim 7, wherein, The direct current node is a reference ground node, the drain reset voltage is not less than a voltage of the reference ground node, and the output reset voltage is not less than the voltage of the reference ground node.

9. The dynamic amplifier of claim 8, wherein, The gate reset voltage is not less than a result between the drain reset voltage and a threshold voltage of the P-type metal oxide semiconductor transistor, and the gate reset voltage is not less than a result between the source reset voltage and the threshold voltage of the P-type metal oxide semiconductor transistor.

10. The dynamic amplifier of claim 1, further comprising a feedback capacitor between the drain node and the output node.

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