Chip test socket and chip test method

Abstract

A chip test socket and a chip test method, wherein the chip test socket comprises: a base having opposite first and second faces; a first placement area on the first face, the first placement area being used for accommodating a first chip; a second placement area on the first face, the second placement area being used for accommodating a second chip; and a conversion board arranged on the base, the first chip and the second chip being coupled through the conversion board. The integrated chip test socket structure provided by the scheme can more conveniently realize the test of the first chip containing the function of the second chip, and can be compatible with the first chip of non-POP packaging and adapt to various test schemes on the test load board.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a chip testing socket and a chip testing method. Background Technology

[0002] A chip test socket is a static connector between a chip and a printed circuit board (PCB), playing a crucial role in chip testing. Currently, there are mature chip test socket solutions available on the market for various types of chips.

[0003] Taking Package on Package (POP) packaged chips as an example, chip test socket manufacturers have corresponding POP chip test socket solutions to test the memory function of POP packaged chips.

[0004] In practical applications, the inventors found that existing chip test sockets are difficult to meet the testing requirements in functional tests that require collaboration with other chips. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a chip test socket that can more conveniently complete the testing of a first chip that includes the function of a second chip, and is compatible with the first chip that is not in POP package, and can be adapted to various test schemes on the test load board.

[0006] To address the aforementioned technical problems, embodiments of the present invention provide a chip test socket, comprising: a base having a first side and a second side facing each other; a first placement area located on the first side, the first placement area being used to accommodate a first chip; a second placement area located on the first side, the second placement area being used to accommodate a second chip; and an adapter plate disposed on the base, the first chip and the second chip being coupled through the adapter plate.

[0007] Optionally, the first placement area and the second placement area are arranged side by side on the first surface.

[0008] Optionally, the chip test socket further includes: a first electrical connector disposed between the first placement area and the adapter board, the first electrical connector being used to couple the adapter board and the first chip.

[0009] Optionally, the first chip includes a storage module, and the first electrical connector is used to couple the adapter board and the storage module.

[0010] Optionally, the chip test socket further includes a second electrical connector disposed between the second placement area and the adapter board, the second electrical connector being used to couple the adapter board and the second chip.

[0011] Optionally, the chip test socket further includes a third electrical connector disposed in the first placement area and extending beyond the base, the third electrical connector being used to couple the first chip and the test load board.

[0012] Optionally, the first chip includes a non-memory module, and the third electrical connector is used to couple the non-memory module and the test load board.

[0013] Optionally, the third electrical connector includes a first end and a second end opposite to each other, the first end being located in the first placement area, and the second end extending beyond the base from the second surface.

[0014] Optionally, the adapter plate has at least one through hole to accommodate the third electrical connector, and the third electrical connector located in the at least one through hole extends from the adapter plate toward the first surface and the second surface.

[0015] Optionally, the chip test socket further includes: a first electrical connector disposed between the first placement area and the adapter board to couple the adapter board and the first chip; a second electrical connector disposed between the second placement area and the adapter board to couple the adapter board and the second chip; and a third electrical connector disposed in the first placement area and extending beyond the base to couple the first chip and the test load board; wherein, within the plane of the first surface, the first electrical connector is closer to the second electrical connector than the third electrical connector.

[0016] Optionally, the first electrical connector, the second electrical connector, and the third electrical connector are selected from conductive rubber and probes.

[0017] Optionally, the chip test socket further includes a cover that can move away from or towards the first surface to expose or close the first placement area and the second placement area.

[0018] Optionally, the chip test socket further includes a retaining portion for applying a force toward the second surface to the first chip located in the first placement area.

[0019] Optionally, the holding portion is also used to apply a force toward the second surface to the second chip located in the second placement area.

[0020] Optionally, the second chip includes a memory chip, which is detachably disposed in the second placement area.

[0021] Optionally, the first chip may also be coupled to a test load board via the adapter board to test the first chip in conjunction with the second chip.

[0022] This invention also provides a chip testing method, comprising: providing a test load board and the aforementioned chip test socket; placing the first chip in a first placement area; placing the second chip in a second placement area; connecting the chip test socket to the test load board; and testing the first chip in conjunction with the second chip to obtain test results.

[0023] Optionally, the chip test socket includes a cover that can move away from or towards the first surface to expose or close the first placement area and the second placement area. The cover has a holding portion on the side facing the first surface. After the second chip is placed in the second placement area, the method further includes: controlling the cover to move towards the first surface until the holding portion holds the first chip against the first placement area and / or the second chip against the second placement area.

[0024] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0025] This invention provides a chip test socket, comprising: a base having a first side and a second side facing each other; a first placement area located on the first side, the first placement area for accommodating a first chip; a second placement area located on the first side, the second placement area for accommodating a second chip; and an adapter board disposed on the base, wherein the first chip and the second chip are coupled through the adapter board. Compared with the prior art, this embodiment places the first chip and the second chip on the same side of the chip test socket by setting the first placement area and the second placement area, both located on the first side. The first chip and the second chip are coupled through the adapter board, enabling the second chip to be used to test the first chip. Therefore, this embodiment can more conveniently realize the testing of the first chip adapting to the function of the second chip, and can be compatible with the first chip in non-POP package. Moreover, the coupling of the first chip and the second chip through the adapter board avoids the problem of through-holes of the test load board seriously affecting signal integrity, and can also avoid back-drilling problems, reducing the requirements for the board manufacturer's production process and reducing the production cost of the test load board.

[0026] Furthermore, the first chip is also coupled to a test load board via the adapter board to at least jointly test the first chip with the second chip. Compared to the prior art scheme where the first chip is coupled to the second chip via a test load board, in this embodiment, the first and second chips are coupled via an adapter board, resulting in a closer distance between the first and second chips and avoiding performance impact on the first chip due to a greater distance between them. Furthermore, compared to the prior art where the first and second chips are placed in two separate chip test sockets, this embodiment provides an integrated chip test socket that simultaneously houses both the first and second chips. One test socket is smaller than two separate test sockets, reducing the layout complexity of the test load board. Furthermore, in the prior art, to facilitate functional testing of the second chip in stages such as final testing, the second chip is typically soldered onto the test load board. This testing method is highly susceptible to damage to the second chip. Specifically, due to the thickness and rapid heat dissipation of the test load board, disassembly and soldering of the second chip are difficult, requiring specialized technicians. The entire process is time-consuming, severely impacting chip mass production testing efficiency and capacity. In comparison, this implementation integrates the second chip into the chip test socket, making the replacement of the second chip easier, and the installation / removal of the second chip is simpler and takes less time, which helps to improve the efficiency and capacity of chip mass production testing.

[0027] Furthermore, the first chip may include a storage module and a non-storage module, with their interfaces located on the same side; the second chip may be a storage chip. Therefore, using the solution of this embodiment, a single chip test socket can achieve coupling between the storage module and the storage chip, as well as coupling between the non-storage module and the test load board, greatly improving the convenience of testing the first chip. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a chip test socket according to an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of the second side of a chip test socket according to an embodiment of the present invention;

[0030] Figure 3 yes Figure 1 Cross-sectional view along the AA direction;

[0031] Figure 4 yes Figure 3 Front view of the adapter plate;

[0032] Figure 5 This is a schematic diagram showing the connection between the first electrical connector, the second electrical connector, the third electrical connector, and the adapter board of a chip test socket according to an embodiment of the present invention.

[0033] Figure 6 This is a schematic diagram of the cover of a chip test socket according to an embodiment of the present invention;

[0034] Figure 7 This is a flowchart of a chip testing method according to an embodiment of the present invention. Detailed Implementation

[0035] As mentioned in the background section, in functional tests that require collaboration with other chips, such as testing the storage function of a memory chip in conjunction with another memory chip, the existing technology uses a POP chip test socket.

[0036] For example, in the final test (FT) conducted after chip packaging, the System-on-Chips (SOC) is connected to the load board via chip test sockets. To test the SOC's storage function, a memory chip is also required. The SOC needs to be coupled with the memory chip and the load board to test the storage function. Specifically, the chip test socket corresponding to the memory chip needs to be placed on the load board, or the memory chip needs to be soldered directly onto the load board. The load board, a PCB, serves as the carrier between the chip and the testing machine, which is the device used for chip testing.

[0037] The problem with the first approach is that, due to the large size of the chip test socket and the limited space on the test load board, placing the chip test sockets corresponding to the SOC and the memory chip on the test load board makes the layout of the test load board difficult. Moreover, this approach also results in a large distance between the SOC and the memory chip, affecting the storage function of the SOC.

[0038] The second approach has several drawbacks: the test load board is relatively thick and large, resulting in rapid heat dissipation and making it difficult to remove and replace the memory chips. Furthermore, test load boards are typically manufactured using through-hole technology, which significantly impacts signal integrity, necessitating back-drilling. Smart terminal SoCs are characterized by small chip areas, small minimum ball pitch, and small ball pads. Back-drilling places high demands on the PCB manufacturer's processes, and the cost of back-drilling both the memory chips and the SoC is substantial.

[0039] To test the storage functionality of POP-packaged chips, manufacturers produce corresponding chip test sockets (hereinafter referred to as POP chip test sockets). The POP chip test socket is characterized by having an upper test socket and a lower test socket. The upper test socket is located above the lower test socket along the height of the POP chip test socket. The POP-packaged chip is characterized by having a storage module interface on its upper surface and a non-storage module interface on its lower surface. The non-storage module interfaces are the interfaces for all other modules on the POP-packaged chip besides the storage module interface. During testing, the upper test socket is used to place the storage chip, and the lower test socket is used to place the POP-packaged SOC. This allows for the testing of the storage functionality of the POP-packaged SOC.

[0040] However, for non-POP packaged SoCs where the interfaces of the storage module and non-storage modules are located on the same side, this top-and-bottom arrangement of two test sockets cannot complete storage function testing. Currently, major chip test socket manufacturers only offer single-chip test socket solutions, meaning one chip test socket each for the storage chip and the SoC chip, and the interface of the SoC's storage module can only be routed to the test load board. Due to the high complexity of circuit design and manufacturing on the test load board, and with the increasing signal transmission rate of storage modules, most SoC manufacturers are now abandoning storage function testing at the FT stage and opting for system-level testing (SLT). However, SLT test coverage and mass production efficiency still need improvement.

[0041] To address the aforementioned technical problems, this invention provides a chip test socket, comprising: a base having a first side and a second side facing each other; a first placement area located on the first side, the first placement area being used to accommodate a first chip; a second placement area located on the first side, the second placement area being used to accommodate a second chip; and an adapter board disposed on the base, the first chip and the second chip being coupled through the adapter board. By employing this embodiment, the first chip and the second chip are placed on the same side of the chip test socket by setting the first placement area and the second placement area, both located on the first side. The first chip and the second chip are coupled through the adapter board, allowing the second chip to be used in conjunction to test the first chip. Therefore, this embodiment can more conveniently achieve testing of the first chip adapting to the function of the second chip, and is compatible with non-POP packaged first chips. Moreover, the coupling of the first chip and the second chip through the adapter board avoids the problem of through-holes on the test load board severely affecting signal integrity, and also avoids back-drilling issues, reducing the requirements for the board manufacturer's production process and lowering the production cost of the test load board.

[0042] Furthermore, the first chip is also coupled to a test load board via the adapter board to at least jointly test the first chip with the second chip. Thus, in this embodiment, the first chip and the second chip are coupled via the adapter board, resulting in a closer distance between them and avoiding any impact on the performance of the first chip due to a larger distance between them. Furthermore, compared to the prior art which uses two separate chip test sockets to house the first and second chips, this embodiment provides an integrated chip test socket that simultaneously houses both the first and second chips. One test socket is smaller than two separate test sockets, reducing the layout complexity of the test load board.

[0043] Furthermore, this implementation integrates the second chip into the chip test socket, making the replacement of the second chip easier, and simplifying the installation / removal of the second chip, while also reducing the time required for operation. This helps to improve the efficiency and capacity of chip mass production testing.

[0044] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0045] Figure 1 This is a schematic diagram of a chip test socket 1 according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the second side 2b of a chip test socket according to an embodiment of the present invention; Figure 3 yes Figure 1 Cross-sectional view along the AA direction;

[0046] Figure 4 yes Figure 3 Front view of intermediate connector plate 3; Figure 5 This is a schematic diagram showing the connection between the first electrical connector 4, the second electrical connector 5, and the third electrical connector 6 of a chip test socket 1 according to an embodiment of the present invention and the adapter plate 3. The diagram shows the through hole 34. Figure 1 The third electrical connector 6 located within the through hole 34 is not shown. This is to demonstrate the structure of the adapter plate 3. Figure 3 Details of the internal structure of base 2 are not shown.

[0047] Reference Figures 1 to 5The chip test socket 1 described in this embodiment may include a base 2, a first placement area 21, a second placement area 22, and an adapter plate 3. The base 2 has opposing first surfaces 2a and second surfaces 2b. The first placement area 21 is located on the first surface 2a and is used to accommodate a first chip. The second placement area 22 is located on the first surface 2a and is used to accommodate a second chip. The adapter plate 3 is disposed on the base 2. The first chip accommodated in the first placement area 21 and the second chip accommodated in the second placement area 22 are coupled through the adapter plate 3. The first chip accommodated in the first placement area 21 is also coupled to a test load board through the adapter plate 3 to at least jointly test the first chip with the second chip.

[0048] In this implementation scheme, the test load board serves as the carrier between the tester and the chip, and the tester is the device for testing the chip. Typically, the chip under test (DUT) is placed on chip test socket 1, which is then placed on the test load board and coupled to the circuitry on the test load board. The test load board is placed on the tester. The tester generates test stimulus signals and acquires the results output by the chip under test.

[0049] In this embodiment, the chip test socket 1 can be an integrated socket for placing the first chip and the second chip. It can be used to couple the first chip (e.g., a SOC) to a test load board, or to couple the first chip and the second chip (e.g., a memory chip), improving the testability of the first chip. The first and second chips share a single chip test socket 1, enabling testing of the first chip including the functions of the second chip (e.g., memory functions). Furthermore, both the first and second chips are flexibly interchangeable, facilitating chip replacement testing by testers and testing equipment. Here, "the first chip including the functions of the second chip" means that the first chip has functions compatible with the second chip; for example, if the second chip is a memory chip, the first chip has memory read / write functions.

[0050] The first chip may include a storage module and non-storage modules. Accordingly, the first chip has an interface for the storage module and an interface for the non-storage modules. The storage module is used to implement memory read / write functions, while the non-storage modules are other modules in the System-on-a-Chip (SoC) besides the storage module. The interfaces for the storage module and the non-storage modules of the first chip are located on the same side of the chip.

[0051] The following example demonstrates the storage function testing of a non-POP packaged SoC. It is worth noting that although this embodiment uses a non-POP packaged SoC as an example, the chip test socket 1 provided in this disclosure can also be used for testing other non-POP packaged chips.

[0052] In this embodiment of the invention, the first chip may be, for example, a non-POP packaged SOC with a storage module interface, and the second chip may be, for example, a storage chip.

[0053] For ease of description, the length direction of the chip test socket 1 in the illustration is denoted as the x-direction, the width direction as the y-direction, and the height direction as the z-direction. In this embodiment, any component A being above any component B means that the direction from component B to component A is the z-direction, and component A being below component B means that the direction from component B to component A is the opposite of the z-direction.

[0054] For example, the first face 2a is located above the second face 2b.

[0055] In some embodiments, the outline shape of the first placement area 21 can be set according to the outline shape of the SOC. Specifically, the first placement area 21 provides accommodating space for the SOC.

[0056] For example, the first surface 2a can be recessed towards the second surface 2b to form a first groove, which is adapted to form a first placement area 21. The contour shape of the groove wall of the first groove can be adapted to the contour shape of the SOC. Thus, the position of the SOC is defined by the groove wall of the first groove, which can fix the SOC in the first placement area 21 and prevent the SOC from moving relative to the base 2 during testing.

[0057] In some embodiments, the first placement area 21 and the base 2 can be detachably connected. For example, the first placement area 21 can be fixed to the first surface 2a of the base 2 by at least one screw 211. This facilitates the disassembly and replacement of the first placement area 21, improving the convenience of maintenance.

[0058] In some embodiments, the first placement area 21 can be integrally formed with the base 2. This simplifies the installation process of the chip test socket 1.

[0059] In some embodiments, the outline shape of the second placement area 22 can be set according to the outline shape of the memory chip. Specifically, the second placement area 22 provides accommodating space for the memory chip.

[0060] For example, the first surface 2a can be recessed towards the second surface 2b to form a second groove, which is adapted to form a second placement area 22. The contour shape of the groove wall of the second groove can be adapted to the contour shape of the memory chip. Thus, the position of the memory chip is defined by the groove wall of the second groove, which can fix the memory chip in the second placement area 22 and prevent the memory chip from moving relative to the base 2 during testing.

[0061] In some embodiments, a base positioning post 23 is provided on the second surface 2b, the base positioning post 23 extending from the second surface 2b in the opposite direction to the z-direction. The base positioning post 23 can be used to fix the base 2 to the test load plate.

[0062] For example, along the z-direction, the test load plate is positioned below the base 2, and the test load plate has base positioning holes corresponding to the base positioning posts 23. Furthermore, the base 2 can be moved in the opposite direction of the z-direction, causing the base positioning posts 23 to engage with the base positioning holes, thereby fixing the base 2 to the test load plate.

[0063] In one specific implementation, the first placement area 21 and the second placement area 22 can be arranged side by side on the first surface 2a. Specifically, within the plane of the first surface 2a, the first placement area 21 and the second placement area 22 can be arranged side by side. In the z-direction, the first placement area 21 and the second placement area 22 are located at the same height.

[0064] In one specific implementation, the base 2 can provide a mounting base for other components in the chip test socket 1. For example, the base 2 can be used to secure the adapter board 3.

[0065] In some embodiments, the adapter plate 3 can be fixed inside the base 2. For example, a receiving cavity 24 can be formed inside the base 2 to house the adapter plate 3.

[0066] In some embodiments, the outline shape of the receiving cavity 24 can be determined based on the outline shape of the adapter plate 3. For example, if the outline shape of the adapter plate 3 is approximately cuboid, the outline shape of the receiving cavity 24 can be set as a cuboid cavity adapted to the size of the adapter plate 3. This securely fixes the adapter plate 3.

[0067] In some embodiments, the adapter plate 3 can be mechanically fixed inside the base 2. For example, the adapter plate 3 has an adapter plate positioning hole 31, and screws (not shown) corresponding to the adapter plate positioning holes 31 can be provided on the base 2 to fix the adapter plate 3.

[0068] For example, a protrusion extending in the z-direction can be provided on the top or bottom wall of the receiving cavity 24, and the protrusion corresponds one-to-one with the positioning hole 31 of the adapter plate and the adapter plate 3 is fixed inside the base 2 by plug-in engagement.

[0069] Furthermore, the position of the adapter plate positioning hole 31 on the adapter plate 3 can be adjusted as needed to fit the base 2.

[0070] In one specific implementation, the adapter board 3 can be a high-density interconnect (HDI) board, which is a type of circuit board with a relatively high line distribution density.

[0071] In some embodiments, the adapter board 3 can be made of high-speed board material with low dielectric constant (DK) and low dissipation factor (DF) values. Here, "high-speed board material" generally refers to low-loss board material used in high-frequency, high-speed printed circuit boards.

[0072] In some embodiments, high-speed board materials with a DK value less than 4 and a DF value less than 0.02 can be used as preferred board materials, such as FR-4 and M6. The DK and DF values ​​can be selected according to the operating speed of the memory chip.

[0073] In one specific implementation, the adapter plate 3 may include a first part 32 and a second part 33. The first part 32 points in the opposite direction to the second part 33.

[0074] Furthermore, at least one through hole 34 may be provided on the adapter plate 3. For example, at least one through hole 34 is provided on the first part 32. In some embodiments, the axial direction of at least one through hole 34 is parallel to the direction from the second surface 2b to the first surface 2a (i.e., the z direction shown in the figure).

[0075] In some embodiments, the number of vias 34 can be set as needed. For example, the number and location distribution of vias 34 can be determined based on the interface of the non-memory modules of the SOC.

[0076] Specifically, the interface of the non-memory module of the SOC includes at least one pad. The number of pads corresponds to the number of vias 34. For example, the number of pads can be equal to the number of vias 34. When the SOC is located in the first placement area 21, for each pad, there is a corresponding via 34 below the pad in the z-direction.

[0077] Furthermore, the first part 32 has an exposed first interface 321. The second part 33 has an exposed second interface 331. The first interface 321 is for coupling the storage module of the SOC, and the second interface 331 is for coupling the storage chip. The first interface 321 and the second interface 331 are coupled through a storage circuit in the adapter board 3. This storage circuit is used to achieve interface adaptation between the SOC and the storage chip when they are coupled.

[0078] In some embodiments, the first part 32 may be disposed below the first placement area 21, and the second part 33 may be disposed below the second placement area 22.

[0079] For example, the adapter plate 3 is placed in the receiving cavity 24, with the first part 32 placed near the first placement area 21 and the second part 33 placed near the second placement area 22.

[0080] Furthermore, the top wall of the receiving cavity 24 may have a first opening 241 near the first interface 321 to communicate with the first placement area 21.

[0081] Furthermore, a second opening 242 may be formed in the top wall of the receiving cavity 24 near the second interface 331 to communicate with the second placement area 22.

[0082] Furthermore, the second surface 2b may have a third opening 243 below it, near at least one through hole 34. The test load plate may be disposed below the third opening 243.

[0083] In one specific implementation, the chip test socket 1 may include a first electrical connector 4, a second electrical connector 5, and a third electrical connector 6.

[0084] In some embodiments, the first electrical connector 4 and the third electrical connector 6 can be probes. The probes may have low insertion loss and low return loss characteristics.

[0085] Furthermore, the length of the probe can affect the high-speed signal transmission performance between coupled components. Specifically, the shorter the probe, made of the same material, the better the signal integrity and the stronger the high-speed signal transmission capability. Signal integrity refers to insertion loss, reflection loss (or simply reflection), and crosstalk characteristics. For example, a high-speed signal undergoes less signal change after passing through a shorter probe, indicating that the short probe transmits the signal with higher quality; while the same high-speed signal may be distorted (or deformed) after passing through a longer probe. This difference in signal integrity performance between short and long probes is due to the difference in signal integrity performance between them. For low-speed signals, the performance difference in signal integrity between short and long probes is not significant.

[0086] To distinguish them, probes can be divided into short probes and long probes based on their length values. Specifically, in the z-direction, probes with a length value less than the distance from the first surface 2a to the second surface 2b are called short probes, and probes with a length value greater than the distance from the first surface 2a to the second surface 2b are called long probes.

[0087] In some embodiments, the lengths of the short and long probes can be determined based on the highest operating rates of the SOC's storage and non-storage modules. For example, the length of the short probe can be set to approximately 2 mm. As another example, the length of the long probe can be set to a range of 3–4 mm.

[0088] In some embodiments, the first electrical connector 4 and the second electrical connector 5 can be conductive rubber, which has low insertion loss and low return loss characteristics. Specifically, the conductive rubber has a conductive part and an insulating part, the insulating part provides a mounting base for the conductive part, and the conductive part can couple components located on opposite sides of the conductive rubber.

[0089] In one specific implementation, the first electrical connector 4 can be disposed between the first placement area 21 and the adapter plate 3, and the first electrical connector 4 can be used to couple the adapter plate 3 and the SOC.

[0090] Specifically, along the z-direction, the first electrical connector 4 has an upper end and a lower end. The lower end of the first electrical connector 4 is coupled to the first interface 321 of the adapter board 3, the upper end of the first electrical connector 4 is coupled to the interface of the storage module of the SOC, and the lower end of the first electrical connector 4 is coupled to the first interface 321.

[0091] In some embodiments, the first electrical connector 4 may be a short probe. For example, the short probe is disposed between the first interface 321 and the first placement area 21, and its two ends are coupled to the interfaces of the first interface 321 and the storage module of the SOC, respectively.

[0092] In some embodiments, the first electrical connector 4 may be made of conductive rubber. For example, the conductive rubber is placed between the first interface 321 and the first placement area 21, and the two ends of the conductive part are coupled to the interfaces of the first interface 321 and the storage module of the SOC, respectively.

[0093] Thus, the SOC's storage module is coupled to the adapter board 3 via short probes or conductive rubber.

[0094] In one specific implementation, the second electrical connector 5 can be disposed between the second placement area 22 and the adapter board 3, and the second electrical connector 5 is used to couple the adapter board 3 and the memory chip.

[0095] Specifically, along the z-direction, the second electrical connector 5 has an upper end and a lower end. The lower end of the second electrical connector 5 is coupled to the second interface 331 of the adapter board 3, and the upper end of the second electrical connector 5 is coupled to the interface of the memory chip.

[0096] In some embodiments, the second electrical connector 5 may be a short probe. For example, the short probe is disposed between the second interface 331 and the second placement area 22, and its two ends are coupled to the second interface 331 and the interface of the memory chip, respectively.

[0097] In some embodiments, the second electrical connector 5 may be made of conductive rubber. For example, the conductive rubber is disposed between the second interface 331 and the second placement area 22, and the two ends of the conductive part are coupled to the second interface 331 and the interface of the memory chip, respectively.

[0098] In short, the memory chip can be coupled to the adapter board 3 via short probes or conductive rubber.

[0099] In some embodiments, the periphery of the conductive rubber can be fixed to the second placement area 22 by compression molding, thereby maintaining contact between the conductive rubber and the adapter plate 3. This simplifies the operation process and improves testing efficiency by requiring only the replacement of the memory chip.

[0100] In some embodiments, when the memory chip is a high-speed memory chip such as LPDDR5 and LPDDR5X, the second electrical connector 5 may be made of conductive rubber.

[0101] Thus, the memory chip and the SOC are coupled through the memory circuit on adapter board 3, enabling the SOC's memory function to operate. Since the memory circuit does not need to be designed on the test load board, the problem of through-holes on the test load board severely affecting signal integrity is avoided. Furthermore, back-drilling is avoided, reducing the requirements for the board manufacturer's production process and lowering the production cost of the test load board. In addition, because the SOC and memory chip are coupled through adapter board 3, the distance between the SOC and memory chip is relatively short, avoiding the impact on the SOC's memory performance caused by a large distance between them.

[0102] In one specific implementation, the third electrical connector 6 may be disposed in the first placement area 21 and extend beyond the base 2. The third electrical connector 6 may be used to couple the SOC and the test load board.

[0103] Furthermore, the third electrical connector 6 may include a first end 6a and a second end 6b opposite to each other, the first end 6a being located in the first placement area 21, and the second end 6b extending out of the base 2 from the second surface 2b.

[0104] In some embodiments, the third electrical connector 6 can be used to couple a non-memory module and a test load board. For example, the third electrical connector 6 is located below the non-memory module, and the test load board (not shown) can be disposed below the third opening 243, with its first end 6a coupled to the interface of the SOC's non-memory module and its second end 6b coupled to the test load board. Thus, the SOC's non-memory module and the test load board are coupled through the third electrical connector 6.

[0105] Furthermore, at least one through hole 34 can accommodate a third electrical connector 6, and the third electrical connector 6 located in at least one through hole 34 can extend from the adapter plate 3 toward the first surface 2a and the second surface 2b.

[0106] For example, the third electrical connector 6 can be a long probe. For instance, the long probe can be disposed within at least one through-hole 34, and the long probe has opposing first and second ends, the first end extending from a first surface 2a and the second end extending from a second surface 2b beyond the base 2. Thus, the non-memory module of the SOC is coupled to the test load board via the long probe. During testing, the SOC's memory function can be tested using the test circuitry on the test load board.

[0107] In some embodiments, the thickness of the adapter board 3 is less than 1 mm. Since the long probe passes through the through-hole 34 of the adapter board 3, if the length of the long probe is too long, it will affect the testing of high-speed signals on the SOC on the test load board. Therefore, the specific thickness of the adapter board 3 can be determined according to the performance requirements of the third electrical connector 6.

[0108] In a preferred embodiment, the thickness of the adapter plate 3 is approximately 0.4 mm.

[0109] In one specific implementation, within the plane containing the first surface 2a, the first electrical connector 4 is closer to the second electrical connector 5 than the third electrical connector 6.

[0110] Specifically, the positions of the first interface 321, the second interface 331, and at least one through hole 34 on the adapter board 3 can be set such that the first interface 321 is closer to the second interface 331 than the at least one through hole 34.

[0111] For example, along the x-direction, the first interface 321 is located between the second interface 331 and at least one via 34. It is worth noting that the distribution of the first interface 321 must correspond to the interfaces of the storage modules on the SOC, and the distribution of the vias 34 must correspond to the interfaces of the non-storage modules on the SOC. In some embodiments, some of the vias 34 may be distributed inside the first interface 321.

[0112] Furthermore, the first electrical connector 4 is disposed above the first interface 321, the second electrical connector 5 is disposed above the second interface 331, and the third electrical connector 6 is housed inside at least one through hole 34.

[0113] Therefore, when conducting chip testing, the SOC's storage module is placed closer to the storage chip, reducing or even eliminating the impact of distance on the SOC's storage function.

[0114] Figure 6 This is a schematic diagram of the cover 7 of a chip test socket 1 according to an embodiment of the present invention.

[0115] In a specific implementation, refer to Figures 1 to 6The chip test socket 1 may also include a cover 7, which can move away from the first surface 2a (the z-direction in the figure) to expose the first placement area 21 and the second placement area 22. Furthermore, the cover 7 can move towards the first surface 2a (the opposite direction of the z-direction in the figure) to close the first placement area 21 and the second placement area 22.

[0116] In some embodiments, when the bottom surface 7a of the cover 7 moves to above the first surface 2a in the opposite direction of the z-direction, the bottom surface 7a of the cover 7 can close the first placement area 21 and the second placement area 22. This allows the SOC located in the first placement area 21 and the memory chip located in the second placement area 22 to be held inside the chip test socket 1, preventing the SOC and memory chip from moving during testing and affecting the test results.

[0117] Furthermore, when the bottom surface 7a of the cover 7 moves away from the first surface 2a along the z-direction, the bottom surface 7a of the cover 7 can expose the first placement area 21 and the second placement area 22. This provides space for chip placement and removal, facilitating the replacement of the SOC and memory chip.

[0118] In one embodiment, the chip test socket 1 may further include a retaining part 8 for applying a force toward the second surface 2b (a force in the opposite direction of the z direction shown in the figure) to the SOC located in the first placement area 21.

[0119] Furthermore, the holding part 8 is also used to apply a force toward the second surface 2b (a force in the opposite direction of the z direction shown in the figure) to the memory chip located in the second placement area 22.

[0120] In some embodiments, the retaining part 8 may be disposed on the bottom surface 7a of the cover part 7, and by pressing the SOC and / or memory chip with the retaining part 8, a force in the opposite direction along the z direction is applied to the SOC and / or memory chip.

[0121] For example, the holding part 8 may include a first pressing block 81 and a second pressing block 82. The first pressing block 81 and the second pressing block 82 may be mounted on the bottom surface 7a of the cover part 7. When the bottom surface 7a of the cover part 7 moves to the first surface 2a, the first pressing block 81 may extend into the first placement area 21, and the second pressing block 82 may extend into the second placement area 22. The first pressing block 81 contacts the SOC, thereby applying a force to the SOC in the opposite direction along the z-direction. Correspondingly, the second pressing block 82 contacts the memory chip, thereby applying a force to the memory chip in the opposite direction along the z-direction.

[0122] In some embodiments, the positions of the first pressing block 81, the second pressing block 82, the first placement area 21, the second placement area 22, the cover positioning post 71, and the cover positioning hole 212 can be designed such that when the cover positioning post 71 is inserted and fixed in the cover positioning hole 212, the first pressing block 81 can extend into the first placement area 21, and the second pressing block can extend into the second placement area 22.

[0123] Furthermore, the first pressing block 81 can continue to move in the opposite direction along the z-axis to squeeze the SOC, and the second pressing block 82 can continue to move in the opposite direction along the z-axis to squeeze the memory chip.

[0124] The first pressure block 81 applies a force in the opposite direction (z-direction) to the SOC, ensuring good contact between the SOC's storage module interface and the first interface 321 of the adapter board 3 via the first electrical connector 4, and good contact between the SOC's non-storage module interface and the test load board via the third electrical connector 6. The second pressure block 82 applies a force in the opposite direction (z-direction) to the storage chip, ensuring good contact between the storage chip interface and the second interface 331 of the adapter board 3 via the second electrical connector 5. This prevents test failure due to poor contact.

[0125] In some embodiments, the thickness of the first pressing block 81 and the second pressing block 82 along the z-direction can be determined based on the forces applied to the conductive rubber, the long probe, and the short probe. For example, this can be determined experimentally. When the first pressing block 81 holds the SOC against the first placement area 21, and the forces applied to the long and short probes are approximately 25–30 gf (gram force), the thickness of the first pressing block 81 is suitable. When the second pressing block 82 holds the memory chip against the second placement area 22, and the forces applied to the conductive rubber are approximately 25 gf, the thickness of the second pressing block 82 is suitable.

[0126] In some embodiments, the first surface 2a may be provided with a plurality of cover positioning holes 212, and the bottom surface of the cover 7 may be provided with a plurality of cover positioning posts 71, wherein the cover positioning holes 212 and the cover positioning posts 71 correspond one-to-one. The cover 7 can be fixed to the base 2 by the insertion and engagement of the cover positioning holes 212 and the cover positioning posts 71. This ensures the accuracy of the cover 7's installation on the base 2.

[0127] In one embodiment, the memory chip is detachably disposed in the second placement area 22.

[0128] For example, the second pressure block 82 can be provided independently of the cover portion 7. The second pressure block 82 may have screw holes 821, and the second placement area 22 has corresponding screw holes 821. When installing the second pressure block 82, the screw holes 821 on the second pressure block 82 correspond to the screw holes 821 on the second placement area 22. The second pressure block 82 can be fixed in the second placement area 22 by the threaded engagement of screws (not shown) and screw holes 821. Furthermore, the force applied by the second pressure block 82 to the memory chip in the opposite direction along the z-direction can be increased by tightening the screws.

[0129] In some embodiments, the second pressure block 82 can also be detachably fixed to the second placement area 22 by means of bolts and nuts.

[0130] Therefore, when testing the storage functionality of multiple SoCs, only the SoC to be tested needs to be replaced, while the storage chip can remain fixed in chip test socket 1 without needing to be disassembled or replaced. This improves the efficiency of chip testing.

[0131] In some embodiments, the thickness of the second pressure block 82 along the z-direction can be determined by the groove depth of the second groove forming the second placement area 22, the thickness of the memory chip, and the force applied to the conductive rubber.

[0132] The chip test socket 1 of this embodiment can couple a System-on-a-Chip (SoC), a memory chip, and a test load board for functional testing, performance testing, and reliability testing of the SoC, such as FT, SLT, and Evaluation Board (EVB) testing scenarios. The main difference between FT, SLT, and EVB tests lies in the different test schemes on the test load board. The chip test socket 1 described in this embodiment can be used for various tests requiring both chip test sockets and memory function testing. It should be noted that although the above description uses an SoC and a memory chip as examples, the chip test socket 1 in this embodiment can also be used to test other types of chips. For example, the first chip can be a baseband chip with an RF interface, and the second chip can be an RF chip.

[0133] Figure 7 This is a flowchart of a chip testing method according to an embodiment of the present invention.

[0134] Specifically, the method can be used in conjunction with the above. Figures 1 to 6 The chip test socket 1 described in the embodiment shown is implemented to more conveniently realize the testing of the first chip containing the function of the second chip through a single chip test socket, and is compatible with the first chip in non-POP package and adaptable to various test schemes on the test load board.

[0135] Furthermore, refer to Figure 7The chip testing method described in this embodiment may include:

[0136] S101 provides a test load board and the above. Figures 1 to 6 The chip test socket 1 shown in the embodiment is described below;

[0137] S102, the first chip is placed in the first placement area 21;

[0138] S103, the second chip is placed in the second placement area 22;

[0139] S104, Connect the chip test socket 1 to the test load board;

[0140] S105, the first chip is tested in conjunction with the second chip to obtain the test results.

[0141] Specifically, the following example demonstrates the storage function testing of a non-POP packaged SOC. Accordingly, the first chip can be, for example, a non-POP packaged SOC, and the second chip can be, for example, a storage chip. When the SOC is placed in the first placement area 21, the non-storage module of the SOC can be coupled to the test load board through the chip test socket 1. Furthermore, when the storage chip is placed in the second placement area 22, the storage module of the SOC can be coupled to the storage chip through the chip test socket 1. Furthermore, the test load board can be used in conjunction with the storage chip to test the storage function of the SOC.

[0142] The order of steps S102, S103, and S104 can be interchanged, meaning that the order of steps S102 to S104 does not affect the SOC test.

[0143] In a typical application scenario, combined with Figures 1 to 7 In step S101, a test load board for testing the storage function of the SOC and the above-mentioned... Figures 1 to 6 The chip test socket 1 shown in the embodiment.

[0144] Furthermore, in step S102, the SOC can be placed in the first placement area 21 using a gripping device. At this time, the interface of the SOC's storage module is coupled to the upper end of the first electrical connector 4, and the interface of the SOC's non-storage module is coupled to the first end 6a of the third electrical connector 6.

[0145] Furthermore, in step S103, the memory chip can be placed in the second placement area 21 by the gripping device, at which time the interface of the memory chip is coupled to the upper end of the second electrical connector 5.

[0146] Furthermore, in step S104, the test load board can be placed on... Figures 1 to 6Below the chip test socket 1 described in the illustrated embodiment. The chip test socket 1 is moved in the opposite direction of the z-direction to insert the base positioning post 23 into the corresponding base positioning hole of the test load board, so that the chip test socket 1 is aligned with the test load board. At this time, the second end 6b of the third electrical connector 6 can be coupled to the test circuit on the test load board.

[0147] Furthermore, in step S105, the test machine is started, and the SOC is made to run the storage function through the storage chip by the test circuit on the test load board, and the test results are output.

[0148] In one specific implementation, the chip test socket 1 may include a cover 7 that can move away from or towards the first surface 2a to expose or close the first placement area 21 and the second placement area 22. The side of the cover 7 facing the first surface 2a is provided with a holding part 8. After the memory chip is placed in the second placement area 22, the cover 7 may be controlled to move towards the first surface 2a until the holding part 8 holds the SOC against the first placement area 21 and / or the memory chip against the second placement area 22.

[0149] Specifically, the cover 7 is used to close the first placement area 21 and / or the second placement area 22 to ensure that the SOC and / or memory chip will not be removed from the chip test socket 1 during testing, and to ensure that chip testing can be carried out stably.

[0150] In some embodiments, the first pressing block 81 can be moved in the opposite direction of the z-direction to compress the SOC against the first placement area 21. The second pressing block 82 can be moved in the opposite direction of the z-direction to compress the memory chip against the second placement area 22.

[0151] Therefore, by applying a force in the opposite direction along the z-direction to the SOC and the memory chip, good contact between the SOC and the memory chip with the adapter board is ensured, thereby guaranteeing the coupling of the SOC's memory module and the memory chip.

[0152] As described above, this embodiment places the first chip and the second chip on the same side of the chip test socket 1 by setting a first placement area 21 and a second placement area 22, both located on the first side 2b. The first chip and the second chip are coupled through an adapter board 3, allowing the second chip to be used to test the first chip. Therefore, this embodiment can more conveniently achieve testing of the first chip adapting to the function of the second chip, and is compatible with non-POP packaged first chips. Furthermore, the coupling of the first chip and the second chip through the adapter board 3 avoids the problem of through-holes on the test load board severely affecting signal integrity, also avoids back-drilling issues, reduces the requirements for the board manufacturer's production process, and lowers the production cost of the test load board.

[0153] Furthermore, in this embodiment, the first chip and the second chip are coupled through the adapter board 3, which brings the first chip and the second chip closer together, thus avoiding the performance of the first chip being affected by the greater distance between the first chip and the second chip.

[0154] Furthermore, this embodiment provides an integrated chip test socket 1 that simultaneously houses the first chip and the second chip. The single chip test socket 1 is smaller in size compared to existing two test sockets, reducing the layout complexity of the test load board.

[0155] Furthermore, by integrating the second chip into the chip test socket 1, this implementation makes it easier to replace the second chip, and the installation / removal of the second chip is simpler and takes less time, which helps to improve the efficiency and capacity of chip mass production testing.

[0156] Furthermore, the first chip may include a storage module and a non-storage module, with their interfaces located on the same side. The second chip may be a storage chip. Therefore, using the solution of this embodiment, a single chip test socket 1 can achieve coupling between the storage module and the storage chip, as well as coupling between the non-storage module and the test load board, greatly improving the convenience of testing the first chip.

[0157] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A chip test socket, characterized by, The chip test socket comprises: a base having opposite first and second faces; a first placement area on the first face for accommodating a first chip; a second placement area on the first face for accommodating a second chip; a conversion board arranged in the base, the first chip and the second chip being coupled through the conversion board; The chip test socket further comprises: a first electrical connector arranged between the first placement area and the conversion board to couple the conversion board and the first chip; a second electrical connector arranged between the second placement area and the conversion board to couple the conversion board and the second chip; a third electrical connector arranged in the first placement area and extending out of the base to couple the first chip and a test load board; wherein, in the plane of the first face, the first electrical connector is closer to the second electrical connector than the third electrical connector.

2. The chip test socket according to claim 1, wherein The first and second placement areas are arranged side by side on the first face.

3. The chip test socket according to claim 1, wherein The first chip comprises a storage module, and the first electrical connector is used to couple the conversion board and the storage module.

4. The chip test socket according to claim 1, wherein The first chip comprises a non-storage module, and the third electrical connector is used to couple the non-storage module and the test load board.

5. The chip test socket according to claim 1, wherein The third electrical connector comprises opposite first and second ends, the first end being located in the first placement area, and the second end extending out of the base from the second face.

6. The chip test socket according to claim 1 or 5, wherein The conversion board is provided with at least one through hole for accommodating the third electrical connector, and the third electrical connector located in the at least one through hole extends out of the conversion board towards the first and second faces.

7. The chip test socket according to claim 1, wherein The first, second and third electrical connectors are selected from conductive rubber and probes.

8. The chip test socket according to claim 1, wherein The chip test socket further comprises: a cover part movable towards or away from the first face to expose or close the first and second placement areas.

9. The chip test socket according to claim 1, wherein The chip test socket further comprises: a holding part for applying a force towards the second face to the first chip located in the first placement area.

10. The chip test socket according to claim 9, wherein The holding part is also used to apply a force towards the second face to the second chip located in the second placement area.

11. The chip test socket according to claim 1, wherein The second chip comprises a storage chip, which is detachably arranged in the second placement area.

12. The chip test socket according to any one of claims 1 to 5 or any one of claims 7 to 11, characterized by, The first chip is also coupled with a test load board through the conversion board to test the first chip in combination with the second chip.

13. A method of testing a chip, characterized by, The chip test socket comprises: providing a test load board and the chip test socket of any one of claims 1-12; placing the first chip in the first placement area; placing the second chip in the second placement area; connecting the chip test socket to the test load board; testing the first chip in combination with the second chip to obtain test results.

14. The method of claim 13, wherein, The chip test socket comprises a cover part movable towards or away from the first face to expose or close the first and second placement areas, and a holding part arranged on the side of the cover part facing the first face, after the second chip is placed in the second placement area, the method further comprises: The cover portion is controlled to move toward the first face until the first chip is held against the first placement area and / or the second chip is held against the second placement area by the holding portion.

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