Detection system and method for a PCIe CEM connection interface in a circuit board

Abstract

The application discloses a detection system and method of a PCIe CEM connection interface in a circuit board. The PCIe CEM connection interface is converted through a test adapter card. The test card generates corresponding differential state information according to the differential signals obtained from the MCIO connection interface of the test card. The test program loaded and executed by the circuit board to be tested or an external test device obtains the differential state information to detect the differential signals of the PCIe CEM connection interface. Thus, the PCIe CEM connection interface differential signal detection can be realized through the test adapter card and the test card.

Description

TECHNICAL FIELD

[0001] The present application relates to a detection system and method thereof, in particular to a detection system and method thereof for detecting PCIe CEM (Card Electromechanical) connection interface in a circuit board through a test adapter card and a test card. BACKGROUND

[0002] The existing test method for PCIe CEM connection interface on a circuit board generally uses different functional test cards to be plugged into the PCIe CEM connection interface to detect the corresponding PCIe CEM connection interface function. Each PCIe CEM connection interface needs to be plugged into a corresponding functional test card. The detection of different functions of the PCIe CEM connection interface requires a large number of functional test cards to complete the detection.

[0003] However, in fact, the PCIe CEM connection interface only needs to detect the electrical characteristics to ensure the quality of the product. The detection of the electrical characteristics of the PCIe CEM connection interface only needs to detect the signal connection and the high-frequency characteristics, and does not need to detect the data transmission. Therefore, the existing detection of the PCIe CEM connection interface should be adjusted with the times, and the detection of the PCIe CEM connection interface by a single test card through a plurality of adapter test cards and a single test card is the desired direction of the present application.

[0004] In summary, it can be seen that the existing detection of the PCIe CEM connection interface in the existing circuit board has been a problem of inconvenient detection caused by complete data transmission detection for a long time. Therefore, it is necessary to propose an improved technical means to solve this problem. SUMMARY

[0005] In view of the problem of inconvenient detection caused by complete data transmission detection of the existing PCIe CEM connection interface in the existing circuit board in the prior art, the present application discloses a detection system and method thereof for PCIe CEM connection interface in a circuit board, wherein:

[0006] The disclosed first embodiment of the PCIe CEM connection interface detection system of the circuit board comprises: a circuit board to be tested, at least one test adapter card, and a test card. The circuit board to be tested further comprises: at least one PCIe CEM insertion slot, a circuit board serial data communication standard interface, a circuit board network connection interface (NET), a storage unit, and a central processing unit. Each test adapter card further comprises: a PCIe CEM insertion interface, a communication unit, and at least one adapter MCIO (MiniCooledge IO) connection interface. The test card further comprises: at least two test card MCIO connection interfaces, a test card serial data communication standard interface, a test card network connection interface, and a Peripheral Component Interconnect Express (PCIe) chip.

[0007] The storage unit stores a test program. The central processing unit is electrically connected to the at least one PCIe CEM insertion slot, the circuit board serial data communication standard interface, the circuit board network connection interface, and the storage unit. The central processing unit loads and executes the test program stored in the storage unit to generate a differential signal. The central processing unit provides the differential signal through one of the at least one PCIe CEM insertion slot. The test program obtains differential state information through the circuit board serial data communication standard interface and / or the circuit board network connection interface to realize the detection of the differential signal corresponding to the at least one PCIe CEM insertion slot.

[0008] The PCIe CEM insertion interface is inserted into one of the at least one PCIe CEM insertion slot to obtain the differential signal from the corresponding at least one PCIe CEM insertion slot. The communication unit is electrically connected to the PCIe CEM insertion interface to provide the differential signal obtained by the PCIe CEM insertion interface. The adapter MCIO connection interface is electrically connected to the communication unit. The adapter MCIO connection interface provides the differential signal obtained by the communication unit through the PCIe CEM insertion interface.

[0009] The at least two test card MCIO connection interfaces determine the electrical connection mode of the test card MCIO connection interfaces and the at least two test card MCIO connection interfaces according to the bandwidth of the corresponding PCIe CEM insertion slot, and the at least two test card MCIO connection interfaces obtain the differential signals from the corresponding test card MCIO connection interfaces; the test card serial data communication standard interface is electrically connected with the circuit board serial data communication standard interface; the test card network connection interface is electrically connected with the circuit board network connection interface; and the PCIe interface chip is electrically connected with the at least two test card MCIO connection interfaces, the test card serial data communication standard interface and the test card network connection interface respectively, the PCIe interface chip generates corresponding differential state information according to the differential signals obtained by the at least two test card MCIO connection interfaces, and provides the differential state information to the test program through the test card serial data communication standard interface or the test card network connection interface.

[0010] The disclosed second embodiment of the circuit board PCIe CEM connection interface detection system comprises: a circuit board to be tested, at least one test adapter card, a test card and an external test device; the circuit board to be tested further comprises: at least one PCIe CEM insertion slot and a central processing unit; each test adapter card further comprises: a PCIe CEM insertion interface, a communication unit and at least one adapter MCIO connection interface; the test card further comprises: at least two test card MCIO connection interfaces, a test card serial data communication standard interface, a test card network connection interface and a PCIe interface chip; and the external test device further comprises: a device serial data communication standard interface, a device network connection interface, a device storage unit and a device central processing unit.

[0011] The central processing unit is electrically connected with the at least one PCIe CEM insertion slot respectively, generates differential signals, and provides the differential signals through one of the at least one PCIe CEM insertion slot.

[0012] The PCIe CEM insertion interface is inserted into one of the at least one PCIe CEM insertion slot, obtains differential signals from the corresponding at least one PCIe CEM insertion slot; the communication unit is electrically connected with the PCIe CEM insertion interface, and provides the differential signals obtained by the PCIe CEM insertion interface; and the adapter MCIO connection interface is electrically connected with the communication unit, and provides the differential signals obtained by the communication unit through the PCIe CEM insertion interface.

[0013] The at least two test card MCIO connection interfaces are connected to the at least two test card MCIO connection interfaces through the MCIO connection lines according to the bandwidth of the corresponding PCIe CEM insertion slot, and the at least two test card MCIO connection interfaces obtain differential signals from the corresponding connection interface; the test card serial data communication standard interface is electrically connected to the circuit board serial data communication standard interface; the test card network connection interface is electrically connected to the circuit board network connection interface; and the PCIe chip is electrically connected to the at least two test card MCIO connection interfaces, the test card serial data communication standard interface and the test card network connection interface, respectively, and generates corresponding differential state information according to the differential signals obtained by the at least two test card MCIO connection interfaces, and provides the differential state information through the test card serial data communication standard interface or the test card network connection interface.

[0014] The device serial data communication standard interface is electrically connected to the test card serial data communication standard interface; the device network connection interface is electrically connected to the test card network connection interface; the device storage unit stores a test program; and the device central processing unit is electrically connected to the device serial data communication standard interface, the device network connection interface and the device storage unit, respectively, and loads and executes the test program stored in the storage unit, and the test program obtains the differential state information from the PCIe chip through the device serial data communication standard interface and / or the device network connection interface to detect the differential signals of the at least one PCIe CEM insertion slot.

[0015] The detection method of the PCIe CEM connection interface of the circuit board of the first embodiment of the present application comprises the following steps:

[0016] First, a circuit board to be tested is provided, which includes at least one PCIe CEM slot, a circuit board serial data communication standard interface, a circuit board network connection interface, a storage unit, and a central processing unit. Next, the central processing unit is electrically connected to the at least one PCIe CEM slot, the circuit board serial data communication standard interface, the circuit board network connection interface, and the storage unit, respectively. Next, at least one test adapter card is provided, each of which includes a PCIe CEM plug-in interface, a communication unit, and at least one adapter MCIO connection interface. Next, the PCIe CEM plug-in interface is plugged into one of the at least one PCIe CEM slot. Next, the communication unit is electrically connected to the PCIe CEM plug-in interface. Next, the adapter MCIO connection interface is electrically connected to the communication unit. Next, a test card is provided, which includes at least two test card MCIO connection interfaces, a PCIe chip, a test card serial data communication standard interface, and a test card network connection interface. Next, the at least two test card MCIO connection interfaces are electrically connected to the adapter MCIO connection interface and the at least two test card MCIO connection interfaces according to the bandwidth of the corresponding plugged-in PCIe CEM slot via MCIO connection lines. Next, the PCIe chip is electrically connected to the at least two test card MCIO connection interfaces, the test card serial data communication standard interface, and the test card network connection interface, respectively. Next, the test card serial data communication standard interface is electrically connected to the circuit board serial data communication standard interface. Next, the test card network connection interface is electrically connected to the circuit board network connection interface. Next, the central processing unit loads and executes a test program stored in the storage unit to generate a differential signal. Next, the central processing unit provides the differential signal to the corresponding plugged-in PCIe CEM plug-in interface via one of the at least one PCIe CEM slot. Next, the communication unit provides the differential signal obtained by the PCIe CEM plug-in interface to the adapter MCIO connection interface. Next, the at least two test card MCIO connection interfaces obtain the differential signal from the corresponding connected adapter MCIO connection interface. Next, the PCIe chip generates corresponding differential state information according to the differential signal obtained by the at least two test card MCIO connection interfaces. Finally, the test program obtains the differential state information via the serial data communication standard interface and / or the network connection interface to achieve the detection of the differential signal of the corresponding at least one PCIe CEM slot.

[0017] The disclosed second embodiment of the circuit board PCIe CEM connection interface detection method includes the following steps:

[0018] First, a circuit board to be tested including at least one PCIe CEM slot and a central processing unit is provided; then, the central processing unit is electrically connected with the at least one PCIe CEM slot; then, at least one test adapter card is provided, each of which further includes a PCIe CEM slot interface, a communication unit and at least one adapter MCIO connection interface; then, the PCIe CEM slot interface is correspondingly plugged into one of the at least one PCIe CEM slot; then, the communication unit is electrically connected with the PCIe CEM slot interface; then, the adapter MCIO connection interface is electrically connected with the communication unit; then, a test card including at least two test card MCIO connection interfaces, a PCI Express interface chip, a test card serial data communication standard interface and a test card network connection interface is provided; then, the at least two test card MCIO connection interfaces are electrically connected with the adapter MCIO connection interface according to the bandwidth of the corresponding plugged-in PCIe CEM slot via MCIO connection lines; then, the PCI Express interface chip is electrically connected with the at least two test card MCIO connection interfaces, the test card serial data communication standard interface and the test card network connection interface, respectively; then, an external testing device having a device serial data communication standard interface, a device network connection interface, a device storage unit and a device central processing unit is provided; then, the device serial data communication standard interface is electrically connected with the test card serial data communication standard interface; then, the device network connection interface is electrically connected with the test card network connection interface; then, the device storage unit stores a test program; then, the device central processing unit is electrically connected with the device serial data communication standard interface, the device network connection interface and the device storage unit, respectively; then, the device central processing unit loads and executes the test program stored in the storage unit; then, the central processing unit generates a differential signal; then, the central processing unit provides the differential signal to the corresponding plugged-in PCIe CEM slot interface via one of the at least one PCIe CEM slot; then, the communication unit provides the differential signal obtained by the PCIe CEM slot interface to the adapter MCIO connection interface; then, the at least two test card MCIO connection interfaces obtain the differential signal from the corresponding connected adapter MCIO connection interface; then, the PCI Express interface chip generates corresponding differential state information according to the differential signal obtained by the at least two test card MCIO connection interfaces; finally, the test program obtains the differential state information from the PCI Express interface chip via the device serial data communication standard interface and / or the device network connection interface to realize the detection of the differential signal of the corresponding at least one PCIe CEM slot.

[0019] The difference between the disclosed system and method and the prior art is that the conversion of the PCIe CEM connection interface is realized by the test adapter card, the corresponding differential state information is generated by the quick peripheral component interconnection interface chip in the test card according to the differential signal obtained from the MCIO connection interface of the test card, and the differential state information is obtained by the test program loaded and executed by the circuit board to be tested or the external test device to realize the detection of the differential signal of the corresponding PCIe CEM plug-in slot.

[0020] Through the above technical means, the technical effect of realizing the differential signal detection of the PCIe CEM connection interface by the test adapter card and the test card can be achieved. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 A block diagram of the test adapter card of the present application is shown.

[0022] Figure 2 A schematic diagram of the electrical connection of the circuit board to be tested, the test adapter card and the test card of the first embodiment of the present application is shown.

[0023] Figure 3 A schematic diagram of the electrical connection of the circuit board to be tested, the test adapter card, the test card and the external test device of the second embodiment of the present application is shown.

[0024] Figures 4A to 4C A flow chart of the method of the first embodiment of the present application is shown.

[0025] Figures 5A to 5C A flow chart of the method of the second embodiment of the present application is shown.

[0026] BRIEF DESCRIPTION OF DRAWINGS

[0027] 10 circuit board to be tested

[0028] 111 first PCIe CEM plug-in slot

[0029] 112 second PCIe CEM plug-in slot

[0030] 113 third PCIe CEM plug-in slot

[0031] 12 circuit board serial data communication standard interface

[0032] 13 circuit board network connection interface

[0033] 14 storage unit

[0034] 15 central processing unit

[0035] 20 test adapter card

[0036] 201 first test adapter card

[0037] 202 second test adapter card

[0038] 203 third test adapter card

[0039] 21 PCIe CEM plug interface

[0040] 22 test logic circuit

[0041] 23 communication unit

[0042] 241 first adapter MCIO connection interface

[0043] 242 second adapter MCIO connection interface

[0044] 30 test card

[0045] 311 first test card MCIO connection interface

[0046] 312 second test card MCIO connection interface

[0047] 313 third test card MCIO connection interface

[0048] 314 fourth test card MCIO connection interface

[0049] 32 test card serial data communication standard interface

[0050] 33 test card network connection interface

[0051] 34 peripheral component interconnect express interface chip

[0052] 40 external test device

[0053] 41 device serial data communication standard interface

[0054] 42 device network connection interface

[0055] 43 device storage unit

[0056] 44 device central processing unit DETAILED DESCRIPTION

[0057] The embodiments of the present application will be described in detail with reference to the drawings and examples, so that the implementation process of how the present application applies technical means to solve technical problems and achieve technical effects can be fully understood and implemented.

[0058] Please refer to Figure 1 shown, Figure 1 shows a block diagram of the test adapter card of the present application.

[0059] The test adapter card 20 comprises a PCIe CEM plug-in interface 21, a test logic circuit 22, a communication unit 23, a first adapter MCIO connection interface 241 and a second adapter MCIO connection interface 242. The PCIe CEM plug-in interface 21 is electrically connected to the test logic circuit 22. The test logic circuit 22 is electrically connected to the communication unit 23. The communication unit 23 is electrically connected to the first adapter MCIO connection interface 241 and the second adapter MCIO connection interface 242. That is, the PCIe CEM plug-in interface 21 is electrically connected to the communication unit 23. PCIe CEM (Card Electromechanical) is an interface specification of the Peripheral Component Interconnect Express (PCIe).

[0060] Please refer to Figure 2 as shown, Figure 2 The first embodiment of the present application is shown in the schematic diagram of the electrical connection between the circuit board to be tested, the test adapter card and the test card.

[0061] The detection system of the PCIe CEM connection interface in the circuit board of the first embodiment of the present application comprises a circuit board to be tested 10, a first test adapter card 201, a second test adapter card 202, a third test adapter card 203 and a test card 30. The circuit board to be tested 10 further comprises a first PCIe CEM plug-in slot 111, a second PCIe CEM plug-in slot 112, a third PCIe CEM plug-in slot 113, a circuit board serial data communication standard interface 12, a circuit board network connection interface (NET) 13, a storage unit 14 and a central processing unit 15. The test card 30 further comprises a first test card MCIO connection interface 311, a second test card MCIO connection interface 312, a third test card MCIO connection interface 313, a fourth test card MCIO connection interface 314, a test card serial data communication standard interface 32, a test card network connection interface 33 and a Peripheral Component Interconnect Express (PCIe) chip 34.

[0062] The bandwidths of the first PCIe CEM slot 111, the second PCIe CEM slot 112 and the third PCIe CEM slot 113 are X8, X8 and X16 respectively, the first test adapter card 201 is plugged into the first PCIe CEM slot 111 to form an electrical connection, the second test adapter card 202 is plugged into the second PCIe CEM slot 112 to form an electrical connection, the third test adapter card 203 is plugged into the third PCIe CEM slot 113 to form an electrical connection, and the first PCIe CEM slot 111, the second PCIe CEM slot 112, the third PCIe CEM slot 113, the circuit board serial data communication standard interface 12, the circuit board network connection interface 13 and the storage unit 14 are electrically connected to the central processing unit 15 respectively.

[0063] The first test card MCIO connection interface 311, the second test card MCIO connection interface 312, the third test card MCIO connection interface 313, the fourth test card MCIO connection interface 314, the test card serial data communication standard interface 32 and the test card network connection interface 33 are electrically connected to the fast peripheral component interconnect interface chip 34 respectively.

[0064] Since the bandwidth of the first PCIe CEM slot 111 plugged into by the first test adapter card 201 is X8, the first adapter MCIO connection interface 241 (or the second adapter MCIO connection interface 242) of the first test adapter card 201 can be used to form an electrical connection with the first test card MCIO connection interface 311 through an MCIO connection line; since the bandwidth of the second PCIe CEM slot 112 plugged into by the second test adapter card 202 is X8, the second adapter MCIO connection interface 242 (or the first adapter MCIO connection interface 241) of the second test adapter card 202 can be used to form an electrical connection with the second test card MCIO connection interface 312 through an MCIO connection line; since the bandwidth of the third PCIe CEM slot 113 plugged into by the third test adapter card 203 is X16, the first adapter MCIO connection interface 241 and the second adapter MCIO connection interface 242 of the third test adapter card 203 are needed to form electrical connections with the third test card MCIO connection interface 313 and the fourth test card MCIO connection interface 314 respectively through MCIO connection lines.

[0065] The circuit board serial data communication standard interface 12 is electrically connected to the test card serial data communication standard interface 32, and the circuit board network connection interface 13 is electrically connected to the test card network connection interface 33.

[0066] The central processing unit 15 loads and executes the test program stored in the storage unit 14 to generate the differential signals, and provides the differential signals to the first test adapter card 201, the second test adapter card 202 or the third test adapter card 203 through the first PCIe CEM plug slot 111, the second PCIe CEM plug slot 112 or the third PCIe CEM plug slot 113.

[0067] The PCIe CEM plug interface 21 of the first test adapter card 201, the second test adapter card 202 or the third test adapter card 203 obtains the differential signals from the corresponding first PCIe CEM plug slot 111, the second PCIe CEM plug slot 112 or the third PCIe CEM plug slot 113, and provides the differential signals to the first adapter MCIO connection interface 241 and / or the second adapter MCIO connection interface 242 through the test logic circuit 22 and the communication unit 23.

[0068] The first test card MCIO connection interface 311, the second test card MCIO connection interface 312, the third test card MCIO connection interface 313 and / or the fourth test card MCIO connection interface 314 can obtain the differential signals from the corresponding first test adapter card 201, the second test adapter card 202 or the third test adapter card 203, and the PCIe chip 34 can generate the corresponding differential state information according to the differential signals, and provide the differential state information generated by the PCIe chip 34 to the board SDCC interface 12 and / or the board network connection interface 13 through the test card SDCC interface 32 and / or the test card network connection interface 33, so that the test program can obtain the differential state information through the board SDCC interface 12 and / or the board network connection interface 13 to detect the differential signals of the corresponding first PCIe CEM plug slot 111, the second PCIe CEM plug slot 112 or the third PCIe CEM plug slot 113.

[0069] Please refer to Figure 3 , Figure 3 The electrical connection diagram of the test circuit board, the test adapter card, the test card and the external test device according to the second embodiment of the present application is shown.

[0070] The detection system of the PCIe CEM connection interface of the circuit board of the second embodiment of the present application comprises: a circuit board to be tested 10, a first test adapter card 201, a second test adapter card 202, a third test adapter card 203, a test card 30, and an external testing device 40. The circuit board to be tested 10 further comprises: a first PCIe CEM insertion slot 111, a second PCIe CEM insertion slot 112, a third PCIe CEM insertion slot 113, and a central processing unit 15. The test card 30 further comprises: a first test card MCIO connection interface 311, a second test card MCIO connection interface 312, a third test card MCIO connection interface 313, a fourth test card MCIO connection interface 314, a test card serial data communication standard interface 32, a test card network connection interface 33, and a peripheral component interconnect express interface chip 34. The external testing device 40 further comprises: a device serial data communication standard interface 41, a device network connection interface 42, a device storage unit 43, and a device central processing unit 44.

[0071] The second embodiment has overlapping with the first embodiment. The overlapping part is described in the first embodiment, which will not be repeated here. The second embodiment only describes the part that is different from the first embodiment. The main difference between the second embodiment and the first embodiment is that the second embodiment has an external testing device 40. The external testing device 40 is, for example, a general computer, a smart device, a server, etc. This is only an example and does not limit the application range of the present application.

[0072] The central processing unit 15 can generate the differential signal from the host or load and execute the test program stored in the device storage unit 43 through the device central processing unit 44, and then provide the instruction to the circuit board to be tested 10 through the test card 30, the first test adapter card 201, the second test adapter card 202, or the third test adapter card 203. The central processing unit 15 generates the differential signal according to the instruction. This is only an example and does not limit the application range of the present application.

[0073] The peripheral component interconnect express interface chip 34 generates the corresponding differential state information according to the differential signal, and then provides the differential state information generated by the peripheral component interconnect express interface chip 34 to the device serial data communication standard interface 41 and / or the device network connection interface 42 through the test card serial data communication standard interface 32 and / or the test card network connection interface 33. The test program obtains the differential state information through the device serial data communication standard interface 41 and / or the device network connection interface 42 to realize the detection of the differential signal of the first PCIe CEM insertion slot 111, the second PCIe CEM insertion slot 112, or the third PCIe CEM insertion slot 113.

[0074] In the first embodiment and the second embodiment, the test program can generate a detection signal, and the test program provides the detection signal to the first test adapter card 201, the second test adapter card 202, or the third test adapter card 203, and the test logic circuit 22 in the first test adapter card 201, the second test adapter card 202, or the third test adapter card 203 can perform the signal connection and the pin state detection of the first PCIe CEM socket 111, the second PCIe CEM socket 112, or the third PCIe CEM socket 113, or the test logic circuit 22 in the first test adapter card 201, the second test adapter card 202, or the third test adapter card 203 can generate a detection result according to the detection signal by reading the state of the first PCIe CEM socket 111, the second PCIe CEM socket 112, or the third PCIe CEM socket 113, measuring the voltage of the power pin, and / or sending the WAKE signal, and the first test adapter card 201, the second test adapter card 202, or the third test adapter card 203 returns the detection result to the test program through the test card serial data communication standard interface 32 and / or the test card network connection interface 33 of the test card 30 to realize the detection of the non-differential signal pin of the first PCIe CEM socket 111, the second PCIe CEM socket 112, and / or the third PCIe CEM socket 113. The detection process of each non-differential signal pin is still described below.

[0075] The first PCIe CEM socket 111, the second PCIe CEM socket 112, or the third PCIe CEM socket 113 is presented as a PCIe interface in the test program, and each downstream port of the PCIe interface is electrically connected with a temporary register to store the characteristics and states of the corresponding first PCIe CEM socket 111, the second PCIe CEM socket 112, or the third PCIe CEM socket 113. The test program reads the state of the corresponding temporary register of the first PCIe CEM socket 111, the second PCIe CEM socket 112, or the third PCIe CEM socket 113 to perform the signal connection and the pin state detection, which includes the detection of the PCIe Link Speed, the Link Width, and the Link Speed Change.

[0076] The test logic circuit 22 in the first test adapter card 201, the second test adapter card 202 or the third test adapter card 203 measures the voltage of the power supply pin of the corresponding first PCIe CEM insertion slot 111, the second PCIe CEM insertion slot 112 or the third PCIe CEM insertion slot 113, and then transmits the voltage measurement result of the power supply pin of the first test adapter card 201, the second test adapter card 202 or the third test adapter card 203 back to the test program through the test card serial data communication standard interface 32 and / or the test card network connection interface 33 of the test card 30 to detect the state of the power supply pin of the corresponding first PCIe CEM insertion slot 111, the second PCIe CEM insertion slot 112 or the third PCIe CEM insertion slot 113.

[0077] The test logic circuit 22 in the first test adapter card 201, the second test adapter card 202 or the third test adapter card 203 also includes an electrically-erasable programmable read-only memory (EEPROM), and the test program reads the electrically-erasable programmable read-only memory of the first test adapter card 201, the second test adapter card 202 or the third test adapter card 203 through a system management bus (SMBus) to detect the signal connection.

[0078] The first test adapter card 201, the second test adapter card 202 or the third test adapter card 203 sends a wake-up (WAKE) signal according to the detection signal, and the wake-up signal is read by a board management controller (BMC) or an I / O controller hub (ICH) of the to-be-tested motherboard 30 to detect the signal connection of the corresponding first test adapter card 201, the second test adapter card 202 or the third test adapter card 203.

[0079] The first test adapter card 201, the second test adapter card 202 or the third test adapter card 203 further includes pull-up resistors and pull-down resistors between the first test adapter card 201, the second test adapter card 202 or the third test adapter card 203 and the corresponding first PCIe CEM socket 111, the second PCIe CEM socket 112 and the third PCIe CEM socket 113. The first test adapter card 201, the second test adapter card 202 or the third test adapter card 203 reads the signal state of the input / output pins (e.g. TMS, TDI, TDO, TCK, PWRBRK and CLKREQ, etc.) in the first PCIe CEM socket 111, the second PCIe CEM socket 112 and the third PCIe CEM socket 113 by controlling the pull-up state, the pull-down state and the no pull-up or pull-down state of the pull-up resistors and the pull-down resistors, so as to detect the high potential, the low potential or the NC potential state of the input / output pins.

[0080] Next, please refer to Figures 4A to 4C together, Figures 4A to 4C a flow chart of the method of the first embodiment of the present application is shown.

[0081] The detection method of the PCIe CEM connection interface of the circuit board of the first embodiment of the present application includes the following steps:

[0082] Firstly, a circuit board to be tested including at least one PCIe CEM slot, a circuit board serial data communication standard interface, a circuit board network connection interface, a storage unit and a central processing unit is provided (step 501); then, the central processing unit is electrically connected with the at least one PCIe CEM slot, the circuit board serial data communication standard interface, the circuit board network connection interface and the storage unit respectively (step 502); then, at least one test adapter card is provided, each of the test adapter cards further including a PCIe CEM plug-in interface, a communication unit and an adapter MCIO connection interface (step 503); then, the PCIe CEM plug-in interface is plugged into one of the at least one PCIe CEM slot (step 504); then, the communication unit is electrically connected with the PCIe CEM plug-in interface (step 505); then, the adapter MCIO connection interface is electrically connected with the communication unit (step 506); then, a test card including at least two test card MCIO connection interfaces, a PCI Express interface chip, a test card serial data communication standard interface and a test card network connection interface is provided (step 507); then, the at least two test card MCIO connection interfaces are electrically connected with the adapter MCIO connection interface and the at least two test card MCIO connection interfaces through MCIO connection lines according to the bandwidth of the corresponding plugged PCIe CEM slot (step 508); then, the PCI Express interface chip is electrically connected with the at least two test card MCIO connection interfaces, the test card serial data communication standard interface and the test card network connection interface respectively (step 509); then, the test card serial data communication standard interface is electrically connected with the circuit board serial data communication standard interface (step 510); then, the test card network connection interface is electrically connected with the circuit board network connection interface (step 511); then, the central processing unit loads and executes a test program stored in the storage unit to generate a differential signal (step 512); then, the central processing unit provides the differential signal to the corresponding plugged PCIe CEM plug-in interface through one of the at least one PCIe CEM slot (step 513); then, the communication unit provides the differential signal obtained by the PCIe CEM plug-in interface to the adapter MCIO connection interface (step 514); then, the at least two test card MCIO connection interfaces obtain the differential signal from the corresponding connected adapter MCIO connection interface (step 515); then, the PCI Express interface chip generates corresponding differential state information according to the differential signal obtained by the at least two test card MCIO connection interfaces (step 516); finally, the test program obtains the differential state information through the serial data communication standard interface and / or the network connection interface to realize the detection of the differential signal of the corresponding at least one PCIe CEM slot (step 517).

[0083] Then, please refer toFigures 5A to 5C shown, Figures 5A to 5C A method flow chart illustrating a second embodiment of the method for detecting a PCIe CEM connection interface in a circuit board of the present application.

[0084] The method for detecting a PCIe CEM connection interface in a circuit board of the second embodiment of the present application comprises the following steps:

[0085] First, a circuit board to be tested including at least one PCIe CEM slot and a central processing unit is provided (step 601); then, the central processing unit is electrically connected with the at least one PCIe CEM slot (step 602); then, at least one test adapter card is provided, each of which further includes a PCIe CEM plug-in interface, a communication unit and an adapter MCIO connection interface (step 603); then, the PCIe CEM plug-in interface is plugged into one of the at least one PCIe CEM slot (step 604); then, the communication unit is electrically connected with the PCIe CEM plug-in interface (step 605); then, the adapter MCIO connection interface is electrically connected with the communication unit (step 606); then, a test card including at least two test card MCIO connection interfaces, a peripheral component interconnect express (PCIe) chip, a test card serial data communication standard interface and a test card network connection interface is provided (step 607); then, the at least two test card MCIO connection interfaces are electrically connected with the adapter MCIO connection interface and the at least two test card MCIO connection interfaces through MCIO connection lines according to the bandwidth of the corresponding plugged-in PCIe CEM slot (step 608); then, the PCIe chip is electrically connected with the at least two test card MCIO connection interfaces, the test card serial data communication standard interface and the test card network connection interface, respectively (step 609); then, an external testing device having a device serial data communication standard interface, a device network connection interface, a device storage unit and a device central processing unit is provided (step 610); then, the device serial data communication standard interface is electrically connected with the test card serial data communication standard interface (step 611); then, the device network connection interface is electrically connected with the test card network connection interface (step 612); then, the device storage unit stores a test program (step 613); then, the device central processing unit is electrically connected with the device serial data communication standard interface, the device network connection interface and the device storage unit, respectively (step 614); then, the device central processing unit loads and executes the test program stored in the storage unit (step 615); then, the central processing unit generates a differential signal (step 616); then, the central processing unit provides the differential signal through one of the at least one PCIe CEM slot to the corresponding plugged-in PCIe CEM plug-in interface (step 617); then, the communication unit provides the differential signal obtained by the PCIe CEM plug-in interface to the adapter MCIO connection interface (step 618); then, the at least two test card MCIO connection interfaces obtain the differential signal from the corresponding connected adapter MCIO connection interface (step 619); then, the PCIe chip generates corresponding differential state information according to the differential signal obtained by the at least two test card MCIO connection interfaces (step 620);Finally, the test program obtains the differential state information of the differential signals corresponding to the at least one PCIe CEM socket from the fast peripheral component interconnect interface chip through the device serial data communication standard interface and / or the device network connection interface (step 621).

[0086] In summary, the difference between the present application and the prior art is that the connection interface conversion is realized by the test adapter card, the differential state information corresponding to the differential signals is generated by the fast peripheral component interconnect interface chip in the test card according to the differential signals obtained from the MCIO connection interface of the test card, and the test program loaded and executed by the circuit board to be tested or the external test device obtains the differential state information to realize the detection of the differential signals of the PCIe CEM socket.

[0087] By means of the technical means, the problem that the detection of the PCIe CEM connection interface in the existing circuit board is inconvenient due to complete data transmission detection in the prior art can be solved, and the technical effect that the differential signal detection of the PCIe CEM connection interface is realized by the test adapter card and the test card is achieved.

[0088] Although the embodiments disclosed in the present application are as above, the content described is not used to directly limit the patent protection scope of the present application. Any person skilled in the art can make some changes in the implementation form and details without departing from the spirit and scope of the present application. The patent protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A detection system for PCIe CEM connection interfaces in a circuit board, characterized in that, A circuit board under test, the circuit board under test further comprising: at least one PCIe CEM socket; a circuit board serial data communication standard interface; a circuit board network connection interface (NET); a storage unit storing a test program; and a central processing unit electrically connected to the at least one PCIe CEM socket, the circuit board serial data communication standard interface, the circuit board network connection interface, and the storage unit, respectively, the central processing unit loading and executing the test program stored in the storage unit to generate a differential signal, the central processing unit providing the differential signal through one of the at least one PCIe CEM socket, the test program obtaining differential state information through the circuit board serial data communication standard interface and / or the circuit board network connection interface to achieve detection of the differential signal corresponding to the at least one PCIe CEM socket; at least one test adapter card, each test adapter card further comprising: a PCIe CEM socket interface corresponding to one of the at least one PCIe CEM socket to obtain the differential signal from the corresponding at least one PCIe CEM socket; a communication unit electrically connected to the PCIe CEM socket interface to provide the differential signal obtained by the PCIe CEM socket interface; and at least one adapter MCIO connection interface electrically connected to the communication unit, the adapter MCIO connection interface providing the differential signal obtained by the communication unit through the PCIe CEM socket interface; and a test card, the test card further comprising: at least two test card MCIO connection interfaces, the electrical connection between the adapter MCIO connection interface and the at least two test card MCIO connection interfaces being determined by the bandwidth of the corresponding PCIe CEM socket through MCIO connection lines, the at least two test card MCIO connection interfaces obtaining the differential signal from the corresponding adapter MCIO connection interface; a test card serial data communication standard interface electrically connected to the circuit board serial data communication standard interface; a test card network connection interface electrically connected to the circuit board network connection interface; and a PCIe interface chip electrically connected to the at least two test card MCIO connection interfaces, the test card serial data communication standard interface, and the test card network connection interface, respectively, the PCIe interface chip generating corresponding differential state information from the differential signal obtained by the at least two test card MCIO connection interfaces and providing the differential state information to the test program through the test card serial data communication standard interface or the test card network connection interface. ​ 2. The system for detecting PCIe CEM connection interface in a circuit board according to claim 1, wherein, Each test adapter further comprises a test logic circuit electrically connected with the communication unit, and the test program further comprises generating a detection signal, the test program provides the detection signal to the at least one test adapter through the PCIe CEM socket, the test logic circuit generates a detection result according to the detection signal, or the test logic circuit generates the detection result according to the detection signal by reading the slot state, measuring the power pin voltage and / or sending the wake-up signal of the corresponding PCIe CEM socket through the PCIe CEM interface, and the test adapter provides the detection result to the test program through the test card.

3. A detection system for a PCIe CEM connection interface in a circuit board, the detection system comprising: a PCIe CEM connection interface; a PCIe CEM connection interface detection circuit; and a PCIe CEM connection interface detection circuit detection circuit. Comprise: A circuit board to be tested, further comprising: At least one PCIe CEM socket; and A central processing unit electrically connected with the at least one PCIe CEM socket respectively, the central processing unit generates a differential signal, and the central processing unit provides the differential signal through one of the at least one PCIe CEM socket; At least one test adapter, each test adapter further comprising: A PCIe CEM interface corresponding to one of the at least one PCIe CEM socket, obtaining the differential signal from the corresponding at least one PCIe CEM socket; A communication unit electrically connected with the PCIe CEM interface, for providing the differential signal obtained by the PCIe CEM interface; and At least one adapter MCIO connection interface electrically connected with the communication unit, the adapter MCIO connection interface provides the differential signal obtained by the communication unit through the PCIe CEM interface; A test card, further comprising: At least two test card MCIO connection interfaces, the electrical connection mode between the adapter MCIO connection interface and the at least two test card MCIO connection interfaces is determined by the bandwidth of the corresponding PCIe CEM socket through the MCIO connection line, and the at least two test card MCIO connection interfaces obtain the differential signal from the corresponding connection adapter MCIO connection interface; A test card serial data communication standard interface electrically connected with a circuit board serial data communication standard interface; A test card network connection interface electrically connected with a circuit board network connection interface; and A PCIe interface chip electrically connected with the at least two test card MCIO connection interfaces, the test card serial data communication standard interface and the test card network connection interface respectively, the PCIe interface chip generates corresponding differential state information according to the differential signal obtained by the at least two test card MCIO connection interfaces, and provides the differential state information through the test card serial data communication standard interface or the test card network connection interface; An external test device, further comprising: ​ a device serial data communication standard interface, which is electrically connected with the test card serial data communication standard interface; a device network connection interface, which is electrically connected with the test card network connection interface; a device storage unit, which stores a test program; a device central processing unit, which is electrically connected with the device serial data communication standard interface, the device network connection interface and the device storage unit respectively, and loads and executes the test program stored in the storage unit, so as to obtain the differential state information from the PCIe CEM plug-in slot through the device serial data communication standard interface and / or the device network connection interface. The test adapter further comprises a test logic circuit, which is electrically connected with the communication unit. The test program further comprises a detection signal. The test program provides the detection signal to the test logic circuit of the test adapter through the test card. The test logic circuit generates a detection result according to the detection signal, or the test logic circuit generates the detection result by reading the slot state, measuring the power pin voltage and / or sending and detecting the wake-up signal of the corresponding PCIe CEM plug-in slot through the PCIe CEM plug-in interface according to the detection signal. The test adapter provides the detection result to the test program through the test card.

4. The system for detecting a PCIe CEM connection interface in a circuit board according to claim 3, wherein, The method comprises the following steps:

5. A method for detecting a PCIe CEM connection interface in a circuit board, characterized in that, providing a circuit board to be tested, which comprises at least one PCIe CEM plug-in slot, a circuit board serial data communication standard interface, a circuit board network connection interface, a storage unit and a central processing unit; the central processing unit is electrically connected with the at least one PCIe CEM plug-in slot, the circuit board serial data communication standard interface, the circuit board network connection interface and the storage unit respectively; providing at least one test adapter, each of which further comprises a PCIe CEM plug-in interface, a communication unit and at least one adapter MCIO connection interface; the PCIe CEM plug-in interface is plugged into one of the at least one PCIe CEM plug-in slot; the communication unit is electrically connected with the PCIe CEM plug-in interface; the adapter MCIO connection interface is electrically connected with the communication unit; providing a test card, which comprises at least two test card MCIO connection interfaces, a PCIe chip, a test card serial data communication standard interface and a test card network connection interface; the at least two test card MCIO connection interfaces are electrically connected with the adapter MCIO connection interface according to the bandwidth of the corresponding PCIe CEM plug-in slot through the MCIO connection line; ​ The fast peripheral component interconnect interface chip is electrically connected with the at least two test card MCIO connection interfaces, the test card serial data communication standard interface and the test card network connection interface respectively; The test card serial data communication standard interface is electrically connected with the circuit board serial data communication standard interface; The test card network connection interface is electrically connected with the circuit board network connection interface; The central processing unit loads and executes a test program stored in the storage unit to generate a differential signal; The central processing unit provides the differential signal to the corresponding PCIe CEM plug-in interface through one of the at least one PCIe CEM plug-in slot; The communication unit provides the differential signal obtained by the PCIe CEM plug-in interface to the switching MCIO connection interface; The at least two test card MCIO connection interfaces obtain the differential signal from the corresponding switching MCIO connection interface; The fast peripheral component interconnect interface chip generates corresponding differential state information according to the differential signal obtained by the at least two test card MCIO connection interfaces; and The test program obtains the differential state information through the serial data communication standard interface and / or the network connection interface to realize detection of the differential signal of the at least one PCIe CEM plug-in slot.

6. The method of detecting a PCIe CEM connection interface in a circuit board according to claim 5, wherein, The detection method of the PCIe CEM connection interface in the circuit board further comprises the following steps: Each test adapter card further comprises a test logic circuit, and the test logic circuit is electrically connected with the communication unit; The test program further comprises generating a detection signal, and the test program provides the detection signal to the at least one test adapter card through the PCIe CEM plug-in slot; The test logic circuit generates a detection result according to the detection signal, or the test logic circuit generates the detection result according to the detection signal by reading the slot state of the corresponding PCIe CEM plug-in slot through the PCIe CEM plug-in interface, measuring the voltage of the power pin and / or sending and detecting the wake-up signal; and The test adapter card provides the detection result to the test program through the test card.

7. A method for detecting a PCIe CEM connection interface in a circuit board, characterized in that, The following steps are included: A circuit board to be tested comprising at least one PCIe CEM plug-in slot and a central processing unit is provided; The central processing unit is electrically connected with the at least one PCIe CEM plug-in slot; At least one test adapter card is provided, and each test adapter card further comprises a PCIe CEM plug-in interface, a communication unit and at least one switching MCIO connection interface; The PCIe CEM plug-in interface is plugged into one of the at least one PCIe CEM plug-in slot; The communication unit is electrically connected with the PCIe CEM plug-in interface; The switching MCIO connection interface is electrically connected with the communication unit; The test card comprises at least two test card MCIO connection interfaces, a PCIe CEM connection interface chip, a test card serial data communication standard interface, and a test card network connection interface. The at least two test card MCIO connection interfaces are connected to the switching MCIO connection interface through MCIO connection lines according to the bandwidth of the corresponding PCIe CEM connection interface. The PCIe CEM connection interface chip is electrically connected to the at least two test card MCIO connection interfaces, the test card serial data communication standard interface, and the test card network connection interface. The external test device comprises a device serial data communication standard interface, a device network connection interface, a device storage unit, and a device central processing unit. The device serial data communication standard interface is electrically connected to the test card serial data communication standard interface. The device network connection interface is electrically connected to the test card network connection interface. The device storage unit stores a test program. The device central processing unit is electrically connected to the device serial data communication standard interface, the device network connection interface, and the device storage unit. The device central processing unit loads and executes the test program stored in the storage unit. The central processing unit generates a differential signal. The central processing unit provides the differential signal to the corresponding PCIe CEM connection interface through one of the at least one PCIe CEM connection slot. The communication unit provides the differential signal obtained by the PCIe CEM connection interface to the switching MCIO connection interface. The at least two test card MCIO connection interfaces obtain the differential signal from the corresponding switching MCIO connection interface. The PCIe CEM connection interface chip generates corresponding differential state information according to the differential signal obtained by the at least two test card MCIO connection interfaces. The test program obtains the differential state information from the PCIe CEM connection interface chip through the device serial data communication standard interface and / or the device network connection interface to detect the differential signal of the at least one PCIe CEM connection slot.

8. The method of detecting a PCIe CEM connection interface in a circuit board according to claim 7, wherein, The detection method of the PCIe CEM connection interface in the circuit board further comprises the following steps: Each test adapter card further comprises a test logic circuit, which is electrically connected to the communication unit. The test program further comprises generating a detection signal, and the test program provides the detection signal to the test logic circuit of the test adapter card through the test card. The test logic circuit generates a detection result according to the detection signal, or the test logic circuit generates the detection result by reading the slot state, measuring the power pin voltage, and / or sending and detecting the wake-up signal of the corresponding PCIe CEM connection slot through the PCIe CEM connection interface according to the detection signal; and The test adapter card provides the test results to the test program through the test card. The test adapter card provides the test results to the test program through the test card.

Images