A method and apparatus for screening chips for potential defects
By performing breakdown voltage and leakage current tests on SiC power semiconductor devices, chips with potential defects can be screened out, solving the problem of unstable device withstand voltage, improving device yield and lifespan, and supporting its commercial application.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHUZHOU CRRC TIMES SEMICON CO LTD
- Filing Date
- 2023-02-10
- Publication Date
- 2026-06-02
AI Technical Summary
Existing technologies cannot effectively identify and screen potential defects in silicon carbide power semiconductor devices, leading to unstable device withstand voltage and affecting the commercialization process.
By performing breakdown voltage and leakage current tests on SiC power semiconductor devices, the reliability of the chips is characterized using static parameters, and chips with potential defects are screened out. This includes multiple leakage current tests and consistency monitoring of the judgment criteria to ensure the accuracy and reliability of the screening process.
It improves the breakdown voltage yield and lifespan of SiC power semiconductor devices, reduces early failure rates at the packaging and application ends, ensures device reliability and stability, and supports the commercialization process of the devices.
Smart Images
Figure CN116148633B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method and apparatus for screening potentially defective chips for SiC power semiconductor devices. Background Technology
[0002] Silicon carbide (SiC) power semiconductor devices possess superior switching characteristics, operating at higher junction temperatures and faster frequencies compared to silicon-based power devices, and are considered third-generation semiconductors. In particular, with the gradual maturation of silicon carbide substrates and epitaxial growth technologies, commercial silicon carbide wafers have transitioned from 4-inch to 6-inch wafers, and are expected to reach 8-inch wafers in two to three years. This will significantly reduce the cost of silicon carbide power devices, leading to explosive growth in the electric vehicle, photovoltaic power generation, and wind power markets.
[0003] Currently, the silicon carbide power semiconductor devices that have been commercialized in the new energy market are mainly SiC SBD (Schottky barrier diode) and SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), with voltage levels mainly at 1200V and single-tube current levels ranging from 10 to 100A.
[0004] However, due to limitations in current materials and process technologies, the defect density of silicon carbide materials is still 1 to 2 orders of magnitude higher than that of silicon materials. Among these defects, silicon carbide substrates contain dislocations, stacking faults, and screw dislocations, while 4H-SiC epitaxial layers contain defects such as triangles, comets, and epitaxial protrusions. These defects make the device's withstand voltage unstable and gradually weaken during application; moreover, they cannot be identified and screened through conventional testing methods, which will affect the commercialization process of silicon carbide power devices. Summary of the Invention
[0005] The present invention aims to identify potential defects in SiC power semiconductor devices, screen out SiC power semiconductor devices with potential defects, reduce the failure rate of SiC power semiconductor devices at the packaging end and the customer end, and improve the yield and lifespan of SiC power semiconductor devices in terms of voltage withstand capability.
[0006] The above-mentioned objectives are mainly achieved through the following technical solutions:
[0007] Firstly, a method for screening chips with potential defects is provided, applicable to SiC power semiconductor devices, including diodes, MOSFETs, IGBTs (Insulated Gate Bipolar Transistors), and SiC SBDs, applicable to chip, discrete device, and module applications, and the method includes the following steps:
[0008] The chip under test is subjected to a breakdown voltage V based on a preset leakage current condition. (BR)DSS Test; Complete V (BR)DSS After the initial test, the chip performs a leakage current test based on a first voltage to obtain a first leakage current test value. After completing the leakage current test at the first voltage, the chip performs a leakage current test based on a second voltage to obtain a second leakage current test value. The first voltage is less than the second voltage, and the second voltage is less than the breakdown voltage V. (BR)DSS Finally, based on the first leakage current test value and the second leakage current test value, the qualified chip (i.e., the chip without potential defects) is determined, and it is determined whether the chip has potential defects.
[0009] Compared to existing technologies, the advantages include: establishing a method for characterizing chip reliability using static parameters, by setting V... (BR)DSS The leakage current static test monitors the change in leakage current of the chip after it is subjected to large electrical stress. It can screen out silicon carbide power semiconductor devices with a high probability of subsequent breakdown voltage failure and high risk, as well as SiC power semiconductor devices with potential defects and soft leakage current curves that cannot be screened by ordinary static tests. This reduces the early failure rate of SiC power semiconductor devices at the application and packaging ends, and improves the yield and lifespan of SiC power semiconductor devices in terms of breakdown voltage. In addition, the method described in this invention can be integrated into wafer-level factory testing to efficiently screen out chips with material or process defects and unstable breakdown voltage capabilities.
[0010] A preferred technical solution, based on the first leakage current test value and the second leakage current test value, determines whether the chip has a potential defect, including: if the first leakage current test value reaches the maximum leakage current of the chip, then the chip is determined to have a potential defect and the chip is marked as failed; otherwise, it is determined whether the second leakage current test value reaches twice the first leakage current test value. If so, the chip is determined to have a potential defect and the chip is marked as failed; otherwise, the chip is determined not to have a potential defect and the chip is marked as qualified.
[0011] Advantages compared with the prior art: When the first leakage current test is qualified, it is still necessary to continue to determine whether the leakage current change rate reaches 100% (i.e., the growth rate is 100%). If it reaches, the chip is still determined to be defective, avoiding misjudgment, and further screening out SiC power semiconductor devices with potential defects and soft leakage current curves that cannot be screened by ordinary static tests, reducing the early failure rate of SiC power semiconductor devices at the application end and the packaging end, and improving the yield and lifespan of SiC power semiconductor devices in terms of voltage withstand.
[0012] Preferred technical solution: When it is determined based on the first leakage current test value and the second leakage current test value that the chip does not have potential defects, it further includes: the chip performs a breakdown voltage test based on a preset leakage current condition; the chip performs a leakage current test based on a first voltage to obtain a third leakage current test value; the chip performs a leakage current test based on a second voltage to obtain a fourth leakage current test value; and it is determined whether the chip has potential defects based on the third leakage current test value and the fourth leakage current test value.
[0013] Advantages compared with the prior art: That is, when it is determined that the chip does not have potential defects, the above test steps are repeatedly executed, and the failure chip determination standard remains consistent. Finally, if the leakage current change of the chip after withstanding a large electrical stress is monitored again, after two leakage current tests, if it is still determined to be a qualified chip, the chip is determined to be a qualified chip. Based on the above technical solution, it is easier to screen out SiC power semiconductor devices with a high probability of subsequent voltage withstand failure and high risk, as well as SiC power semiconductor devices with potential defects and soft leakage current curves that cannot be screened by ordinary static tests, further reducing the early failure rate of SiC power semiconductor devices at the application end and the packaging end, and further improving the yield and lifespan of SiC power semiconductor devices in terms of voltage withstand.
[0014] Preferred technical solution: Determining whether the chip has potential defects based on the third leakage current test value and the fourth leakage current test value includes: if the third leakage current test value reaches the maximum leakage current of the chip, it is determined that the chip has potential defects, and the chip is marked as defective; otherwise, it is judged whether the fourth leakage current test value reaches twice the third leakage current test value. If so, it is determined that the chip has potential defects, and the chip is marked as defective; otherwise, it is determined that the chip does not have potential defects, and the chip is marked as qualified.
[0015] Compared to existing technologies, the advantages are: maintaining the same criteria for judging failed chips, avoiding discrepancies in judgment due to inconsistencies between the criteria in two testing processes, preventing qualified chips from being judged as failed chips, causing unnecessary cost waste, or judging unqualified chips with potential defects as qualified chips, leading to a high risk of voltage withstand failure later, thus affecting the commercialization process of silicon carbide power devices (increasing the early failure rate of SiC power semiconductor devices at the application and packaging ends, and reducing the yield and lifespan of SiC power semiconductor devices in terms of voltage withstand).
[0016] In a preferred embodiment, the first voltage is the rated voltage of the chip, and the second voltage is 120% * rated voltage.
[0017] Compared to existing technologies, the advantages are: by setting leakage current tests at rated voltage and 120% of rated voltage respectively, the leakage current change of the chip after being subjected to greater electrical stress can be monitored, and chips that meet the withstand voltage requirements but have V (BR)DSS The test curves of SiC power semiconductor devices are relatively soft, and the leakage current turn-on point is low. This further reduces the early failure rate of SiC power semiconductor devices at the application and packaging levels, and improves the yield and lifespan of SiC power semiconductor devices in terms of voltage withstand capability.
[0018] A preferred technical solution further includes: determining the preset leakage current conditions.
[0019] The preferred technical solution includes the following specific steps for determining the preset leakage current condition:
[0020] Step 1: Select M target chips. These target chips are those that have passed a leakage current test based on their rated voltage. The leakage current test on each target chip yields a fifth leakage current test value based on its rated voltage. M is a positive integer. The leakage current test pass / fail determination can be: determine if the fifth leakage current test value is less than the chip's maximum leakage current. If it is less, the chip is considered pass and selected as a target chip. Alternatively: select a chip, first perform a leakage current test based on its rated voltage to obtain a leakage current test value I1, then perform a leakage current test based on 120% * rated voltage to obtain a leakage current test value I2. If I1 is less than the chip's maximum leakage current, and If the chip is determined to have no potential defects, it is considered a qualified chip and will be used as the target chip. Specific testing methods are not limited here; any chip that can be deemed qualified based on leakage current testing at rated voltage is considered a target chip and falls within the protection scope of this invention.
[0021] Step 2, the target chip undergoes at least one breakdown voltage V at room temperature based on a first initial leakage current condition. (BR)DSS test;
[0022] Step 3, complete V (BR)DSS After the test, the leakage current of the target chip under rated voltage was tested again and recorded as the sixth leakage current test value.
[0023] Step 4, compare V (BR)DSS The leakage current test results before and after the test are compared to determine whether the target chip is qualified. Specifically, the fifth and sixth leakage current test values are used to determine if the target chip has potential defects. If the target chip is determined not to have potential defects, the process returns to step 2, iterates to the next target chip, and performs V... (BR)DSS Testing; if the target chip is determined to have a potential defect, the target chip is marked as failed. Calculate N = N + 1, where N is a positive integer and represents the number of target chips marked as failed. This is done by accumulating and counting the number of failed chips until... If the preset value is met, the first initial leakage current condition is determined as the preset leakage current condition.
[0024] A preferred technical solution, based on the fifth leakage current test value and the sixth leakage current test value, determines whether the target chip has potential defects, including:
[0025] Determine whether the sixth leakage current test value is twice the fifth leakage current test value, i.e., V. (BR)DSS If the leakage current increases by more than 100% under the rated voltage after testing, the target chip is determined to have a potential defect; otherwise, the target chip is determined not to have a potential defect.
[0026] or,
[0027] Determine whether the difference between the sixth leakage current test value and the fifth leakage current test value reaches a preset difference, i.e., V. (BR)DSS After testing, the leakage current at rated voltage is lower than V. (BR)DSS If the growth rate before testing meets a preset value, then the target chip is determined to have a potential defect; otherwise, the target chip is determined not to have a potential defect.
[0028] The preferred technical solution also includes:
[0029] Step 5, if after traversing M target chips, If the preset value is not met, then re-examine the above M target chips and repeat steps 2 to 4 until... The preset value is met, and the first initial leakage current condition is adjusted to the second initial leakage current condition. That is, the initial leakage current in the test is increased every time it is re-traversed. For example, if the target chip is a diode, the second initial leakage current is doubled compared to the first initial leakage current each time; otherwise, if it is a MOSFET, IGBT or SiC SBD, the second initial leakage current is increased by 10μA compared to the first initial leakage current each time.
[0030] Step 6, until If the preset value is met, the second initial leakage current condition is determined as the preset leakage current condition.
[0031] Compared to existing technologies, the advantages are as follows: by determining the preset leakage current conditions, it can be ensured that SiC power semiconductor devices are subjected to appropriate electrical stress during the screening process. In this way, while identifying potential defects in chips, other qualified chips will not be excessively damaged, and the high-temperature reverse bias life of qualified chips will not be affected. This helps to reduce chip damage caused during the screening process and lower costs.
[0032] Secondly, an apparatus for screening chips with potential defects includes:
[0033] The breakdown voltage test module is used to perform breakdown voltage tests on the chip under test based on preset leakage current conditions.
[0034] The first leakage current test module is used to perform a leakage current test on the chip based on a first voltage to obtain a first leakage current test value.
[0035] The second leakage current test module is used to perform a leakage current test on the chip based on a second voltage to obtain a second leakage current test value, wherein the first voltage is less than the second voltage and the second voltage is less than the breakdown voltage.
[0036] The first judgment module determines whether the chip has potential defects based on the first leakage current test value and the second leakage current test value.
[0037] Thirdly, an electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the steps of a method for screening chips with potential defects as described in the first aspect.
[0038] Fourthly, a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of a method for screening chips with potential defects as described in the first aspect.
[0039] Fifthly, a computer program product includes a computer program that, when executed by a processor, implements the steps of a method for screening chips with potential defects as described in the first aspect. Attached Figure Description
[0040] Figure 1 A flowchart illustrating a method for screening chips with potential defects according to the present invention is shown.
[0041] Figure 2 A flowchart illustrating the process of determining the preset leakage current conditions in this invention is shown.
[0042] Figure 3 V in this invention is shown (BR)DSS Test waveform diagram;
[0043] Figure 4 A schematic diagram of a device for screening chips with potential defects according to the present invention is shown.
[0044] Figure 5 A schematic diagram of the structure of an electronic device according to the present invention is shown. Detailed Implementation
[0045] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0046] Example 1
[0047] This invention provides a method for screening chips with potential defects, such as... Figure 1 As shown, it includes the following steps:
[0048] S1, the chip under test is subjected to a breakdown voltage V at room temperature based on a preset leakage current condition. (BR)DSS test.
[0049] S2, complete V (BR)DSS After the test, the chip is subjected to a leakage current test based on the chip's rated voltage to obtain the first leakage current test value.
[0050] S3. After completing the leakage current test under the rated voltage, the chip performs a leakage current test based on 120%*rated voltage to obtain the second leakage current test value.
[0051] S4. The chip is qualified based on the first leakage current test value and the second leakage current test value.
[0052] The specific determination method can be as follows: if the first leakage current test value reaches the maximum leakage current of the chip, the chip is determined to have a potential defect and is marked as failed; otherwise, it is determined whether the second leakage current test value reaches twice the first leakage current test value. If so, the chip is determined to have a potential defect and is marked as failed; otherwise, the chip is determined not to have a potential defect and is marked as qualified.
[0053] This invention establishes a method for characterizing chip reliability using static parameters, by setting V (BR)DSS The leakage current static test monitors the change in leakage current of the chip after it is subjected to large electrical stress. It can screen out silicon carbide power semiconductor devices with a high probability of subsequent breakdown voltage failure and high risk, as well as SiC power semiconductor devices with potential defects and soft leakage current curves that cannot be screened by ordinary static tests. This reduces the early failure rate of SiC power semiconductor devices at the application and packaging ends, and improves the yield and lifespan of SiC power semiconductor devices in terms of breakdown voltage. In addition, the method described in this invention can be integrated into wafer-level factory testing to efficiently screen out chips with material or process defects and unstable breakdown voltage capabilities.
[0054] By setting leakage current tests at both the rated voltage and 120% of the rated voltage, the changes in leakage current of the chip under significant electrical stress can be monitored. This allows for the screening of chips that, even if their withstand voltage meets the requirements, have leakage current issues. (BR)DSS The test curves of SiC power semiconductor devices are relatively soft, and the leakage current turn-on point is low. This further reduces the early failure rate of SiC power semiconductor devices at the application and packaging levels, and improves the yield and lifespan of SiC power semiconductor devices in terms of voltage withstand capability.
[0055] In a more preferred embodiment, if the chip is determined to have no potential defects, the testing process of steps S1 to S4 is repeated, and the criteria for determining a failed chip remain consistent. Finally, if the leakage current change of the chip is monitored again after being subjected to significant electrical stress, and the chip is still determined to be a qualified chip after two leakage current tests, then the chip is confirmed to be a qualified chip. Based on the above technical solution, it is easier to screen out silicon carbide power semiconductor devices with high probability and risk of subsequent breakdown voltage failure, as well as SiC power semiconductor devices with potential defects and soft leakage current curves that cannot be screened by ordinary static testing. This further reduces the early failure rate of SiC power semiconductor devices at the application and packaging ends, and further improves the yield and lifespan of SiC power semiconductor devices in terms of breakdown voltage.
[0056] In a more preferred embodiment, the method further includes determining the preset leakage current condition before step S1.
[0057] like Figure 2 As shown, the specific implementation method can be as follows:
[0058] S 11 Seventy-seven target chips were selected, which were chips that passed the leakage current test based on the rated voltage.
[0059] The implementation method for determining the pass / fail status of leakage current testing based on rated voltage can be as follows: Determine if the fifth leakage current test value is less than the chip's maximum leakage current. If it is less, the chip is deemed passable and selected as the target chip. Alternatively, select a chip, first perform a leakage current test based on the rated voltage to obtain a leakage current test value I1, then perform a leakage current test based on 120% * rated voltage to obtain a leakage current test value I2. If I1 is less than the chip's maximum leakage current, and If the chip is determined to have no potential defects, it is considered a qualified chip and will be used as the target chip. Specific testing methods are not limited here; any chip that can be deemed qualified based on leakage current testing at rated voltage is considered a target chip and falls within the protection scope of this invention.
[0060] Each target chip undergoes a leakage current test at its rated voltage, resulting in the fifth leakage current test value, which corresponds to the target chip's leakage current at V. (BR)DSS Leakage current test results before the actual test.
[0061] S 12 The target chip undergoes 20 breakdown voltage V tests at room temperature based on a first initial leakage current condition. (BR)DSS The test was conducted with the initial leakage current condition set at 50 μA, and it was a curve test. During the test, the leakage current was scanned from 0 μA to the target condition (i.e., the initial leakage current condition). Figure 3 As shown.
[0062] S 13 Complete V (BR)DSS After the initial test, the leakage current of the target chip under rated voltage was further tested. Specifically, the target chip underwent a leakage current test based on its rated voltage, yielding a sixth leakage current test value. This sixth value represents the leakage current of the target chip at V... (BR)DSS The leakage current test results after the test was completed.
[0063] Leakage current testing is performed at specific points.
[0064] S 14 Compared to V (BR)DSSThe leakage current test results before and after the test are compared to determine whether the target chip is qualified. Specifically, the fifth and sixth leakage current test values are used to determine whether the target chip has potential defects. If the target chip is determined not to have potential defects, i.e., the target chip is qualified, then the process returns to step S. 12 Iterate through the next target chip and perform V... (BR)DSS Test; if the target chip is determined to have a potential defect, the target chip is marked as failed, the number of failed chips is accumulated and counted until the number of failed chips is ≥48, then the first initial leakage current condition (i.e., the 50μA set above) is determined as the preset leakage current condition, and the process of determining the preset leakage current condition ends.
[0065] The determination of whether the target chip has potential defects based on the fifth and sixth leakage current test values can be implemented as follows:
[0066] Determine whether the sixth leakage current test value is twice the fifth leakage current test value, i.e., V. (BR)DSS If the leakage current increases by more than 100% under the rated voltage after testing, the target chip is determined to have a potential defect; otherwise, the target chip is determined not to have a potential defect.
[0067] or,
[0068] Determine whether the difference between the sixth leakage current test value and the fifth leakage current test value reaches a preset difference, i.e., V. (BR)DSS After testing, the leakage current at rated voltage is lower than V. (BR)DSS If the increase in leakage current before testing meets a preset value, the target chip is determined to have a potential defect; otherwise, the target chip is determined not to have a potential defect. For example, if the sixth leakage current test value increases by 1 μA or more compared to the fifth leakage current test value, the target chip is determined to be a failed chip.
[0069] In a more preferred embodiment, if the number of failed chips determined after traversing all target chips is ≤48, then all target chips are traversed again, and step S is executed again in a loop. 12 ~S 14 The test continues until the number of identified failed chips reaches ≥48. Each time the test is repeated, the initial leakage current is increased. If the target chip is a diode, the initial leakage current doubles (50μA for the first test, 100μA for the second, and so on). If it is a MOSFET, IGBT, or SiCSBD, the initial leakage current increases by 10μA (50μA for the first test, 60μA for the second, and so on). This process continues until the number of identified failed chips reaches ≥48, at which point the updated initial leakage current condition is used as the preset leakage current condition.
[0070] By defining preset leakage current conditions, it can be ensured that SiC power semiconductor devices are subjected to appropriate electrical stress during the screening process. This prevents excessive damage to other qualified chips while identifying potential defects, and does not affect the high-temperature reverse bias lifespan of qualified chips. This helps reduce chip damage during screening and lowers costs. Furthermore, screening only requires confirming the screening conditions once for the same chip product, improving efficiency.
[0071] Example 2
[0072] This invention also provides an apparatus for screening chips with potential defects, such as... Figure 4 As shown, the device 400 includes:
[0073] The first breakdown voltage test module 410 is used to perform a breakdown voltage test on the chip under test based on a preset leakage current condition.
[0074] The first leakage current test module 420 is used to perform a leakage current test on the chip based on a first voltage to obtain a first leakage current test value.
[0075] The second leakage current test module 430 is used to perform a leakage current test on the chip based on a second voltage to obtain a second leakage current test value, wherein the first voltage is less than the second voltage and the second voltage is less than the breakdown voltage.
[0076] The first judgment module 440 determines whether the chip has potential defects based on the first leakage current test value and the second leakage current test value.
[0077] In a preferred embodiment, the first determining module 440 is specifically used for:
[0078] If the first leakage current test value reaches the maximum leakage current of the chip, the chip is determined to have a potential defect and is marked as failed; otherwise, it is determined whether the second leakage current test value reaches twice the first leakage current test value. If so, the chip is determined to have a potential defect and is marked as failed; otherwise, the chip is determined not to have a potential defect and is marked as qualified.
[0079] In a preferred embodiment, the device 400 further includes:
[0080] The second breakdown voltage test module 450 is used to perform a breakdown voltage test on the chip based on a preset leakage current condition.
[0081] The third leakage current test module 460 is used to perform a leakage current test on the chip based on the first voltage to obtain a third leakage current test value.
[0082] The fourth leakage current test module 470 is used to perform leakage current test on the chip based on the second voltage to obtain the fourth leakage current test value;
[0083] The second judgment module 480 determines whether the chip has potential defects based on the third leakage current test value and the fourth leakage current test value.
[0084] In a preferred embodiment, the second determining module 480 is specifically used for:
[0085] If the third leakage current test value reaches the maximum leakage current of the chip, the chip is determined to have a potential defect and is marked as failed; otherwise, it is determined whether the fourth leakage current test value reaches twice the third leakage current test value. If so, the chip is determined to have a potential defect and is marked as failed; otherwise, the chip is determined not to have a potential defect and is marked as qualified.
[0086] In a preferred embodiment, the first voltage is the rated voltage of the chip, and the second voltage = 120% * rated voltage.
[0087] In a preferred embodiment, the device 400 further includes:
[0088] The determination module 490 is used to determine the preset leakage current condition.
[0089] In a preferred embodiment, the determining module 490 is specifically used for:
[0090] A selection unit is used to select M target chips, wherein the target chips are chips that have passed the leakage current test based on the rated voltage, and the fifth leakage current test value is obtained by the leakage current test of the target chips based on the rated voltage, and M is a positive integer;
[0091] A breakdown voltage test unit is used to perform at least one breakdown voltage test on the target chip at room temperature based on a first initial leakage current condition.
[0092] Leakage current testing unit is used to perform leakage current testing on the target chip based on the rated voltage to obtain a sixth leakage current test value;
[0093] The determination unit is used to determine whether the target chip has a potential defect based on the fifth and sixth leakage current test values. If the target chip is determined not to have a potential defect, the process returns to step 2; if the target chip is determined to have a potential defect, the target chip is marked as failed, and N = N + 1 is calculated, where N is a positive integer and N is the number of target chips marked as failed, until... If the preset value is met, the first initial leakage current condition is determined as the preset leakage current condition.
[0094] In a preferred embodiment, the determining unit is specifically used for:
[0095] Determine whether the sixth leakage current test value is twice the fifth leakage current test value. If so, the target chip is determined to have a potential defect; otherwise, the target chip is determined not to have a potential defect.
[0096] or,
[0097] Determine whether the difference between the sixth leakage current test value and the fifth leakage current test value reaches a preset difference. If so, determine that the target chip has a potential defect; otherwise, determine that the target chip does not have a potential defect.
[0098] In a preferred embodiment, the determining module 490 further includes:
[0099] The adjustment unit, if it traverses M target chips, If the preset value is not met, then repeat steps 2 to 4 for each of the M target chips until... The preset value is met, and the first initial leakage current condition is adjusted to the second initial leakage current condition; the second initial leakage current condition is determined as the preset leakage current condition.
[0100] In a preferred embodiment, if the target chip is a diode, the second initial leakage current is set to twice the first initial leakage current; otherwise, the second initial leakage current = the first initial leakage current + 10μA.
[0101] This invention provides an apparatus for screening chips with potential defects, corresponding to the method for screening chips with potential defects described in the above embodiments, and implements the corresponding functions. Since the implementation method for screening chips with potential defects has been described in detail in the above embodiments, it will not be repeated here.
[0102] Example 3
[0103] This invention also provides an electronic device 5, such as... Figure 5 As shown, it includes a memory 51, a processor 52, and a computer program 53 stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of a method for screening chips with potential defects as described in the above embodiment.
[0104] Example 4
[0105] This invention also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of a method for screening chips with potential defects as described in the above embodiments.
[0106] Example 5
[0107] This invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of a method for screening chips with potential defects as described in the above embodiments.
[0108] The embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.
Claims
1. A method for screening chips with potential defects, characterized in that, include: The chip under test is subjected to breakdown voltage testing based on preset leakage current conditions; The chip performs a leakage current test based on a first voltage to obtain a first leakage current test value; The chip performs a leakage current test based on a second voltage to obtain a second leakage current test value. The first voltage is less than the second voltage, and the second voltage is less than the breakdown voltage. Based on the first leakage current test value and the second leakage current test value, determine whether the chip has a potential defect; Also includes: Determine the preset leakage current condition; Determining the preset leakage current condition includes: Step 1: Select M target chips. The target chips are chips that have passed the leakage current test based on the rated voltage. The fifth leakage current test value is obtained by performing a leakage current test on the target chips based on the rated voltage. M is a positive integer. Step 2: The target chip undergoes at least one breakdown voltage test at room temperature based on a first initial leakage current condition; Step 3: The target chip undergoes a leakage current test based on the rated voltage to obtain the sixth leakage current test value; Step 4: Based on the fifth and sixth leakage current test values, determine whether the target chip has a potential defect. If the target chip does not have a potential defect, return to step 2. If the target chip has a potential defect, mark the target chip as failed, and calculate N = N + 1, where N is a positive integer and N is the number of target chips marked as failed, until... If the preset value is met, the first initial leakage current condition is determined as the preset leakage current condition. Step 5, if after traversing M target chips, If the preset value is not met, steps 2-4 are repeated for each of the M target chips. Each time the chips are re-traversed, the initial leakage current during the test is increased until... If the preset value is met, the first initial leakage current condition is adjusted to the second initial leakage current condition. If the target chip is a diode, the second initial leakage current is set to twice the first initial leakage current; otherwise, the second initial leakage current = the first initial leakage current + 10μA. Step 6: Determine the second initial leakage current condition as the preset leakage current condition.
2. The method for screening chips with potential defects as described in claim 1, characterized in that, Determining whether the chip has potential defects based on the first leakage current test value and the second leakage current test value includes: If the first leakage current test value reaches the maximum leakage current of the chip, the chip is determined to have a potential defect and is marked as failed; otherwise, it is determined whether the second leakage current test value reaches twice the first leakage current test value. If so, the chip is determined to have a potential defect and is marked as failed; otherwise, the chip is determined not to have a potential defect and is marked as qualified.
3. The method for screening chips with potential defects as described in claim 1, characterized in that, Determining that the chip does not have potential defects based on the first leakage current test value and the second leakage current test value also includes: The chip undergoes a breakdown voltage test based on preset leakage current conditions; The chip performs a leakage current test based on a first voltage to obtain a third leakage current test value; The chip performs a leakage current test based on a second voltage to obtain a fourth leakage current test value; The chip is determined to have potential defects based on the third and fourth leakage current test values.
4. The method for screening chips with potential defects as described in claim 3, characterized in that, Determining whether the chip has potential defects based on the third and fourth leakage current test values includes: If the third leakage current test value reaches the maximum leakage current of the chip, the chip is determined to have a potential defect and is marked as failed; otherwise, it is determined whether the fourth leakage current test value reaches twice the third leakage current test value. If so, the chip is determined to have a potential defect and is marked as failed; otherwise, the chip is determined not to have a potential defect and is marked as qualified.
5. The method for screening chips with potential defects as described in claim 1, characterized in that, The first voltage is the rated voltage of the chip, and the second voltage is 120% of the rated voltage.
6. The method for screening chips with potential defects as described in claim 1, characterized in that, Determining whether the target chip has potential defects based on the fifth and sixth leakage current test values includes: Determine whether the sixth leakage current test value is twice the fifth leakage current test value. If so, the target chip is determined to have a potential defect; otherwise, the target chip is determined not to have a potential defect. or, Determine whether the difference between the sixth leakage current test value and the fifth leakage current test value reaches a preset difference. If so, the target chip is determined to have a potential defect; otherwise, the target chip is determined not to have a potential defect.
7. An apparatus for screening chips with potential defects, characterized in that, include: The breakdown voltage test module is used to perform breakdown voltage tests on the chip under test based on preset leakage current conditions. The first leakage current test module is used to perform a leakage current test on the chip based on a first voltage to obtain a first leakage current test value. The second leakage current test module is used to perform a leakage current test on the chip based on a second voltage to obtain a second leakage current test value. The first voltage is less than the second voltage, and the second voltage is less than the breakdown voltage. The first judgment module determines whether the chip has potential defects based on the first leakage current test value and the second leakage current test value. Also includes: A determination module is used to determine the preset leakage current condition; The module to be determined includes: A selection unit is used to select M target chips, wherein the target chips are chips that have passed the leakage current test based on the rated voltage, and the fifth leakage current test value is obtained by the leakage current test of the target chips based on the rated voltage, and M is a positive integer; A breakdown voltage test unit is used to perform at least one breakdown voltage test on the target chip at room temperature based on a first initial leakage current condition. Leakage current testing unit is used to perform leakage current testing on the target chip based on the rated voltage to obtain a sixth leakage current test value; The determination unit is used to determine whether the target chip has a potential defect based on the fifth leakage current test value and the sixth leakage current test value. If the target chip is determined not to have a potential defect, the process returns to step 2; if the target chip is determined to have a potential defect, the target chip is marked as failed, and N = N + 1 is calculated, where N is a positive integer and N is the number of target chips marked as failed, until... If the preset value is met, the first initial leakage current condition is determined as the preset leakage current condition. The adjustment unit is used to adjust the number of target chips after traversing M chips. If the preset value is not met, steps 2-4 are repeated for each of the M target chips. Each time the chips are re-traversed, the initial leakage current during the test is increased until... The preset value is met, and the first initial leakage current condition at this time is adjusted to the second initial leakage current condition; the second initial leakage current condition is determined to be the preset leakage current condition. If the target chip type is a diode, the second initial leakage current is set to twice the first initial leakage current; otherwise, the second initial leakage current = the first initial leakage current + 10μA.
8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of a method for screening chips with potential defects as described in any one of claims 1 to 6.
9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of a method for screening chips with potential defects as described in any one of claims 1 to 6.
10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of a method for screening chips with potential defects as described in any one of claims 1 to 6.