Low dropout linear regulator circuit

Abstract

The present application discloses a low-voltage-dropout linear regulator circuit, comprising a voltage regulating tube having an input terminal coupled to an input node, an output terminal coupled to an output node, and a control terminal for receiving a control signal; an error amplifier configured to modulate the control signal based on a voltage difference between a feedback voltage of the output node and a reference voltage so that the voltage at the output node is regulated; and an error amplifier power supply circuit configured to adaptively adjust the operating voltage of the error amplifier based on the output voltage of the output node, thereby enabling the output of the low-voltage-dropout linear regulator to remain stable when the input voltage varies over a wide range and the output load varies over a wide range, so that the output can reach the full voltage and full load application range.

Description

Technical Field

[0001] The present invention relates to the technical field of linear regulators, and more particularly to a low voltage difference linear regulator circuit. Background Art

[0002] Chips have become indispensable core components in modern electronic products. With the increasing sophistication of integrated circuit manufacturing processes and the desire to integrate more complex functions within the most limited chip area possible, a small system-on-chip (SOC) has emerged. This type of SOC typically includes a microprocessor (MCU), analog IP cores, digital IP cores, embedded memory modules, external communication interface modules, and a power management module. In actual chip design, SOC chips often use devices with different voltage tolerances (such as 1V, 1.5V, 1.8V, 3.3V, and 5V) based on the relationship between area, speed, and power consumption. This requires a corresponding power supply voltage.

[0003] Most portable electronic products use lithium batteries as their peripheral power supply. The voltage range of lithium batteries is 2.6V to 3.6V, which obviously cannot directly power low-voltage modules. Therefore, different power supply voltages need to be designed inside the SOC chip to power related modules. Low Dropout Regulator (LDO) is often used for on-chip power management of mobile consumer electronic device chips because of its simple structure, low static power consumption, and small output voltage ripple.

[0004] Figure 1 FIG. 1 shows a schematic circuit diagram of a low voltage drop linear regulator according to the prior art. Figure 1 As shown, the low-dropout linear regulator 100 includes a reference voltage VBG, a feedback network, an error amplifier EA, and a voltage regulator MNOUT. The voltage regulator MNOUT is connected between the power input and power output terminals and is used to provide an output voltage VOUT to the downstream loads CL and RL based on the input voltage VIN provided by the power input. The feedback network formed by resistors R1 and R2 is connected between the power output terminal and the reference ground. The common terminal of the resistors R1 and R2 is used to provide a feedback voltage VFB for the output voltage VOUT. The error amplifier EA has an inverting input terminal, a non-inverting input terminal, and an output terminal. The inverting input terminal is used to receive the feedback voltage VFB, the non-inverting input terminal is used to receive the reference voltage VBG, and the output terminal is connected to the control terminal of the voltage regulator MNOUT. The error amplifier EA is used to compare the feedback voltage VFB with the reference voltage VBG and adjust the gate-source voltage drop of the voltage regulator MNOUT based on the voltage difference between the two, thereby stabilizing the output voltage VOUT.

[0005] To reduce circuit power consumption while maintaining compatibility with the low operating voltage of the digital core within MCU chips and improving system compatibility, existing LDOs must have an adjustable output voltage between 0.5V and 5V. This means their input supply voltage must vary over a wide range, such as 0.8V to 12V. However, existing low-dropout linear regulator circuits suffer from the drawback of not being able to output voltages across the full voltage range. First, using a 0.8V supply voltage to generate the voltage reference VBG is difficult in conventional integrated circuit processes. Second, to drive the voltage regulator, the error amplifier typically requires a minimum voltage equal to the output voltage plus a 1.5V margin. For example, with a minimum output voltage of 0.5V, the error amplifier requires a minimum voltage of at least 2V. Clearly, using a 0.8V supply voltage is insufficient.

[0006] Therefore, it is necessary to improve the existing LDO to provide a low-dropout linear regulator that can be used for low input power supply voltage and has a wide swing. Summary of the Invention

[0007] In view of this, an object of the present invention is to provide a low voltage dropout linear regulator circuit that can adaptively adjust the operating voltage of the error amplifier in the feedback loop according to the output voltage so that the output can reach the full voltage application range.

[0008] According to an embodiment of the present invention, a low-voltage-dropout linear regulator circuit is provided, comprising: a voltage regulating tube having an input terminal coupled to an input node, an output terminal coupled to an output node, and a control terminal for receiving a control signal; an error amplifier configured to modulate the control signal based on a voltage difference between a feedback voltage of the output node and a reference voltage so that the voltage at the output node is regulated; and an error amplifier power supply circuit configured to adaptively adjust the operating voltage of the error amplifier based on the output voltage of the output node.

[0009] Optionally, the low voltage dropout linear regulator circuit further includes: a front-end voltage stabilization circuit configured to obtain a low voltage signal based on the input voltage of the input node.

[0010] Optionally, the low-voltage difference linear regulator circuit further includes: a first charge pump configured to perform a voltage doubling operation based on the low-voltage signal to obtain a first charge pump voltage; and a reference circuit configured to generate the reference voltage based on the first charge pump voltage.

[0011] Optionally, the error amplifier power supply circuit includes: a voltage divider circuit, configured to divide the output voltage to obtain a voltage divider signal; a comparator, configured to compare the voltage divider signal with a first reference voltage to generate a comparison signal; an oscillator, configured to generate a clock signal based on the comparison signal, the clock frequency of the clock signal being controlled by the comparison signal; and a second charge pump, configured to perform a multiple voltage operation on the low voltage signal based on the clock frequency of the clock signal to generate a corresponding second charge pump voltage for use as the operating voltage of the error amplifier.

[0012] Optionally, when the comparison signal indicates that the voltage divided signal is lower than the first reference voltage, the clock signal has a first clock frequency; when the comparison signal indicates that the voltage divided signal is higher than the first reference voltage, the clock signal has a second clock frequency, and the second clock frequency is lower than the first clock frequency.

[0013] Optionally, the oscillator includes a ring oscillator.

[0014] Optionally, the low-dropout linear regulator circuit further includes: an isolation circuit coupled between the output terminal of the second charge pump and the power supply terminal of the error amplifier to provide a higher power supply rejection ratio.

[0015] Optionally, the front-end voltage stabilization circuit is configured to make the low-voltage signal follow the input voltage when the input voltage is lower than a set value, and to make the low-voltage signal a fixed voltage when the input voltage is higher than a set value.

[0016] Optionally, the front-end voltage stabilization circuit includes a depletion-mode NMOS transistor.

[0017] Optionally, the depletion-mode NMOS transistor has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the input node, the control terminal is configured to receive a second reference voltage, and the second terminal is configured to provide the low-voltage signal.

[0018] The low-dropout linear regulator circuit provided by an embodiment of the present invention also includes an error amplifier power supply circuit that can adaptively adjust the operating voltage of the error amplifier based on the output voltage of the output node. This ensures that the LDO output is stable even when the input voltage varies over a wide range, allowing the output to operate within the full voltage range. Compared to existing charge pumps powered by a fixed voltage, the error amplifier power supply circuit of this embodiment can adaptively adjust the operating voltage of the error amplifier based on the output voltage, eliminating power consumption and significantly improving circuit efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0020] Figure 1 FIG. 1 shows a schematic circuit diagram of a low voltage dropout linear regulator according to the prior art.

[0021] Figure 2 A schematic circuit diagram of a low voltage dropout linear regulator circuit according to an embodiment of the present invention is shown.

[0022] Figure 3 A schematic circuit diagram of a front-end voltage stabilizing circuit according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0023] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0024] It should be understood that in the following description, a "circuit" refers to a conductive loop composed of at least one element or subcircuit connected electrically or electromagnetically. When an element or circuit is said to be "coupled to" another element or an element / circuit is said to be "coupled between" two nodes, it can be directly coupled or connected to the other element or there can be intermediate elements. The connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two elements.

[0025] In the present application, the voltage regulator provides a transistor for a current path, including one selected from a bipolar transistor or a field-effect transistor. The input terminal and the output terminal of the voltage regulator are respectively the high potential end and the low potential end on the current path, and the control terminal is used to receive a drive signal to control the voltage drop of the voltage regulator. The voltage regulator can be a PMOS (N-Metal-Oxide-Semiconductor) transistor or an NMOS (N-Metal-Oxide-Semiconductor) transistor. The first terminal, the second terminal and the control terminal of the PMOS transistor are the source, the drain and the gate, respectively, and the first terminal, the second terminal and the control terminal of the NMOS transistor are the drain, the source and the gate, respectively.

[0026] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] Reference Figure 2 , Figure 2A schematic circuit diagram of a low-dropout linear regulator circuit according to an embodiment of the present invention is shown. The low-dropout linear regulator circuit 200 includes a front-end voltage regulator circuit 210, a first charge pump 220, a voltage reference circuit 230, an error amplifier 240, an error amplifier power supply circuit 250, and a voltage regulator MNOUT. The voltage regulator MNOUT has a source-drain current path coupled between an input voltage VIN and an output voltage VOUT and configured to provide current to an output node. Specifically, the voltage regulator MNOUT is implemented using an NMOS transistor, whose drain is coupled to the input voltage VIN node and whose source is coupled to the output voltage VOUT node. The gate terminal of the voltage regulator MNOUT is configured to receive a control signal NG, which serves as the gate voltage of the voltage regulator MNOUT and can control the current flowing through the voltage regulator MNOUT. A load capacitor CL and a load resistor RL are connected between the output voltage VOUT node and ground.

[0028] The error amplifier 240 has a non-inverting input, an inverting input, and an output. Its inverting input is used to receive the feedback voltage VFB of the output voltage VOUT, and its non-inverting input is used to receive the reference voltage VBG. Its output is connected to the gate terminal of the voltage regulator MNOUT to output the control signal NG. The error amplifier 240 compares the feedback voltage VFB with the reference voltage VBG. When a deviation occurs between the two, the error amplifier 240 amplifies the deviation and controls the gate-source voltage drop of the voltage regulator MNOUT. In this embodiment, when the output voltage VOUT decreases, the voltage difference between the feedback voltage VFB and the reference voltage VBG increases, causing the voltage applied to the control terminal of the voltage regulator MNOUT to increase. This reduces the on-resistance between the first and second terminals of the voltage regulator MNOUT, and reduces the voltage drop across the voltage regulator MNOUT. This increases the voltage at the output terminal of the low-dropout linear regulator circuit 100, restoring the output voltage VOUT to a normal level.

[0029] In other embodiments of the present invention, the low-dropout linear regulator circuit 200 further includes a resistor feedback network connected between the output voltage node VOUT and ground, and the error amplifier 240 generates the control signal NG based on the voltage difference between the feedback voltage VFB provided by the resistor feedback network and the reference voltage VBG. As an example, the low-dropout linear regulator circuit 200 includes resistors R1 and R2 connected in series between the output voltage node VOUT and ground, with the node between resistors R1 and R2 being used to provide a feedback voltage VFB of the output voltage VOUT.

[0030] The front-end voltage regulator circuit 210 is configured to convert the wide swing of the input voltage VIN into a fixed low voltage for output. This is because the LDO power supply voltage range is very wide and may have high voltage conditions, such as 12V. However, in general integrated circuit processes, the area of MOS devices that can withstand high voltage is very large and the threshold voltage is also very high, making them unsuitable for use in large areas and low voltage conditions. Common low-voltage MOS devices cannot withstand the high voltage of 12V and can usually only operate at voltages of 1.8V, 3.3V or 5V. Therefore, by converting the input voltage VIN into a fixed low-voltage signal through the front-end voltage regulator circuit 210, subsequent modules can use standard low-voltage devices, which helps reduce circuit cost and power consumption.

[0031] Specifically, the front-end voltage regulator circuit 210 is coupled to an input voltage node VIN and is configured to generate a low-voltage signal Vreg based on the input voltage VIN. For example, when the input voltage VIN is low, such as below a set value, the front-end voltage regulator circuit 210 causes the low-voltage signal Vreg to follow the input voltage VIN. When the input voltage VIN is high, such as above the set value, the front-end voltage regulator circuit 210 causes the low-voltage signal Vreg to have a fixed voltage value.

[0032] Figure 3 FIG. 4 shows an implementation of a front-end voltage stabilizing circuit 210 according to an embodiment of the present invention. Figure 3 As shown, the front-end voltage regulator circuit 210 of this embodiment can be implemented using a depletion-type NMOS transistor M1. The transistor M1 has a source, a drain, and a gate. The drain is coupled to the input voltage VIN node, the gate is configured to receive a reference voltage Vref2, and the source is configured to provide the low-voltage signal Vreg. By setting the voltage value of the reference voltage Vref2, the desired low-voltage signal Vreg can be obtained at the source of the transistor M1.

[0033] Continue to refer to Figure 2 The first charge pump 220 is coupled to the output of the front-end voltage regulator circuit 210 and is configured to double the voltage of the low-voltage signal Vreg output by the front-end voltage regulator circuit 210 to generate a charge pump voltage Vpump1. Because the front-end voltage regulator circuit 210 outputs a relatively low voltage, the voltage doubled by the first charge pump 220 is still very low, allowing the use of low-voltage MOS devices.

[0034] The reference circuit 230 is coupled to the output of the first charge pump 220 and is configured to generate a stable reference voltage VBG based on the charge pump voltage Vpump1 output by the first charge pump 220. Specifically, the reference circuit 230 of this embodiment is primarily used to provide a reference voltage VBG that is substantially invariant with temperature and power supply voltage. This reference voltage VBG can be implemented using various bandgap reference voltage sources known in the art, and the present invention is not limited thereto.

[0035] Since the charge pump voltage Vpump1 generated by the first charge pump 220 is still insufficient to drive the voltage adjustment tube MNOUT to generate an output, for example, the voltage output by the front-end voltage regulator circuit 210 is 0.8V, and the first charge pump 220 doubles the voltage to 1.6V (actually, due to load capacity and other requirements, the actual voltage is stable at around 1.5V). However, in order to obtain an output voltage VOUT of 0.5V, the actual error amplifier 240 requires an operating voltage of 2V. Therefore, the low-voltage difference linear regulator circuit 200 of this embodiment also includes an error amplifier power supply circuit 250. The error amplifier power supply circuit 250 is configured to adaptively adjust the operating voltage of the error amplifier 240 based on the voltage value of the output voltage VOUT, so that the output of the LDO can be stable when the input voltage varies over a wide range.

[0036] Specifically, the error amplifier power supply circuit 250 includes a voltage divider circuit formed by resistors R3 and R4, a comparator 251, an oscillator 252, and a second charge pump 253. Resistors R3 and R4 are coupled between the output voltage node VOUT and ground and are configured to divide the output voltage VOUT to obtain a divided voltage signal Vs. The comparator 251 has a non-inverting input, an inverting input, and an output. The non-inverting input is configured to receive a reference voltage Vref1, and the inverting input is coupled to the common node between resistors R3 and R4 to receive the divided voltage signal Vs. The comparator 251 is configured to compare the divided voltage signal Vs with the reference voltage Vref1 to provide a comparison signal Vc at its output. The oscillator 252 is implemented, for example, by a ring oscillator, which has the advantage of a low power supply voltage. The oscillator is configured to generate a clock signal Vosc based on the comparison signal Vc, with the clock frequency of the clock signal Vosc being controlled by the comparison signal Vc. The second charge pump 253 is coupled to the oscillator 252 and the output of the front-end voltage regulator circuit 210 and is configured to perform a multiplication operation on the low voltage signal Vreg based on the clock frequency of the clock signal Vosc to generate a charge pump voltage Vpump2 for the operating voltage of the error amplifier 240.

[0037] When the output voltage VOUT is low, the voltage-divided signal Vs is lower than the reference voltage Vref1, and the comparison signal Vc output by the comparator 251 is high. In response to the high-level comparison signal Vc, the oscillator 252 controls the clock signal Vosc to have a first clock frequency, causing the second charge pump 253 to amplify the low-voltage signal Vreg by multiple times, for example, by tripling or quadrupling the voltage. This generates a sufficient operating voltage to drive the error amplifier 240 and the voltage regulator MNOUT, thereby increasing the output voltage VOUT to a set value. When the output voltage VOUT rises to a certain value, the voltage-divided signal Vs is higher than the reference voltage Vref1, and the comparison signal Vc output by the comparator 251 flips to a low level. In response to the low-level comparison signal Vc, the oscillator 252 controls the clock signal Vosc to decrease in frequency to the second clock frequency, or even stops operating, thereby causing the output voltage of the second charge pump 253 to decrease and stabilize at a constant value.

[0038] In some embodiments, in order to stabilize the output of the LDO 200, an isolation circuit may be coupled between the output of the second charge pump 253 and the power supply terminal of the error amplifier 240 to provide a high power supply rejection ratio and a low ripple operating voltage for the error amplifier 240 and the voltage regulator MNOUT.

[0039] In addition, the error amplifier power supply circuit 250 of this embodiment has the following advantages: First, the second charge pump 253 uses the low-voltage signal Vreg output by the front-end voltage regulator circuit 210 as its power source, which allows it to utilize a large number of low-voltage MOS devices. Because the charge pump, as the power source for the subsequent circuit, requires a certain load capacity, the required MOS devices are inherently large. If high-voltage MOS devices were used, the chip area would be very large, significantly increasing the circuit cost. Second, because the charge pump voltage Vpump2 output by it can be adaptively adjusted according to the output voltage VOUT, there is only a small voltage margin between it and the output voltage VOUT. This voltage margin is only required for the error amplifier 240 to operate. Therefore, a large number of low-voltage MOS devices can be used in the error amplifier 240, further reducing circuit cost. Finally, compared with existing charge pumps powered by fixed voltages, the error amplifier power supply circuit 250 of this embodiment can adaptively adjust the operating voltage of the error amplifier according to the output voltage, eliminating power consumption and significantly improving circuit efficiency.

[0040] Correspondingly, an embodiment of the present invention further provides an electronic device, which includes the low-dropout linear regulator circuit 200 provided in the above embodiment.

[0041] In one embodiment of the present invention, the electronic device provided by the present invention may be a portable electronic device such as a cellular phone.

[0042] In summary, the low-dropout linear regulator circuit provided by an embodiment of the present invention also includes an error amplifier power supply circuit that can adaptively adjust the operating voltage of the error amplifier based on the output voltage of the output node. This ensures that the LDO output remains stable even when the input voltage varies over a wide range, allowing the output to operate within the full voltage range. Compared to existing charge pumps powered by a fixed voltage, the error amplifier power supply circuit of this embodiment can adaptively adjust the operating voltage of the error amplifier based on the output voltage, eliminating power consumption and significantly improving circuit efficiency.

[0043] It should be noted that relational terms such as first and second, etc., herein are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0044] The embodiments of the present invention are described above, but these embodiments do not describe all details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and modify and use it based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A low-dropout linear regulator circuit, comprising: A voltage regulating tube having an input terminal coupled to the input node, an output terminal coupled to the output node, and a control terminal for receiving a control signal; an error amplifier configured to modulate the control signal based on a voltage difference between a feedback voltage of the output node and a reference voltage so that the voltage at the output node is regulated; a front-end voltage stabilizing circuit configured to obtain a low-voltage signal based on an input voltage of the input node; as well as an error amplifier power supply circuit, configured to adaptively adjust an operating voltage of the error amplifier based on an output voltage of the output node; Wherein, the error amplifier power supply circuit includes: A voltage dividing circuit is configured to divide the output voltage to obtain a voltage dividing signal; a comparator configured to compare the divided voltage signal with a first reference voltage to generate a comparison signal; an oscillator configured to generate a clock signal based on the comparison signal, wherein a clock frequency of the clock signal is controlled by the comparison signal; and The second charge pump is configured to perform a multiple voltage operation on the low voltage signal based on the clock frequency of the clock signal to generate a corresponding second charge pump voltage for use as an operating voltage of the error amplifier.

2. The low-dropout linear regulator circuit according to claim 1 , further comprising: a first charge pump configured to perform a voltage doubling operation based on the low voltage signal to obtain a first charge pump voltage; as well as A reference circuit is configured to generate the reference voltage based on the first charge pump voltage.

3. The low-dropout linear regulator circuit according to claim 1, wherein: When the comparison signal indicates that the voltage-divided signal is lower than the first reference voltage, the clock signal has a first clock frequency; when the comparison signal indicates that the voltage-divided signal is higher than the first reference voltage, the clock signal has a second clock frequency, and the second clock frequency is lower than the first clock frequency.

4. The low-dropout linear regulator circuit according to claim 1, wherein: The oscillator includes a ring oscillator.

5. The low-dropout linear regulator circuit according to claim 1, wherein: Also includes: An isolation circuit is coupled between the output terminal of the second charge pump and the power supply terminal of the error amplifier to provide a higher power supply rejection ratio.

6. The low-dropout linear regulator circuit according to claim 1, wherein: The front-end voltage regulator circuit is configured to make the low-voltage signal follow the input voltage when the input voltage is lower than a set value, and to make the low-voltage signal a fixed voltage when the input voltage is higher than the set value.

7. The low-dropout linear regulator circuit according to claim 6, wherein: The front-end voltage stabilizing circuit includes a depletion-type NMOS transistor.

8. The low-dropout linear regulator circuit according to claim 7, wherein: The depletion-mode NMOS transistor has a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the input node, the control terminal is configured to receive a second reference voltage, and the second terminal is configured to provide the low-voltage signal.

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