Controller, Electronic Device, and Data Transmission System

Abstract

The present application provides a controller, an electronic device, and a data transmission system. The controller belongs to a master device and includes: a shared storage unit for storing protocol commands sent by the master device to a slave device and storing target data returned by the slave device based on the protocol commands; a first counter for counting the number of bytes of the protocol commands sent; wherein, the counting result of the first counter is used to indicate whether the protocol commands have been sent completely; a second counter for counting the number of bytes of the received target data; wherein, the counting result of the second counter is used to indicate whether the target data has been received completely. By the above method, during the data transmission process in the chip, the control logic is simplified, the number of registers or FIFOs set is reduced, the utilization rate of the registers or FIFOs is improved, and the chip area is reduced.

Description

Technical Field

[0001] This application relates to the technical field of data transmission, and in particular, to a controller, an electronic device, and a data transmission system. Background Art

[0002] PMBus (Power Management Bus) is an open standard digital power management protocol. In some systems of power management chips, in the data transmission scenario based on the PMBus protocol, the Central Processing Unit (CPU) is usually required to participate in scheduling and resource allocation. The CPU sends data to the PMBUS controller through the Advanced Peripheral Bus (APB), and then the PMBUS controller sends the data to the power management chip.

[0003] In the prior art, two registers are usually set in the PMBUS controller: a command data sending register and a received data register, or two FIFOs (First Input First Output): a data command sending FIFO and a data receiving FIFO. The PMBUS data sending method is usually: sending protocol commands and data based on the command data sending register or the data command sending FIFO, and receiving protocol data based on the received data register or the data receiving FIFO. However, the above method will lead to disadvantages such as an increase in the number of registers or FIFOs, more complex logic control, low utilization rate of registers or FIFOs, and an increase in chip area. Summary of the Invention

[0004] The purpose of the embodiments of this application is to provide a controller, an electronic device, and a data transmission system, which are used to simplify the control logic, reduce the number of registers or FIFOs set, improve the utilization rate of registers or FIFOs, and reduce the chip area during the data transmission process in the chip.

[0005] In a first aspect, this application provides a controller, which belongs to a master device. The controller includes: a shared storage unit, which is used to store the protocol commands sent by the master device to the slave device, and store the target data returned by the slave device based on the protocol commands; a first counter, which is used to count the number of bytes of the sent protocol commands; wherein, the counting result of the first counter is used to indicate whether the protocol command is sent completely; a second counter, which is used to count the number of bytes of the received

[0006] target data; wherein, the counting result of the second counter is used to indicate whether the target data is received completely.

[0007] In an embodiment of the present application, only one shared storage unit is provided in the controller to store protocol commands and target data. A first counter is set to count the number of bytes of the issued protocol commands, and the counting result of the first counter is compared with the number of bytes of the protocol commands to determine that the issued protocol commands are sent out from the shared storage

[0008] unit; A second counter is set to count the number of bytes of the received target data, and the counting result of the second counter is compared with the number of bytes of the target data

[0009] to determine that the reception of the target data protocol commands is completed. Compared with the prior art solution of setting two registers to implement data sending and receiving, the controller provided in the embodiment of the present application simplifies the control logic and reduces the number of settings of registers or FIFOs, improves the utilization rate of registers or FIFOs, and reduces the chip area.

[0010] In an optional implementation manner, the controller further includes: a first read-write control circuit; the first read-write control circuit is connected to the shared storage unit, and the first read-write control circuit is configured to write the protocol commands sent by the processor in the master device into the shared storage unit, and read the target data from the shared storage unit and send the target data to the processor.

[0011] In an optional implementation manner, the controller further includes: a second read-write control circuit; the second read-write control circuit is connected to the shared storage unit, and the second read-write control circuit is configured to send the protocol commands stored in the shared storage unit to the slave device, and determine that the protocol commands are sent out based on the counting result of the first counter; and receive the target data from the slave device and store it in the shared storage unit, and determine that the reception of the target data is completed based on the counting result of the second counter.

[0012] In an optional implementation manner, the slave device includes: a power management chip, and the master device and the slave device are connected through a PMbus bus.

[0013] In a second aspect, the present application provides an electronic device, including: a shared storage unit, configured to store protocol commands sent to a slave device, and store target data returned by the slave device based on the protocol commands; a controller, configured to count the number of bytes of the issued protocol commands to determine whether the protocol commands are sent out; and count the received target data to determine whether the target data is received.

[0014] In an alternative embodiment, the electronic device further includes a processor, and the controller is further configured to write the protocol command sent by the processor into the shared storage unit, read the target data from the shared storage unit, and send the target data to the processor.

[0015] In an alternative embodiment, the controller is further configured to send the protocol command stored in the shared storage unit to the slave device, and determine that the protocol command has been sent completely based on the counting result of the protocol command; and receive the target data from the slave device and store it in the shared storage unit, and determine that the target data has been received completely based on the counting result of the target data.

[0016] In a third aspect, the present application provides a data transmission system, including: a master device and a slave device connected by a communication bus; the master device includes: a shared storage unit, configured to store a protocol command sent to the slave device, and store target data returned by the slave device based on the protocol command; the master device is configured to count the number of bytes of the issued protocol command to determine whether the protocol command has been sent completely; and count the received target data to determine whether the target data has been received completely.

[0017] In an alternative embodiment, the master device further includes a processor, and the master device is further configured to write the protocol command sent by the processor into the shared storage unit, read the target data from the shared storage unit, and send the target data to the processor.

[0018] In an alternative embodiment, the master device is further configured to send the protocol command stored in the shared storage unit to the slave device, and determine that the protocol command has been sent completely based on the counting result of the protocol command; and receive the target data from the slave device and store it in the shared storage unit, and determine that the target data has been received completely based on the counting result of the target data. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation of the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0020] Figure 1 It is a structural block diagram of a controller provided by an embodiment of the present application;

[0021] Figure 2 Block diagram of another controller provided by an embodiment of the present application;

[0022] Figure 3 Schematic diagram of a data transmission system including a controller provided by an embodiment of the present application;

[0023] Figure 4 Schematic diagram of a write word protocol command provided by an embodiment of the present application;

[0024] Figure 5 Schematic diagram of a read byte protocol command provided by an embodiment of the present application;

[0025] Figure 6 Block diagram of an electronic device provided by an embodiment of the present application;

[0026] Figure 7 Block diagram of a data transmission system provided by an embodiment of the present application.

[0027] Icons: 100 - Controller; 101 - Shared storage unit; 102 - First counter; 103 - Second counter; 104 - First read / write control circuit; 105 - Second read / write control circuit; 600 - Electronic device; 601 - Shared storage unit; 602 - Controller; 700 - Data transmission system; 701 - Master device; 702 - Slave device. Detailed implementation manners

[0028] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings in the embodiments of the present application.

[0029] Next, through embodiments and in combination with the accompanying drawings, the technical solutions of the present application will be clearly and completely described. However, the present application is not limited to the following described embodiments. Based on the following embodiments, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application. For clarity, parts unrelated to the description of the exemplary embodiments are omitted in the drawings.

[0030] It should be understood that terms such as "including" or "having" in the present application are intended to indicate the existence of the features, numbers, steps, actions, components, or combinations thereof disclosed in this specification, and do not exclude the possibility of the existence or addition of one or more other features, numbers, steps, actions, components, or combinations thereof. In the present application, "a plurality" generally can be interpreted as meaning two or more.

[0031] The purpose of the embodiments of the present application is to provide a controller, an electronic device, and a data transmission system, which can simplify the control logic, reduce the number of registers or FIFOs set, improve the utilization rate of registers or FIFOs, and reduce the chip area during the data transmission process in a chip.

[0032] Please refer to Figure 1 , Figure 1 which is a structural block diagram of a controller provided by the embodiments of the present application. The controller 100 belongs to the master device. The controller 100 includes: a shared storage unit 101, a first counter 102, and a second counter 103.

[0033] In the embodiments of the present application, the controller 100 is set in the master device. The master device and the slave device are connected through a communication bus to achieve data transmission. The shared storage unit 101 is used to store the protocol commands sent by the master device to the slave device, and to store the target data returned by the slave device based on the protocol commands. The first counter 102 is used to count the number of bytes of the sent protocol commands, and the counting result of the first counter 102 is used to indicate whether the protocol command has been sent completely. The second counter 103 is used to count the number of bytes of the received target data, and the counting result of the second counter 103 is used to indicate whether the target data has been received completely.

[0034] It should be noted that the embodiments of the present application do not limit the data communication protocol adopted between the master device and the slave device. The data communication protocol adopted between the master device and the slave device can be: PMbus protocol (Power Management Bus), SMbus protocol (System Management Bus), IIC protocol (Inter-Integrated Circuit), etc.

[0035] Correspondingly, when the PMbus protocol is used for data communication between the master device and the slave device, the controller 100 is a PMbus controller; when the SMbus protocol is used for data communication between the master device and the slave device, the controller 100 is an SMbus controller; when the IIC protocol is used for data communication between the master device and the slave device, the controller 100 is an IIC controller.

[0036] The protocol command is a command generated by the master device based on the data communication protocol adopted between itself and the slave device for controlling the slave device. The target data is the relevant parameter information returned by the slave device to the master device in response to the protocol command after receiving the protocol command sent by the master device.

[0037] For example, the PMbus protocol is used for data communication between the master device and the slave device. The protocol commands sent by the master device to the slave device can be various commands defined in the PMbus protocol, such as the write word protocol command, the read byte protocol command, etc. Specifically, the protocol command can include: the address of the slave device, the command code, or the address of the slave device, the command code, and the configuration parameters. The target data can be parameter data such as the voltage and current of the slave device.

[0038] In order to reduce the number of registers or FIFOs set in the chip, improve the utilization rate of the registers or FIFOs, and reduce the chip area, only one shared storage unit 101 is set in the controller 100 provided by the embodiment of the present application. During the communication between the master device and the slave device, both the protocol command sent by the master device to the slave device and the target data returned by the slave device based on the protocol command sent by the master device are stored in the shared storage unit 101.

[0039] It should be noted that the embodiment of the present application does not limit the specific implementation manner of the shared storage unit 101. The shared storage unit 101 can be a module with a data storage function such as a register, a FIFO queue, etc. Further, when the shared storage unit 101 is a FIFO queue, the FIFO queue can be a software FIFO or a hardware FIFO. The shared storage unit 101 being a software FIFO can be understood as setting a region in the memory of the controller 100 and accessing this memory region according to the first-in-first-out rule, thereby forming a software FIFO. The shared storage unit 101 being a hardware FIFO can be understood as integrating a hardware memory unit in the controller 100 to implement the FIFO function.

[0040] When the master device sends a protocol command to the slave device based on the bus protocol, the protocol command is stored in the shared storage unit 101, and then the controller 100 sends the protocol command stored in the shared storage unit 101 to the slave device. After receiving the protocol command, the slave device obtains its own relevant data (i.e., the above-mentioned target data) according to the protocol command, and then sends the target data to the master device based on the bus protocol. The controller 100 in the master device stores the target data in the shared storage unit 101.

[0041] Since only one shared storage unit 101 is set in the controller 100 to store the protocol command sent by the master device to the slave device and the target data returned by the slave device based on the protocol command, in order to ensure that all the data in the protocol command sent by the master device can be sent to the slave device in an orderly manner, and the target data returned by the slave device based on the protocol command can be received in an orderly manner, a first counter 102 and a second counter 103 are set in the controller.

[0042] In the stage where the master device sends a protocol command to the slave device, the number of bytes of the protocol command sent this time is determined. The controller 100 sequentially sends the protocol commands in the shared storage unit 101 to the slave device. The first counter 102 counts the number of bytes of the protocol commands sent from the shared storage unit 101. When the counting result of the first counter 102 is the same as the number of bytes of the protocol command sent this time, the controller 100 determines that the protocol command has been sent and ends the sending of this protocol command.

[0043] In the stage where the slave device returns target data to the master device based on the protocol command, the number of bytes of the target data received this time is determined. The controller 100 reads the target data from the slave device and stores it in the shared storage unit 101. The second counter 103 counts the number of bytes of the received target data. When the counting result of the second counter 103 is the same as the number of bytes of the target data received this time, the controller 100 determines that the target data has been received and ends the reception of this target data.

[0044] In the above manner, when the controller only sets one shared storage unit to store the protocol command and the target data, sets the first counter to count the number of bytes of the sent protocol command, compares the counting result of the first counter with the number of bytes of the protocol command, and determines that the protocol command sent from the shared storage unit is completed; sets the second counter to count the number of bytes of the received target data, compares the counting result of the second counter with the number of bytes of the target data, and determines that the target data protocol command has been received. Compared with the prior art solution of setting two registers to implement data sending and receiving, the controller provided by the embodiment of the present application simplifies the control logic and reduces the number of settings of registers or FIFOs, improves the utilization rate of registers or FIFOs, and reduces the chip area.

[0045] Further, please refer to Figure 2 , a processor is further provided in the master device. The processor has signal processing capabilities and participates in scheduling and resource allocation during the data transmission between the master device and the slave device. The processor can be a general-purpose processor, such as a central processing unit (CPU), a graphics processing unit (GPU), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The present application does not make specific limitations on this.

[0046] During the data transmission between the master device and the slave device, the processor generates protocol commands to control the working state of the slave device, and receives the target data returned by the slave device based on the protocol commands, so as to realize the scheduling and resource allocation of the entire system.

[0047] Further, the controller 100 further includes: a first read-write control circuit 104. The first read-write control circuit 104 is connected to the shared storage unit 101. The first read-write control circuit 104 is configured to write the protocol commands sent by the processor in the master device into the shared storage unit 101, and read the target data from the shared storage unit 101, and send the target data to the processor.

[0048] Further, the controller 100 further includes: a second read-write control circuit 105. The second read-write control circuit 105 is connected to the shared storage unit 101. The second read-write control circuit is configured to send the protocol commands stored in the shared storage unit 101 to the slave device, and determine that the protocol commands are sent successfully based on the counting result of the first counter 102; and receive the target data from the slave device and store it in the shared storage unit 101, and determine that the target data is received successfully based on the counting result of the second counter 103.

[0049] It can be understood that the first read-write control circuit 104 is arranged between the processor and the shared storage unit 101 to realize the data interaction between the processor and the shared storage unit 101. The second read-write control circuit 105 is arranged between the shared storage unit 101 and the slave device to realize the data interaction between the shared storage unit 101 and the slave device.

[0050] It can be understood that the first read-write control circuit 104 and the second read-write control circuit 105 are circuits for realizing the data read-write function, and the embodiments of the present application do not limit the specific implementation manners of the first read-write control circuit 104 and the second read-write control circuit 105.

[0051] The working process of the controller 100 provided by the embodiments of the present application will be introduced below in combination with specific examples.

[0052] Please refer to Figure 3 , Figure 3Schematic diagram of a data transmission system including a controller 100 provided by an embodiment of the present application. The data transmission system includes a master device and multiple slave devices (corresponding to Slave Device 1, Slave Device 2, and Slave Device 3 in the figure). The master device includes a controller 100 and a CPU, and the multiple slave devices are multiple power management chips (Power Management Integrated Circuit, PMIC). Communication between the master device and the slave devices is carried out through the PMbus protocol. The shared storage unit 101 is a shared FIFO queue.

[0053] Taking a write word protocol command as an example, as Figure 4 shown, the write word protocol command includes slave device address information (corresponding to Figure 4 Address and Wr in it, with a length of 1 byte), a command code (corresponding to Figure 4 Command Code in it, with a length of 1 byte), and configuration parameters (corresponding to Figure 4 Date Byte Low and Date Byte High in it, with a length of 2 bytes).

[0054] The CPU writes the slave device address information, command code, and configuration parameters in the write word protocol command into the shared FIFO queue in sequence through the first read / write control circuit 104, and sets the length of the data to be sent by this shared FIFO queue to 4. After the master device starts start (corresponding to Figure 4 S in it), the second read / write control circuit 105 sends the slave device address information, command code, and configuration parameters in the shared FIFO queue to the slave device in sequence according to the PMbus protocol when the slave device meets the response condition. During the sending process, the first counter 102 counts once for each byte of data sent. When the counting result of the first counter 102 is 4, the second read / write control circuit 105 determines that the sending of this write word protocol command is completed, generates a stop condition (corresponding to Figure 4 P in it), and ends the communication between the master device and the slave device this time.

[0055] Taking a read byte protocol command as an example, as Figure 5 shown, the read byte protocol command includes first slave device address information (corresponding to Figure 5 Slave Address and Wr in it, with a length of 1 byte), a command code (corresponding to Figure 5 CommandCode in it, with a length of 1 byte), and second slave device address information (corresponding to Figure 5 Slave Address and Rd in it, with a length of 1 byte).

[0056] The CPU writes the first slave device address information, command code, and second slave device address information in the read byte protocol command into the shared FIFO queue in sequence through the first read / write control circuit 104, and sets the length of the data to be sent by the shared FIFO queue this time to 3. After the master device starts start (corresponding to Figure 4 the S in it), according to the PMbus protocol, the second read / write control circuit 105 sends the first slave device address information, command code, and second slave device address information in the shared FIFO queue to the slave device in sequence when the slave device meets the response condition. During the sending process, the first counter 102 counts once for each byte of data sent. When the counting result of the first counter 102 is 3, the second read / write control circuit 105 determines that the sending of this read byte protocol command is completed and enters the data reading stage.

[0057] When generating this read byte protocol command, the CPU determines that the target data to be read from the slave device in this communication is 1 byte in length. After entering the data reading stage, the second read / write control circuit 105 reads the target data from the slave device according to the PMbus protocol and stores the target data in the shared FIFO queue. During the reading process, the second counter 103 counts once for each byte of data read. When the counting result of the second counter 103 is 1, the second read / write control circuit 105 determines that the execution of this read byte protocol command is completed, generates a stop condition (corresponding to Figure 5 the P in it), and ends the communication between the master device and the slave device this time.

[0058] It can be understood that after the communication between the master device and the slave device ends, the first read / write control circuit 104 sends the target data stored in the shared FIFO queue to the CPU of the master device so that the CPU can schedule and allocate resources for the operation of the entire system according to the target data.

[0059] Based on the same inventive concept, an electronic device is also provided in an embodiment of the present application. Please refer to Figure 6 Figure 6 which is a structural block diagram of an electronic device provided in an embodiment of the present application. The electronic device 600 includes a shared storage unit 601 and a controller 602.

[0060] In an embodiment of the present application, the shared storage unit 601 is connected to the controller 602. The shared storage unit 601 is used to store the protocol commands sent to the slave device and store the target data returned by the slave device based on the protocol commands. The controller 602 is used to count the number of bytes of the issued protocol commands to determine whether the protocol commands are sent completed; and count the received target data to determine whether the target data is received completed.

[0061] In an alternative embodiment, the electronic device 600 further includes a processor. The controller 602 is further configured to write the protocol commands sent by the processor into the shared storage unit 601, read the target data from the shared storage unit 601, and send the target data to the processor.

[0062] In an alternative embodiment, the controller 602 is further configured to send the protocol commands stored in the shared storage unit 601 to the slave device, and determine that the protocol commands are sent completely based on the counting result of the protocol commands; and receive the target data from the slave device and store it in the shared storage unit 601, and determine that the target data is received completely based on the counting result of the target data.

[0063] It should be noted that, compared with the foregoing controller 100, in the electronic device 600 provided in the embodiment of the present application, the shared storage unit 601 in the electronic device 600 is disposed outside the controller 602 and is connected to the controller 602. In addition, the specific implementation manner of the controller 602 provided in the embodiment of the present application is similar to the specific implementation manner of the foregoing controller 100, and the same or similar parts can be referred to each other. For the sake of simplicity of the specification, it will not be elaborated here.

[0064] Based on the same inventive concept, an embodiment of the present application further provides a data transmission system. Please refer to Figure 7 , Figure 7 which is a block diagram of a data transmission system provided in an embodiment of the present application. The data transmission system 700 includes a master device 701 and a slave device 702 connected by a communication bus.

[0065] The master device 701 includes: a shared storage unit, configured to store protocol commands sent to the slave device 702, and store target data returned by the slave device 702 based on the protocol commands; the master device 701 is configured to count the number of bytes of the issued protocol commands to determine whether the protocol commands are sent completely; and count the received target data to determine whether the target data is received completely.

[0066] In an alternative embodiment, the master device 701 further includes a processor. The master device 701 is further configured to write the protocol commands sent by the processor into the shared storage unit, read the target data from the shared storage unit, and send the target data to the processor.

[0067] In an alternative embodiment, the master device 701 is further configured to send the protocol commands stored in the shared storage unit to the slave device 702, and determine that the protocol commands are sent completely based on the counting result of the protocol commands; and receive the target data from the slave device 702 and store it in the shared storage unit, and determine that the target data is received completely based on the counting result of the target data.

[0068] It should be noted that the number of slave devices 702 in the embodiments of the present application is not specifically limited, and may be 3, 5, 10, etc.

[0069] In some embodiments, as Figure 7 shown, a controller 100 as in the foregoing embodiment is provided in the master device 701. The specific implementation manner of the controller 100 in the master device 701 is similar to that of the foregoing controller 100. The same or similar parts can be referred to each other. For the sake of simplicity of the specification, it will not be elaborated here.

[0070] In other embodiments, an electronic device 600 as in the foregoing embodiment may be provided in the master device 701. The specific implementation manner of the electronic device 600 in the master device 701 is similar to that of the foregoing electronic device 600. The same or similar parts can be referred to each other. For the sake of simplicity of the specification, it will not be elaborated here.

[0071] In the embodiments provided in the present application, it should be understood that the disclosed device and method can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces. The indirect coupling or communication connection of the device or unit may be in an electrical, mechanical or other form.

[0072] In addition, the units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0073] Furthermore, in each embodiment of the present application, the various functional modules may be integrated together to form an independent part, or each module may exist alone, or two or more modules may be integrated to form an independent part.

[0074] It should be noted that if a function is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0075] In this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0076] The above are only the embodiments of the present application and are not used to limit the protection scope of the present application. For those skilled in the art, the present application can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A controller, characterized in that, Belonging to the master device, the controller includes: A shared storage unit for storing the protocol commands sent by the master device to the slave device and storing the target data returned by the slave device based on the protocol commands; A first counter for counting the number of bytes of the issued protocol commands; wherein, the counting result of the first counter is used to indicate whether the protocol command has been sent completely; A second counter for counting the number of bytes of the received target data; wherein, the counting result of the second counter is used to indicate whether the target data has been received completely.

2. The controller according to claim 1, characterized in that, The controller further includes: a first read-write control circuit; the first read-write control circuit is connected to the shared storage unit, and the first read-write control circuit is used to write the protocol commands sent by the processor in the master device into the shared storage unit, and read the target data from the shared storage unit and send the target data to the processor.

3. The controller according to claim 2, characterized in that, The controller further includes: a second read-write control circuit; the second read-write control circuit is connected to the shared storage unit, and the second read-write control circuit is used to send the protocol commands stored in the shared storage unit to the slave device and determine that the protocol command has been sent completely based on the counting result of the first counter; and receive the target data from the slave device and store it in the shared storage unit, and determine that the target data has been received completely based on the counting result of the second counter.

4. The controller according to any one of claims 1-3, characterized in that, The slave device includes: a power management chip, and the master device and the slave device are connected through a PMbus bus.

5. An electronic device, characterized in that, Including: A shared storage unit for storing the protocol commands sent to the slave device and storing the target data returned by the slave device based on the protocol commands; A controller for counting the number of bytes of the issued protocol commands to determine whether the protocol command has been sent completely; And counting the received target data to determine whether the target data has been received completely.

6. The electronic device according to claim 5, wherein The electronic device further includes a processor, and the controller is further used to write the protocol commands sent by the processor into the shared storage unit, and read the target data from the shared storage unit and send the target data to the processor.

7. The electronic device according to claim 6, characterized in that, The controller is further used to send the protocol commands stored in the shared storage unit to the slave device and determine that the protocol command has been sent completely based on the counting result of the protocol commands; And receive the target data from the slave device and store it in the shared storage unit, and determine that the target data has been received completely based on the counting result of the target data.

8. A data transmission system, characterized in that, Including: A master device and a slave device connected through a communication bus; The master device includes: a shared storage unit for storing the protocol commands sent to the slave device and storing the target data returned by the slave device based on the protocol commands; The master device is used to count the number of bytes of the issued protocol commands to determine whether the protocol command has been sent completely; and count the received target data to determine whether the target data has been received completely.

9. The data transmission system according to claim 8, wherein The master device further includes a processor, and is further configured to write the protocol command sent by the processor into the shared storage unit, read the target data from the shared storage unit, and send the target data to the processor.

10. The data transmission system according to claim 9, characterized in that, The master device is further configured to send the protocol command stored in the shared storage unit to the slave device, and determine that the protocol command has been sent completely based on the counting result of the protocol command; and receive the target data from the slave device and store it in the shared storage unit, and determine that the target data has been received completely based on the counting result of the target data.

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