A divider circuit based on voltage-controlled current source and division calculation method

Abstract

The present invention relates to the field of analog control circuits and aims to provide a divider circuit and division calculation method based on a voltage-controlled current source. The circuit includes a comparator, a sawtooth wave generator, a voltage-controlled current source, a capacitor, two resistors, a single-pole double-throw switch, and a single-pole single-throw switch. The two switches are electronically controlled, with their control terminals connected to the output terminals of the comparator, and a PWM signal is used to control the operation and on / off of the two switches. The dividend voltage is connected to the two terminals of the voltage-controlled current source, one terminal of which is connected to the fixed terminal of the single-pole double-throw switch, and the other terminal is grounded. The single-pole single-throw switch is connected in series with a resistor and then connected in parallel to the two terminals of the capacitor. The capacitor is also connected to the two moving terminals of the single-pole double-throw switch, one of which is grounded via a resistor, and the voltage of the other moving terminal relative to ground is used as the output voltage of the divider circuit. The present invention implements division calculation through the circuit, which can reduce the system complexity of the analog circuit and the chip computing burden.

Description

Technical Field

[0001] The present invention relates to the field of analog control circuits, and in particular to a divider circuit based on a voltage-controlled current source and a division calculation method. Background Art

[0002] In commonly used digital or analog control circuits, in order to realize the division function, it is often necessary to use a more complex analog division circuit. If the division calculation is directly implemented using a CNC chip, the chip's computational burden will be greatly increased. At the same time, other auxiliary circuits will also need to be introduced, increasing the system complexity and hindering the reduction of system costs.

[0003] Therefore, it is necessary to propose a divider circuit with low cost, simple structure and no additional burden on the circuit to solve the above problems. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the deficiencies in the prior art and provide a divider circuit based on a voltage-controlled current source and a division calculation method.

[0005] To solve the technical problem, the solution of the present invention is:

[0006] A divider circuit based on a voltage-controlled current source is provided, which includes: a comparator Comp1, a sawtooth wave generator V s , a voltage-controlled current source I S1 , a capacitor C B , resistors R1 and R2, single-pole double-throw switch S2 and single-pole single-throw switch S1; where,

[0007] The inverting terminal of the comparator Comp1 is connected to the sawtooth wave generator V s The positive terminal of the sawtooth wave generator V s The negative terminal of the comparator Comp1 is grounded; the voltage to ground at its non-inverting terminal is the divisor voltage V den , by comparing the divisor voltage V dem and sawtooth voltage V s , generate PWM signal;

[0008] The SPDT switch S2 and SPST switch S1 are electronically controlled products. Their control terminals are connected to the output terminals of the comparator Comp1. The PWM signal is used to control the operation and on / off of the two switches. The dividend voltage V num Connected to voltage controlled current source I S1 At both ends, the voltage-controlled current source I S1 One end of the single-pole double-throw switch S2 is connected to the fixed end, and the other end is grounded; the single-pole single-throw switch S1 is connected in series with the resistor R2 and connected in parallel with the capacitor C B The two ends of the capacitor CB The two ends of the divider are connected to the two moving ends of the single-pole double-throw switch S2, one of which is grounded through the resistor R1, and the voltage of the other moving end to the ground is used as the output voltage V of the divider circuit. quo .

[0009] The present invention further provides a method for implementing division calculation using the aforementioned divider circuit, wherein the comparator Comp1 compares the divisor voltage V den and sawtooth voltage V s Generate PWM signal; PWM signal controls the action of single-pole double-throw switch S2 and single-pole single-throw switch S1, and realizes the capacitance C by controlling the on-off of the switch. B The charge and discharge of the output voltage V is output after the division calculation. quo .

[0010] As a preferred embodiment of the present invention, the specific process of implementing the division calculation in the divider circuit is as follows:

[0011] (1) When the divisor voltage V den Greater than the sawtooth voltage V s When the comparator Comp1 outputs a high-level PWM signal, the single-pole single-throw switch S1 is turned on and the capacitor C B Discharge through single-pole single-throw switch S1 and resistor R2; voltage-controlled current source I S1 The current is grounded through the single-pole double-throw switch S2 and the resistor R1;

[0012] (2) When the divisor voltage V den Less than the voltage sawtooth wave V s When the comparator Comp1 outputs a low-level PWM signal, the single-pole single-throw switch S1 is disconnected and the single-pole double-throw switch S2 is switched to the other active end. S1 Through the single-pole double-throw switch S2 and resistor R1, the capacitor C B Charge;

[0013] (3) When the divider circuit reaches a stable working state, the average current of the capacitor reaches a stable state based on the ampere-second balance principle, and finally the output voltage V quo Proportional to the dividend voltage V num Divide by the divisor voltage V den The calculated value is:

[0014] V quo =kV num / V den

[0015] Where k is a constant.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] 1. In digital or analog control circuits, division operations can consume the computing power of digital control chips. Unlike existing technologies, the present invention implements a divider circuit using a simple circuit, where the output voltage Vquo is proportional to the dividend voltage Vnum divided by the divisor voltage Vden to perform the division operation. This circuit-based division operation can reduce the system complexity of analog circuits and the chip computing burden.

[0018] 2. The circuit structure of the present invention is relatively simple, and a series of sampling circuits and AD / DA circuits can be omitted, thereby reducing circuit complexity.

[0019] 3. The present invention only requires the most basic electronic components, and the requirements for electronic components are not high. They can be easily obtained, which has positive significance for reducing system costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of the divider circuit in the present invention.

[0021] Figure 2 It is the working timing diagram of the divider circuit. DETAILED DESCRIPTION

[0022] The embodiments of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention.

[0023] like Figure 1 As shown in the figure, the voltage-controlled current source divider circuit provided in the example includes: a comparator Comp1, a sawtooth wave generator V s , a voltage-controlled current source I S1 , a capacitor C B , resistors R1 and R2, single-pole double-throw switch S2 and single-pole single-throw switch S1; where,

[0024] The inverting terminal of the comparator Comp1 is connected to the sawtooth wave generator V s The positive terminal of the sawtooth wave generator V s The negative terminal of the comparator Comp1 is grounded; the voltage to ground at its non-inverting terminal is the divisor voltage V den , by comparing the divisor voltage V den and sawtooth voltage V s , generate PWM signal;

[0025] The SPDT switch S2 and SPST switch S1 are electronically controlled products. Their control terminals are connected to the output terminals of the comparator Comp1. The PWM signal is used to control the operation and on / off of the two switches. The dividend voltage V num Connected to voltage controlled current source IS1 At both ends, the voltage-controlled current source I S1 One end of the single-pole double-throw switch S2 is connected to the fixed end, and the other end is grounded; the single-pole single-throw switch S1 is connected in series with the resistor R2 and connected in parallel with the capacitor C B The two ends of the capacitor C B The two ends of the divider are connected to the two moving ends of the single-pole double-throw switch S2, one of which is grounded through the resistor R1, and the voltage of the other moving end to the ground is used as the output voltage V of the divider circuit. quo .

[0026] Specifically, the voltage-controlled current source I S1 One output end of the single-pole double-throw switch S2 is connected to the fixed end, and the moving end of the single-pole double-throw switch S2 is connected to the resistor R1 and the capacitor C B One end of the capacitor C B The other end is also connected to the resistor R1; the capacitor C B One end connected to the SPDT switch S2 is also connected to one end of the SPST switch S1. The other end of the SPST switch S1 is connected to one end of the resistor R2. The other end of the resistor R2 is connected to the resistor R1 and the capacitor C. B One end of the resistor R1 is connected to the voltage-controlled current source I S1 The ground terminal is connected to the capacitor C B The voltage of one end connected to switches S1 and S2 to ground is used as the output voltage V of the divider circuit. quo .

[0027] like Figure 2 As shown in FIG, the specific process of the above divider circuit operation is:

[0028] When the circuit is working normally, the divisor voltage V den With sawtooth wave generator V s The sawtooth wave generated (the sawtooth wave is also V s The dividend voltage V num The voltage-controlled current source converts the current into the voltage V num A certain proportion of the current gV num , where g is the voltage-controlled current source I S1 transfer conductance.

[0029] (1) When the divisor voltage V den Greater than sawtooth wave V s When the comparator Comp1 outputs a high level, that is, the PWM signal is a high level; when the PWM signal is a high level, the capacitor C B Discharge is performed through the single-pole single-throw switch S1 and the resistor R2, while the current source I S1The current flows through the single-pole double-throw switch S2 and the resistor R1 to the ground. B The current i c and the output voltage V quo The sizes are:

[0030]

[0031] V quo =V C +gV num R1

[0032] Among them, V c Represents the voltage across the capacitor.

[0033] (2) When the divisor voltage V den Less than sawtooth wave V s When PWM is low, the comparator outputs a low level, that is, the PWM signal is low; when PWM is low, the single-pole single-throw switch S1 is disconnected, and the single-pole double-throw switch S2 and the capacitor C B connected, giving capacitor C B Charging, at this time the current flows through the capacitor C B The current and output voltage are:

[0034] i C =gV num

[0035] V out =V C +gV num R1

[0036] According to the ampere-second balance principle of capacitance, in the stable working state of the circuit, one switching cycle T s Inside, flows through capacitor C B The average current is zero:

[0037]

[0038] (<> Ts The symbol represents the switching cycle average, that is, the average value of the signal within one switching cycle)

[0039] Combining the above formula, it can be calculated that the output voltage V quo and the dividend voltage V num The relationship between them is:

[0040]

[0041] Where d represents the duty cycle of the PWM signal, d′ = 1-d; if R1 = R2 and g = 1 / R1, we can get:

[0042]

[0043] Furthermore, for the PWM signal in this embodiment, it is composed of a sawtooth wave V s and the divisor voltage V den Comparison is generated. Therefore, according to Figure 2 As shown in the waveform diagram, V sp Represents sawtooth wave V s The peak value of the PWM signal can be seen as follows:

[0044]

[0045] Combining the above formulas, we can know that:

[0046]

[0047] Because V sp is a settable constant (for ease of writing, it is rewritten as constant k), so it can be considered that the output voltage V quo Proportional to the dividend voltage V num Divide by the divisor voltage V den , thus realizing the division operation.

[0048] The specific implementation methods described above provide a detailed description of the technical solutions and beneficial effects of the present invention. It should be understood that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, supplements and equivalent substitutions made within the scope of the principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A divider circuit based on a voltage-controlled current source, characterized in that: The circuit includes: a comparator Comp1, a sawtooth wave generator V s , a voltage-controlled current source I S1 , a capacitor C B , resistors R1 and R2, single-pole double-throw switch S2 and single-pole single-throw switch S1; where, The inverting terminal of the comparator Comp1 is connected to the sawtooth wave generator V s The positive terminal of the sawtooth wave generator V s The negative terminal of the comparator Comp1 is grounded; the voltage to ground at its non-inverting terminal is the divisor voltage V den , by comparing the divisor voltage V den and sawtooth voltage V s , generate PWM signal; The SPDT switch S2 and SPST switch S1 are electronically controlled products. Their control terminals are connected to the output terminals of the comparator Comp1. The PWM signal is used to control the operation and on / off of the two switches. The dividend voltage V num Connected to voltage controlled current source I S1 At both ends, the voltage-controlled current source I S1 One end of the single-pole double-throw switch S2 is connected to the fixed end, and the other end is grounded; the single-pole single-throw switch S1 is connected in series with the resistor R2 and connected in parallel with the capacitor C B The two ends of the capacitor C B The two ends of the divider are connected to the two moving ends of the single-pole double-throw switch S2, one of which is grounded through the resistor R1, and the voltage of the other moving end to the ground is used as the output voltage V of the divider circuit. quo .

2. A method for implementing division calculation using the divider circuit according to claim 1, characterized in that: Comparator Comp1 compares the divisor voltage V den and sawtooth voltage V s Generate PWM signal; PWM signal controls the action of single-pole double-throw switch S2 and single-pole single-throw switch S1, and realizes the capacitance C by controlling the on-off of the switch. B The charge and discharge of the output voltage V is output after the division calculation. quo .

3. The method according to claim 2, characterized in that The specific process of implementing division calculation in the divider circuit is: (1) When the divisor voltage V den Greater than the sawtooth voltage V s When the comparator Comp1 outputs a high-level PWM signal, the single-pole single-throw switch S1 is turned on and the capacitor C B Discharge through single-pole single-throw switch S1 and resistor R2; voltage-controlled current source I S1 The current is grounded through the single-pole double-throw switch S2 and the resistor R1; (2) When the divisor voltage V den Less than the voltage sawtooth wave V s When the comparator Comp1 outputs a low-level PWM signal, the single-pole single-throw switch S1 is disconnected and the single-pole double-throw switch S2 is switched to the other active end. S1 Through the single-pole double-throw switch S2 and resistor R1, the capacitor C B Charge; (3) When the divider circuit reaches a stable working state, the average current of the capacitor reaches a stable state based on the ampere-second balance principle, and finally the output voltage V quo Proportional to the dividend voltage V num Divide by the divisor voltage V den The calculated value is: V quo =kV num / V den Where k is a constant.

Images