An apparatus and layout planning method for physical design layout planning

Abstract

The application provides a device and a layout planning method for physical design layout planning, and relates to the technical field of integrated circuit physical design. EDA tools can introduce various types of template macro units in the form of physical units, the arrangement of standard units in any template macro unit meets the requirements of continuous splicing at the template macro unit boundary of the wiring track and the power supply ground connection network, and the port placement position is arranged on any module boundary line, and the position of the port placement position meets the physical design rules. The application reduces the time of netlist synthesis and accelerates the operation speed of the layout and wiring tool. The change of the module level layout planning information can be synchronized at the top level and the module level. The module arrangement port work is simpler, and the port alignment work is simplified. The iteration cycle of the module level design is greatly reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit physical design, and in particular to a device and a layout planning method for physical design. Background Art

[0002] Standard cell design is a mature methodology in integrated circuit design. In practice, it is typically broken down into the following phases: netlist synthesis, floorplanning (FP), placement and optimization, clock tree generation and optimization, routing, post-routing optimization, and signoff repair. The phases from placement and optimization to post-routing optimization are referred to as the place and route (PR) phase.

[0003] As designs scale, a hierarchical design approach, often also called layered design, becomes necessary. In this approach, the top level of the chip is broken down into modules. Each higher-level module is then broken down into lower-level modules. Complete module-level design is completed within the appropriate module level, and then gradually assembled into a complete chip.

[0004] The above decomposition process is usually completed in the FP stage at the top level of the chip. The main tasks of this stage are: reading in the synthesized netlist, determining the chip's outer boundary, determining the chip's IO ring placement, determining the chip's core area boundary (the chip core area is a special term in physical design, interpreted as the "standard cell layout area"), generating the standard cell arrangement rows (Row) in the core area, generating the chip's wiring tracks (Track), generating the chip's power and ground (PG) connection network, defining and dividing the module boundaries, and placing and aligning the ports of each module.

[0005] The split module-level FP information is then provided to each module. This module-level FP information includes module boundaries, row, track, PG connection network, and module port locations. The next module-level design tasks include netlist synthesis, importing the top-level split module-level FP information, performing PR, and signoff and repair. If the top-level split module boundaries or module port locations are found to be unsuitable for implementation, adjustments are negotiated with the top-level design team. Once the top-level design team regenerates the adjusted module-level FP information, the module-level design process is repeated.

[0006] Since the development of the module level design depends on the FP information of the top layer and the splitting work, the above-mentioned repeated work not only makes the port arrangement and alignment work of the module time-consuming, but also causes the iteration cycle of the whole module level design to be longer. How to reduce the data interaction between the top layer and the module level, shorten the time consumption of the port arrangement and alignment work of the module, and reduce the iteration cycle of the module level design is a problem to be solved. SUMMARY

[0007] In view of the above problems, the present application is to provide an apparatus and a layout planning method for physical design layout planning which can overcome the above problems or at least partially solve the above problems.

[0008] The first aspect of the embodiment of the present application provides an apparatus for physical design layout planning, applied to an EDA tool, wherein the EDA tool can introduce multiple types of template macro units in the form of physical units, each type of template macro unit comprising: a standard cell arrangement row, a power ground connection network, a routing track, and a module boundary line;

[0009] The standard cell arrangement row, the routing track, and the power ground connection network in any template macro unit meet the requirement of continuous splicing at the template macro unit boundary;

[0010] The pattern of the module boundary line in any type of template macro unit is different from the pattern of the module boundary line in other types of template macro units;

[0011] A port placement site is arranged on any module boundary line, and the position of the port placement site meets the physical design rule;

[0012] The apparatus is configured to:

[0013] According to the boundary expected by the hierarchical module in the core region of the chip, the type and the number of the template macro units are selected, and the actual boundary of the hierarchical module is spliced by using the module boundary line of the selected template macro unit;

[0014] Based on the position of the port placement site of the selected template macro unit, the layout planning is performed by using the EDA tool.

[0015] Optionally, the pattern of the standard cell arrangement row, the pattern of the routing track, and the pattern of the power ground connection network in any template macro unit are centrally symmetrically distributed on the template macro unit, so that the pattern of the standard cell arrangement row, the pattern of the routing track, and the pattern of the power ground connection network remain unchanged before and after the template macro unit is flipped;

[0016] Wherein, the flipping refers to that the template macro unit is flipped along the horizontal direction, or the template macro unit is flipped along the vertical direction.

[0017] Optionally, the continuous stitching requirement includes: the pattern of the standard cell arrangement row, the pattern of the routing track, and the pattern of the power and ground connection network in any template macro cell, when the template macro cell is stitched with any other template macro cell, the pattern of the standard cell arrangement row, the pattern of the routing track, and the pattern of the power and ground connection network at the joint boundary meet the process rule requirement in the physical design, and each pattern is continuous.

[0018] Optionally, the standard cell arrangement rows in any template macro cell are arranged in back-to-back form in the template macro cell, and are even rows.

[0019] Optionally, the distance between one routing track adjacent to the boundary of the template macro cell and the boundary of the template macro cell is half of the distance between the other two adjacent routing tracks in the template macro cell.

[0020] Optionally, the two adjacent routing tracks in the template macro cell refer to two adjacent routing tracks in the template macro cell that are not adjacent to the boundary of the template macro cell.

[0021] Optionally, the number of pairs of the power and ground connection network in any template macro cell is even.

[0022] The number of pairs of the power and ground connection network is half at the boundary closest to the template macro cell, and the power and ground connection network closest to the upper and lower boundaries of the template macro cell is of the same potential, and the power and ground connection network closest to the left and right boundaries of the template macro cell is of the same potential.

[0023] Optionally, the module boundary lines in any type of template macro cell are divided into horizontal boundary lines and vertical boundary lines.

[0024] All the horizontal boundary lines are equidistant from the horizontal center line of the template macro cell.

[0025] All the vertical boundary lines are equidistant from the vertical center line of the template macro cell.

[0026] The distance is adjusted according to the requirements of the physical design.

[0027] Optionally, the port placement positions in the same type of template macro cell have unique numbers, and the relative relationship between different unique numbers in the same type of template macro cell is recorded.

[0028] All the port placement positions are on the routing tracks, and the distance between one port placement position and the adjacent port placement position is equal to the distance between the two adjacent routing tracks.

[0029] If any of the port placement bit positions conflict with the routing of the power ground network, the port placement bit positions cannot be placed.

[0030] Optionally, the unique numbers corresponding to the different port placement bit positions in each template macro unit are different, so that there are multiple groups of unique numbers in each template macro unit.

[0031] If the numbers in any two groups of the multiple groups of unique numbers are the same, the two placement bit positions corresponding to the same numbers are the aligned positions between the two hierarchical modules.

[0032] Optionally, the device is configured to:

[0033] According to the area requirement of the hierarchical module in the chip core region, a certain number of template macro units of several types are selected to splice the chip core region.

[0034] Based on the chip core region, the template macro units at different positions are replaced according to the expected boundary routing of the hierarchical module.

[0035] Optionally, the device is further configured to:

[0036] According to the position and side length of the selected template macro unit, the boundary coordinates of the hierarchical module are determined, and then converted into top-level coordinates of the top-level coordinate system of the chip.

[0037] According to the top-level coordinates corresponding to the boundary coordinates of the hierarchical module, a cutting operation is performed.

[0038] After the cutting operation is completed, according to the top-level coordinates corresponding to the boundary coordinates of the hierarchical module, the unique number of each template macro unit in the selected template macro unit, and the unique number of the port placement bit in each template macro unit, the top-level coordinates of each port in the hierarchical module are obtained, and the top-level coordinates of each port in the hierarchical module are converted into a recognizable file of the EDA tool and imported into the EDA tool.

[0039] Optionally, the device is configured to:

[0040] According to the top-level coordinates corresponding to the boundary coordinates of the hierarchical module, the top-level coordinates corresponding to the line segments of each boundary in the hierarchical module are determined.

[0041] According to the top-level coordinates corresponding to the line segments of each boundary in the hierarchical module, the top-level coordinates corresponding to the vertices of each boundary in the hierarchical module are determined.

[0042] The top-level coordinates corresponding to the vertices of each boundary are imported into a layout routing tool to obtain a boundary definition of the hierarchical module.

[0043] The boundary definition is imported into the EDA tool for a cutting operation.

[0044] Optionally, the device is configured to:

[0045] The position of each port in the hierarchical module is arranged in combination with the top coordinates of each port in the hierarchical module.

[0046] The position of the port to be aligned is found in a template macro unit;

[0047] The unique identifier of the port in another template macro unit to be aligned with the port to be aligned is obtained by querying the unique identifier of the port to be aligned;

[0048] The top coordinates of the port in the other template macro unit are obtained according to the unique identifier of the port in the other template macro unit;

[0049] The port alignment operation is performed according to the top coordinates of the port to be aligned and the top coordinates of the port in the other template macro unit.

[0050] The second aspect of the embodiment of the application provides a layout planning method applied to an EDA tool, which can introduce various types of template macro units in the form of physical units, and each type of template macro unit includes: a standard cell arrangement row, a power ground connection network, a routing track, and a module boundary line.

[0051] The standard cell arrangement row, the routing track, and the power ground connection network in any template macro unit meet the requirement of continuous splicing at the template macro unit boundary, the pattern of the module boundary line in any type of template macro unit is different from the pattern of the module boundary line in other types of template macro units, a port placement site is arranged on any module boundary line, and the position of the port placement site meets the physical design rule.

[0052] The layout planning method includes:

[0053] According to the expected boundary of the hierarchical module in the core region of a chip, the type and number of template macro units are selected, and the actual boundary of the hierarchical module is spliced by using the module boundary line of the selected template macro unit.

[0054] Based on the position of the port placement site of the selected template macro unit, the EDA tool is used for layout planning.

[0055] Optionally, according to the expected boundary of the hierarchical module in the core region of a chip, the type and number of template macro units are selected, and the actual boundary of the hierarchical module is spliced by using the module boundary line of the selected template macro unit, which includes:

[0056] According to the area requirement of the hierarchical module in the chip core region, a certain number and several types of template macro units are selected to splice the chip core region;

[0057] Based on the chip core region, different positions of the template macro units are replaced according to the expected boundary routing of the hierarchical module.

[0058] Optionally, before the layout planning by the EDA tool, the method further comprises:

[0059] According to the position and side length of the selected template macro unit, the boundary coordinates of the hierarchical module are determined, and then converted into top-level coordinates of the top-level coordinate system of the chip;

[0060] According to the top-level coordinates corresponding to the boundary coordinates of the hierarchical module, a cutting operation is performed;

[0061] After the cutting operation, according to the top-level coordinates corresponding to the boundary coordinates of the hierarchical module, the unique number of each template macro unit in the selected template macro unit, and the unique number of the port placement bit in each template macro unit, the top-level coordinates of each port in the hierarchical module are obtained, and the top-level coordinates of each port in the hierarchical module are converted into a recognizable file of the EDA tool and imported into the EDA tool.

[0062] Optionally, according to the top-level coordinates corresponding to the boundary coordinates of the hierarchical module, the cutting operation comprises:

[0063] According to the top-level coordinates corresponding to the boundary coordinates of the hierarchical module, the top-level coordinates corresponding to the line segments of each boundary in the hierarchical module are determined;

[0064] According to the top-level coordinates corresponding to the line segments of each boundary in the hierarchical module, the top-level coordinates corresponding to the vertices of each boundary in the hierarchical module are determined;

[0065] The top-level coordinates corresponding to the vertices of each boundary are imported into a layout and routing tool to obtain a boundary definition of the hierarchical module;

[0066] The boundary definition is imported into the EDA tool to perform a cutting operation.

[0067] Optionally, the layout planning by the EDA tool comprises:

[0068] In combination with the top-level coordinates of each port in the hierarchical module, the positions of each port in the hierarchical module are arranged;

[0069] In a template macro unit, the position of the port to be aligned is found;

[0070] By the unique number of the port needing alignment, the unique number of the port in another template macro cell aligning with the port needing alignment is queried;

[0071] According to the unique number of the port in the another template macro cell, the top coordinates of the port in the another template macro cell are obtained;

[0072] According to the top coordinates of the port needing alignment and the top coordinates of the port in the another template macro cell, a port alignment operation is performed.

[0073] The device for physical design layout planning provided by the application is applied to an EDA tool, which can introduce various types of template macro cells in the form of physical units, each type of template macro cell including Row, PG connection network, Track and module boundary line; Row, PG connection network and Track in any template macro cell meet the requirement of continuous splicing at the boundary of the template macro cell; the pattern of the module boundary line in any type of template macro cell is different from that in other types of template macro cells. In this way, the various types of template macro cells can be selected in use according to the expected boundary of the hierarchical module and the different patterns of the module boundary line, so that the selected template macro cells are connected to each other to form a closed loop by using the respective module boundary lines, and the actual boundary of the hierarchical module is spliced.

[0074] Since the hierarchical module is spliced by various types and quantities of template macro cells, the top layer and the module level design use the same template macro cells, and only a small amount of data interaction is needed to determine the changes of both. Each template macro cell has Row, Track, PG connection network and other elements, and the template macro cell is introduced into the PR tool as a physical unit, so that the top layer design does not need to read the netlist after synthesis when entering the FP stage, the time of netlist synthesis is reduced, and the running speed of the PR tool is accelerated.

[0075] More importantly, since the top layer design and the module level design use the same MBTM, each template macro cell has Row, Track, PG connection network and other elements, therefore, the FP information obtained by the module level through self modification is completely consistent with the FP information obtained by the top layer design, so that the change of the module level FP information can be synchronized at the top layer and the module level. The iteration cycle of the module level design is reduced.

[0076] In addition, the port placement positions are arranged on the module boundary line, the positions of the port placement positions satisfy the physical design rule, and the port placement positions have unique numbers in the same type of template macro cell, and the relative relationship between different numbers is recorded in the same type of template macro cell. Since the template macro cell contains the legal positions of the ports on the module boundary, the number of these positions is much less than the number of positions when the ports are freely arranged. This makes the work of arranging the ports of the key module simpler on the one hand - only the position number of the port needs to be specified, without the need to deal with the legality of its placement; on the other hand, the port alignment work is simplified - since the corresponding relationship of the port positions between the modules has been recorded in the template macro cell, the port position of the other party can be quickly converted into the port position of the self, and the two parties only need to interact the unique number of the template macro cell and the unique number of the port position in the template macro cell. The time-consuming of the port arrangement and alignment of the module is shortened, and the iteration cycle of the module level design is further reduced.

[0077] In summary, the device of the present application proposes a template macro cell that can be used to standardize FP information. The template macro cell contains FP information and standardizes the module boundary and the port position of the module, so that the template macro cell can be flexibly spliced. The data interaction between the top level and the module level is reduced, so that the change of the module level FP information can be synchronized between the top level and the module level, the time-consuming of the port arrangement and alignment of the module is shortened, and the iteration cycle of the module level design is greatly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0078] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0079] Figure 1 Fig. 1A, 1B and 1C are structural schematic diagrams of a preferred template macro cell layout Row, Track and PG wiring network according to an embodiment of the present application;

[0080] Figure 2 Fig. 2 is a structural schematic diagram of a preferred template macro cell layout module boundary line according to an embodiment of the present application;

[0081] Figure 3 Fig. 3 is a structural schematic diagram of a preferred template macro cell layout port placement position according to an embodiment of the present application;

[0082] Figure 4 Fig. 4 is a structural schematic diagram of 17 types of template macro cells according to a module boundary line according to an embodiment of the present application;

[0083] Figure 5 Exemplary shows the chip structure schematic diagram which is spliced out by 8 types, 24 template macro units according to the boundary of three hierarchical modules in the embodiment of the application. DETAILED DESCRIPTION

[0084] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are some but not all of the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the application.

[0085] The inventor finds that the current module level design depends on the top FP information and the splitting work, and the repeated work mode proposed in the background art not only takes a long time for the module port arrangement and alignment work, but also takes a long iteration cycle for the whole module level design.

[0086] The inventor further finds that there are two methods known to solve the above problems:

[0087] 1) The automatic module boundary adjustment optimization and module port alignment function is provided by the electronic design automation (Electronic design automation, EDA for short) tool. The working steps are as follows: reading in the netlist after synthesis, setting and generating the core area boundary, Row, Track and PG connection network, setting some modules as to-be-split modules, pre-layout routing, module boundary adjustment optimization, splitting modules, module port arrangement and alignment. Among them, the pre-layout routing, module boundary adjustment optimization, splitting modules, and module port arrangement and alignment are automatically completed by the tool. However, the prerequisite for the tool to automatically complete the module port arrangement and alignment is to complete the pre-layout routing. It should be noted that the pre-layout routing and the module boundary adjustment optimization are automatically completed by the tool, which still needs running time.

[0088] 2) Since the module level FP information automatically generated by the EDA tool in the above technical 1) has great randomness, it is not conducive to the continuous optimization of the module level design. Therefore, the second method is that in actual work, the designer will manually specify the boundary of the module according to experience, and the working steps in the above technical 1) can omit the two steps of "pre-layout routing" and "module boundary optimization", thereby speeding up the progress of the FP stage.

[0089] Meanwhile, the designer will prioritize the needs of the key modules (usually the timing more nervous modules) for the port position. That is, first arrange the port in the key module, and then adjust the port of other modules on the top layer to align with it. Compared with the above technique 1), the module-level FP information obtained by technique 2) has better continuity, which is beneficial to the module-level design optimization work to some extent.

[0090] However, the inventors have found again after in-depth research that in the above technique 1), when the input netlist changes, not only the boundary shape of the module will change, but also the relative position between the modules will change, thereby causing a large change in the module port arrangement. For the module-level design, the change of the module shape and the port has a great impact on the design progress. More seriously, if it is found in the subsequent work that the module boundary or the port needs to be adjusted, it is necessary to return to the top layer to make adjustments and re-subdivision. The above iteration process is "serial", that is, the module-level design needs to wait for the top layer to re-do the FP and subdivision before starting a new round of work, which will seriously delay the work progress when repeated iterations occur.

[0091] A more pessimistic situation is that the module-level design starts earlier than the overall chip design, which is a common situation in actual work. The module needs to generate module-level FP information by itself to start physical design. However, since the module does not know the positional relationship between itself, the whole chip and the adjacent module (if any) at the beginning of the design, the FP information generated by the module itself will be more different from the FP information obtained by the top layer subdivision, and the number of repeated iterations will be more, which will seriously lengthen the iteration cycle of the module-level design.

[0092] As for technique 2), although the module-level FP information obtained has better continuity, which is beneficial to the module-level design optimization work to some extent. However, technique 2) introduces more manual work in the implementation process. Technique 2) omits pre-layout routing and module boundary adjustment optimization, thereby reducing the tool running time, but also leading to the fact that the module port arrangement and alignment cannot be automatically run by the tool, and manual operation is needed. The port arrangement of the key module and the port alignment between the modules all need to spend a lot of time. On the one hand, it is because the number of ports that need to be placed manually is large, and on the other hand, the boundary conditions (mainly referring to the network routing conditions of the PG connection) between two modules are different.

[0093] In addition, there are not many restrictions in the above manual work process. The module-level cannot accurately estimate the changes brought by the top layer adjustment, so the work of the top layer and the module-level still needs to be "serially" carried out. If repeated iterations occur, the impact on the design progress will still be great, and the iteration cycle of the module-level design will also be delayed.

[0094] In view of the above problems, the inventors have creatively proposed the device for physical design layout planning of the present application after a large number of designs, researches and tests, which well solves the above problems. The device of the present application is described in detail below.

[0095] The device for physical design layout planning of the present application comprises a plurality of types of template macro units, each type of template macro unit comprising a standard cell arrangement row, a power ground connection network, a routing track and a module boundary line. The standard cell arrangement row, the power ground connection network and the routing track in the template macro unit can be designed according to the rules of the standard cell design method. The shape of the template macro unit can be designed as a rectangle, of course, other shapes can also be designed, but the shape of the template macro unit needs to be a shape that is convenient for splicing, such as a rectangle, a square, a diamond, a hexagon, an octagon, etc. Circular and elliptical shapes are not convenient for splicing, so they are not suitable.

[0096] For any template macro unit, the standard cell arrangement row, the routing track and the power ground connection network arranged thereon meet the requirement of continuous splicing at the boundary of the template macro unit. That is, for the three elements of Row, Track and PG connection network, when arranged on each template macro unit, they need to be centrally symmetrically distributed and meet the requirement of continuous splicing at the boundary of the template macro unit. The specific pattern, arrangement method and number can be determined according to actual needs, as long as the above conditions are met.

[0097] In order to facilitate splicing and standardize the boundary line, different types of template macro units need to be designed. For any type of template macro unit, the pattern of the module boundary line arranged thereon is different from that of the module boundary line in other types of template macro units, which can meet the demand of different hierarchical module boundary routing. According to the structure of the known integrated circuit chip, 17 types of template macro units are designed, which can meet the demand of different hierarchical module boundary routing.

[0098] For the arrangement of ports, port placement positions are arranged on any module boundary line. The positions of these port placement positions need to meet the physical design rules, and each port placement position has a unique number in the same type of template macro unit, and the relative relationship between different numbers and port placement positions is recorded in the same type of template macro unit. This lays a foundation for subsequent port arrangement and alignment.

[0099] In the actual use of the template macro units of various types, according to the traces of the expected boundaries of the hierarchical module and the module boundary lines of different patterns, the type and number of the template macro units are selected so that the selected template macro units are connected with each other by the respective module boundary lines to form a closed loop and splice the actual boundary of the hierarchical module. The hierarchical module is an actually existing module in the chip code, and the designer who is usually responsible for the layout planning has an expectation for the shape of the hierarchical module according to experience. The process of using the template macro units is a process of splicing the expected shape of the hierarchical module by using the template macro units.

[0100] Since the type of the template macro unit of the present application is mainly determined by the different module boundary line patterns arranged thereon, the template macro unit can be called a module boundary template macro unit, which can be translated into Module Boundary Template Macro (MBTM) in English.

[0101] In combination with the above design, since the hierarchical module is spliced by template macro units of various types and numbers, after the top-level personnel splice the shape of the hierarchical module by using the template macro units, the module design personnel is informed of the type of the template macro units used and how to arrange the template macro units. The module design personnel can easily understand the shape of the module and some details (such as ROW, Track, PG network, etc.) in the module are also determined following the template macro units. In this way, the top-level and module-level designs use the same template macro units, and only a small amount of data interaction is required to determine the changes of both. Each template macro unit has Row, Track, PG connection network elements, and the template macro unit is introduced into the PR tool as a physical unit. Therefore, the top-level design does not need to read the netlist after synthesis when entering the FP stage, which reduces the time of netlist synthesis and speeds up the running speed of the PR tool.

[0102] More importantly, since the top-level and module-level designs use the same template macro units, and each template macro unit has Row, Track, PG connection network elements, the FP information obtained by the module-level through self-modification is completely consistent with that obtained by the top-level design division, so that the changes of the module-level FP information can be synchronized at the top-level and module-level. The iteration cycle of the module-level design is reduced.

[0103] In addition, the module boundary line is arranged with port placement positions, the positions of the port placement positions satisfy the required rules of physical design, and the port placement positions have unique numbers in the same type of template macro cell, and the relative relationship between different numbers is recorded in the same type of template macro cell. Since the template macro cell contains the legal positions of the ports on the module boundary, the number of these positions is much less than the number of positions when the ports are freely arranged. This makes the port arrangement of the key module simpler on the one hand, and simplifies the port alignment work on the other hand. Shortening the port arrangement and alignment work of the module further reduces the iteration cycle of the module level design, and the changes of the integrated module level FP information can be synchronized at the top level and the module level, thereby greatly reducing the iteration cycle of the module level design as a whole.

[0104] For the standard cell arrangement row, the wiring track, and the power and ground connection network, the requirement is that they are centrally symmetrically distributed on the template macro cell. The most important standard is that the pattern of the standard cell arrangement row, the pattern of the wiring track, and the pattern of the power and ground connection network in any template macro cell remain unchanged before and after the template macro cell is flipped, and the patterns are completely consistent; wherein, the flipping refers to that the template macro cell is flipped along the horizontal direction, or the template macro cell is flipped along the vertical direction. That is, for each template macro cell, whether it is flipped along the horizontal direction or along the vertical direction, the patterns of the three elements of Row, Track, and PG connection network arranged thereon are completely consistent before and after the flipping.

[0105] If the standard cell arrangement row, the wiring track, and the power and ground connection network are not centrally symmetrically distributed on the template macro cell (all of them are in the form of pattern in the EDA tool, so the description of the patterns of the three elements below is essentially the three elements themselves), the standard cell arrangement row, the wiring track, and the power and ground connection network cannot remain unchanged before and after the template macro cell is flipped, and the patterns are completely consistent, then a large number of template macro cells of different types may be needed to meet the subsequent splicing requirements. Therefore, the optimal distribution mode is that the standard cell arrangement row, the wiring track, and the power and ground connection network are centrally symmetrically distributed on the template macro cell.

[0106] For the standard cell rows, the routing tracks and the power ground net, the most important criterion for the requirement of the continuous stitching at the template macro cell boundary is that the pattern of the standard cell rows, the pattern of the routing tracks and the pattern of the power ground net in any template macro cell are continuous at the boundary when the template macro cell is stitched with any other template macro cell, and each pattern is continuous (for example, the pattern of two routing tracks is continuous, which means that the two routing tracks are continuous). In addition, the template macro cell or any other template macro cell can be flipped before being stitched. The main purpose of flipping the template macro cell before being stitched is to reduce the number of template macro cell types, because it is time-consuming and laborious to maintain a set of template macro cells, and the less the number of template macro cell types, the easier it is to maintain. It should be noted that the power ground net generally refers to a metal mesh composed of regular connection of high level (usually about 1.0V) and low level (usually ground).

[0107] To achieve the above requirements, there are many ways to arrange the Row, Track and PG net. For example, a relatively optimal Row arrangement is that the standard cell rows in any template macro cell are arranged in back-to-back form and are even rows in the template macro cell. Generally, the Row is divided into upper and lower, and the back-to-back form means that the upper of one Row is connected to the upper of another Row, and the lower of the one Row is connected to the lower of a third Row.

[0108] A relatively optimal Track arrangement is that the distance between the adjacent Track and the template macro cell boundary is half the distance between the other two adjacent Tracks in the template macro cell. The other two adjacent Tracks in the template macro cell refer to the two Tracks in the template macro cell that are not adjacent to the template macro cell boundary. Such an arrangement ensures that the distance between any two adjacent Tracks is the same after the template macro cells are stitched.

[0109] A relatively optimal PG net arrangement is that the power ground net in any template macro cell has an even number of pairs of lines (i.e., two lines), and the line closest to the boundary of the template macro cell is half a pair of lines (i.e., one line). In addition, the lines closest to the upper and lower boundaries of the template macro cell are of the same potential, and the lines closest to the left and right boundaries of the template macro cell are of the same potential.

[0110] Reference Figure 1Fig. 1A, 1B, 1C, exemplary show a preferred structure of the Row, Track, PG routing network of the template macro unit of the embodiment of the present application. In which, Figure 1 Fig. 1A shows a preferred structure of the Row of the template macro unit, Figure 1 Fig. 1B shows a preferred structure of the Track of the template macro unit, Figure 1 Fig. 1C shows a preferred structure of the PG routing network of the template macro unit. Figure 1 In Fig. 1A, the outer frame 1 represents the template macro unit, the rectangle surrounded by the solid line 2 represents the Row, and the arrow 2 points to the outer frame of the Row; the Row is arranged in back-to-back form and is an even number of rows.

[0111] Figure 1 In Fig. 1B, the dashed line 3 represents the Track, and it should be noted that the Track is not only arranged in the horizontal direction, but also needs to be arranged in the vertical direction, Figure 1 In Fig. 1B, the Track in the vertical direction is not shown for simplicity of illustration. Figure 1 In Fig. 1B, the uppermost 3 represents a routing track adjacent to the upper boundary of the template macro unit, and the spacing between the routing track 3 and the upper boundary is half the spacing between any two routing tracks that are not adjacent to the boundary of the template macro unit, so that when another template macro unit is spliced above the template macro unit, the spacing between the routing track 3 and the routing track closest to the lower boundary of the other template macro unit is the same as the spacing between any two routing tracks that are not adjacent to the boundary of the template macro unit.

[0112] Figure 1 In Fig. 1C, 4 represents the routing of the PG routing network arranged, and the routing of the PG routing network that is not adjacent to the four boundaries of the template macro unit is an even number of pairs, and the routing of the PG routing network adjacent to the four boundaries (upper, lower, left, and right boundaries) of the template macro unit is half a pair of routing. Figure 1The uppermost 15 in C represents the traces of the PG wire network adjacent to the upper boundary of the template macro cell, and the number of the traces of the PG wire network is one, the uppermost 4 represents the traces of the PG wire network not adjacent to the boundary of the template macro cell, and the number of the traces of the PG wire network is two, forming a trace pair; similarly, the leftmost 15 represents the traces of the PG wire network adjacent to the left boundary of the template macro cell, and the number of the traces of the PG wire network is also one half of a trace pair, and the number of the traces of the PG wire network of the rest is even, i.e. one trace pair. Thus, when the second template macro cell is spliced above the template macro cell, and when the third template macro cell is spliced to the left of the template macro cell, the traces 4 of the PG wire network form an even pair with the traces of the PG wire network closest to the lower boundary in the second template macro cell, and form an even pair with the traces of the PG wire network closest to the right boundary in the third template macro cell. In addition, in order to ensure the correct splicing, the traces of the PG wire network closest to the upper and lower boundaries of the template macro cell are set to the same potential, and the traces of the PG wire network closest to the left and right boundaries of the template macro cell are set to the same potential.

[0113] The template macro cell takes the pattern of the module boundary line as the standard for type classification, and the pattern of the module boundary line of the template macro cell of the same type is the same. The module boundary line in any template macro cell is divided into horizontal boundary lines and vertical boundary lines, and in order to ensure the correct subsequent splicing, a more preferred module boundary line setting mode is that: the distance of all horizontal boundary lines from the horizontal center line of the template macro cell is equal; the distance of all vertical boundary lines from the vertical center line of the template macro cell is equal; and this distance can be adjusted according to the needs of physical design.

[0114] Referring to Figure 2 , an exemplary preferred template macro cell structure diagram for setting the module boundary line is shown. Figure 2 All horizontal boundary lines in C are represented by 5, and the distance of all horizontal boundary lines from the horizontal center line 6 of the template macro cell is equal. All vertical boundary lines are represented by 7, and the distance of all vertical boundary lines from the vertical center line 8 of the template macro cell is equal.

[0115] The arrangement and alignment of hierarchical module ports are key parts in physical design layout planning. In order to arrange the ports and align the boundaries subsequently, a relatively optimal setting is that all port placement positions are arranged on the wiring tracks, and the distance between a port placement position and an adjacent port placement position is equal to the distance between two adjacent wiring tracks. Considering that the positions of the port placement positions may conflict with the wiring of the PG connection network, the position of any port placement position should be avoided if it conflicts with the wiring of the power supply and ground connection network. Since there may be different port placement positions in each template macro unit, the unique numbers corresponding to different port placement positions are different, so that there are multiple groups of unique numbers in each template macro unit. If the numbers in any two groups of unique numbers are the same, the two placement positions corresponding to the same numbers are the alignment positions between two hierarchical modules.

[0116] Referring to Figure 3 , an exemplary structure diagram of a preferred template macro unit for arranging port placement positions is shown. Figure 3 In the diagram, 9, 10 and 11 represent different port placement positions. In the template macro unit, each different port placement position has a unique number, and the relative relationship between different groups of unique numbers is recorded. For example, 9C1-9C9 represent the part of the first port placement position on the horizontal boundary line, and 11A1-11A20 represent the second port placement position. The placement positions with the same numbers in the two groups of unique numbers are the alignment positions between two hierarchical modules, and the port alignment is achieved.

[0117] In the device of the present application, 17 types of template macro units are designed according to the shapes of the current chip and each hierarchical module, so as to realize the splicing of the template macro units according to the boundary line wiring of the hierarchical module. Referring to Figure 4 , exemplary structure diagrams of the 17 types of template macro units according to the module boundary line are shown. Each type of template macro unit is named with different numbers, such as 0000, 1111, 1000, etc. The wiring of Row, Track and PG connection network in each type of template macro unit is completely consistent. Figure 4 In the diagram, the wiring of Row, Track and PG connection network is not shown for simplicity, and only the module boundary line is shown. The solid line in the inside of the template macro unit represents the module boundary line of the template macro unit, except for the 0000 type of template macro unit. The 0000 type of template macro unit does not have a module boundary line.

[0118] Referring to Figure 5, exemplary shows the chip structure schematic diagram which is spliced out by 8 types, 24 template macro units according to the boundary of three hierarchical modules in the embodiment of the application, wherein 3 0000 type template macro units, 4 1000 type template macro units, 5 1200 type template macro units, 4 0120 type template macro units, 3 1100 type template macro units, 3 1123 type template macro units, 1 1121 type template macro unit and 1 2121 type template macro unit are used. Figure 5 The patterns surrounded by the middle line segments 12, 13 and 14 are the boundaries of the three hierarchical modules A, B and C respectively.

[0119] According to the above explanation and description, in a possible embodiment, the device for physical design layout planning is configured as follows:

[0120] According to the area requirement of the hierarchical module in the chip core region, a certain number of template macro units of several types are selected to splice the chip core region; and then based on the chip core region, the template macro units in different positions are replaced according to the expected boundary routing of the hierarchical module.

[0121] Preferably, the device for physical design layout planning is further configured as follows:

[0122] According to the position and length of the selected template macro unit, the boundary coordinates of the hierarchical module are determined, and then converted into top layer coordinates of the top layer coordinate system of the chip;

[0123] According to the top layer coordinates corresponding to the boundary coordinates of the hierarchical module, the cutting operation is performed;

[0124] After the cutting operation is completed, according to the top layer coordinates corresponding to the boundary coordinates of the hierarchical module, the unique number of each template macro unit in the selected template macro unit and the unique number of the port placement bit in each template macro unit, the top layer coordinates of each port in the hierarchical module are obtained, and the top layer coordinates of each port in the hierarchical module are converted into an identifiable file of the EDA tool and imported into the EDA tool.

[0125] Preferably, the device for physical design layout planning is configured as follows:

[0126] According to the top layer coordinates corresponding to the boundary coordinates of the hierarchical module, the top layer coordinates corresponding to the line segments of each boundary in the hierarchical module are determined;

[0127] According to the top layer coordinates corresponding to the line segments of each boundary in the hierarchical module, the top layer coordinates corresponding to the vertices of each boundary in the hierarchical module are determined;

[0128] The top layer coordinates corresponding to the vertices of each boundary are imported into the layout routing tool to obtain the boundary definition of the hierarchical module.

[0129] The boundary definition is imported into an EDA tool to perform a cutting operation.

[0130] Preferably, the device for physical design layout planning is configured as follows:

[0131] The positions of the ports in the hierarchical module are arranged in combination with the top coordinates of the ports in the hierarchical module.

[0132] The position of the port to be aligned is found in a template macro cell.

[0133] The unique identifier of the port in another template macro cell to be aligned with the port to be aligned is obtained by querying the unique identifier of the port to be aligned.

[0134] The top coordinates of the port in the other template macro cell are obtained according to the unique identifier of the port in the other template macro cell.

[0135] Finally, the port alignment operation is performed according to the top coordinates of the port to be aligned and the top coordinates of the port in the other template macro cell.

[0136] Based on the device for physical design layout planning, the embodiment of the present application further provides a layout planning method, which is applied to an EDA tool capable of introducing various types of template macro cells in the form of physical cells. Each type of template macro cell includes a standard cell arrangement row, a power ground connection network, a routing track, and a module boundary line.

[0137] The standard cell arrangement row, the routing track, and the power ground connection network in any template macro cell meet the requirement of continuous splicing at the boundary of the template macro cell. The pattern of the module boundary line in any type of template macro cell is different from the pattern of the module boundary line in other types of template macro cells. A port placement site is arranged on any module boundary line, and the position of the port placement site meets the physical design rule.

[0138] The layout planning method includes the following steps.

[0139] Step S1: According to the expected boundary of the hierarchical module in the core region of the chip, the type and number of template macro cells are selected, and the module boundary lines of the selected template macro cells are spliced to obtain the actual boundary of the hierarchical module.

[0140] First, introduce multiple types of template macro cells into the layout and routing tool in the form of physical units; that is, introduce all types of template macro cells as physical units into the PR tool in this form, for example: a feasible way is to use the LEF format file to describe the template macro cell, and introduce all types of template macro cells into the PR tool in the form of physical units. The advantage of introducing physical units is that it can be independent of the logical netlist. Because according to the traditional method: the PR tool needs to input a logical netlist before starting the "layout planning" step, but the generation of this logical netlist needs a long time. Using physical units can allow the designer to start "layout planning" in advance, in parallel with the logical netlist generation stage, saving design time.

[0141] Then, according to the area requirement of the hierarchical module in the chip core area, select a certain number of template macro cells of several types to splice out the chip core area.

[0142] For example: according to the chip area requirement, 4 1000 type template macro cells and a certain number of 0000, 0120, and 1200 type template macro cells can be used to splice out the initial chip core area, and during the splicing process, the 0120 and 1200 type template macro cells may need to be vertically or horizontally flipped.

[0143] Then, based on the chip core area, according to the expected boundary routing of the hierarchical module and the module boundary lines of different patterns, replace the template macro cells at different positions with appropriate types, so as to finally select the appropriate types and quantities of template macro cells, and use the selected template macro cells to form a closed loop by connecting each other to form the actual boundary of the hierarchical module.

[0144] For example, as shown in the structure diagram of Figure 5 According to the actual boundary routing of the three hierarchical modules A, B, and C, and in combination with the module boundary lines of different patterns in different types of template macro cells, replace the template macro cells at different positions with appropriate types, and finally select the types and quantities of template macro cells. It can be understood that during the process of splicing out the chip core area or the actual boundary of the hierarchical module, the template macro cells used need to be horizontally flipped or vertically flipped according to the actual splicing requirement.

[0145] In addition, after selecting the types and quantities of template macro cells, a certain rule (which can be the currently known rule) is used to number the selected template macro cells, to obtain the unique number of each selected template macro cell. One possible numbering rule is to number by row-column number, to provide a basis for subsequent port arrangement and alignment.

[0146] After step S1 and before step S2, the boundary coordinates of the hierarchical module need to be determined based on the position and side length of the selected template macro unit, and then converted into top-level coordinates in the chip's top-level coordinate system. For example, the coordinates of the hierarchical module boundary line in the template macro unit plus the coordinates of the template macro unit's origin in the full chip will be the coordinates of the hierarchical module boundary line in the chip's top-level coordinate system.

[0147] Since the position and side length of each template macro unit are known, the coordinates of the module boundary can be converted into the coordinates of the chip top-level coordinate system through simple conversion.

[0148] Perform segmentation based on the top-level coordinates corresponding to the boundary coordinates of the hierarchical module. The specific method is:

[0149] According to the top-level coordinates corresponding to the boundary coordinates of the hierarchical module, the top-level coordinates corresponding to the line segments of each boundary in the hierarchical module are determined. Then, according to the top-level coordinates corresponding to the line segments of each boundary in the hierarchical module, the top-level coordinates corresponding to the vertices of each boundary in the hierarchical module are determined. The top-level coordinates corresponding to the vertices of each boundary are then imported into the layout and routing tool to obtain the boundary definition of the hierarchical module.

[0150] For example, Figure 5 Taking the structural diagram shown in the figure as an example, the top-level coordinates corresponding to the boundary coordinates of hierarchical module A are used to determine the top-level coordinates corresponding to the line segments 12 (horizontal and vertical segments) of each boundary in hierarchical module A. Based on the top-level coordinates corresponding to the line segments 12 of each boundary in hierarchical module A, the top-level coordinates corresponding to the vertices of each boundary in hierarchical module A are determined. The top-level coordinates corresponding to each boundary vertex are then imported into the PR tool to obtain the boundary definition of hierarchical module A. The remaining hierarchical modules B and C are processed in the same manner. Finally, the boundary definition is imported into the electronic design automation tool (EDA tool) for segmentation.

[0151] After the splitting operation is completed, the top-level coordinates of each port in the hierarchical module are obtained according to the top-level coordinates corresponding to the boundary coordinates of the hierarchical module, the unique number of each template macro unit in the selected template macro unit, and the unique number of the port placement position in each template macro unit. The top-level coordinates of each port in the hierarchical module are converted into a file that can be recognized by the EDA tool and imported into the EDA tool.

[0152] Step S2: Based on the position of the port placement of the selected template macro unit, use EDA tools to perform layout planning. The specific method is:

[0153] The positions of the ports in the hierarchical module are arranged according to the top coordinates of the ports. Since each port in the template macro unit has a unique number, the position of each port can be represented by the unique number of the template macro unit + the unique number of the port placement site. According to the position of the template macro unit, the flip situation and the relative position of the unique number of the port placement site in the template macro unit, the specific top coordinates of the ports in the hierarchical module can be obtained through simple conversion, so as to conveniently arrange the positions of the ports.

[0154] For port alignment, the following method is used:

[0155] The position of the port to be aligned is found in a template macro unit; the unique number of the port to be aligned is used to query the unique number of the port in another template macro unit to be aligned with the port to be aligned; the top coordinates of the port in the other template macro unit are obtained according to the unique number of the port in the other template macro unit; and the port alignment operation is performed according to the top coordinates of the port to be aligned and the top coordinates of the port in the other template macro unit.

[0156] Since the port alignment operation is generally performed in the same template macro unit, the unique number of the port to be aligned can be easily obtained by querying the unique number of the port to be aligned, so as to obtain the unique number of the other template macro unit after alignment + the unique number of the aligned port, and then the specific top coordinates of the aligned port can be obtained through the above conversion, and finally the port alignment operation is performed based on the top coordinates of the two aligned ports.

[0157] It should be noted that the template macro units and elements, module boundary lines and the like shown in the above description and illustrations are exemplary examples, and do not represent the proportions and quantities in the actual design.

[0158] Through the above examples, the device for physical design layout planning of the application is used. Since the hierarchical module is composed of a plurality of types and a plurality of numbers of template macro units, the same template macro unit is used for top-level and module-level design, and only a small amount of data interaction is required to determine the changes of both. Each template macro unit has Row, Track, PG and other elements, and the template macro unit is introduced into the PR tool as a physical unit, so that the top-level design does not need to read the netlist after synthesis when entering the FP stage, reducing the time of netlist synthesis and speeding up the operation of the PR tool.

[0159] More importantly, since the same template macro cell is used in the top-level and module-level designs, each template macro cell has Row, Track, PG, and other elements, so the FP information obtained by the module-level modification is consistent with the FP information obtained by the top-level design, and the module-level FP information can be changed synchronously in the top-level and module-level designs, which reduces the iteration period of the module-level design.

[0160] In addition, the module boundary line is arranged with port placement positions, the port placement positions meet the rules required by physical design, and the port placement positions have unique numbers in the same type of template macro cell, and the relative relationship between different numbers is recorded in the same type of template macro cell. Since the template macro cell contains the legal positions of the ports on the module boundary, the number of these positions is much less than the number of positions when the ports are freely arranged. This makes the port arrangement of the key module simpler on the one hand, and simplifies the port alignment work on the other hand. The port arrangement and alignment work of the module is shortened, and the iteration period of the module-level design is further reduced. The change of the module-level FP information can be synchronized in the top-level and module-level designs, so as to greatly reduce the iteration period of the module-level design as a whole.

[0161] It should be noted that in this document, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusions, so that processes, methods, articles, or devices including a series of elements not only include those elements, but also include other elements not explicitly listed, or inherent to such processes, methods, articles, or devices. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article, or device including the element.

[0162] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the above-described specific embodiments, and the above-described specific embodiments are only illustrative, but not limiting. Those skilled in the art can make many forms under the inspiration of the present application without departing from the purpose of the present application and the scope protected by the claims, and these are all within the protection of the present application.

Claims

1. A device for physical design layout planning, applied to EDA tools, characterized in that: The EDA tool can introduce multiple types of template macro cells in the form of physical units, each type of template macro cell includes: standard cell arrangement rows, power and ground connection networks, routing tracks and module boundary lines; The standard cell arrangement rows, the wiring tracks and the power ground connection network in any template macro unit meet the requirement of continuous splicing at the template macro unit boundary; The graphics of the module boundary lines in any type of template macro unit are different from the graphics of the module boundary lines in other types of template macro units; Port placement positions are arranged on any module boundary line, and the positions of the port placement positions meet physical design rules; The device is configured as follows: Selecting the type and quantity of template macro units according to the expected boundaries of the hierarchical modules in the core area of ​​the chip, and splicing the actual boundaries of the hierarchical modules using the module boundary lines of the selected template macro units; Based on the positions of the port placement bits of the selected template macro cells, the EDA tool is used to perform layout planning.

2. The device according to claim 1, characterized in that The pattern of the standard cell arrangement row, the pattern of the wiring track, and the pattern of the power ground connection network in any template macro unit are centrally symmetrically distributed on the template macro unit, so that the pattern of the standard cell arrangement row, the pattern of the wiring track, and the pattern of the power ground connection network remain unchanged before and after the template macro unit is flipped; The flipping refers to flipping the template macro unit in a horizontal direction, or flipping the template macro unit in a vertical direction.

3. The device according to claim 1, characterized in that The continuous splicing requirements include: the graphics of the standard cell arrangement rows, the graphics of the wiring tracks, and the graphics of the power ground connection network in any template macro unit. When the template macro unit is continuously spliced ​​with any other template macro unit, the graphics of the standard cell arrangement rows, the graphics of the wiring tracks, and the graphics of the power ground connection network at the connecting boundaries meet the process rule requirements in the physical design, and each graphic is continuous.

4. The device according to any one of claims 1 to 3, characterized in that: The standard cell arrangement rows in any template macro unit are set in a back-to-back form in the template macro unit and are an even number of rows.

5. The device according to any one of claims 1 to 3, characterized in that: The distance between a routing track adjacent to the border of the template macro unit in any template macro unit and the border of the template macro unit is half the distance between the other two adjacent routing tracks in the template macro unit; The two adjacent wiring tracks in the template macro unit refer to two adjacent wiring tracks in the template macro unit that are not adjacent to the boundary of the template macro unit.

6. The device according to any one of claims 1 to 3, characterized in that: The routing of the power ground connection network in any template macro unit is an even number of pairs; The routing of the power ground connection network is half a routing pair at the point closest to the template macro unit boundary, and the routing closest to the upper and lower boundaries of the template macro unit is at the same potential, and the routing closest to the left and right boundaries of the template macro unit is at the same potential.

7. The device according to claim 1, characterized in that The module boundary lines in any type of template macro unit are divided into horizontal boundary lines and vertical boundary lines; All the horizontal boundary lines are equidistant from the horizontal center line of the template macro unit in which they are located; All vertical boundary lines are equidistant from the vertical center line of the template macro unit in which they are located; The distance is adjusted according to the requirements of the physical design.

8. The device according to claim 5, characterized in that The port placement position has a unique number in the same type of template macro unit, and the relative relationship between different unique numbers is recorded in the same type of template macro unit; All the port placement positions are on the wiring track, and the distance between one port placement position and an adjacent port placement position is equal to the distance between the two adjacent wiring tracks; If the location of any of the port placements conflicts with the routing of the power ground connection network, it must be avoided and cannot be placed.

9. The device according to claim 8, characterized in that The unique numbers corresponding to different port placement positions in each template macro unit are different, so that each template macro unit has multiple sets of unique numbers; If the numbers in any two groups of unique numbers in the plurality of groups of unique numbers are the same, the two placement positions corresponding to the same numbers are the positions where the two hierarchical modules are aligned.

10. The device according to claim 1, characterized in that The device is configured as follows: According to the area requirement of the hierarchical module in the chip core area, a certain number and types of template macro units are selected to splice the chip core area; Based on the core area of ​​the chip, template macro cells at different positions are replaced according to the routing of the expected boundaries of the hierarchical module.

11. The device according to claim 10, characterized in that The apparatus is further configured to: Determine the boundary coordinates of the hierarchical module according to the position and side length of the selected template macro unit, and then convert them into top-level coordinates of the top-level coordinate system of the chip; Performing a segmentation operation according to the top-level coordinates corresponding to the boundary coordinates of the hierarchical module; After the splitting operation is completed, the top-level coordinates of each port in the hierarchical module are obtained based on the top-level coordinates corresponding to the boundary coordinates of the hierarchical module, the unique number of each template macro unit in the selected template macro unit, and the unique number of the port placement position in each template macro unit, and the top-level coordinates of each port in the hierarchical module are converted into a recognizable file of the EDA tool and imported into the EDA tool.

12. The device according to claim 11, characterized in that The device is configured as follows: Determining the top-level coordinates corresponding to the line segments of each boundary in the hierarchical module according to the top-level coordinates corresponding to the boundary coordinates of the hierarchical module; Determining the top-level coordinates corresponding to the vertices of each boundary in the hierarchical module according to the top-level coordinates corresponding to the line segments of each boundary in the hierarchical module; Importing the top-level coordinates corresponding to the vertices of each boundary into a placement and routing tool to obtain the boundary definition of the hierarchical module; The boundary definition is imported into the EDA tool to perform a segmentation operation.

13. The device according to claim 11, characterized in that The device is configured as follows: Arranging the positions of the ports in the hierarchical module in combination with the top-level coordinates of the ports in the hierarchical module; Find the location of the port that needs to be aligned in a template macro cell; Using the unique number of the port that needs to be aligned, query and obtain the unique number of the port in another template macro unit to be aligned with the port that needs to be aligned; Obtaining top-level coordinates of the port in the another template macro unit according to the unique label of the port in the another template macro unit; A port alignment operation is performed according to the top-level coordinates of the ports to be aligned and the top-level coordinates of the ports in the other template macro unit.

14. A layout planning method, applied to an EDA tool, characterized in that: The EDA tool can introduce multiple types of template macro cells in the form of physical units, each type of template macro cell includes: standard cell arrangement rows, power and ground connection networks, routing tracks and module boundary lines; The standard cell arrangement rows, the wiring tracks, and the power ground connection network in any template macro unit meet the requirement of continuous splicing at the template macro unit boundary. The pattern of the module boundary line in any type of template macro unit is different from the pattern of the module boundary line in other types of template macro units. Port placement positions are arranged on any module boundary line, and the positions of the port placement positions meet the physical design rules. The layout planning method comprises: Selecting the type and quantity of template macro units according to the expected boundaries of the hierarchical modules in the core area of ​​the chip, and splicing the actual boundaries of the hierarchical modules using the module boundary lines of the selected template macro units; Based on the positions of the port placement bits of the selected template macro cells, the EDA tool is used to perform layout planning.

15. The layout planning method according to claim 14, characterized in that: Selecting the type and quantity of template macro units according to the expected boundaries of the hierarchical modules in the core area of ​​the chip, and splicing the actual boundaries of the hierarchical modules using the module boundary lines of the selected template macro units, including: According to the area requirement of the hierarchical module in the chip core area, a certain number and types of template macro units are selected to splice the chip core area; Based on the core area of ​​the chip, template macro cells at different positions are replaced according to the routing of the expected boundaries of the hierarchical module.

16. The layout planning method according to claim 15, characterized in that: Before using the EDA tool for layout planning, it also includes: Determine the boundary coordinates of the hierarchical module according to the position and side length of the selected template macro unit, and then convert them into top-level coordinates of the top-level coordinate system of the chip; Performing a segmentation operation according to the top-level coordinates corresponding to the boundary coordinates of the hierarchical module; After the splitting operation is completed, the top-level coordinates of each port in the hierarchical module are obtained based on the top-level coordinates corresponding to the boundary coordinates of the hierarchical module, the unique number of each template macro unit in the selected template macro unit, and the unique number of the port placement position in each template macro unit, and the top-level coordinates of each port in the hierarchical module are converted into a recognizable file of the EDA tool and imported into the EDA tool.

17. The layout planning method according to claim 16, characterized in that: A segmentation operation is performed according to the top-level coordinates corresponding to the boundary coordinates of the hierarchical module, including: Determining the top-level coordinates corresponding to the line segments of each boundary in the hierarchical module according to the top-level coordinates corresponding to the boundary coordinates of the hierarchical module; Determining the top-level coordinates corresponding to the vertices of each boundary in the hierarchical module according to the top-level coordinates corresponding to the line segments of each boundary in the hierarchical module; Importing the top-level coordinates corresponding to the vertices of each boundary into a placement and routing tool to obtain the boundary definition of the hierarchical module; The boundary definition is imported into the EDA tool to perform a segmentation operation.

18. The layout planning method according to claim 16, wherein: Utilize the EDA tools to perform floorplanning, including: Arranging the positions of the ports in the hierarchical module in combination with the top-level coordinates of the ports in the hierarchical module; Find the location of the port that needs to be aligned in a template macro cell; Using the unique number of the port that needs to be aligned, query and obtain the unique number of the port in another template macro unit to be aligned with the port that needs to be aligned; Obtaining top-level coordinates of the port in the another template macro unit according to the unique label of the port in the another template macro unit; A port alignment operation is performed according to the top-level coordinates of the ports to be aligned and the top-level coordinates of the ports in the other template macro unit.

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