Memory device and method of operation thereof

Abstract

The present disclosure provides a memory device and an operating method thereof. The memory device includes a P-type well region, a common source line, a ground select line, at least one dummy ground select line, a plurality of word lines, at least one dummy string select line, a string select line, at least one bit line, and at least one memory string. The word line is disposed between the dummy ground select line and the dummy string select line, and a plurality of memory cells of the memory string are connected to the word line. The operating method includes the following steps: for a selected word line, applying a read voltage to the selected word line, and applying a pass voltage to the unselected other word lines and the ground select line. Before the read operation ends, the voltage of the string select line and the dummy string select line is first lowered in advance, and then the voltage of the bit line is raised.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a memory device and an operating method thereof, and more particularly to a three-dimensional and NAND memory device and an operating method for suppressing read operation interference. BACKGROUND

[0002] With the evolution of semiconductor technology, the structure of memory devices has evolved from a planar form to a three-dimensional form. For a three-dimensional memory device, particularly in a gate-all-around (GAA) structure, the storage cells are not directly connected to a P-well; thus, during a specific access operation, the channel region of the storage cells can be in a floating state.

[0003] Based on the above structural characteristics of a three-dimensional memory device with a gate-all-around structure, during a specific access operation (particularly a read operation), hot carrier effects can occur in some word lines, thus causing the threshold voltage of the transistors of the storage cells on these word lines to rise, resulting in read interference of these word lines.

[0004] Due to the miniaturization of memory devices, the spacing between word lines is greatly reduced; and, in response to complex and computationally resource-intensive practical applications, the number of programming operations and read operations of memory devices has also greatly increased, making the technical problem of read interference increasingly serious.

[0005] Therefore, the skilled persons in the relevant industry of the technical field have devoted themselves to improving the operating method of a three-dimensional memory device in order to reduce the read interference between word lines. SUMMARY

[0006] According to an aspect of the present disclosure, a memory device is provided. The memory device includes a plurality of P-well regions, a plurality of common source lines, a plurality of ground select lines, at least one dummy ground select line, a plurality of word lines, at least one dummy string select line, a string select line, at least one bit line, at least one memory string, and a control circuit. The plurality of common source lines are disposed between adjacent P-well regions. The plurality of word lines are disposed between the at least one dummy ground select line and the at least one dummy string select line. The at least one memory string is disposed between the plurality of common source lines and the at least one bit line. A plurality of memory cells of the at least one memory string are respectively connected to the plurality of word lines. The control circuit is configured to select one of the plurality of word lines for a read operation, to apply a read voltage to the selected one of the plurality of word lines, and to apply a pass voltage to unselected ones of the plurality of word lines, the plurality of ground select lines, the at least one dummy ground select line, the string select line, and the at least one dummy string select line, wherein the pass voltage is greater than the read voltage. Before the read operation is completed, the control circuit is configured to first lower voltages of the string select line and the at least one dummy string select line, and to then raise a voltage of the at least one bit line after the voltages of the string select line and the at least one dummy string select line are lowered.

[0007] According to another aspect of the present disclosure, a method of operating a memory device is provided. The memory device includes a plurality of P-well regions, a plurality of common source lines, a plurality of ground select lines, at least one dummy ground select line, a plurality of word lines, at least one dummy string select line, a string select line, at least one bit line, and at least one memory string. The plurality of common source lines are disposed between adjacent P-well regions. The plurality of word lines are disposed between the at least one dummy ground select line and the at least one dummy string select line. The at least one memory string is disposed between the plurality of common source lines and the at least one bit line. A plurality of memory cells of the at least one memory string are respectively connected to the plurality of word lines. The method includes selecting one of the plurality of word lines for a read operation, applying a read voltage to the selected one of the plurality of word lines, and applying a pass voltage to unselected ones of the plurality of word lines, the plurality of ground select lines, the at least one dummy ground select line, the string select line, and the at least one dummy string select line, wherein the pass voltage is greater than the read voltage. Before the read operation is completed, the method includes first lowering voltages of the string select line and the at least one dummy string select line, and then raising a voltage of the at least one bit line after the voltages of the string select line and the at least one dummy string select line are lowered.

[0008] Other aspects and advantages of the present disclosure will become apparent from the following detailed description, from the accompanying drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 Equivalent circuit diagram of a memory device according to an embodiment of the present disclosure.

[0010] Figure 2 、 Figure 3A 、 Figure 3BA timing chart of an operation voltage of a memory device of an embodiment of the present disclosure.

[0011] Figure 4 、 Figure 5 A voltage level distribution diagram of a memory string of a memory device of an embodiment of the present disclosure.

[0012] Figure 6A 、 Figure 6B A flowchart of an operation method of a memory device of an embodiment of the present disclosure.

[0013] Explanation of Reference Numerals

[0014] 1000: Memory device

[0015] 100: Memory string

[0016] 100(0) to 100(N): Transistor

[0017] GSM: Ground select transistor

[0018] SSM: String select transistor

[0019] WL(P): Selected word line

[0020] WL(0) to WL(N): Word line

[0021] WL(n): First word line

[0022] WL(n+k): Second word line

[0023] GSL: Ground select line

[0024] GSLd: Dummy ground select line

[0025] SSL: String select line

[0026] SSLd: Dummy string select line

[0027] BL1: Bit line

[0028] PWI: P-type well region

[0029] CSL: Common source line

[0030] Vread, Vread1, Vread2: Read voltage

[0031] Vpass: Pass voltage

[0032] VBL: First precharge voltage

[0033] VCSL: Second precharge voltage

[0034] VPWI: Voltage of P-type well region

[0035] T1~T4: Time Period

[0036] S110~S160: Steps Detailed Implementation

[0037] The technical terms used in this specification refer to those commonly used in the field. Where this specification provides further explanation or definition for certain terms, the explanation or definition herein shall prevail. Each embodiment of this disclosure has one or more technical features. Where feasible, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0038] Figure 1 This is a schematic diagram of the equivalent circuit of a memory device 1000 according to an embodiment of this disclosure. Please refer to... Figure 1 In this embodiment, the memory device 1000 is, for example, a three-dimensional NAND flash memory device. The memory device 1000 includes at least one memory string 100, which is arranged in a three-dimensional form above the P-well. Figure 1 (The P-well region is not shown). The memory string 100 includes multiple memory cells, each including transistors 100(0) to 100(N). In one example, the memory device 1000 has a three-dimensional gate-all-around (GAA) architecture, where the channel regions of transistors 100(0) to 100(N) of the memory string 100 are surrounded by the gates of transistors 100(0) to 100(N). Therefore, during a particular operation, the channel regions of transistors 100(0) to 100(N) of the memory string 100 may be electrically isolated from the P-well region or other structural elements.

[0039] In addition, the memory device 1000 also includes a common source line CSL, a ground selection line GSL, at least one dummy ground selection line GSLd, multiple word lines WL(0) to WL(N), at least one dummy string selection line SSLd, one string selection line SSL, and at least one bit line BL1. In the arrangement of the above components, the common source line CSL is located in an adjacent P-type well region (…). Figure 1(The P-type well region is not shown in the image), while the ground select line GSL and the dummy ground select line GSLd are disposed on the adjacent common source line CSL, and the word lines WL(0) to WL(N) are disposed between the dummy ground select line GSLd and the dummy serial select line SSLd. Furthermore, the transistors 100(0) to 100(N) of the memory cells of the memory string 100 are disposed and connected between the common source line CSL and the bit line BL1. Moreover, the ground select line GSL is connected to the gate of the ground select transistor GSM, the serial select line SSL is connected to the gate of the serial select transistor SSM, and the word lines WL(0) to WL(N) are respectively connected to the gates of the transistors 100(0) to 100(N) of the memory cells of the memory string 100. In addition to the memory string 100, the memory device 1000 may include other memory strings ( Figure 1 (Not shown in the text), and word lines WL(0) to WL(N) can be connected to the transistor gates of memory cells in other memory strings.

[0040] The memory device 1000 may further include a control circuit. Figure 1 (Not shown in the image), this control circuit controls the operating voltage applied to word lines WL(0) to WL(N), common source line CSL, ground select line GSL, serial select line SSL, and bit line BL1 to perform different types of access operations on memory string 100, including programming, verifying, reading, and erasing operations, etc. In one example, an erasing operation can be performed on memory string 100 first. After the erasing operation is completed, transistors 100(0) to 100(N) are in the erase state and have a low threshold voltage Vt. Then, programming operations can be performed on some of the word lines to write data. For example, a programming operation can be performed on the memory cell connected to the first word line WL(n) and the second word line WL(n+k) in word lines WL(0) to WL(N). After the programming operation is completed, the transistor 100(n) connected to the first word line WL(n) and the transistor 100(n+k) connected to the second word line WL(n+k) have a high voltage level threshold voltage Vt. The other transistors 100(0) to 100(n-1), 100(n+1) to 100(n+k-1), and 100(n+k+1) to 100(N) that have not been programmed remain at a low voltage level threshold voltage Vt. In this embodiment, the first word line WL(n) and the second word line WL(n+k) are not adjacent to each other, that is, k is a positive integer and k is greater than 1. Furthermore, after the programming operation is completed, the channel region of the memory string 100 located between the first word line WL(n) and the second word line WL(n+k) has a channel potential Vch.

[0041] After the programming operations of the first word line WL(n) and the second word line WL(n+k), one of the word lines WL(P) can be selected from the word lines WL(0) to WL(N) and a read operation is performed on the memory cells connected to the selected word line WL(P). During the read operation, the control circuit can further control the voltages of the dummy string select line SSLd, the string select line SSL and the bit line BL1 to suppress the read disturbance that can occur during the read operation. The operation method of the memory device 1000 to suppress the read disturbance during the read operation is described below in conjunction with the timing diagram of the operation voltages shown in Figure 2 , Figure 3A , Figure 3B the timing diagram of the operation voltages shown in FIG. 4 and the flow chart of the operation method shown in Figure 6A , Figure 6B .

[0042] Figure 2 , Figure 3A , Figure 3B the timing diagram of the operation voltages of the memory device 1000 of one embodiment of the present disclosure, Figure 6A , Figure 6B the flow chart of the operation method of the memory device 1000 of one embodiment of the present disclosure. Please refer to Figure 2 and Figure 6A , in step S110, one of the word lines WL(P) is selected from the word lines WL(0) to WL(N) of the memory device 1000 to perform a read operation on the transistor 100(p) of the memory cells connected to the selected word line WL(P). Then, in step S120, a read voltage Vread is applied to the selected word line WL(P); in this embodiment, the read voltage Vread can include two stages of a read voltage Vread1 and a read voltage Vread2. Also, a pass voltage Vpass is applied to the unselected word lines, the ground select line GSL, the dummy ground select line GSLd, the string select line SSL and the dummy string select line SSLd. In this embodiment, the pass voltage Vpass is greater than the read voltage Vread1 and the read voltage Vread2. In addition, a first pre-charge voltage VBL (e.g. 1.3V) is applied to the bit line BL1 and a second pre-charge voltage VCSL (e.g. 0.7V) is applied to the common source line CSL.

[0043] More specifically, during time period T1 of the read operation, the voltages of the unselected word line, ground select line GSL, dummy ground select line GSLd, serial select line SSL, and dummy serial select line SSLd are ramped up from zero (0V) to the pass voltage Vpass, the voltage of bit line BL1 is ramped up from zero (0V) to the first precharge voltage VBL, and the voltage of common source line CSL is ramped up from zero (0V) to the second precharge voltage VCSL. Then, during time period T2 of the read operation, the voltages of the unselected word line, ground select line GSL, dummy ground select line GSLd, serial select line SSL, and dummy serial select line SSLd are maintained at the pass voltage Vpass, the voltage of bit line BL1 is maintained at the first precharge voltage VBL, and the voltage of common source line CSL is maintained at the second precharge voltage VCSL.

[0044] On the other hand, during time period T2 of the read operation, the voltage of the selected word line WL(P) is ramped up from zero (0V) to the read voltage Vread1, and then further ramped up to the read voltage Vread2. Furthermore, during time periods T1 and T2 of the read operation, the voltage VPWI of the P-type well region PWI remains at zero (0V).

[0045] like Figure 2 As shown, during time period T3 (before the end of the read operation), the voltages of the unselected word line, ground select line GSL, dummy ground select line GSLd, serial select line SSL, and dummy serial select line SSLd remain at the pass voltage Vpass, the voltage of bit line BL1 remains at the first precharge voltage VBL, and the common source line CSL remains at the second precharge voltage VCSL. Then, during time period T4 (near the end of the read operation), the voltages of the unselected word line, ground select line GSL, dummy ground select line GSLd, serial select line SSL, dummy serial select line SSLd, bit line BL1, and common source line CSL slope down to zero (0V). Furthermore, the voltage VPWI of the P-type well region PWI remains zero (0V) during both time periods T3 and T4.

[0046] As shown in the voltage level distribution diagram of the memory string 100, the channel potential Vch of the channel region of the memory string 100 between the first word line WL(n) and the second word line WL(n+k) is down coupled to a negative voltage level of about -4V. Thus, a large potential difference is formed between the first word line WL(n) and the adjacent word line WL(n-1), which can cause the generation of hot electron current (also known as "hot carrier current") in the channel region between the first word line WL(n) and the adjacent word line WL(n-1). The hot carrier current can cause the threshold voltage Vt of the transistor of the memory cell on the word line WL(n-1) to rise (step by step with the number of read operations) and form read disturbance. Similarly, a large potential difference is also formed between the second word line WL(n+k) and the adjacent word line WL(n+k+1), which can cause the generation of hot carrier current, causing the threshold voltage Vt of the transistor of the memory cell on the word line WL(n+k+1) to rise. Figure 4 As shown in the voltage level distribution diagram of the memory string 100, the channel potential Vch of the channel region of the memory string 100 between the first word line WL(n) and the second word line WL(n+k) is down coupled to a negative voltage level of about -4V. Thus, a large potential difference is formed between the first word line WL(n) and the adjacent word line WL(n-1), which can cause the generation of hot electron current (also known as "hot carrier current") in the channel region between the first word line WL(n) and the adjacent word line WL(n-1). The hot carrier current can cause the threshold voltage Vt of the transistor of the memory cell on the word line WL(n-1) to rise (step by step with the number of read operations) and form read disturbance. Similarly, a large potential difference is also formed between the second word line WL(n+k) and the adjacent word line WL(n+k+1), which can cause the generation of hot carrier current, causing the threshold voltage Vt of the transistor of the memory cell on the word line WL(n+k+1) to rise.

[0047] To suppress the disturbance of the hot carrier current as described above, the voltage of the string select line SSL, dummy string select line SSLd and bit line BL1 can be controlled to generate band-to-band hot hole current and inject into the channel region of the memory string 100 and eliminate the down coupled channel potential before the read operation is completed. The detailed operation method is described in the following Figure 3A , Figure 3B and Figure 6A, in step S130, for the time period T3 (the time period T3 is before the end of the read operation), at the beginning of the time period T3 (i.e., the starting time point), first, the voltage of the string selection line SSL and dummy string selection line SSLd is lowered to zero (0V) or a negative voltage level (e.g., -3V to -5V) by the pass voltage Vpass. After the voltage of the string selection line SSL and dummy string selection line SSLd is lowered, the voltage of the bit line BL1 is raised to a first positive voltage level (e.g., 5V) or a second positive voltage level (e.g., 2V) from the first pre-charge voltage VBL. In summary, in the example of Figure 3A , first, the voltage of the string selection line SSL and dummy string selection line SSLd is lowered to zero (0V) by the pass voltage Vpass, and after the voltage of the string selection line SSL and dummy string selection line SSLd is lowered, the voltage of the bit line BL1 is raised to a first positive voltage level (e.g., 5V) from the first pre-charge voltage VBL; in the embodiment of Figure 3A , the bit line BL1 has a sufficient potential difference (5V) with the string selection line SSL, dummy string selection line SSLd to generate a band-to-band hot hole current at the junction region of the bit line BL1. On the other hand, in the example of Figure 3B , first, the voltage of the string selection line SSL and dummy string selection line SSLd is lowered to a lower negative voltage level (e.g., -3V to -5V) by the pass voltage Vpass, and after the voltage of the string selection line SSL and dummy string selection line SSLd is lowered, the voltage of the bit line BL1 is raised to a second positive voltage level (e.g., 2V) from the first pre-charge voltage VBL, which can be lower than the first positive voltage level (e.g., 5V) of the example; in the embodiment of Figure 3A , the bit line BL1 still has a sufficient potential difference (5V) with the string selection line SSL, dummy string selection line SSLd to generate a band-to-band hot hole current at the junction region of the bit line BL1. Figure 3B

[0048] Then, in step S140, the voltage of the selected word line WL(P) is maintained at the read voltage Vread2, and the voltage of the unselected word lines, ground selection line GSL and dummy ground selection line GSLd is maintained at the pass voltage Vpass; the above voltage maintenance is maintained throughout the time period T3 until the starting time point of the time period T4.

[0049] Then, referring to Figure 6B , in step S150, at the time period T4, when the read operation is ended, the voltage of the selected word line WL(P), unselected word lines, ground selection line GSL and dummy ground selection line GSLd is ramped down to zero (0V) ​

[0050] Also, in step S160, the voltage of the string select line SSL, dummy string select line SSLd is maintained at zero (0V) or a negative voltage level (e.g., -3V to -5V), and the voltage of the bit line BL1 is maintained at a first positive voltage level (e.g., 5V) or a second positive voltage level (e.g., 2V) during the period that the voltage of the selected word line WL(P), unselected word lines, ground select line GSL, and dummy ground select line GSLd is ramped down to zero (0V).

[0051] In another example, to more effectively maintain the band-to-band hot hole current in the channel region between the first word line WL(n) and the second word line WL(n+k), the common source line CSL can be electrically connected to the P-type well region PWI such that the common source line CSL and the P-type well region PWI are at the same potential. Also, the voltage VCSL of the common source line CSL and the voltage VPWI of the P-type well region PWI are maintained at the second pre-charge voltage (0.7V) (i.e., VCSL = VPWI = 0.7V) during the period T2 and the period T3 of the read operation, such that the potential of the P-type well region is higher than the channel potential Vch of the channel region between the first word line WL(n) and the second word line WL(n+k).

[0052] In summary, during the read operation of the memory device 1000, the voltages of the bit line BL1 and the string select line SSL, dummy string select line SSLd can be controlled such that there is a sufficient potential difference between the bit line BL1 and the string select line SSL, dummy string select line SSLd, causing the junction region of the bit line BL1 to generate a band-to-band hot hole current to cancel the downwardly coupled channel potential of the channel region between the first word line WL(n) and the second word line WL(n+k), thereby suppressing the read disturbance caused by the hot carrier current. See, e.g., the voltage level distribution diagram of the memory string 100 shown in FIG. 6B. Figure 5 After the band-to-band hot hole current cancels the downwardly coupled channel potential of the channel region between the first word line WL(n) and the second word line WL(n+k), the channel potential Vch remains substantially at a positive voltage level and is not downwardly coupled. Thus, the hot carrier current is not generated between the first word line WL(n) and the adjacent word line WL(n-1) (or between the second word line WL(n+k) and the adjacent word line WL(nN+k+1)).

[0053] While the disclosure has been disclosed in detail by preferred embodiments and examples with reference to the drawings, it will be appreciated that these examples are intended to illustrate but not to limit the scope of the disclosure. It is contemplated that various modifications and combinations of the embodiments disclosed herein will occur to those skilled in the art to which the disclosure pertains, and such modifications and combinations are within the scope of the disclosure and the appended claims.

Claims

1. A memory device, characterized in that, include: A P-type well region, a common source line, a ground select line, at least one dummy ground select line, multiple word lines, at least one dummy serial select line, a serial select line, and at least one bit line, wherein the common source line is located adjacent to the P-type well region, and the word lines are located between the at least one dummy ground select line and the at least one dummy serial select line. At least one memory string is disposed between the common source line and the at least one bit line, and the gates of a plurality of memory cells of the at least one memory string are respectively connected to these word lines; as well as A control circuit is configured to select a word line from among these word lines for a read operation by applying a read voltage to the selected word line and applying a pass voltage to the other unselected word lines, the ground select line, the at least one dummy ground select line, the serial select line, and the at least one dummy serial select line, wherein the pass voltage is greater than the read voltage. Before the read operation ends, the control circuit first reduces the voltage of the serial select line and the at least one dummy serial select line, and after the voltage of the serial select line and the at least one dummy serial select line is reduced, the voltage of the at least one bit line is increased.

2. The memory device according to claim 1, characterized in that, Prior to the read operation, a plurality of memory cells connected to a first word line and a second word line of these word lines have been programmed to have a high threshold voltage, and the first word line and the second word line are not adjacent, and the at least one memory string has a channel potential in a channel region located between the first word line and the second word line.

3. The memory device according to claim 2, characterized in that, Before the read operation ends, the control circuit pre-boosts the voltage of the at least one bit line to generate an interband thermal hole current in a junction region of the at least one bit line, and injects the interband thermal hole current into the channel region of the at least one memory string to eliminate the downwardly coupled channel potential.

4. The memory device according to claim 3, characterized in that, Before the read operation ends, the control circuit first reduces the voltage of the serial select line and the at least one dummy serial select line from the pass voltage to zero (0V) or a negative voltage level. After the voltage of the serial select line and the at least one dummy serial select line is reduced, the voltage of the at least one bit line is increased from a first precharge voltage to a first positive voltage level or a second positive voltage level.

5. The memory device according to claim 4, characterized in that, If the voltage of the serial select line and the at least one dummy serial select line is reduced to zero (0V) by the pass voltage beforehand, then the voltage of the at least one bit line is increased from a first precharge voltage to the first positive voltage level. If the voltage of the serial select line and the at least one dummy serial select line is reduced to the negative voltage level by the pass voltage beforehand, then the voltage of the at least one bit line is increased from a first precharge voltage to the second positive voltage level, which is lower than the first positive voltage level.

6. The memory device according to claim 4, characterized in that, The control circuit maintains the voltage of the selected word line at the read voltage and maintains the voltages of the unselected other word lines, the ground selection line, and the at least one dummy ground selection line at the pass voltage until the read operation ends. When the read operation ends, the control circuit gradually reduces the voltages of the selected word line, the unselected other word lines, the ground selection line, and the at least one dummy ground selection line to zero (0V).

7. The memory device according to claim 6, characterized in that, At the end of the read operation, during the period when the voltage of the selected word line, the other unselected word lines, the ground select line, and the at least one dummy ground select line slopes down to zero (0V), the control circuit maintains the voltage of the serial select line and the at least one dummy serial select line at zero (0V) or the negative voltage level, and maintains the voltage of the at least one bit line at the first positive voltage level or the second positive voltage level.

8. The memory device according to claim 4, characterized in that, Before the read operation ends, the control circuit reduces the voltage of the serial select line and the at least one dummy serial select line from the pass voltage to zero (0V) or the negative voltage level in advance, so as to turn off the serial select line or at least one serial select transistor on the at least one dummy serial select line.

9. The memory device according to claim 4, characterized in that, The common source line is connected to the P-type well region to have the same potential, and the control circuit maintains the voltage between the common source line and the P-type well region at a second pre-charge voltage.

10. A method of operating a memory device, characterized in that, The memory device includes a P-type well region, a common source line, a ground select line, at least one dummy ground select line, multiple word lines, at least one dummy serial select line, a serial select line, at least one bit line, and at least one memory string. The common source line is disposed adjacent to the P-type well region. The word lines are disposed between the at least one dummy ground select line and the at least one dummy serial select line. The at least one memory string is disposed between the common source line and the at least one bit line. The gates of multiple memory cells in the at least one memory string are respectively connected to the word lines. The operation method includes: Select one of these word lines to perform a read operation; Apply a read voltage to the selected word line; Applying a voltage through to the unselected word line, the ground select line, the at least one dummy ground select line, the serial select line, and the at least one dummy serial select line, the voltage through being greater than the read voltage; and Before the read operation ends, the voltage of the serial select line and the at least one dummy serial select line is first reduced, and after the voltage of the serial select line and the at least one dummy serial select line is reduced, the voltage of the at least one bit line is increased.

11. The operating method according to claim 10, characterized in that, Prior to the read operation, a plurality of memory cells connected to a first word line and a second word line of these word lines have been programmed to have a high threshold voltage, and the first word line and the second word line are not adjacent, and the at least one memory string has a channel potential in a channel region located between the first word line and the second word line.

12. The operating method according to claim 11, characterized in that, Before the read operation is completed, the operation method includes: The voltage of the at least one bit line is pre-increased to generate an interband thermal hole current in a junction region of the at least one bit line; and Injecting the interband thermal hole current into the channel region of the at least one memory string to eliminate the downwardly coupled channel potential.

13. The operating method according to claim 12, characterized in that, Before the read operation is completed, the operation method includes: First, the voltage between the serial select line and the at least one dummy serial select line is reduced from the pass voltage to zero (0V) or a negative voltage level; and After the voltage of the serial select line and the at least one dummy serial select line decreases, the voltage of the at least one bit line is increased from a first precharge voltage to a first positive voltage level or a second positive voltage level.

14. The operating method according to claim 13, characterized in that, If the voltage of the serial select line and the at least one dummy serial select line is reduced to zero (0V) by the pass voltage beforehand, then the voltage of the at least one bit line is increased from a first precharge voltage to the first positive voltage level. If the voltage of the serial select line and the at least one dummy serial select line is reduced to the negative voltage level by the pass voltage beforehand, then the voltage of the at least one bit line is increased from a first precharge voltage to the second positive voltage level, which is lower than the first positive voltage level.

15. The operating method according to claim 13, characterized in that, include: Maintain the voltage of the selected word line at the read voltage; Maintain the voltage of the other unselected word lines, the ground selection line, and the at least one dummy ground selection line at the pass voltage; as well as When the read operation is completed, the voltage of the selected word line, the other unselected word lines, the ground select line, and the at least one dummy ground select line is ramped down to zero (0V).

16. The operating method according to claim 15, characterized in that, When the read operation ends, the operation method includes: During the period when the voltage of the selected word line, the other unselected word lines, the ground select line, and the at least one dummy ground select line slopes down to zero (0V), the voltage of the serial select line and the at least one dummy serial select line is maintained at zero (0V) or the negative voltage level, and the voltage of the at least one bit line is maintained at the first positive voltage level or the second positive voltage level.

17. The operating method according to claim 13, characterized in that, Before the read operation is completed, the operation method includes: The voltage between the serial select line and the at least one dummy serial select line is reduced from the through voltage to zero (0V) or the negative voltage level in advance to turn off the serial select line or at least one serial select transistor on the at least one dummy serial select line.

18. The operating method according to claim 13, characterized in that, include: Connect the common source line to the P-type well region to achieve equipotentiality; as well as The voltage between the common source line and the P-type well region is maintained at a second pre-charge voltage.

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